EP4620033A1

EP4620033A1 - Method of removing a handle substrate from a solid-state die

Info

Publication number: EP4620033A1
Application number: EP23895294.9A
Authority: EP
Inventors: Peter O. WEIGEL; Takashi Orimoto; Chia-Ming Chang
Original assignee: Psiquantum Corp
Current assignee: Psiquantum Corp
Priority date: 2022-11-22
Filing date: 2023-11-17
Publication date: 2025-09-24
Also published as: WO2024112606A1; AU2023385346A1

Abstract

A method of removing a solid-state die handle substrate from a solid-state die may include providing a substrate structure including a first substrate, a second substrate bonded to the first substrate and the solid-state die bonded to the first substrate in an opening in the second substrate, forming a planarizing material in the opening, and removing at least a portion of the solid-state die handle substrate and at least a portion of the second substrate.

Description

Attorney Docket No.35113-452WO METHOD OF REMOVING A HANDLE SUBSTRATE FROM A SOLID-STATE DIE FIELD [0001] The present disclosure relates to solid-state device processing in general and to a method of removing a handle substrate from a solid-state die in particular. BACKGROUND [0002] Semiconductor dies containing electronic dies containing semiconductor devices, such as transistors may be formed on a handle substrate, such as a silicon wafer, for ease of processing. The semiconductor dies may be bonded to a device wafer followed by removing the silicon wafer prior to singulating (i.e., dicing) the semiconductor dies. It is straightforward to remove the silicon wafer from the semiconductor dies on the device wafer due to the silicon wafer’s substantially circular shape (excluding the wafer flat(s)) and due to silicon wafer’s edges not including critical device regions. SUMMARY [0003] According to an aspect of the present disclosure, a method of removing a solid- state die handle substrate from a solid-state die may include providing a substrate structure including a first substrate, a second substrate bonded to the first substrate and the solid-state die bonded to the first substrate in an opening in the second substrate, forming a planarizing material in the opening, and removing at least a portion of the solid-state die handle substrate and at least a portion of the second substrate. [0004] According to another aspect of the present disclosure, a method of removing a solid-state die handle substrate from a solid-state die may include bonding the solid-state die to a first substrate, after the bonding of the solid-state die to the first substrate, bonding a wafer to the first substrate such that the solid-state die is located in an opening of the wafer, forming a planarizing material on the wafer and in the opening such that a height of the planarizing material in the opening that is greater than a height of the solid-state die handle substrate and greater than a height of the wafer, polishing a surface of the solid-state die handle substrate, a surface of the planarizing material and a surface of the wafer to remove a portion of the solid-state die handle substrate, a portion of the planarizing material, and a portion of the wafer, and performing an etching process to remove a remainder of the solid- Attorney Docket No.35113-452WO state die handle substrate, a remainder of the planarizing material and a remainder of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS [0005] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the Figures. [0006] FIG.1A is a vertical cross-sectional view of an intermediate structure including a solid-state die mounted on a first substrate according to one or more embodiments. [0007] FIG.1B is a plan view (e.g., top-down view) of an intermediate structure including a plurality of the solid-state dies mounted on the first substrate according to one or more embodiments. [0008] FIG.2A is a vertical cross-sectional view of an intermediate structure including a second substrate (e.g., waffle substrate or waffle wafer) bonded to the first substrate according to one or more embodiments. [0009] FIG.2B is a plan view (e.g., top-down view) of an intermediate structure including second substrate bonded to the first substrate according to one or more embodiments. [0010] FIG.3A is a vertical cross-sectional view of an intermediate structure including a planarizing material on the second substrate according to one or more embodiments. [0011] FIG.3B is a plan view (e.g., top-down view) of an intermediate structure including the planarizing material according to one or more embodiments. [0012] FIG.4A is a vertical cross-sectional view of an intermediate structure after a planarizing process according to one or more embodiments. [0013] FIG.4B is a plan view (e.g., top-down view) of the intermediate structure after the planarizing process according to one or more embodiments. [0014] FIG.5A is a vertical cross-sectional view of an intermediate structure after a polishing process according to one or more embodiments. [0015] FIG.5B is a plan view (e.g., top-down view) of the intermediate structure after the polishing process according to one or more embodiments. [0016] FIG.6A is a vertical cross-sectional view of an intermediate structure after an etching process according to one or more embodiments. Attorney Docket No.35113-452WO [0017] FIG.6B is a plan view (e.g., top-down view) of the intermediate structure after the etching process according to one or more embodiments. [0018] FIG.7A is a vertical cross-sectional view of an intermediate structure after another etching process according to one or more embodiments. [0019] FIG.7B is a plan view (e.g., top-down view) of the intermediate structure after the other etching process according to one or more embodiments. [0020] FIG.8 is a flow chart illustrating a method of removing a solid-state die handle substrate from a solid-state die according to one or more embodiments. [0021] FIG.9 is a flow chart illustrating another method of removing a solid-state die handle substrate from a solid-state die according to one or more embodiments. DETAILED DESCRIPTION [0022] As discussed above, the embodiments of the present disclosure are directed a method of removing a solid-state die handle substrate from a solid-state die, the various aspects of which are discussed herein in detail. The drawings are not necessarily drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a “layer” refers to a continuous portion of at least one material including a region having a thickness. A layer may consist of a single material portion having a homogeneous composition, or may include multiple material portions having different compositions. [0023] As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0 x 10⁵ S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0 x 10^-5 S/cm. As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0 x 10^-5 S/cm to 1.0 x 10⁵ S/cm. As used herein, a “metallic Attorney Docket No.35113-452WO material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition. [0024] A problem with the typical approach of removing a handle substrate from a solid- state die is that the typical approach may be limited to cases having wafer to wafer bonded stacks. For low-yield/high-cost materials such as barium titanate (BaTiO3 or BTO), device platforms where multiple dies are to be bonded, or stacks of wafers of different sizes, wafer- wafer bonding may be either undesirable or impossible. This is especially severe when only one of the bonded pairs is a silicon wafer or a silicon-on-insulator (SOI) wafer, since silicon wafers and SOI wafers may be about 200mm to about 300 mm in diameter compared with about 50 mm to about 100 mm for substrates containing photonic die, such as photonic die containing interferometers which include BTO layers, or research and development scale (R&D scale) materials. [0025] An embodiment of the present disclosure may provide a robust, scalable method of removing a handle substrate from a solid-state die. In particular, the method may especially effective at removing the handle substrate in the case of a bonded die-wafer pair. The method may utilize, for example, a substrate (e.g., a waffle substrate or waffle wafer) including openings at locations corresponding to locations of solid-state dies mounted on an underlying device substrate (e.g., device wafer). The method may be used to remove the handle substrate from solid-state dies of any size and at any orientation. [0026] It should be noted that the method may be used to remove only a portion of the solid-state die handle substrate. In some cases, it may be desirable to leave a portion of the solid-state die handle substrate with the solid-state die. [0027] FIGS.1A-7B illustrate various intermediate structures in a method of removing a solid-state die handle substrate from a solid-state die, according to one or more embodiments. In particular, FIG.1A is a vertical cross-sectional view of an intermediate structure including a solid-state die 120 mounted on a first (e.g., device) substrate 110 according to one or more embodiments. FIG.1B is a plan view (e.g., top-down view) of an intermediate structure including a plurality of the solid-state dies 120 mounted on the first substrate 110 according to one or more embodiments. [0028] As illustrated in FIG.1A, the first substrate 110 may include a smooth, planarized substrate wafer that may or may not include one or more integrated circuits (ICs) including photonic devices and/or electrical devices. The first substrate 110 may include, for example, a bulk semiconductor layer 112 (e.g., first silicon wafer). The bulk semiconductor layer 112 may optionally include an active region including the photonic and/or electrical devices and Attorney Docket No.35113-452WO integrated circuits (ICs). For example, the bulk semiconductor layer 112 may comprise a silicon wafer containing transistor integrated circuits used to control photonic devices (e.g., interferometers) used in various photonic integrated circuits. The first substrate 110 may optionally include a first oxide layer 114 on the bulk semiconductor layer 112. The first oxide layer may comprise a silicon oxide layer located over the ICs. [0029] Any number of the solid-state dies 120 may be mounted on the first substrate 110. In one embodiment, the solid-state dies 120 may be mounted on the first substrate 110 by dielectric bonding, where planarized dielectric surfaces (e.g., silicon oxide surfaces) are bonded to each other using solid state bonding. In another embodiment, the solid-state dies 120 may be mounted on the first substrate 110 by conductive bonding, such as by bonding opposing electrically conductive bonding pads and/or structures (not shown for clarity). The bonding pads and/or bonding structures (e.g., copper bonding pads and/or solder bonding structures) may protrude through the first oxide layer 114. In another embodiment, the solid- state dies 120 may be mounted on the first substrate 110 by hybrid conductive and dielectric bonding, in which opposing conductors are bonded to each other and opposing dielectrics are bonded to each other. [0030] The solid-state dies 120 may include an active region 121 that may contain, for example, one or more integrated circuits (ICs), such as photonic devices and/or electrical devices. In one embodiment, the active region 121 includes photonic devices, such as interferometers containing one or more BTO layers which are optically coupled to one or more waveguides, such as silicon or silicon nitride waveguides. The solid-state die 120 may also include a solid-state die handle substrate 122 on the active region 121. The handle substrate 122 may comprise a silicon substrate or a silicon-on-insulator (SOI) substrate, such as an SOI substrate containing a supporting silicon substrate, a silicon-on-insulating layer and a buried oxide layer located between the supporting silicon substrate and the silicon-on- insulator layer. The photonic devices, such as interferometers / phase shifters containing one or more BTO layers and/or waveguides, are located on the silicon-on-insulator layer. The photonic devices may be covered by an dielectric encapsulating material, such as a silicon oxide encapsulating layer, which faces the first substrate 110. In one embodiment, the encapsulating material may be bonded to the first silicon oxide layer 114 by dielectric bonding. [0031] As illustrated in FIG.1B, plural solid-state dies 120 may be bonded in pre- determined locations on the surface of the first substrate 110. The solid-state dies 120 may be arranged in the form of an array having rows and columns. The solid-state dies 120 have a Attorney Docket No.35113-452WO horizontal area which is smaller than that of the first substrate 110, and the handle substrate 122 has a major surface (i.e., horizontal surface) which is smaller than a major surface (i.e., horizontal surface) of the bulk semiconductor layer 112. [0032] FIG.2A is a vertical cross-sectional view of an intermediate structure including a second substrate 130 (e.g., “waffle” substrate or “waffle” wafer) bonded to the first substrate 110 according to one or more embodiments. FIG.2B is a plan view (e.g., top-down view) of an intermediate structure including second substrate 130 bonded to the first substrate 110 according to one or more embodiments. [0033] Referring to FIG.2A, the second substrate 130 may include, for example, a second oxide layer 134 and a bulk semiconductor layer 132 (e.g., handle portion) on the second oxide layer 134. The bulk semiconductor layer 132 may comprise a second silicon wafer. The second substrate 130 may include a thermally oxidized silicon “waffle” wafer, which is a wafer with openings 136 formed through it in specific locations. The openings 136 correspond to the locations of the solid-state dies 120 on the first substrate 110. Each opening 136 has a greater area than a respective solid-state die 120 configured to be located in the opening 136. [0034] Referring to FIG.2B, the second substrate 130 may be bonded to the first substrate 110 substrate in such a way that the bonded solid-state dies 120 pass through openings 136 (e.g., waffle wafer etched openings) in the second substrate 130. For example, the second substrate 130 may be prefabricated with the openings 136 extending through its entire thickness, followed by bonding the second substrate 130 to the first substrate 110 while allowing the previously bonded solid state dies 120 located on the first substrate 110 to pass through the respective openings 136 in the second substrate 130. [0035] Note that, depending on a thickness of the solid-state dies 120 and a thickness of the second substrate 130 thickness, the process of FIGS.1A, 1B and the process of FIGS.2A, 2B can be reversed in the process flow. In other words, the second substrate 130 may be bonded to the first substrate 110 (e.g., via dielectric bonding between the first oxide layer 114 and the second oxide layer 134) followed by bonding the solid-state die 120 to the first substrate 110 through the openings 136 in the second substrate 130. In this alternative embodiment, the second substrate 130 may be prefabricated with the openings 136 extending through its entire thickness, followed by bonding the second substrate 130 to the first substrate 110. Alternatively, the second substrate 130 may first be bonded to the first substrate 110, followed by etching the openings 136 through the second substrate 130 to expose the bonding locations of the solid-state die 120 on the first substrate 110. Attorney Docket No.35113-452WO [0036] FIG.3A is a vertical cross-sectional view of an intermediate structure including a planarizing material 140 on the second substrate 130 according to one or more embodiments. FIG.3B is a plan view (e.g., top-down view) of an intermediate structure including the planarizing material 140 according to one or more embodiments. [0037] Referring to FIGS.3A and 3B, after the solid-state die 120 and the second substrate 130 are bonded to the first substrate 110 to form the intermediate structure (e.g., bonded stack), a layer of planarizing material 140 may be formed on the second substrate 130 and in the openings 136. The intermediate structure may be spin-coated with, deposited with, or submerged in the planarizing material 140. The planarizing material 140 may include a fluid, a semi-solid, a solid, or a suspension. The planarizing material 140 can be, but is not limited to, spin-on glass, photoresist, or wax. Alternatively, a polymer or another planarizing material 140 may be deposited using a solid-state deposition method followed by thermally reflowing the material to form a substantially planar upper surface. A height of the upper surface of the planarizing material (in the z-direction) may be greater than a height of an upper surface of the second substrate 130 and greater than a height of the solid-state die 120. The entire intermediate structure (bonded stack) may at this point resemble a wafer to wafer bonded stack rather than plural die bonded to common wafer stack, and will be easier to thin without damaging layers of the solid-state die 120 or sensitive structures, such as optional ICs, within the first substrate 110 (e.g., substrate wafer). [0038] FIG.4A is a vertical cross-sectional view of an intermediate structure after a planarizing process according to one or more embodiments. FIG.4B is a plan view (e.g., top-down view) of the intermediate structure after the planarizing process according to one or more embodiments. [0039] Referring to FIGS.4A and 4B, a rough backside grinding planarization process may be performed on the upper surface of the second substrate 130, the upper surface of the planarizing material 140 and the upper surface of the solid-state die 120. The planarization process may result in the upper surface of the solid-state die 120 (e.g., upper surface of solid- state die handle substrate 122) being substantially coplanar with the upper surface of the second substrate 130 (e.g., upper surface of the bulk semiconductor layer 132) and the upper surface of the planarizing material 140. The planarization process may use, for example, a high-grit mechanical or chemical-mechanical polishing (CMP) tool to grind through the planarizing material 140, the solid-state die handle substrate 122 and the bulk semiconductor layer 132 (e.g., the backside handle substrate of bonded waffle wafer). How much material is to be removed in this way is flexible and application-specific. Attorney Docket No.35113-452WO [0040] FIG.5A is a vertical cross-sectional view of an intermediate structure after a polishing process according to one or more embodiments. FIG.5B is a plan view (e.g., top- down view) of the intermediate structure after the polishing process according to one or more embodiments. [0041] Referring to FIGS.5A and 5B, a polishing process may be performed on the intermediate structure in order to polish and smooth the upper surface of solid-state die handle substrate 122, the upper surface of bulk semiconductor layer 132 and the upper surface of the planarizing material 140. The polishing process may include, for example, a CMP polishing process. At this point, a small portion of the solid-state die handle substrate 122 may remain. If desirable, a die singulation process may be performed at this point in order to singulate the solid-state dies 120. In an alternative embodiment, the separate rough grinding planarization process and fine polishing process may be combined into a single planarization step, such as a single CMP step. [0042] FIG.6A is a vertical cross-sectional view of an intermediate structure after an etching process according to one or more embodiments. FIG.6B is a plan view (e.g., top- down view) of the intermediate structure after the etching process according to one or more embodiments. [0043] The solid-state die handle substrate 122 of the solid-state dies 120 as well as the bulk semiconductor layer 132 of the second substrate 130 are at least partially removed and may be completely removed. For example, a selective reactive ion etch (RIE) may be performed in order to remove any remaining portions of the solid-state die handle substrate 122 and any remaining portions of the bulk semiconductor layer 132. The removal may also comprise either an additional CMP step and a highly selective reactive ion etch (RIE), or an isotropic gaseous etch (e.g., XeF2 etch) combined with wet etches and/or further RIE etching, or a wet etch combined with an RIE etching. The process steps used for removing the solid- state die handle substrate 122 and the bulk semiconductor layer 132 after backside grinding in FIGS.4A and 4B depend on the specific application and material being removed. One of the benefits of this approach is that it may cater to a wide variety of materials. [0044] FIG.7A is a vertical cross-sectional view of an intermediate structure after another etching process according to one or more embodiments. FIG.7B is a plan view (e.g., top-down view) of the intermediate structure after the other etching process according to one or more embodiments. [0045] Referring to FIGS.7A and 7B, another selective removal step, such as a reactive ion etch (RIE) or ashing may be performed in order to remove any remaining portions of the Attorney Docket No.35113-452WO planarizing material 140. After an entirety of the solid-state die handle substrate 122 and the bulk semiconductor layer 132 (e.g., handle materials) has been removed or thinned as desired, any remaining planarizing material 140 can either be left (as in the case of spin-on glass) or easily removed by ashing or selective etching (as in the case of photoresist or wax). As a result of this selective removal step, only the active region 121 of the solid-state die 120 and optionally at least a portion of the second oxide layer 134 may remain on the first substrate 110. [0046] After the step shown in FIGS.7A and 7B, the active region 121 (e.g., interferometers containing BTO layer(s) and/or waveguides) may be left on the first (e.g., device) substrate 110. The first substrate 110 and the active regions 121 may be placed into a device (e.g., a quantum computer, etc.) or they may be singulated (i.e., diced) to form a plurality of free standing die (e.g., photonic die). [0047] FIG.8 is a flow chart illustrating a method of removing a solid-state die handle substrate from a solid-state die according to one or more embodiments. Step 810 may include providing a substrate structure including a first substrate, a second substrate bonded to the first substrate and the solid-state die bonded to the first substrate in an opening in the second substrate. Step 820 may include forming a planarizing material in the opening. Step 830 may include planarizing the substrate structure including the planarizing material to remove at least a portion of the solid-state die handle substrate and a portion of the second substrate. Step 840 may include etching the substrate structure to remove a remainder of the solid-state die handle substrate and a remainder of the second substrate. In an alternative embodiment, steps 830 and 840 may be comprise a single step in which at least a portion, and optionally the entirety of the solid-state die handle substrate and at least a portion of the second substrate are removed. Preferably, removing at least a portion of the solid-state die handle substrate and at least a portion of the second substrate comprises removing the entire solid-state handle substrate and removing the entire silicon wafer 132 of the second substrate 130 while retaining at least a portion of the second silicon oxide layer 134. [0048] FIG.9 is a flow chart illustrating another method of removing a solid-state die handle substrate from a solid-state die according to one or more embodiments. Step 910 may include bonding the solid-state die to a first substrate. Step 920 may include after the bonding of the solid-state die to the first substrate, bonding a waffle wafer to the first substrate such that the solid-state die is located in an opening of the waffle wafer. Step 930 may include forming a planarizing material on the waffle wafer and in the opening such that a height of the planarizing material in the opening that is greater than a height of the solid-state Attorney Docket No.35113-452WO die handle and greater than a height of the waffle wafer. Step 940 may include polishing a surface of the solid-state die handle, a surface of the planarizing material and a surface of the waffle wafer to remove a portion of the solid-state die handle, a portion of the planarizing material, and a portion of the waffle wafer. Step 950 may include performing an etching process to remove a remainder of the solid-state die handle, a remainder of the planarizing material and a remainder of the waffle wafer. [0049] One or more embodiments of the methods illustrated in FIGS.1A-9 may include several alternative designs and/or processing steps. In particular, the type of planarizing material may be varied. Although spin-on glasses, waxes, and photoresists may be used, there are potentially other materials, such as solids that can be reflowed or thick deposited layers. The material, shape, or size of the second substrate 130 (e.g., waffle wafer). The specifics of the bond interface between the first substrate 110 and second substrate 130 may also be varied. [0050] Further, the order in which the method steps are performed may be varied. In addition, the handle grinding, CMP, and RIE etch can be performed differently. This approach is quite versatile, and can support a variety of handle removal approaches and different sorts of handle materials being removed. The material, materials, or stack of material(s) being transferred from the solid-state die 120 to the first substrate 110 may be varied. While FIGS.1A and 1B may depict a single film type, the solid-state die 120 may include a stack of films. The solid-state dies may also be different types of dies, each with a different type of film or stack of films. [0051] The method of FIGS.1A-7B may provide several advantages. A difference between the embodiments of this disclosure and existing solutions is that existing solutions may rely on handle removal either prior to bonding or at the wafer level. This may severely limit what kind of 3D material stacks can be fabricated. Another approach may be to partially dice through a wafer, bond it, and then perform a backside grind. However, this approach may also have some significant issues. The approach may rely on the substrate wafer (e.g., first substrate 110) being of similar size to the partially diced wafer, precluding many atypical solid state materials (e.g., BTO) from consideration in large-scale wafer processing. In addition, the approach may limit the backside removal depth to the precision of a dicing blade cut depth. In addition, it may not protect the delicate wafer surface, which means further processing for precise layer stripping or further handle removal may not be possible. Attorney Docket No.35113-452WO [0052] One or more embodiments of the present disclosure may avoid the challenges of existing methods and provide variety of die/wafer bonding combination while minimizing the risk of damage to either the solid-state die 120 or first substrate 110 (e.g., device wafer). Because the sacrificial second substrate 130 (e.g., waffle wafer) can be customized to be any size, shape, orientation, thickness, or pattern, the second substrate 130 may accommodate a wide variety of die bonding options. [0053] The method may be used, for example, to fabricate three-dimensional (3D) material stacks for use in integrated photonics. Examples include laser-on-a-chip platforms, hybrid modulator or hybrid detector devices, and photonic devices for medical applications. The method may be used to transfer BTO films (e.g., where the active region 121 may include a BTO film) to a device substrate or interposer. The method may also be used for handle substrate removal of source and detector dies. [0054] Example 1: A method of removing a solid-state die handle substrate from a solid- state die, comprising: providing a substrate structure including a first substrate, a second substrate bonded to the first substrate and the solid-state die bonded to the first substrate in an opening in the second substrate; forming a planarizing material in the opening; and removing at least a portion of the solid-state die handle substrate and at least a portion of the second substrate. [0055] Example 2: The method as example 1 describes, wherein the removing at least the portion of the solid-state die handle substrate comprises removing the entire solid-state handle substrate. [0056] Example 3: The method as either of examples 1 or 2 describe, wherein the removing at least the portion of the solid-state die handle substrate comprises: planarizing the substrate structure including the planarizing material to remove the portion of the solid-state die handle substrate and the portion of the second substrate; and etching the substrate structure to remove a remainder of the solid-state die handle substrate. [0057] Example 4: The method as any of examples 1-3 describe, wherein the planarizing of the substrate structure comprises planarizing a surface of the solid-state die handle substrate, a surface of the planarizing material and a surface of the second substrate. [0058] Example 5: The method as any of examples 1-4 describe, wherein the planarizing of the substrate structure further comprises removing a portion of the planarizing material. [0059] Example 6: The method as any of examples 1-5 describe, further comprising removing a remainder of the planarizing material after the etching of the substrate structure. Attorney Docket No.35113-452WO [0060] Example 7: The method as any of examples 1-6 describe, wherein the planarizing of the substrate structure comprises at least one of chemical-mechanical polishing (CMP) of the substrate structure or grinding the substrate structure. [0061] Example 8: The method as any of examples 1-7 describe, wherein the etching of the substrate structure comprises performing a selective reactive ion etching of the substrate structure. [0062] Example 9: The method as any of examples 1-8 describe, wherein the forming of the planarizing material comprises forming a layer including one of spin-on glass, photoresist, or wax in the opening and on an upper surface of the second substrate. [0063] Example 10: The method as any of examples 1-9 describe, wherein the forming of the planarizing material comprises forming the planarizing material to have a height in the opening that is greater than a height of the solid-state die handle substrate and greater than a height of the second substrate. [0064] Example 11: The method as any of examples 1-10 describe, wherein the providing of the substrate structure comprises: bonding the solid-state die to the first substrate; and after the bonding of the solid-state die to the first substrate, bonding the second substrate to the first substrate such that the solid-state die is located in the opening in the second substrate. [0065] Example 12: The method as any of examples 1-11 describe, wherein the providing of the substrate structure comprises: bonding the second substrate to the first substrate; and after the bonding of the second substrate to the first substrate, bonding the solid-state die to the first substrate such that the solid-state die is located in the opening in the second substrate. [0066] Example 13: The method as any of examples 1-12 describe, wherein: the solid- state die comprises a photonic die containing an interferometer including a barium titanate layer located over the handle substrate; the first substrate comprises a first silicon wafer containing a first silicon oxide layer; and the second substrate comprises a second silicon wafer containing a second silicon oxide layer and the opening extending through the second silicon wafer and the second silicon oxide layer. [0067] Example 14: The method as any of examples 1-13 describe, further comprising bonding the first silicon oxide layer to the second silicon oxide layer. [0068] Example 15: The method as any of examples 1-14 describe, wherein the removing at least the portion of the solid-state die handle substrate and at least the portion of the second substrate comprises removing the entire solid-state handle substrate and removing the entire second silicon wafer while retaining at least a portion of the second silicon oxide layer. Attorney Docket No.35113-452WO [0069] Example 16: A method of removing a solid-state die handle substrate from a solid-state die, the method comprising: bonding the solid-state die to a first substrate; and after the bonding of the solid-state die to the first substrate, bonding a wafer to the first substrate such that the solid-state die is located in an opening of the wafer; forming a planarizing material on the wafer and in the opening such that a height of the planarizing material in the opening that is greater than a height of the solid-state die handle substrate and greater than a height of the wafer; polishing a surface of the solid-state die handle substrate, a surface of the planarizing material and a surface of the wafer to remove a portion of the solid- state die handle substrate, a portion of the planarizing material, and a portion of the wafer; and performing an etching process to remove a remainder of the solid-state die handle substrate, a remainder of the planarizing material and a remainder of the wafer. [0070] The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

Attorney Docket No.35113-452WO CLAIMS 1. A method of removing a solid-state die handle substrate from a solid-state die, comprising: providing a substrate structure including a first substrate, a second substrate bonded to the first substrate and the solid-state die bonded to the first substrate in an opening in the second substrate; forming a planarizing material in the opening; and removing at least a portion of the solid-state die handle substrate and at least a portion of the second substrate. 2. The method of claim 1, wherein the removing at least the portion of the solid-state die handle substrate comprises removing the entire solid-state handle substrate. 3. The method of claim 2, wherein the removing at least the portion of the solid-state die handle substrate comprises: planarizing the substrate structure including the planarizing material to remove the portion of the solid-state die handle substrate and the portion of the second substrate; and etching the substrate structure to remove a remainder of the solid-state die handle substrate. 4. The method of claim 3, wherein the planarizing of the substrate structure comprises planarizing a surface of the solid-state die handle substrate, a surface of the planarizing material and a surface of the second substrate. 5. The method of claim 4, wherein the planarizing of the substrate structure further comprises removing a portion of the planarizing material. 6. The method of claim 5, further comprising removing a remainder of the planarizing material after the etching of the substrate structure. Attorney Docket No.35113-452WO 7. The method of claim 3, wherein the planarizing of the substrate structure comprises at least one of chemical-mechanical polishing (CMP) of the substrate structure or grinding the substrate structure. 8. The method of claim 3, wherein the etching of the substrate structure comprises performing a selective reactive ion etching of the substrate structure. 9. The method of claim 1, wherein the forming of the planarizing material comprises forming a layer including one of spin-on glass, photoresist, or wax in the opening and on an upper surface of the second substrate. 10. The method of claim 1, wherein the forming of the planarizing material comprises forming the planarizing material to have a height in the opening that is greater than a height of the solid-state die handle substrate and greater than a height of the second substrate. 11. The method of claim 1, wherein the providing of the substrate structure comprises: bonding the solid-state die to the first substrate; and after the bonding of the solid-state die to the first substrate, bonding the second substrate to the first substrate such that the solid-state die is located in the opening in the second substrate. 12. The method of claim 1, wherein the providing of the substrate structure comprises: bonding the second substrate to the first substrate; and after the bonding of the second substrate to the first substrate, bonding the solid-state die to the first substrate such that the solid-state die is located in the opening in the second substrate. 13. The method of claim 1, wherein: the solid-state die comprises a photonic die containing an interferometer including a barium titanate layer located over the handle substrate; the first substrate comprises a first silicon wafer containing a first silicon oxide layer; and Attorney Docket No.35113-452WO the second substrate comprises a second silicon wafer containing a second silicon oxide layer and the opening extending through the second silicon wafer and the second silicon oxide layer. 14. The method of claim 13, further comprising bonding the first silicon oxide layer to the second silicon oxide layer. ^ 15. The method of claim 14, wherein the removing at least the portion of the solid-state die handle substrate and at least the portion of the second substrate comprises removing the entire solid-state handle substrate and removing the entire second silicon wafer while retaining at least a portion of the second silicon oxide layer. ^ 16. A method of removing a solid-state die handle substrate from a solid-state die, the method comprising: bonding the solid-state die to a first substrate; and after the bonding of the solid-state die to the first substrate, bonding a wafer to the first substrate such that the solid-state die is located in an opening of the wafer; forming a planarizing material on the wafer and in the opening such that a height of the planarizing material in the opening that is greater than a height of the solid-state die handle substrate and greater than a height of the wafer; polishing a surface of the solid-state die handle substrate, a surface of the planarizing material and a surface of the wafer to remove a portion of the solid-state die handle substrate, a portion of the planarizing material, and a portion of the wafer; and performing an etching process to remove a remainder of the solid-state die handle substrate, a remainder of the planarizing material and a remainder of the wafer.