EP4609019A2 - Low temperature epitaxy of polar semiconductors - Google Patents

Low temperature epitaxy of polar semiconductors

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Publication number
EP4609019A2
EP4609019A2 EP23883642.3A EP23883642A EP4609019A2 EP 4609019 A2 EP4609019 A2 EP 4609019A2 EP 23883642 A EP23883642 A EP 23883642A EP 4609019 A2 EP4609019 A2 EP 4609019A2
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EP
European Patent Office
Prior art keywords
semiconductor layer
layer
heterostructure
sputtered
polar semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP23883642.3A
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German (de)
French (fr)
Inventor
Ping Wang
Ding Wang
Zetian Mi
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University of Michigan System
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University of Michigan System
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Publication date
Application filed by University of Michigan System filed Critical University of Michigan System
Publication of EP4609019A2 publication Critical patent/EP4609019A2/en
Pending legal-status Critical Current

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Definitions

  • the disclosure relates generally to epitaxial growth of semiconductors.
  • Ill-nitride semiconductors e.g., InN, GaN, AIN and their heterostructures, nanostructures, and alloying with group II IB elements such as Sc, have attracted growing interest and facilitated a wealth of applications in optoelectronics, electronics, acoustics, green energy, and quantum devices and systems.
  • CMOS complementary-metal-oxide-semiconductor
  • MBE molecular beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • a universal adsorption-migration-epitaxy thermal dynamic process is employed at the growth front in both methods, during which the temperature of the substrate during growth and the element ratio, i.e., 111/V ratio, are used for sufficient adatom migration.
  • the growth temperature of Ill-nitrides in both methods has been limited to above 400 °C, e.g., about 500 °C for InN, about 800 °C for GaN, and about 1000 °C for AIN.
  • These high growth temperatures are not CMOS compatible, preventing the seamless integration of Ill-nitride materials and devices with the advanced processing techniques and mainstream semiconductor technology like CMOS.
  • Other growth techniques such as atomic layer deposition, sputtering, and pulsed laser deposition, generally yield polycrystalline, or even amorphous materials with very limited quality.
  • a method of forming a heterostructure includes providing a substrate, forming a template layer of the heterostructure such that the template layer is supported by the substrate, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the template layer.
  • the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline.
  • the non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius.
  • a method of fabricating a device includes forming a metal structure of a complementary metal-oxide-semiconductor (CMOS) component of the device, the metal structure being supported by a substrate, and, after forming the metal structure, implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of a heterostructure of the device, the polar semiconductor layer being supported by the substrate.
  • CMOS complementary metal-oxide-semiconductor
  • the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline.
  • a device in accordance with yet still another aspect of the disclosure, includes a substrate, a complementary metal-oxide-semiconductor (CMOS) component supported by a substrate, the CMOS transistor including a structure, and a polar semiconductor layer supported by the structure.
  • CMOS complementary metal-oxide-semiconductor
  • the polar semiconductor layer has a single-crystalline, wurtzite crystal structure.
  • a method of forming a heterostructure includes providing a substrate, forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer including aluminum, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the metal layer.
  • the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline.
  • Forming the metal layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal layer and implementing the non-sputtered, epitaxial growth procedure.
  • a method of forming a heterostructure includes providing a substrate, forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer including molybdenum, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the metal layer.
  • the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline. Forming the metal layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal layer and implementing the non-sputtered, epitaxial growth procedure.
  • the devices and/or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features.
  • the non-sputtered, epitaxial growth procedure is implemented in nitrogen-rich conditions. Forming the template layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the template layer and implementing the non-sputtered, epitaxial growth procedure. Forming the template layer includes implementing a surface treatment procedure to remove oxide from a surface of the template layer.
  • the growth temperature is less than about 300 degrees Celsius.
  • the growth temperature is greater than about 20 degrees Celsius.
  • the growth temperature falls in a range from about 20 degrees Celsius to about 100 degrees Celsius.
  • the polar semiconductor layer includes a Ill-nitride material or alloy thereof.
  • the polar semiconductor layer includes AIN or an alloy thereof.
  • the template layer includes a metal compatible with complementary metal-oxide-semiconductor (CMOS) fabrication.
  • CMOS complementary metal-oxide-semiconductor
  • the template layer includes GaN.
  • the polar semiconductor layer includes AIN or an alloy thereof.
  • the non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius.
  • the non-sputtered, epitaxial growth procedure is implemented in nitrogen-rich conditions.
  • the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is configured such that the polar semiconductor layer is in contact with the metal structure.
  • Forming the metal structure and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal structure and implementing the non-sputtered, epitaxial growth procedure.
  • Forming the metal structure includes implementing a surface treatment procedure to remove oxide from a surface of the metal structure.
  • the method further includes forming a template layer of the heterostructure before implementing the non-sputtered, epitaxial growth procedure such that the polar semiconductor layer is in contact with the template layer.
  • the structure includes metal.
  • the polar semiconductor layer includes multiple columnar domains. A surface of the polar semiconductor layer in contact with the structure has an atomically smooth surface.
  • the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is implemented at a growth temperature compatible with complementary metal-oxide-semiconductor (CMOS) fabrication.
  • CMOS complementary metal-oxide-semiconductor
  • Figure 1 depicts low temperature epitaxy of ScAIN on GaN template, including (a) a schematic view of a heterostructure having a Ill-nitride-based layer (e.g., a ScAIN film) grown on a GaN template in accordance with one example, (b) an SEM image of the example heterostructure, (c) a graphical plot of (0002) plane XRD 20-co scans of the example heterostructure, and (d) a graphical plot of (0002) and (1012) planes XRC FWHM of Sco.i8Alo.82N films grown on GaN templates.
  • a schematic view of a heterostructure having a Ill-nitride-based layer e.g., a ScAIN film grown on a GaN template in accordance with one example
  • an SEM image of the example heterostructure e.g., a ScAIN film
  • a graphical plot of (0002) plane XRD 20-co scans of the example heterostructure e.g.,
  • Figure 2 depicts microstructure analysis of Sco.i8Alo.82N films grown at different temperatures on a GaN template, including (a) a HAADF-STEM image of the ScAIN/GaN interface of a ScAIN example grown at 700 °C, (b) an ABF-STEM image of the ScAIN region for the ScAIN example grown at 700 °C, (c) a HAADF-STEM image of the ScAIN/GaN interface of a ScAIN example grown at 100 °C, and (d) an ABF-STEM image of the ScAIN region for the ScAIN example grown at 100 °C, in which shaded balls for the Sc/AI and N atoms are embedded in parts b and d to better visualize the atomic stacking sequence.
  • Figure 3 depicts low temperature epitaxy of a heterostructure having a ScAIN film on an Al/Si template (e.g., Al template in combination with a Si substrate) in accordance with one example, including (a) a schematic view of the example heterostructure, and (b) an SEM image of the example heterostructure, and (c, d) graphical plots of (0002) plane XRD 20-co scans of example heterostructures having ScAIN grown on Al/Si templates with varying Sc contents and varying film thicknesses.
  • Al/Si template e.g., Al template in combination with a Si substrate
  • Figure 4 depicts microstructural analysis of an example heterostructure having a Sco.2Alo.8N layer grown at 100 °C on Al/Si template, including (a) a cross-sectional HAADF- STEM image of the ScAIN/AI/Si heterostructure, (b, c) HAADF-STEM images of the Al/Si and ScAIN/AI interfaces, and (d) an ABF-STEM image acquired from the ScAIN region, in which shaded balls for the Sc/AI and N atoms are embedded in part (d) to better visualize the atomic stacking sequence.
  • RMS 0.69 nm
  • Figure 6 is a flow diagram of a method of fabricating a device with a heterostructure having a polar semiconductor layer grown at a low temperature in accordance with one example.
  • Figure 1 1 depicts example high power AI(Ga)N p-i-n diodes, in which the p- and n- AI(Ga) layers may be grown under low temperature or high temperature, while an i-AI(Ga)N layer is grown at low temperature, and in which the low temperature i-AI(Ga)N layer leads to an improved breakdown voltage of the diodes.
  • Figure 12 depicts example high power AI(Ga)N Schottky diodes, in which n-AI(Ga) layers may be grown under low temperature or high temperature, while an n-AI(Ga)N layer is grown at low temperature, and in which the low temperature n-AI(Ga)N layer leads to an improved breakdown voltage of the diodes.
  • Figure 13 depicts example high power AI(Ga)N bipolar transistors, in which n-and p- AI(Ga) layers may be grown under low temperature, which leads to an improved breakdown voltage of the transistors.
  • Figure 15 depicts example deep ultraviolet LED structures based on low temperature epitaxially grown semiconductor heterostructures: (a) normal AI(Ga)N-based DUV-LED structure grown on a low temperature grown AI(Ga)N buffer, and (b) low temperature grown AI(Ga)N-based DUV-LED structure, which is useful in connection with some substrates or applications.
  • Figure 16 depicts an example self-powered photodetector using an low temperature epitaxially grown polar semiconductor AI(Ga,ln,Sc)N as the light absorption layer.
  • the disclosed methods and devices exploit a previously unexplored growth regime for achieving crystalline nitride semiconductors is the low temperature growth region, i.e., with growth temperatures less than 400 °C that are CMOS compatible.
  • This low temperature growth has several potential advantages: i) it releases the constraints on the processing conditions before and after film deposition, providing better compatibility with different material platforms and semiconductor technologies like silicon CMOS technology; ii) in the high temperature growth regime, adatom migration leads to “jump over” effect close to surface imperfections like nano-gaps/dots, while low temperature growth provides better surface coverage, fast coalescence, and uniform thickness; iii) nucleation process is easier at low temperature, favoring hetero-epitaxy of Ill-nitride semiconductors on different materials like metal substrates; iv) following ii) and iii), this kind of “on-site” growth enabled by low temperature, is immune to surface thermal dynamics, thus can be done in a very wide growth window, i.
  • Examples of low temperature, CMOS compatible epitaxy of polar nitride semiconductors are described. Epitaxial growth of single-crystalline wurtzite phase ScAIN, AIN, and AIGaN with high crystal quality and atomically sharp interface has been demonstrated in a wide growth temperature range (from about 700 to about 20 °C), which had been previously unattainable. An on-site growth mechanism is presented to describe the epitaxy of crystalline material under such low growth temperatures, which is explained by a polar surface controlled adsorption-epitaxy process, compared to the conventional adsorption-migration-epitaxy process for epitaxy at high temperatures.
  • the disclosed methods and devices establish that low temperature growth of Ill-nitride semiconductors can maintain the wurtzite crystal structure and provide reasonable crystal quality, interface, and chemical composition control that are comparable to conventional high temperature growth, but with better compatibility with different substrates and processing techniques.
  • Examples of ScAIN thin films with various thicknesses and Sc contents and AIN films have been grown on GaN and metal substrates at low temperatures ( ⁇ 100 °C).
  • the ScAIN films exhibit good wurtzite atomic stacking sequence with sharp interface, and atomically smooth surface on both GaN and metal (Al, Mo) substrates. Those results open the avenue for growing high quality Ill-nitride semiconductors at low temperatures toward advanced hybrid and emerging integrated circuits across different technology and material platforms.
  • Examples described herein were grown utilizing a Veeco GENxplor MBE system, equipped with dual filament SUMO Knudsen cells for Al (purity 6N5) and Ga sources (purity 7N), a high-temperature Knudsen cell for Sc source (purity 5N), and a Veeco Unibulb radio frequency (RF) plasma source.
  • the N source was operated with a N 2 gas (purity 6N) flow of 0.35 seem and RF power of 350 W. While the total metal flux was controlled to maintain a N- rich growth conditions with a II 1/V ratio of about 0.8.
  • the GaN templates and Si substrates were cleaned by acetone, methanol, and deionized water prior to loading into the MBE system. And then degassed at 200 and 600 °C for 2 h in the MBE load-lock chamber and preparation chamber, respectively.
  • Examples involving low temperature epitaxy of ScAIN on GaN were grown on GaN templates, as shown in Figure 1 , part a.
  • the GaN template may constitute a layer or structure of a CMOS component of a device.
  • 100-nm-thick Si-doped n + -GaN was firstly grown on the GaN template to obtain an atomically smooth and clean surface. After that, the excess Ga adatoms on the surface were reevaporated, and in situ surface nitridation was further performed to obtain a Ga-free surface. Subsequently, 100-nm-thick ScAIN was grown with various growth temperatures.
  • Figure 1 part b, displays the typical scanning electron microscope image of the ScAIN/GaN films grown at 100 °C, showing a granular surface, which is consistent with previous reports on ScAIN grown under N-rich conditions. Meanwhile, it was found that the surface morphology is insensitive with growth temperature. All examples showed similar granular surface, while the grain size is slightly larger at higher growth temperatures.
  • Figure 1 shows the (0002) plane XRD 20-co scans for the ScAIN films grown at various temperatures. All examples possess a clear and strong characteristic diffraction peak at 36° for wurtzite ScAIN. Additionally, in the long range scans (20-100°), no other peaks originated from either cubic phase or misoriented structures were observed, indicating a single-crystalline wurtzite crystal structure for those ScAIN films. To the applicant's knowledge, this is the first ever demonstration of epitaxial growth of single-crystalline wurtzite nitride semiconductors at such unexplored low growth temperature (even lower than room temperature). For comparison, previous reports always showed polycrystalline structure when growing AIN at room temperature.
  • HAADF high-angle annular dark field
  • ABSF annular bright field
  • ABAB wurtzite atomic stacking sequence
  • the lattice-polarity was checked using ABF-STEM, as shown in Figure 2, parts b and d.
  • the darkest contrasts correspond to the heaviest atoms. Therefore, the process was capable of configuring the atomic stacking sequence of Sc/AI and N atoms, which are embedded in Figure 2, parts b and d. Comparing the atomic model of wurtzite crystal structure with the experimental results, one can easily confirm that the initial metal (M)-polar lattice in the GaN template was inherited perfectly in the ScAIN films, i.e., the ScAIN films grown at 700 and 100 °C have a M-polar lattice.
  • M initial metal
  • the ScAIN Due to the N-rich growth conditions and the low growth temperature, the ScAIN shows a columnar-like growth, in which slightly mis-orientated (less than 1 °) domains coexist. However, no inverted domains with nitrogen (N)-polar were observed in the ScAIN films, suggesting all films have a high uniform M-polar lattice, which is in contrast to the polycrystalline or mixed phase material deposited by using sputtering at the same temperature range.
  • nitride alloys including highly reactive atoms such as Sc, Al etc.
  • the epitaxial growth of nitride alloys including highly reactive atoms, such as Sc, Al etc. is not limited to the conventional narrow growth window, i.e., relatively high growth temperatures.
  • Single-crystalline wurtzite phase nitrides can be also grown or achieved at low growth temperatures without significantly degrading the crystal quality.
  • the strong polarization of wurtzite nitrides provides a strong electrostatic potential fluctuation on the surface. Except for the polar lattice induced surface potential, the kink and vacancy sites of the lattice can generate additional electrostatic potential fluctuation on the surface.
  • adatoms have enough energy to migrate to a site with the lowest energy and join the growth. Generally, the diffusion length is hundreds of nanometers to tens of micrometers. Although at low temperature the adatoms could not achieve a long-range diffusion, due to the lattice continuity, there are still low potential sites near the atoms landing site, which are within the short-range diffusion length.
  • Nitride alloys including high reactive atoms, such as Al and Sc were grown under low temperatures while maintaining the single-crystalline wurtzite phase. This phenomenon suggests that the bonding strength also contributes to the proposed on-site growth mechanism, i.e., a larger bonding strength is favorable for the low temperature epitaxy. Moreover, a clean and crystalline surface is useful to avoid misoriented nucleation formation at the beginning and would be useful to initialize such growth at low temperature. This achievement provides a viable path for the fully epitaxial integration of Ill-nitride architectures on special application scenarios, such as nitrides grown on CMOS compatible metal electrodes.
  • Sco.3Alo.7N layers with a thickness of 30, 100, and 150 nm were grown on the same Al/Si template. Similar diffraction peaks for the wurtzite phase were clearly observed in these three samples, as shown in Figure 3, part d. Due to the lattice mismatch induced in-plane strain between Al and ScAIN, cracks were observed on the ScAIN surface with a thickness beyond 200 nm.
  • FIG. 4 presents the HAADF- STEM image of the Al/Si interface, showing a clear cubic crystal structure for the MBE grown Al template.
  • the ScAIN/AI interface is shown in Figure 4, part c.
  • a clear lattice transition from cubic Al to wurtzite ScAIN is observed; the interface thickness is only a few monolayers.
  • the ScAIN layer has a highly ordered wurtzite stacking sequence (ABABAB). During the STEM measurements, the in-plane rotation for the domains is less than 1 °.
  • Figure 5 part b displays a long range XRD 20-co scan of the AIN/AI/Si heterostructure. Only the characteristic diffraction peaks for AIN ⁇ 0002> planes are observed, confirming a single-crystalline wurtzite crystal structure of this AIN film.
  • Figure 5, part c shows the HAADF-STEM image and the corresponding ABF-STEM image captured from the near surface region.
  • the well aligned wurtzite phase atomic stacking sequence (ABABAB) is well maintained up to the top surface, indicating that the proposed low temperature on-site growth mechanism does not degenerate the crystal structure.
  • the stacking sequence for Al and N atoms has been labeled with blue and red balls, respectively, in the ABF-STEM image. Comparing with the crystal structure of wurtzite AIN, a uniform M-polar lattice is confirmed for the as-grown AIN on Al/Si template. Furthermore, epitaxial growth of AIGaN can also be achieved at low growth temperatures ( ⁇ 100 °C). The low temperature growth of AIN is thus not limited to the metal substrates (Al and Mo). Low temperature growth can be also realized on either GaN or AIN templates. These achievements provide for growing AIN as well as AIGaN alloys under a low temperature, which can be used not only as an in-situ high-quality passivation layer but also for the hybrid integration with other material platforms.
  • Figure 6 depicts a method 600 of fabricating a heterostructure having a singlecrystalline polar semiconductor layer grown at a low temperature in accordance with one example.
  • the method 600 is configured such that a Ill-nitride-based or other polar semiconductor layer may be grown on a metal or other template at a low temperature, e.g., sufficiently low for compatibility with CMOS fabrication.
  • the polar semiconductor layer may or may not exhibit piezoelectric or ferroelectric behavior.
  • the method 600 may be used to fabricate the examples of devices, heterostructures, and other structures having polar semiconductor films or layers as described herein, and/or other devices, heterostructures or structures.
  • the method 600 may begin with an act 602 in which a substrate is prepared and/or otherwise provided.
  • the act 602 includes providing a silicon substrate in an act 604.
  • the silicon substrate may have a (111) orientation.
  • the substrate may be patterned or otherwise processed to configure the substrate to reduce defect formation in subsequently grown layers of the heterostructure and/or otherwise improve material quality therein. Such processing may also facilitate the formation of a different regions of the heterostructure.
  • substrate materials including, for instance, sapphire, bulk GaN, bulk AIN, or other semiconductor material. Still other materials may be used, including, for instance, silicon carbide.
  • a metal substrate may be used.
  • the metal substrate may be composed of, or otherwise include, Al, Pt, and/or Mo.
  • the substrate may be cleaned in an act 606.
  • a native or other oxide layer may be removed from a substrate surface in an act 608.
  • the oxide removal may include multiple steps, including, for instance, an etch step and an annealing step.
  • the substrate thus may or may not have a uniform composition.
  • the substrate may be a uniform or composite structure. Any number of layers or structures may be deposited on the substrate prior to the implementation of the acts described below.
  • the method 600 may include an act 610, in which one or more template or other layers are formed or otherwise provided.
  • the template layer is composed of, or otherwise includes, a metal such as Al or Mo.
  • the template layer is composed of, or otherwise includes, a Ill-nitride layer (e.g., GaN) or other semiconductor layer.
  • the template layer is supported by the substrate.
  • the template layer is in contact with the substrate.
  • one or more buffer or other layers or structures are disposed between the template layer and the substrate.
  • the act 610 is part of a CMOS fabrication procedure directed to fabricating a CMOS component (e.g., CMOS transistor, diode, etc.) of the device.
  • CMOS component e.g., CMOS transistor, diode, etc.
  • a number of layers or other structures may be formed during the CMOS fabrication procedure, including, for instance, various types of electrodes, contacts, and other structures.
  • one of the structures of the CMOS component may be configured or act as a template layer.
  • the act 610 includes an act 612 in which the template layer(s) are deposited.
  • the template layer(s) are patterned in an act 614.
  • the act 610 may include the deposition or other formation of one or more other metal layers or structures.
  • a bottom contact may be formed in an act 616.
  • the act 616 may be implemented in parallel with (e.g., as part of) the act 612.
  • the number and other characteristics of the metal layers or structures may vary in accordance with the configuration of the device (e.g., the number of terminals).
  • the metal layers or structures may be part of a CMOS component of the device being fabricated.
  • the metal layer or structure may be an electrode of a CMOS transistor, CMOS diode, or other CMOS component.
  • the metal layer or structure is formed in a chamber also used for implementation of an epitaxial growth procedure to form a polar semiconductor layer. That is, the same chamber is used to form the metal layer or structure and grow the polar semiconductor layer. As a result, the metal layer (or other layer or portion of a heterostructure being formed) is not exposed to an ambient between formation of the metal structure and implementation of the non-sputtered, epitaxial growth procedure.
  • the method 600 includes an act 618 in which a surface treatment procedure is implemented to remove oxide from a surface of the metal layer.
  • the act 618 includes annealing the polycrystalline metal layer in a vacuum in an act 620.
  • the temperature of the annealing may vary, e.g., with the composition of the metal layer and/or other structures of the device (e.g., CMOS component structures).
  • Mo0 3 has a relatively low melting point (795 °C), in which case annealing above the melting point, e.g., at about 900 °C, may be used.
  • the annealing may also improve the surface roughness of the metal layer.
  • the oxide may be removed in additional or alternative ways to achieve a highly ordered atomically smooth surface.
  • the oxide may be removed via an etching procedure using, e.g., an acid solution, such as hydrochloric acid (HCI) or buffered hydrofluoric acid (BHF).
  • HCI hydrochloric acid
  • BHF buffered hydrofluoric acid
  • the singlecrystalline polar semiconductor layer may be composed of, or otherwise includes, a Ill- nitride-based material (e.g., an alloy of a Ill-nitride material).
  • polar semiconductors e.g., ZnO
  • ZnO polar semiconductors
  • the surface treatment of the act 618 may be implemented before (e.g., in preparation for) implementing the epitaxial growth procedure in which a wurtzite structure is formed.
  • the wurtzite structure may thus be formed on the metal layer.
  • the metal layer may thus act as a template for the wurtzite structure and/or other elements of the heterostructure.
  • the act 612 may include an act 628 in which the single-crystalline semiconductor layer is grown in a chamber in which the template layer is formed.
  • the same chamber may be used to form a metal template layer (e.g., Mo or Al template layer) and grow the polar semiconductor layer.
  • the substrate may remain within, e.g., is not removed from, the epitaxial growth chamber between forming the metal layer and growing the single-crystalline semiconductor layer. Exposure to the ambient is thus avoided.
  • the resulting wurtzite structure is monocrystalline.
  • the resulting wurtzite structure is monocrystalline to a degree not realizable via, for instance, sputtering-based procedures for forming ScAIN layers.
  • Such procedures are only capable of producing structures with x-ray diffraction rocking curve line widths on the order of a few degrees at best.
  • the structures grown by the disclosed methods exhibit x-ray diffraction rocking curve line widths on the order of a few hundred arc-seconds or less, well over an order of magnitude less.
  • leakage current paths may be minimized or otherwise sufficiently reduced so that, in ferroelectric cases, the resulting wurtzite structure has a suitably high breakdown field strength level, e.g., sufficiently greater than the ferroelectric coercive field strength.
  • Differences in crystal quality evidenced via x-ray diffraction rocking curve line widths may be used to distinguish between monocrystalline (or single-crystalline) and polycrystalline structures.
  • polycrystalline refers to structures having x-ray diffraction rocking curve line widths on the order of a few degrees or higher.
  • monocrystalline or “single-crystalline” refer to structures having x- ray diffraction rocking curve line widths at least one order of magnitude lower than the order of a few degrees.
  • crystal quality may be used to distinguish between single-crystalline (or monocrystalline) and polycrystalline structures.
  • polycrystalline refers to structures having multiple grains.
  • monocrystalline or “single crystalline” may refer to structures having multiple domains.
  • Control of the flux ratio between metal and nitrogen sources may be useful for improving the material quality of the Ill-nitride-based or other polar semiconductor layer.
  • the N-rich growth conditions may be useful in connection with the growth of ScAIN to avoid Sc-AI intermetallic, Sc 3 AIN perovskite phase formation, and/or other defects.
  • the single-crystalline polar semiconductor layer may then be annealed in an act 632.
  • the annealing may be implemented at a temperature greater than the growth temperature.
  • the annealing temperature falls in a range from about 700 Celsius to about 1500 degrees Celsius.
  • the polar semiconductor layer is not annealed at such high temperatures to remain compatible with CMOS components of the device being fabricated.
  • Such post-growth high-temperature annealing of ScAIN may be performed in-situ in the same growth chamber (e.g., the same MBE chamber) in an act 634. In other cases, the annealing is performed ex-situ in a chamber directed to annealing procedures.
  • the annealing process may be implemented under high vacuum in an act 636 (e.g., in-situ in the growth chamber). In other cases, the annealing may be implemented either with nitrogen plasma radiation or under nitrogen gas flow in an act 638.
  • the method 600 may include an act 640 in which one or more layers (e.g., semiconductor layers) are formed after growth of the wurtzite structure.
  • the act 640 includes an act 644 in which one or more metal or other conductive layers or structures are formed.
  • a metal layer may be deposited on the polar semiconductor layer, in which case the polar semiconductor layer is disposed between, and in contact with, two metal layers.
  • the layers or structures may be deposited or otherwise formed.
  • the conductive structure is configured as an upper or top contact.
  • the conductive structure may be a gate.
  • the method 600 includes an act 646, in which the substrate is removed.
  • the substrate may be partially or fully removed. With the substrate fully removed, the heterostructure becomes freestanding.
  • the act 646 includes implementation of an etching procedure, such as a wet or dry etch procedure. Alternatively or additionally, the substrate is removed mechanically. The manner in which the substrate is removed may thus vary accordingly.
  • the method 600 may include fewer, additional, or alternative acts.
  • one or more acts may be directed to forming other structures or regions of the device that includes the heterostructure.
  • the nature of the regions or structures may vary in accordance with the nature of the device.
  • the method 600 does not include an act 618 in which an oxide layer is removed from a metal layer or structure because, for instance, the heterostructure is not exposed to the ambient between formation of the metal layer and growth of the polar semiconductor layer.
  • the order of the acts of the method 600 may differ from the example shown in Figure 6.
  • contacts and/or other structures formed in the act 610 may be implemented after the growth of the ferroelectric layer.
  • a wide variety of devices may be fabricated by the method 600 of Figure 6, and/or another method of fabricating a heterostructure having a polar semiconductor layer as described herein.
  • the ferroelectric ScAIN or other alloy of a Ill-nitride material may be useful in various types of nonvolatile memory devices (e.g., FeRAM, FeFET, FTJ, and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe- HEMT, Fe-capacitor, and SAW devices), various types of photodetection, photovoltaic and optoelectronic devices (e.g., self-driven photodetector and solar cell devices), and various homojunction devices (e.g., devices that use a laterally distributed charge plate to tune the Fermi level in adjacent layers).
  • Still other types of devices may be fabricated, including, for instance, FE-based thin-film bulk acoustic wave resonators (FBAR) devices.
  • FBAR FE-
  • the device includes a CMOS component (e.g., a CMOS transistor or diode).
  • CMOS component may include a structure that supports the polar semiconductor layer.
  • Figure 7 depicts a number of example heterostructures having a polar semiconductor layer grown via low temperature epitaxy.
  • multilayer nitride heterostructures are grown on metal electrodes, but Si or other substrates/templates may be used in other cases (e.g., in examples involving multi-mode, high-frequency, and low-loss acoustic resonators and filters, memory electronics, MEMS/NEMS, as well as various flexible nitride devices).
  • the metal electrodes serve as a template for the polar semiconductor layer and may correspond with a layer or structure of a CMOS component of a device.
  • the quasi three-dimensional growth at low temperatures described herein releases the stress in the multilayer structures.
  • the three example heterostructures include an AIGaN/AIN heterostructure bilayer grown on an Al/Si template, a ScAIN/AIN bilayer heterostructure grown on a Mo/Si template, and an AIN/ScAIN/AIN trilayer heterostructure grown on a Mo/Si template.
  • Parts d-f of Figure 7 show the surface morphology of the three multilayer structures grown at 100 degrees Celsius. No obvious cracks were observed on any of the examples, indicating that the stress between each layer has been released. On the other hand, no other high energy electron diffraction (RHEED) patterns were observed at the end of growth for all of the examples, except for the RHEED patterns for a wurtzite structure. This indicates that all of the low temperature grown multilayers maintain a well-defined wurtzite crystal structure, which was also confirmed by XRD measurements. Therefore, the low temperature epitaxy method is useful for the growth of monocrystalline multilayer nitride heterostructures.
  • RHEED high energy electron diffraction
  • the ScAIN layer may be made ferroelectric. Therefore, the polarity of the ScAIN layer can be poled (changing from metal polar to nitrogen polar, vice versa) while the polarity of the AIN layer remains the same.
  • Multi-layer structures may also include many stacks of AIN/ScAIN, metal/ScAIN, metal/AIN, GaN/AIN, GaN/ScAIN, 2D TMD/ScAIN, or other periodic structures including rare-earth elements doped Ill-nitrides.
  • the rare-earth elements doped Ill-nitrides are designed to be ferroelectric, but in other cases, enhanced piezoelectric and/or optical properties may be utilized in the multi-layer structures.
  • thicknesses of the multi-layer structures may vary. For instance, for acoustic filters/resonators related applications, the thickness may fall in a range around 100 nm, whereas the thicknesses may be on the nanometer scale for memory and/or quantum related applications.
  • Figure 8 depicts examples of (a) Ga-polar and (b) N-polar AI(Ga,ln)N/GaN high electron mobility transistor (HEMT) devices having a polar semiconductor layer grown using a low growth temperature.
  • the polar semiconductor layer is composed of AIN.
  • the AIN layer may be grown in situ (e.g., in the same growth chamber used to grow the underlying layer) as described herein.
  • the polar semiconductor layer is configured as a high-k gate dielectric layer of the HEMT devices.
  • Figure 9 depicts examples of transistor structures using a low temperature grown polar semiconductor layer as a dielectric layer.
  • the polar semiconductor layer is composed of AIN or ScAIN.
  • the dielectric layer is disposed adjacent a channel layer composed of, or otherwise including, a two-dimensional (2D) material, such as hexagonal BN (hBN).
  • 2D hexagonal BN
  • hBN hexagonal BN
  • Figure 10 depicts an example of an AIN-based transistor device having one or more low temperature grown AIN-based layers.
  • the transistor includes source and drain contacts spaced from an n-type AIN body region by respective polarization-graded AIGaN layers.
  • Each AIGaN layer may be grown as described herein.
  • Figure 11 depicts an example of a high power AI(Ga)N P-l-N diode having one or more low temperature grown AIN-based layers.
  • p- and n- AI(Ga) layers can be grown under low temperature or high temperature, while the intrinsic (i)-AI(Ga)N layer is grown at low temperature. Growth of the i-AI(Ga)N layer at low temperature as described herein helps improve the breakdown voltage of the diode for the reasons set forth above.
  • Figure 13 depicts an example of a high power AI(Ga)N bipolar transistor having a number of low temperature grown AIN-based layers.
  • the device includes n- and p-type AI(Ga) layers that are grown at low temperature, which will improve the breakdown voltage of the transistor for the reasons set forth above.
  • Figure 14 depicts an example of a ferroelectric-transistor random-access memory cell device having a low temperature grown AIN-based layer.
  • the device includes a capacitor with a low temperature grown ferroelectric ScAIN layer disposed between two metal layers.
  • the device also includes a silicon or GaN based write-read transistor.
  • Figure 15 depicts examples of deep ultraviolet LED devices having one or more low temperature epitaxially grown Ill-nitride layers.
  • the example shown in part a of Figure 15 is a AI(Ga)N-based DUV-LED device having a low temperature grown AI(Ga)N buffer layer.
  • the example shown in part b of Figure 15 has a low temperature grown AI(Ga)N-based DUV-LED structure.
  • Figure 16 depicts an example of a self-powered photodetector having a low temperature epitaxially grown Ill-nitride layer.
  • the Ill-nitride layer is a AI(Ga,ln,Sc)N layer configured to act as a light absorption layer.
  • Figure 17 depicts three examples of thin film acoustic wave resonator devices having a low temperature grown Ill-nitride layer.
  • the Ill-nitride layer is composed of AI(Sc)N and configured to act as a piezolayer.
  • the examples of parts a, b, and c are a bulk resonator, a free-standing resonator based on surface micromachining, and a free-standing resonator based on bulk micromachining, respectively.
  • the examples described above demonstrate low temperature epitaxy of singlecrystalline wurtzite phase nitrides utilizing MBE on both GaN and CMOS compatible Al metal electrodes. Highly ordered wurtzite atomic stacking sequence and atomically sharp interface were achieved in a low growth temperature of 100 °C. A polar surface controlled on-site growth mechanism explains the successful epitaxy of single-crystalline polar nitrides under low temperature. Furthermore, growth of wurtzite phase ScAIN with a Sc content up to 0.4 and AIN films on CMOS compatible Al metal electrodes has been achieved by using the proposed on-site epitaxy method. The examples demonstrate the epitaxy of polar nitride semiconductors at an unexplored low temperature regime, which supports integration with CMOS technology and also advanced hybrid and integrated circuits across a wide variety of technology and material platforms.
  • the terms “atomically smooth” or “atomically smooth surface” may be used herein in connection with a layer of a heterostructure to indicate that the layer has a surface roughness (e.g., a root mean square, or RMS, roughness) less than or on the order of 1 nm. In some cases, the RMS roughness of such atomically smooth layers is less than 1% of the thickness of the layer.
  • the surface roughness may vary in accordance with the growth conditions, parameters, and other aspects of the fabrication processes described and/or referenced herein and/or other processes

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Abstract

A method of forming a heterostructure includes providing a substrate, forming a template layer of the heterostructure such that the template layer is supported by the substrate, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the template layer. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline. The non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius.

Description

LOW TEMPERATURE EPITAXY OF POLAR SEMICONDUCTORS
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. provisional application entitled “Low Temperature Epitaxy of Polar Semiconductors,” filed October 24, 2020, and assigned Serial No. 63/418,951 , the entire disclosure of which is hereby expressly incorporated by reference.
BACKGROUND OF THE DISCLOSURE
Field of the Disclosure
[0002] The disclosure relates generally to epitaxial growth of semiconductors.
Brief Description of Related Technology
[0003] Due to their widely tunable direct bandgap, high electron mobility, large breakdown field, strong piezoelectric and spontaneous polarization, and large exciton binding energy, Ill-nitride semiconductors, e.g., InN, GaN, AIN and their heterostructures, nanostructures, and alloying with group II IB elements such as Sc, have attracted growing interest and facilitated a wealth of applications in optoelectronics, electronics, acoustics, green energy, and quantum devices and systems. Furthermore, as nitride-based devices go beyond discrete, there has been a growing interest in integrating nitride devices and circuits with state-of-the-art silicon complementary-metal-oxide-semiconductor (CMOS) technology or even all nitride CMOS technology to reduce latency between hybrid integrated circuits and cost and to enable enhanced multi-functionality. All those pose significant challenges on the conventional epitaxial growth of Ill-nitride semiconductors.
[0004] To date, molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have shown to produce high quality Ill-nitrides with precise doping, composition and thickness control, and have dominated the epitaxial growth of Ill-nitride semiconductors. To produce high quality materials with a smooth surface/interface, a universal adsorption-migration-epitaxy thermal dynamic process is employed at the growth front in both methods, during which the temperature of the substrate during growth and the element ratio, i.e., 111/V ratio, are used for sufficient adatom migration. In this regard, the growth temperature of Ill-nitrides in both methods has been limited to above 400 °C, e.g., about 500 °C for InN, about 800 °C for GaN, and about 1000 °C for AIN. These high growth temperatures, however, are not CMOS compatible, preventing the seamless integration of Ill-nitride materials and devices with the advanced processing techniques and mainstream semiconductor technology like CMOS. Other growth techniques, such as atomic layer deposition, sputtering, and pulsed laser deposition, generally yield polycrystalline, or even amorphous materials with very limited quality.
SUMMARY OF THE DISCLOSURE
[0005] In accordance with one aspect of the disclosure, a method of forming a heterostructure includes providing a substrate, forming a template layer of the heterostructure such that the template layer is supported by the substrate, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the template layer. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline. The non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius.
[0006] In accordance with another aspect of the disclosure, a method of fabricating a device includes forming a metal structure of a complementary metal-oxide-semiconductor (CMOS) component of the device, the metal structure being supported by a substrate, and, after forming the metal structure, implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of a heterostructure of the device, the polar semiconductor layer being supported by the substrate. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline.
[0007] In accordance with yet another aspect of the disclosure, a heterostructure includes a substrate and a polar semiconductor layer supported by the substrate. The polar semiconductor layer has a single-crystalline, wurtzite crystal structure. The polar semiconductor layer includes multiple columnar domains.
[0008] In accordance with yet still another aspect of the disclosure, a device includes a substrate, a complementary metal-oxide-semiconductor (CMOS) component supported by a substrate, the CMOS transistor including a structure, and a polar semiconductor layer supported by the structure. The polar semiconductor layer has a single-crystalline, wurtzite crystal structure. [0009] In accordance with yet another aspect of the disclosure, a method of forming a heterostructure includes providing a substrate, forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer including aluminum, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the metal layer. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline. Forming the metal layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal layer and implementing the non-sputtered, epitaxial growth procedure.
[0010] In accordance with yet another aspect of the disclosure, a method of forming a heterostructure includes providing a substrate, forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer including molybdenum, and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the metal layer. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline. Forming the metal layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal layer and implementing the non-sputtered, epitaxial growth procedure.
[0011] In connection with any one of the aforementioned aspects, the devices and/or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features. The non-sputtered, epitaxial growth procedure is implemented in nitrogen-rich conditions. Forming the template layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the template layer and implementing the non-sputtered, epitaxial growth procedure. Forming the template layer includes implementing a surface treatment procedure to remove oxide from a surface of the template layer. The growth temperature is less than about 300 degrees Celsius. The growth temperature is greater than about 20 degrees Celsius. The growth temperature falls in a range from about 20 degrees Celsius to about 100 degrees Celsius. The polar semiconductor layer includes a Ill-nitride material or alloy thereof. The polar semiconductor layer includes AIN or an alloy thereof. The template layer includes a metal compatible with complementary metal-oxide-semiconductor (CMOS) fabrication. The template layer includes GaN. The polar semiconductor layer includes AIN or an alloy thereof. The non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius. The non-sputtered, epitaxial growth procedure is implemented in nitrogen-rich conditions. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is configured such that the polar semiconductor layer is in contact with the metal structure. Forming the metal structure and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal structure and implementing the non-sputtered, epitaxial growth procedure. Forming the metal structure includes implementing a surface treatment procedure to remove oxide from a surface of the metal structure. The method further includes forming a template layer of the heterostructure before implementing the non-sputtered, epitaxial growth procedure such that the polar semiconductor layer is in contact with the template layer. The structure includes metal. The polar semiconductor layer includes multiple columnar domains. A surface of the polar semiconductor layer in contact with the structure has an atomically smooth surface. The non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is implemented at a growth temperature compatible with complementary metal-oxide-semiconductor (CMOS) fabrication.
BRIEF DESCRIPTION OF THE DRAWING FIGURES
[0012] For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawing figures, in which like reference numerals identify like elements in the figures.
[0013] Figure 1 depicts low temperature epitaxy of ScAIN on GaN template, including (a) a schematic view of a heterostructure having a Ill-nitride-based layer (e.g., a ScAIN film) grown on a GaN template in accordance with one example, (b) an SEM image of the example heterostructure, (c) a graphical plot of (0002) plane XRD 20-co scans of the example heterostructure, and (d) a graphical plot of (0002) and (1012) planes XRC FWHM of Sco.i8Alo.82N films grown on GaN templates.
[0014] Figure 2 depicts microstructure analysis of Sco.i8Alo.82N films grown at different temperatures on a GaN template, including (a) a HAADF-STEM image of the ScAIN/GaN interface of a ScAIN example grown at 700 °C, (b) an ABF-STEM image of the ScAIN region for the ScAIN example grown at 700 °C, (c) a HAADF-STEM image of the ScAIN/GaN interface of a ScAIN example grown at 100 °C, and (d) an ABF-STEM image of the ScAIN region for the ScAIN example grown at 100 °C, in which shaded balls for the Sc/AI and N atoms are embedded in parts b and d to better visualize the atomic stacking sequence.
[0015] Figure 3 depicts low temperature epitaxy of a heterostructure having a ScAIN film on an Al/Si template (e.g., Al template in combination with a Si substrate) in accordance with one example, including (a) a schematic view of the example heterostructure, and (b) an SEM image of the example heterostructure, and (c, d) graphical plots of (0002) plane XRD 20-co scans of example heterostructures having ScAIN grown on Al/Si templates with varying Sc contents and varying film thicknesses.
[0016] Figure 4 depicts microstructural analysis of an example heterostructure having a Sco.2Alo.8N layer grown at 100 °C on Al/Si template, including (a) a cross-sectional HAADF- STEM image of the ScAIN/AI/Si heterostructure, (b, c) HAADF-STEM images of the Al/Si and ScAIN/AI interfaces, and (d) an ABF-STEM image acquired from the ScAIN region, in which shaded balls for the Sc/AI and N atoms are embedded in part (d) to better visualize the atomic stacking sequence.
[0017] Figure 5 depicts low temperature epitaxy of an example heterostructure having an AIN layer on an Al/Si template, including (a) an AFM image (RMS = 0.69 nm) and (b) a graphical plot of an XRD 20-co scan of AIN grown at 100 °C on the Al/Si template, and (c) HAADF-STEM (left) and ABF-STEM (right) images of AIN grown at 100 °C on the Al/Si template, in which shaded balls for the Al and N atoms are embedded in the ABF-STEM image to better visualize the atomic stacking sequence.
[0018] Figure 6 is a flow diagram of a method of fabricating a device with a heterostructure having a polar semiconductor layer grown at a low temperature in accordance with one example.
[0019] Figure 7 depicts example heterostructures having Ill-nitride-based layers grown via low-temperature epitaxy, including schematic views of (a) an AIGaN/AIN bilayer heterostructure grown on an Al/Si template, (b) a ScAIN/AIN bilayer heterostructure grown on a Mo/Si template, and (c) an AIN/ScAIN/AIN trilayer heterostructure grown on a Mo/Si template, as well as (d-f) corresponding SEM images of the surface morphology of the multilayer heterostructures shown in parts (a-c) grown at 100 degrees Celsius.
[0020] Figure 8 depicts example (a) Ga-polar and (b) N-polar AI(Ga,ln)N/GaN HEMTs using low temperature in situ epitaxially grown AIN as the high-k gate dielectric layer. [0021] Figure 9 depicts example transistor structures using low temperature grown polar semiconductor AI(Sc)N as the dielectric layer and a 2D material as the channel: (a) global (back) gate structure and (b) local (top) gate structure.
[0022] Figure 10 depicts an example low temperature grown AIN transistor.
[0023] Figure 1 1 depicts example high power AI(Ga)N p-i-n diodes, in which the p- and n- AI(Ga) layers may be grown under low temperature or high temperature, while an i-AI(Ga)N layer is grown at low temperature, and in which the low temperature i-AI(Ga)N layer leads to an improved breakdown voltage of the diodes.
[0024] Figure 12 depicts example high power AI(Ga)N Schottky diodes, in which n-AI(Ga) layers may be grown under low temperature or high temperature, while an n-AI(Ga)N layer is grown at low temperature, and in which the low temperature n-AI(Ga)N layer leads to an improved breakdown voltage of the diodes.
[0025] Figure 13 depicts example high power AI(Ga)N bipolar transistors, in which n-and p- AI(Ga) layers may be grown under low temperature, which leads to an improved breakdown voltage of the transistors.
[0026] Figure 14 depicts a ferroelectric-transistor random-access memory cell with a metal- low temperature grown ferroelectric ScAIN-metal capacitor and a silicon or GaN based writeread transistor in accordance with one example.
[0027] Figure 15 depicts example deep ultraviolet LED structures based on low temperature epitaxially grown semiconductor heterostructures: (a) normal AI(Ga)N-based DUV-LED structure grown on a low temperature grown AI(Ga)N buffer, and (b) low temperature grown AI(Ga)N-based DUV-LED structure, which is useful in connection with some substrates or applications.
[0028] Figure 16 depicts an example self-powered photodetector using an low temperature epitaxially grown polar semiconductor AI(Ga,ln,Sc)N as the light absorption layer.
[0029] Figure 17 depicts three examples of thin film acoustic wave resonator structures using a low temperature grown polar semiconductor AI(Sc)N as a piezolayer: (a) bulk resonator, (b) free-standing resonator based on surface micromachining, and (c) freestanding resonator based on bulk micromachining.
[0030] The embodiments of the disclosed devices and methods may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein. DETAILED DESCRIPTION OF THE DISCLOSURE
[0031] Methods of fabrication including low-temperature epitaxy are described. In some cases, the epitaxy may be implemented at an ultralow temperature. Devices fabricated by the disclosed methods are also described. As described herein, the disclosed methods may be useful for fabricating devices having a highly reactive Ill-nitride layer or other polar semiconductor layer.
[0032] The disclosed methods include low temperature epitaxial growth (e.g., growth at CMOS compatible temperatures, such as less than 400 degrees C) of single crystalline Ill- nitride semiconductor layers. There are some previous studies by sputtering, but those are not single crystalline, not epitaxial growth. In some cases, Ill-nitride semiconductor layers or other polar semiconductor layers are grown on metal templates and/or substrates, such as Al. The growth/epitaxy of the Ill-nitride semiconductor layers and metals may be implemented in the same reaction chamber, which can avoid the formation of surface oxides and the incorporation of interface impurities. A further metal layer may be deposited on the Ill-nitride semiconductor layers to form, e.g., a top electrode.
[0033] The low-temperature growth of Ill-nitrides of the disclosed methods may be used to fabricate a broad range of devices, including, for instance, transistors, memories, acoustic resonators/filters, and MEMS devices. For instance, the devices may include multi-layer structures having stacks of metal/l I l-nitride layers, AIN/ScAIN layers, and/or other layer combinations. In some cases, the multilayer structures may include stacks of AIN/ScAIN with opposite polarity. Ferroelectric layers or materials may also be epitaxially grown directly on metal substrates at low temperature.
[0034] Although described in connection with MBE-based examples, other epitaxial growth processes may be used, including, for instance, MOCVD, atomic layer epitaxy, and pulsed laser deposition.
[0035] Although described herein in connection with Ill-nitride-based examples (e.g., Al- based examples), other polar semiconductors may be used and/or formed via the low- temperature epitaxy techniques described herein, including, for instance, ZnO, Ga2O3, GaAs, and BaTiO3. The disclosed methods and devices are accordingly not limited to Ill- nitrides and their alloys (e.g., AIN and ScAIN).
[0036] The disclosed methods and devices exploit a previously unexplored growth regime for achieving crystalline nitride semiconductors is the low temperature growth region, i.e., with growth temperatures less than 400 °C that are CMOS compatible. This low temperature growth has several potential advantages: i) it releases the constraints on the processing conditions before and after film deposition, providing better compatibility with different material platforms and semiconductor technologies like silicon CMOS technology; ii) in the high temperature growth regime, adatom migration leads to “jump over” effect close to surface imperfections like nano-gaps/dots, while low temperature growth provides better surface coverage, fast coalescence, and uniform thickness; iii) nucleation process is easier at low temperature, favoring hetero-epitaxy of Ill-nitride semiconductors on different materials like metal substrates; iv) following ii) and iii), this kind of “on-site” growth enabled by low temperature, is immune to surface thermal dynamics, thus can be done in a very wide growth window, i.e., wide temperature and 111/V ratio window; v) low temperature growth tends to produce multi-domain films, which potentially blocks the penetration of dislocations that is unavoidable during high temperature growth, which is useful for improving the breakdown strength of the material. However, compared with the conventional high temperature growth, low temperature growth lacks sufficient adatoms migration, and tends to provide low quality materials. In principle, this can be mostly addressed by using high quality substrates or templates and optimum growth rates.
[0037] Examples of low temperature, CMOS compatible epitaxy of polar nitride semiconductors are described. Epitaxial growth of single-crystalline wurtzite phase ScAIN, AIN, and AIGaN with high crystal quality and atomically sharp interface has been demonstrated in a wide growth temperature range (from about 700 to about 20 °C), which had been previously unattainable. An on-site growth mechanism is presented to describe the epitaxy of crystalline material under such low growth temperatures, which is explained by a polar surface controlled adsorption-epitaxy process, compared to the conventional adsorption-migration-epitaxy process for epitaxy at high temperatures. Furthermore, epitaxial growth of wurtzite phase ScAIN with various Sc contents and film thicknesses as well as AIN on CMOS compatible aluminum metal electrodes has been achieved using the proposed low temperature on-site growth method. Such significant expansion of the growth window of polar Ill-nitrides enables the fully epitaxial integration of nitride architectures with a variety of other semiconductor platforms and technologies.
[0038] With ScAIN and AIN as an example, the disclosed methods and devices establish that low temperature growth of Ill-nitride semiconductors can maintain the wurtzite crystal structure and provide reasonable crystal quality, interface, and chemical composition control that are comparable to conventional high temperature growth, but with better compatibility with different substrates and processing techniques. Examples of ScAIN thin films with various thicknesses and Sc contents and AIN films have been grown on GaN and metal substrates at low temperatures (< 100 °C). The ScAIN films exhibit good wurtzite atomic stacking sequence with sharp interface, and atomically smooth surface on both GaN and metal (Al, Mo) substrates. Those results open the avenue for growing high quality Ill-nitride semiconductors at low temperatures toward advanced hybrid and emerging integrated circuits across different technology and material platforms.
[0039] Examples described herein were grown utilizing a Veeco GENxplor MBE system, equipped with dual filament SUMO Knudsen cells for Al (purity 6N5) and Ga sources (purity 7N), a high-temperature Knudsen cell for Sc source (purity 5N), and a Veeco Unibulb radio frequency (RF) plasma source. The N source was operated with a N2 gas (purity 6N) flow of 0.35 seem and RF power of 350 W. While the total metal flux was controlled to maintain a N- rich growth conditions with a II 1/V ratio of about 0.8. The GaN templates and Si substrates were cleaned by acetone, methanol, and deionized water prior to loading into the MBE system. And then degassed at 200 and 600 °C for 2 h in the MBE load-lock chamber and preparation chamber, respectively.
[0040] Examples involving low temperature epitaxy of ScAIN on GaN. ScAIN films with a Sc content about 18% were grown on GaN templates, as shown in Figure 1 , part a. As described herein, the GaN template may constitute a layer or structure of a CMOS component of a device. For this series of examples, 100-nm-thick Si-doped n+-GaN was firstly grown on the GaN template to obtain an atomically smooth and clean surface. After that, the excess Ga adatoms on the surface were reevaporated, and in situ surface nitridation was further performed to obtain a Ga-free surface. Subsequently, 100-nm-thick ScAIN was grown with various growth temperatures. The growth temperature was varied from the commonly used high-temperature (700 °C) to an unexplored low temperature (20 °C). Figure 1 , part b, displays the typical scanning electron microscope image of the ScAIN/GaN films grown at 100 °C, showing a granular surface, which is consistent with previous reports on ScAIN grown under N-rich conditions. Meanwhile, it was found that the surface morphology is insensitive with growth temperature. All examples showed similar granular surface, while the grain size is slightly larger at higher growth temperatures.
[0041] Figure 1 , part c, shows the (0002) plane XRD 20-co scans for the ScAIN films grown at various temperatures. All examples possess a clear and strong characteristic diffraction peak at 36° for wurtzite ScAIN. Additionally, in the long range scans (20-100°), no other peaks originated from either cubic phase or misoriented structures were observed, indicating a single-crystalline wurtzite crystal structure for those ScAIN films. To the applicant's knowledge, this is the first ever demonstration of epitaxial growth of single-crystalline wurtzite nitride semiconductors at such unexplored low growth temperature (even lower than room temperature). For comparison, previous reports always showed polycrystalline structure when growing AIN at room temperature.
[0042] The evolution of crystal quality with growth temperature has been characterized using XRD rocking curve (XRC). Shown in Figure 1 , part d, the full width at half maximum of both (0002) and (10 2) planes XRC gradually increase with reducing growth temperature. The FWHM of (0002) plane XRC for the ScAIN grown at 20 °C (330 arc sec) only increased 22% compared to the ScAIN grown at 700 °C (270 arc sec). However, the FWHM of (10 2) plane XRC increased 137% after reducing the growth temperature to 20 °C, indicating an increase of edge dislocation density with reducing growth temperature. Overall, the lower growth temperature does not degenerate the crystal quality significantly.
[0043] The crystal structure of the examples was further characterized using high-angle annular dark field (HAADF) and annular bright field (ABF) scanning transmission electron microscope (STEM). Figure 2, parts a and c, show the HAADF-STEM image acquired from the ScAIN/GaN interface, in which the ScAIN epilayer was grown at 700 and 100 °C, respectively. An atomically smooth, clean, and sharp ScAIN/GaN interface was observed for both ScAIN films. The wurtzite atomic stacking sequence (ABAB) was well maintained along the growth direction, no clear insert planes or absent planes were observed.
[0044] Furthermore, the lattice-polarity was checked using ABF-STEM, as shown in Figure 2, parts b and d. In the ABF-STEM image, the darkest contrasts correspond to the heaviest atoms. Therefore, the process was capable of configuring the atomic stacking sequence of Sc/AI and N atoms, which are embedded in Figure 2, parts b and d. Comparing the atomic model of wurtzite crystal structure with the experimental results, one can easily confirm that the initial metal (M)-polar lattice in the GaN template was inherited perfectly in the ScAIN films, i.e., the ScAIN films grown at 700 and 100 °C have a M-polar lattice. Due to the N-rich growth conditions and the low growth temperature, the ScAIN shows a columnar-like growth, in which slightly mis-orientated (less than 1 °) domains coexist. However, no inverted domains with nitrogen (N)-polar were observed in the ScAIN films, suggesting all films have a high uniform M-polar lattice, which is in contrast to the polycrystalline or mixed phase material deposited by using sputtering at the same temperature range.
[0045] Polar surface controlled on-site epitaxy. Based on the above-described analysis and examples, the epitaxial growth of nitride alloys including highly reactive atoms, such as Sc, Al etc., is not limited to the conventional narrow growth window, i.e., relatively high growth temperatures. Single-crystalline wurtzite phase nitrides can be also grown or achieved at low growth temperatures without significantly degrading the crystal quality. These results are in contrary to early reports, in which polycrystalline nitrides were often observed when the growth temperature was lower than 300 °C.
[0046] The successful growth of wurtzite nitride under low temperature is attributed to a polar surface controlled on-site epitaxy mechanism or process. With reducing growth temperature, the adatoms diffusion capability is suppressed dramatically, and the desorption rate is also negligible. Therefore, the conventional adsorption-migration-epitaxy process is simplified to an adsorption-epitaxy process. Under the low growth temperatures, the kinetic energy of the impinging atoms could support a short-range diffusion for the adatoms to an adjacent site with the lowest surface potential energy. However, long-range diffusion commonly seen in conventional high temperature growth regime would not happen. The strong polarization of wurtzite nitrides provides a strong electrostatic potential fluctuation on the surface. Except for the polar lattice induced surface potential, the kink and vacancy sites of the lattice can generate additional electrostatic potential fluctuation on the surface. For the conventional high growth temperature, adatoms have enough energy to migrate to a site with the lowest energy and join the growth. Generally, the diffusion length is hundreds of nanometers to tens of micrometers. Although at low temperature the adatoms could not achieve a long-range diffusion, due to the lattice continuity, there are still low potential sites near the atoms landing site, which are within the short-range diffusion length. Therefore, as long as the adatoms can diffuse to those sites the wurtzite lattice can be maintained and keep growing. Considering the diffusion length (nanometer- or even sub-nanometer scale) at a low temperature would be much shorter than the conventional high temperature growth, it can be regarded as an on-site growth with negligible surface diffusion.
[0047] Nitride alloys including high reactive atoms, such as Al and Sc, were grown under low temperatures while maintaining the single-crystalline wurtzite phase. This phenomenon suggests that the bonding strength also contributes to the proposed on-site growth mechanism, i.e., a larger bonding strength is favorable for the low temperature epitaxy. Moreover, a clean and crystalline surface is useful to avoid misoriented nucleation formation at the beginning and would be useful to initialize such growth at low temperature. This achievement provides a viable path for the fully epitaxial integration of Ill-nitride architectures on special application scenarios, such as nitrides grown on CMOS compatible metal electrodes.
[0048] Low temperature epitaxy of ScAIN on aluminum. Aluminum (Al) is a commonly used metal electrode in CMOS technology. However, the relatively low melting point of Al (about 660 °C) makes it unbearable for high temperature processes. Therefore, epitaxially grown Ill-nitrides on the Al electrodes was unattainable previously, due to the limitation the widely used high growth temperature. To further explore the extensibility of the low temperature epitaxy approach, examples of ScAIN films with varying Sc contents and thicknesses were also grown on a crystalline Al/Si template, as schematically shown in Figure 3, part a. As described herein, the Al/Si template may constitute a layer or structure of a CMOS component of a device. For instance, the Al structure may correspond with an electrode or contact of the CMOS component. In these examples, 100-nm-thick Al was firstly deposited on Si(1 11 ) substrates at 100 °C, followed by ScAIN growth under the same temperature. The surface morphology of ScAIN grown on Al/Si shows a granular surface (Figure 3, part b), which is similar to the ScAIN grown on GaN under the same conditions (Figure 1 , part b). XRD 20-co scans for these ScAIN films are shown in Figure 3, part c. XRD 20-co scan for the Al/Si template shows a characteristic diffraction peak at 38.5°, suggesting a cubic crystal structure for the MBE grown Al film. After ScAIN growth, a characteristic peak for wurtzite phase at 36° was observed, and no other peaks from either cubic phase or misoriented domains appeared in the long-range scan, confirming a single-crystalline wurtzite crystal structure for this ScAIN film. Furthermore, ScAIN films with varying Sc content up to 0.4 have been also successfully grown on such Al/Si template. In the XRD 20- co scans, the diffraction peak for ScAIN gradually shifts to the higher angle side. This trend is similar to the previous reports on ScAIN grown by MBE under higher temperature (700 °C). Meanwhile, the effect of film thickness on such low temperature epitaxy of ScAIN on Al/Si template was also analyzed. Sco.3Alo.7N layers with a thickness of 30, 100, and 150 nm were grown on the same Al/Si template. Similar diffraction peaks for the wurtzite phase were clearly observed in these three samples, as shown in Figure 3, part d. Due to the lattice mismatch induced in-plane strain between Al and ScAIN, cracks were observed on the ScAIN surface with a thickness beyond 200 nm.
[0049] The microstructure of ScAIN grown on Al/Si at an low temperature of 100 °C was characterized using HAADF-STEM and ABF-STEM. Figure 4, part a, shows the cross- sectional HAADF-STEM image for a 50-nm-thick ScAIN grown on 100-nm-thick Al/Si. Sharp and clear interfaces were observed for the ScAIN/AI/Si heterostructure. There is a diffraction contrast fluctuation in the ScAIN layer, which indicates that the ScAIN domains have a columnar-like structure. The diameter for each domain is about 10 nm, agreeing well with the granular surface morphology (Figure 3, part b). The columnar-like domain formation is mainly due to the N-rich growth condition as well as the low growth temperature, which limit the diffusion length of impinging atoms dramatically. Figure 4, part b, presents the HAADF- STEM image of the Al/Si interface, showing a clear cubic crystal structure for the MBE grown Al template. The ScAIN/AI interface is shown in Figure 4, part c. A clear lattice transition from cubic Al to wurtzite ScAIN is observed; the interface thickness is only a few monolayers. The ScAIN layer has a highly ordered wurtzite stacking sequence (ABABAB). During the STEM measurements, the in-plane rotation for the domains is less than 1 °. Based on the atomic stacking sequence at the interface, the epitaxial relationship in the ScAIN/AI/Si heterostructures can be confirmed as [001 ](1 120)SCAIN| |[111 ](T10)AI| |[111 ](T10)si- Figure 4, part d, illustrates the ABF-STEM image captured from the ScAIN layer. Sc/AI and N atoms are embedded inside to visualize the atomic stacking sequence. Compared with the atomic structure of wurtzite Ill-nitrides, one can easily confirm that the ScAIN grown on Al/Si template has a M-polar lattice. This in contrast to the ScAIN deposited by sputtering, in which similar lower growth temperatures were employed but the ScAIN layers favor a N- polar lattice. The fully epitaxial method and free of buffer layer may play a crucial role in maintain the M-polar lattice.
[0050] Low temperature epitaxy of ScAIN on molybdenum. Epitaxial growth of wurtzite ScAIN under low temperature can be achieved on molybdenum (Mo) substrates. Mo is not only a desired metal electrode for CMOS technology, but also a useful bottom electrode for filters and resonators due to the high acoustic velocity. Therefore, epitaxially grown ScAIN on Mo provides a viable path to achieve both CMOS compatible ferroelectric nitrides and a new class of low loss, and ultrahigh frequency acoustoelectronic devices.
[0051] Low temperature epitaxy of AIN and AIGaN. The low temperature epitaxial growth of AIN and AIGaN films was also analyzed. Due to the ultrawide bandgap, AIN has been widely used as in-situ surface passivation layer to improve the device performance. However, partially amorphous AIN was achieved at growth temperatures below 250 °C. The low temperature epitaxy of AIN on Al/Si templates was explored. Figure 5, part a, shows the atomic force microscope (AFM) image of the as-grown AIN on Al/Si template, showing a root mean square (RMS) roughness of 0.69 nm for a scan area of 3 x 3 |im2. Even though N-rich growth conditions were employed during the low temperature growth of AIN, a reasonably atomically smooth surface was achieved, which is even smoother than the AIN grown at higher growth temperature with the same N-rich conditions. This is mainly due to the suppressed diffusion process under lower growth temperature, therefore, the typical three- dimensional (3D) growth induced by the surface diffusion at a high growth temperature was avoided.
[0052] Figure 5, part b, displays a long range XRD 20-co scan of the AIN/AI/Si heterostructure. Only the characteristic diffraction peaks for AIN <0002> planes are observed, confirming a single-crystalline wurtzite crystal structure of this AIN film. Figure 5, part c, shows the HAADF-STEM image and the corresponding ABF-STEM image captured from the near surface region. The well aligned wurtzite phase atomic stacking sequence (ABABAB) is well maintained up to the top surface, indicating that the proposed low temperature on-site growth mechanism does not degenerate the crystal structure. As shown in Figure 5, part c, the stacking sequence for Al and N atoms has been labeled with blue and red balls, respectively, in the ABF-STEM image. Comparing with the crystal structure of wurtzite AIN, a uniform M-polar lattice is confirmed for the as-grown AIN on Al/Si template. Furthermore, epitaxial growth of AIGaN can also be achieved at low growth temperatures (< 100 °C). The low temperature growth of AIN is thus not limited to the metal substrates (Al and Mo). Low temperature growth can be also realized on either GaN or AIN templates. These achievements provide for growing AIN as well as AIGaN alloys under a low temperature, which can be used not only as an in-situ high-quality passivation layer but also for the hybrid integration with other material platforms.
[0053] Figure 6 depicts a method 600 of fabricating a heterostructure having a singlecrystalline polar semiconductor layer grown at a low temperature in accordance with one example. As described herein, the method 600 is configured such that a Ill-nitride-based or other polar semiconductor layer may be grown on a metal or other template at a low temperature, e.g., sufficiently low for compatibility with CMOS fabrication. The polar semiconductor layer may or may not exhibit piezoelectric or ferroelectric behavior. The method 600 may be used to fabricate the examples of devices, heterostructures, and other structures having polar semiconductor films or layers as described herein, and/or other devices, heterostructures or structures.
[0054] The method 600 may begin with an act 602 in which a substrate is prepared and/or otherwise provided. In some cases, the act 602 includes providing a silicon substrate in an act 604. The silicon substrate may have a (111) orientation. The substrate may be patterned or otherwise processed to configure the substrate to reduce defect formation in subsequently grown layers of the heterostructure and/or otherwise improve material quality therein. Such processing may also facilitate the formation of a different regions of the heterostructure.
[0055] Alternative or additional substrate materials may be used, including, for instance, sapphire, bulk GaN, bulk AIN, or other semiconductor material. Still other materials may be used, including, for instance, silicon carbide. In still other cases, a metal substrate may be used. For instance, the metal substrate may be composed of, or otherwise include, Al, Pt, and/or Mo.
[0056] The substrate may be cleaned in an act 606. In some cases, a native or other oxide layer may be removed from a substrate surface in an act 608. The oxide removal may include multiple steps, including, for instance, an etch step and an annealing step.
[0057] Additional or alternative processing may be implemented in other cases, including, for instance, doping or deposition procedures. The substrate thus may or may not have a uniform composition. The substrate may be a uniform or composite structure. Any number of layers or structures may be deposited on the substrate prior to the implementation of the acts described below.
[0058] The method 600 may include an act 610, in which one or more template or other layers are formed or otherwise provided. In some cases, the template layer is composed of, or otherwise includes, a metal such as Al or Mo. In other cases, the template layer is composed of, or otherwise includes, a Ill-nitride layer (e.g., GaN) or other semiconductor layer. The template layer is supported by the substrate. In some cases, the template layer is in contact with the substrate. In other cases, one or more buffer or other layers or structures (e.g., CMOS component structures) are disposed between the template layer and the substrate.
[0059] In some cases, the act 610 is part of a CMOS fabrication procedure directed to fabricating a CMOS component (e.g., CMOS transistor, diode, etc.) of the device. A number of layers or other structures may be formed during the CMOS fabrication procedure, including, for instance, various types of electrodes, contacts, and other structures. In some cases, one of the structures of the CMOS component may be configured or act as a template layer.
[0060] In the example of Figure 6, the act 610 includes an act 612 in which the template layer(s) are deposited. A wide variety of deposition procedures may be used. In some cases, the template layer(s) are patterned in an act 614.
[0061] The act 610 may include the deposition or other formation of one or more other metal layers or structures. For example, a bottom contact may be formed in an act 616. The act 616 may be implemented in parallel with (e.g., as part of) the act 612. The number and other characteristics of the metal layers or structures may vary in accordance with the configuration of the device (e.g., the number of terminals). [0062] As described herein, the metal layers or structures may be part of a CMOS component of the device being fabricated. For example, the metal layer or structure may be an electrode of a CMOS transistor, CMOS diode, or other CMOS component.
[0063] As described herein, in some cases, the metal layer or structure is formed in a chamber also used for implementation of an epitaxial growth procedure to form a polar semiconductor layer. That is, the same chamber is used to form the metal layer or structure and grow the polar semiconductor layer. As a result, the metal layer (or other layer or portion of a heterostructure being formed) is not exposed to an ambient between formation of the metal structure and implementation of the non-sputtered, epitaxial growth procedure.
[0064] Alternatively, the method 600 includes an act 618 in which a surface treatment procedure is implemented to remove oxide from a surface of the metal layer. In some cases, the act 618 includes annealing the polycrystalline metal layer in a vacuum in an act 620. The temperature of the annealing may vary, e.g., with the composition of the metal layer and/or other structures of the device (e.g., CMOS component structures). For instance, Mo03 has a relatively low melting point (795 °C), in which case annealing above the melting point, e.g., at about 900 °C, may be used. The annealing may also improve the surface roughness of the metal layer. In one example involving annealing at 900 °C for 10 minutes, except for the domain boundaries, a smooth surface was observed on each domain. Furthermore, after the high-temperature annealing, the domain boundaries were more uniform with significantly reduced misoriented clusters. The oxide may be removed in additional or alternative ways to achieve a highly ordered atomically smooth surface. For instance, the oxide may be removed via an etching procedure using, e.g., an acid solution, such as hydrochloric acid (HCI) or buffered hydrofluoric acid (BHF).
[0065] After forming the metal structure or other template, a non-sputtered, epitaxial growth procedure is implemented in an act 622 to form a single-crystalline polar semiconductor layer supported by, and in contact with, the template layer. As described above, the singlecrystalline polar semiconductor layer may be composed of, or otherwise includes, a Ill- nitride-based material (e.g., an alloy of a Ill-nitride material). Other polar semiconductors (e.g., ZnO) may be grown.
[0066] The polar semiconductor layer may or may not be ferroelectric or piezoelectric. As described herein, the polar semiconductor layer may have a wurtzite structure. For instance, the polar semiconductor material may be AIN. Additional or alternative Ill-nitride materials may be used, including, for instance, gallium nitride (GaN), indium nitride (InN), and their alloys. [0067] The epitaxial growth procedure may be configured to incorporate scandium and/or another group 111 B element into the alloy of the Ill-nitride material. The alloy may thus be ScAIN or YAIN, for example. In some cases, the act 622 includes an act 624 in which an MBE procedure is implemented. In other cases, an MOCVD or other non-sputtered epitaxial growth procedure is implemented in an act 626.
[0068] The surface treatment of the act 618 may be implemented before (e.g., in preparation for) implementing the epitaxial growth procedure in which a wurtzite structure is formed. The wurtzite structure may thus be formed on the metal layer. The metal layer may thus act as a template for the wurtzite structure and/or other elements of the heterostructure. In some cases, the act 612 may include an act 628 in which the single-crystalline semiconductor layer is grown in a chamber in which the template layer is formed. For instance, the same chamber may be used to form a metal template layer (e.g., Mo or Al template layer) and grow the polar semiconductor layer. As a result, the substrate may remain within, e.g., is not removed from, the epitaxial growth chamber between forming the metal layer and growing the single-crystalline semiconductor layer. Exposure to the ambient is thus avoided.
[0069] As described herein, the epitaxial growth procedure may be implemented at a low temperature. In some cases, the growth temperature may be about less than about 400 degrees Celsius or other temperature compatible with CMOS fabrication. For instance, the growth temperature may be about 300 degrees Celsius or less. As with the examples described herein, the growth temperature may fall in a range from about 20 degrees Celsius to about 100 degrees Celsius. The growth temperature may correspond with the temperature measured at a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may be slightly different. The growth temperature is accordingly approximated via the temperature measurement at the thermocouple. The upper and/or lower bounds of the growth temperature range may vary in accordance with the polar semiconductor material and/or the epitaxial growth technique.
[0070] At each level within the above-described ranges of suitable growth temperatures, the resulting wurtzite structure is monocrystalline. The resulting wurtzite structure is monocrystalline to a degree not realizable via, for instance, sputtering-based procedures for forming ScAIN layers. Such procedures are only capable of producing structures with x-ray diffraction rocking curve line widths on the order of a few degrees at best. In contrast, the structures grown by the disclosed methods exhibit x-ray diffraction rocking curve line widths on the order of a few hundred arc-seconds or less, well over an order of magnitude less. In this manner, leakage current paths may be minimized or otherwise sufficiently reduced so that, in ferroelectric cases, the resulting wurtzite structure has a suitably high breakdown field strength level, e.g., sufficiently greater than the ferroelectric coercive field strength.
[0071] Differences in crystal quality evidenced via x-ray diffraction rocking curve line widths may be used to distinguish between monocrystalline (or single-crystalline) and polycrystalline structures. As used herein, the term "polycrystalline" refers to structures having x-ray diffraction rocking curve line widths on the order of a few degrees or higher. As used herein, the terms "monocrystalline" or "single-crystalline" refer to structures having x- ray diffraction rocking curve line widths at least one order of magnitude lower than the order of a few degrees.
[0072] Additional or alternative differences in crystal quality may be used to distinguish between single-crystalline (or monocrystalline) and polycrystalline structures. As used herein, the term "polycrystalline" refers to structures having multiple grains. As described and used herein, the terms "monocrystalline" or "single crystalline" may refer to structures having multiple domains.
[0073] In some cases, the epitaxial growth procedure is implemented under a nitrogen-rich condition. For example, the nitrogen-to-metal flux ratio may be set in an act 630 in which the nitrogen flow is controlled. In some cases, the unbalanced flux ratio may be set to a highly or extremely nitrogen (N)-rich condition, such as a N-to-metal flux ratio of 2-to- 1 or higher.
[0074] Control of the flux ratio between metal and nitrogen sources may be useful for improving the material quality of the Ill-nitride-based or other polar semiconductor layer. For instance, the N-rich growth conditions may be useful in connection with the growth of ScAIN to avoid Sc-AI intermetallic, Sc3AIN perovskite phase formation, and/or other defects.
[0075] In some cases, the single-crystalline polar semiconductor layer may then be annealed in an act 632. The annealing may be implemented at a temperature greater than the growth temperature. In some cases, the annealing temperature falls in a range from about 700 Celsius to about 1500 degrees Celsius. In other cases, the polar semiconductor layer is not annealed at such high temperatures to remain compatible with CMOS components of the device being fabricated.
[0076] Such post-growth high-temperature annealing of ScAIN may be performed in-situ in the same growth chamber (e.g., the same MBE chamber) in an act 634. In other cases, the annealing is performed ex-situ in a chamber directed to annealing procedures. The annealing process may be implemented under high vacuum in an act 636 (e.g., in-situ in the growth chamber). In other cases, the annealing may be implemented either with nitrogen plasma radiation or under nitrogen gas flow in an act 638. [0077] The method 600 may include an act 640 in which one or more layers (e.g., semiconductor layers) are formed after growth of the wurtzite structure. As a result, the layer(s) may be in contact with the wurtzite structure. For instance, one or more Ill-nitride (e.g., GaN or AIGaN) or other semiconductor layers may be epitaxially grown in an act 642. The act 642 may be implemented in the same epitaxial growth chamber used to grow the wurtzite structure. As a result, the substrate (and heterostructure) is not removed from the epitaxial growth chamber between implementing the acts 622 and 640.
[0078] Alternatively or additionally, the act 640 includes an act 644 in which one or more metal or other conductive layers or structures are formed. For example, a metal layer may be deposited on the polar semiconductor layer, in which case the polar semiconductor layer is disposed between, and in contact with, two metal layers. The layers or structures may be deposited or otherwise formed. In some cases, the conductive structure is configured as an upper or top contact. For instance, the conductive structure may be a gate.
[0079] In some cases, the method 600 includes an act 646, in which the substrate is removed. The substrate may be partially or fully removed. With the substrate fully removed, the heterostructure becomes freestanding. In some cases, the act 646 includes implementation of an etching procedure, such as a wet or dry etch procedure. Alternatively or additionally, the substrate is removed mechanically. The manner in which the substrate is removed may thus vary accordingly.
[0080] The method 600 may include fewer, additional, or alternative acts. For example, one or more acts may be directed to forming other structures or regions of the device that includes the heterostructure. The nature of the regions or structures may vary in accordance with the nature of the device. In another example, the method 600 does not include an act 618 in which an oxide layer is removed from a metal layer or structure because, for instance, the heterostructure is not exposed to the ambient between formation of the metal layer and growth of the polar semiconductor layer.
[0081] The order of the acts of the method 600 may differ from the example shown in Figure 6. For example, contacts and/or other structures formed in the act 610 may be implemented after the growth of the ferroelectric layer.
[0082] A wide variety of devices may be fabricated by the method 600 of Figure 6, and/or another method of fabricating a heterostructure having a polar semiconductor layer as described herein. For example, the ferroelectric ScAIN or other alloy of a Ill-nitride material may be useful in various types of nonvolatile memory devices (e.g., FeRAM, FeFET, FTJ, and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe- HEMT, Fe-capacitor, and SAW devices), various types of photodetection, photovoltaic and optoelectronic devices (e.g., self-driven photodetector and solar cell devices), and various homojunction devices (e.g., devices that use a laterally distributed charge plate to tune the Fermi level in adjacent layers). Still other types of devices may be fabricated, including, for instance, FE-based thin-film bulk acoustic wave resonators (FBAR) devices.
[0083] A number of example devices are described below. In some cases, the device includes a CMOS component (e.g., a CMOS transistor or diode). As described herein, the CMOS component may include a structure that supports the polar semiconductor layer.
[0084] Figure 7 depicts a number of example heterostructures having a polar semiconductor layer grown via low temperature epitaxy. In these cases, multilayer nitride heterostructures are grown on metal electrodes, but Si or other substrates/templates may be used in other cases (e.g., in examples involving multi-mode, high-frequency, and low-loss acoustic resonators and filters, memory electronics, MEMS/NEMS, as well as various flexible nitride devices). As described herein, the metal electrodes serve as a template for the polar semiconductor layer and may correspond with a layer or structure of a CMOS component of a device. The quasi three-dimensional growth at low temperatures described herein (e.g., under N-rich conditions) releases the stress in the multilayer structures. The three example heterostructures include an AIGaN/AIN heterostructure bilayer grown on an Al/Si template, a ScAIN/AIN bilayer heterostructure grown on a Mo/Si template, and an AIN/ScAIN/AIN trilayer heterostructure grown on a Mo/Si template.
[0085] Parts d-f of Figure 7 show the surface morphology of the three multilayer structures grown at 100 degrees Celsius. No obvious cracks were observed on any of the examples, indicating that the stress between each layer has been released. On the other hand, no other high energy electron diffraction (RHEED) patterns were observed at the end of growth for all of the examples, except for the RHEED patterns for a wurtzite structure. This indicates that all of the low temperature grown multilayers maintain a well-defined wurtzite crystal structure, which was also confirmed by XRD measurements. Therefore, the low temperature epitaxy method is useful for the growth of monocrystalline multilayer nitride heterostructures.
[0086] Additionally, for the structure shown in Figure 7, part c, the ScAIN layer may be made ferroelectric. Therefore, the polarity of the ScAIN layer can be poled (changing from metal polar to nitrogen polar, vice versa) while the polarity of the AIN layer remains the same. Such a unique design allows for the design and development of reconfigurable electronic, acoustic, and photonic devices. Multi-layer structures may also include many stacks of AIN/ScAIN, metal/ScAIN, metal/AIN, GaN/AIN, GaN/ScAIN, 2D TMD/ScAIN, or other periodic structures including rare-earth elements doped Ill-nitrides. In many cases, the rare-earth elements doped Ill-nitrides are designed to be ferroelectric, but in other cases, enhanced piezoelectric and/or optical properties may be utilized in the multi-layer structures. In addition, thicknesses of the multi-layer structures may vary. For instance, for acoustic filters/resonators related applications, the thickness may fall in a range around 100 nm, whereas the thicknesses may be on the nanometer scale for memory and/or quantum related applications.
[0087] Figure 8 depicts examples of (a) Ga-polar and (b) N-polar AI(Ga,ln)N/GaN high electron mobility transistor (HEMT) devices having a polar semiconductor layer grown using a low growth temperature. In these examples, the polar semiconductor layer is composed of AIN. The AIN layer may be grown in situ (e.g., in the same growth chamber used to grow the underlying layer) as described herein. In these examples, the polar semiconductor layer is configured as a high-k gate dielectric layer of the HEMT devices.
[0088] Figure 9 depicts examples of transistor structures using a low temperature grown polar semiconductor layer as a dielectric layer. In these examples, the polar semiconductor layer is composed of AIN or ScAIN. The dielectric layer is disposed adjacent a channel layer composed of, or otherwise including, a two-dimensional (2D) material, such as hexagonal BN (hBN). Those and other aspects of the transistor structures may vary. For instance, the example shown in part a of Figure 9 has a global (back) gate structure, while the example shown in part (b) has a local (top) gate structure.
[0089] Figure 10 depicts an example of an AIN-based transistor device having one or more low temperature grown AIN-based layers. In this case, the transistor includes source and drain contacts spaced from an n-type AIN body region by respective polarization-graded AIGaN layers. Each AIGaN layer may be grown as described herein.
[0090] Figure 11 depicts an example of a high power AI(Ga)N P-l-N diode having one or more low temperature grown AIN-based layers. In this case, p- and n- AI(Ga) layers can be grown under low temperature or high temperature, while the intrinsic (i)-AI(Ga)N layer is grown at low temperature. Growth of the i-AI(Ga)N layer at low temperature as described herein helps improve the breakdown voltage of the diode for the reasons set forth above.
[0091] Figure 12 depicts an example of a high power AI(Ga)N Schottky diode having one or more low temperature grown AIN-based layers. The diode includes an n+-doped AI(Ga)N layer that may be grown under low temperature or high temperature, while an n-type AI(Ga)N layer is grown at low temperature. Growth of the n-type AI(Ga)N layer at low temperature as described herein helps improve the breakdown voltage of the diode for the reasons set forth above.
[0092] Figure 13 depicts an example of a high power AI(Ga)N bipolar transistor having a number of low temperature grown AIN-based layers. The device includes n- and p-type AI(Ga) layers that are grown at low temperature, which will improve the breakdown voltage of the transistor for the reasons set forth above.
[0093] Figure 14 depicts an example of a ferroelectric-transistor random-access memory cell device having a low temperature grown AIN-based layer. In this example, the device includes a capacitor with a low temperature grown ferroelectric ScAIN layer disposed between two metal layers. The device also includes a silicon or GaN based write-read transistor.
[0094] Figure 15 depicts examples of deep ultraviolet LED devices having one or more low temperature epitaxially grown Ill-nitride layers. The example shown in part a of Figure 15 is a AI(Ga)N-based DUV-LED device having a low temperature grown AI(Ga)N buffer layer. The example shown in part b of Figure 15 has a low temperature grown AI(Ga)N-based DUV-LED structure.
[0095] Figure 16 depicts an example of a self-powered photodetector having a low temperature epitaxially grown Ill-nitride layer. In this example, the Ill-nitride layer is a AI(Ga,ln,Sc)N layer configured to act as a light absorption layer.
[0096] Figure 17 depicts three examples of thin film acoustic wave resonator devices having a low temperature grown Ill-nitride layer. In these cases, the Ill-nitride layer is composed of AI(Sc)N and configured to act as a piezolayer. The examples of parts a, b, and c are a bulk resonator, a free-standing resonator based on surface micromachining, and a free-standing resonator based on bulk micromachining, respectively.
[0097] The examples described above demonstrate low temperature epitaxy of singlecrystalline wurtzite phase nitrides utilizing MBE on both GaN and CMOS compatible Al metal electrodes. Highly ordered wurtzite atomic stacking sequence and atomically sharp interface were achieved in a low growth temperature of 100 °C. A polar surface controlled on-site growth mechanism explains the successful epitaxy of single-crystalline polar nitrides under low temperature. Furthermore, growth of wurtzite phase ScAIN with a Sc content up to 0.4 and AIN films on CMOS compatible Al metal electrodes has been achieved by using the proposed on-site epitaxy method. The examples demonstrate the epitaxy of polar nitride semiconductors at an unexplored low temperature regime, which supports integration with CMOS technology and also advanced hybrid and integrated circuits across a wide variety of technology and material platforms.
[0098] As used herein, the terms "atomically smooth" or "atomically smooth surface" may be used herein in connection with a layer of a heterostructure to indicate that the layer has a surface roughness (e.g., a root mean square, or RMS, roughness) less than or on the order of 1 nm. In some cases, the RMS roughness of such atomically smooth layers is less than 1% of the thickness of the layer. The surface roughness may vary in accordance with the growth conditions, parameters, and other aspects of the fabrication processes described and/or referenced herein and/or other processes
[0099] The term "about" is used herein in a manner to include deviations from a specified value that would be understood by one of ordinary skill in the art to effectively be the same as the specified value due to, for instance, the absence of appreciable, detectable, or otherwise effective difference in operation, outcome, characteristic, or other aspect of the disclosed methods and devices.
[00100] The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not to be limiting of the disclosure. Changes, additions and/or deletions may be made to the examples without departing from the spirit and scope of the disclosure.
[00101] The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

What is Claimed is:
1. A method of forming a heterostructure, the method comprising: providing a substrate; forming a template layer of the heterostructure such that the template layer is supported by the substrate; and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the template layer; wherein: the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline; and the non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius.
2. The method of claim 1 , wherein the non-sputtered, epitaxial growth procedure is implemented in nitrogen-rich conditions.
3. The method of claim 1 , wherein forming the template layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the template layer and implementing the non-sputtered, epitaxial growth procedure.
4. The method of claim 1 , wherein forming the template layer comprises implementing a surface treatment procedure to remove oxide from a surface of the template layer.
5. The method of claim 1 , wherein the growth temperature is less than about 300 degrees Celsius.
6. The method of claim 1 , wherein the growth temperature is greater than about 20 degrees Celsius.
7. The method of claim 1 , wherein the growth temperature falls in a range from about
20 degrees Celsius to about 100 degrees Celsius.
8. The method of claim 1 , wherein the polar semiconductor layer comprises a Ill-nitride material or alloy thereof.
9. The method of claim 1 , wherein the polar semiconductor layer comprises AIN or an alloy thereof.
10. The method of claim 1 , wherein the template layer comprises a metal compatible with complementary metal-oxide-semiconductor (CMOS) fabrication.
11. The method of claim 1 , wherein: the template layer comprises GaN; and the polar semiconductor layer comprises AIN or an alloy thereof.
12. A method of fabricating a device, the method comprising: forming a metal structure of a complementary metal-oxide-semiconductor (CMOS) component of the device, the metal structure being supported by a substrate; and after forming the metal structure, implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of a heterostructure of the device, the polar semiconductor layer being supported by the substrate; wherein the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline.
13. The method of claim 12, wherein the non-sputtered, epitaxial growth procedure is implemented at a growth temperature less than about 400 degrees Celsius.
14. The method of claim 12, wherein the non-sputtered, epitaxial growth procedure is implemented in nitrogen-rich conditions.
15. The method of claim 12, wherein the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is configured such that the polar semiconductor layer is in contact with the metal structure.
16. The method of claim 12, wherein forming the metal structure and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal structure and implementing the non-sputtered, epitaxial growth procedure.
17. The method of claim 12, wherein forming the metal structure comprises implementing a surface treatment procedure to remove oxide from a surface of the metal structure.
18. The method of claim 12, further comprising forming a template layer of the heterostructure before implementing the non-sputtered, epitaxial growth procedure such that the polar semiconductor layer is in contact with the template layer.
19. A heterostructure comprising : a substrate; and a polar semiconductor layer supported by the substrate; wherein: the polar semiconductor layer has a single-crystalline, wurtzite crystal structure; and the polar semiconductor layer comprises multiple columnar domains.
20. The heterostructure of claim 19, wherein the polar semiconductor layer comprises AIN or an alloy thereof.
21. The heterostructure of claim 19, wherein the polar semiconductor layer comprises an AIN alloy, the AIN alloy comprising a Group 11 IB element.
22. The heterostructure of claim 19, wherein the polar semiconductor layer is piezoelectric.
23. The heterostructure of claim 19, wherein the polar semiconductor layer is ferroelectric.
24. The heterostructure of claim 19, further comprising a template layer disposed between the substrate and the polar semiconductor layer, the polar semiconductor layer being in contact with the template layer.
25. The heterostructure of claim 24, wherein the template layer and the polar semiconductor layer have opposite polarities.
26. The heterostructure of claim 24, wherein the template layer comprises a metal.
27. The heterostructure of claim 24, wherein a surface of the polar semiconductor layer at an interface with the template layer has an atomically smooth surface.
28. A device comprising: a substrate; a complementary metal-oxide-semiconductor (CMOS) component supported by a substrate, the CMOS transistor comprising a structure; and a polar semiconductor layer supported by the structure; wherein the polar semiconductor layer has a single-crystalline, wurtzite crystal structure.
29. The device of claim 28, wherein the structure comprises metal.
30. The device of claim 28, wherein the polar semiconductor layer comprises multiple columnar domains.
31. The device of claim 28, wherein a surface of the polar semiconductor layer in contact with the structure has an atomically smooth surface.
32. A method of forming a heterostructure, the method comprising: providing a substrate; forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer comprising aluminum; and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the metal layer; wherein: the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline; forming the metal layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal layer and implementing the non-sputtered, epitaxial growth procedure.
33. The method of claim 32, wherein the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is implemented at a growth temperature compatible with complementary metal-oxide-semiconductor (CMOS) fabrication.
34. A method of forming a heterostructure, the method comprising: providing a substrate; forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer comprising molybdenum; and implementing a non-sputtered, epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by, and in contact with, the metal layer; wherein: the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is single-crystalline; forming the metal layer and implementing the non-sputtered, epitaxial growth procedure are implemented in a same chamber such that the heterostructure is not exposed to an ambient between forming the metal layer and implementing the non-sputtered, epitaxial growth procedure.
35. The method of claim 34, wherein the non-sputtered, epitaxial growth procedure is configured such that the polar semiconductor layer is implemented at a growth temperature compatible with complementary metal-oxide-semiconductor (CMOS) fabrication.
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