EP4335052A1

EP4335052A1 - Devices and methods for transmission rate adjustment

Info

Publication number: EP4335052A1
Application number: EP21751664.0A
Authority: EP
Inventors: Aleksei Eduardovich Maevskii; Yumeng Yang; Boris Glebovich ZHENGUROV; Oleg Feat'evich KURMAEV
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-28
Filing date: 2021-05-28
Publication date: 2024-03-13
Also published as: CN117397186A; WO2022250563A1

Abstract

A transceiver apparatus (110) is disclosed, comprising a communication interface (130) configured to communicate with a further transceiver apparatus (160) via a communication link (150) using an adjustable transmission rate. Moreover, the transceiver apparatus (110) further comprises a processing circuitry (120) configured to encode an adjustable number of a plurality of data symbols with a multidimensional multi-level code, including an outer FEC code and an inner FEC code, wherein the outer FEC code is a Reed-Solomon code and the inner FEC code is a Bose, Chaudhuri, and Hocquenghem, BCH, code. The processing circuitry (120) is further configured to modulate the encoded data symbols with a pulse-amplitude modulation, РАМ. Moreover, the processing circuitry (120) is further configured to adjust the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols encoded by the multidimensional multilevel code. Furthermore, a corresponding communication method is disclosed.

Description

DEVICES AND METHODS FOR TRANSMISSION RATE ADJUSTMENT

TECHNICAL FIELD

The present disclosure relates to telecommunications. More specifically, the present disclosure relates to devices and methods for transmission rate adjustment in a communication system.

BACKGROUND

The data transmission rate is one of the fundamental characteristics of the communication between transceivers of a communication system via a communication link. Generally, the data transmission rate is determined by several factors, ranging from technical ones such as the frequency band and the modulation technique, to implementation features such as the complexity of the transceiver. Usually, there is a direct relation between data transmission rate, link budget, and achievable range. Therefore, the capability of adjusting the data transmission rate is a desirable feature of a communication system.

SUMMARY

It is an object of the present disclosure to provide devices and methods for improved transmission rate adjustment in a communication system.

The foregoing and other objects are achieved by the subject matter of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

Generally, embodiments disclosed herein enable an improved rate adaptation (RA). For instance, for communication systems in accordance with the family of standards IEEE

802.3 embodiments disclosed herein provide a larger number of different data transmission rates, which are almost uniformly distributed between the conventional rates of 10G and 5G, 5G and 2.5G, and so on. Embodiments disclosed herein use for the first downshift, i.e. reduction step the same order of modulation as the next higher rate, such as 10G, 5G, and the like. Thus, embodiments disclosed herein allow to avoid a retrain procedure after such a downshift.

More specifically, according to a first aspect a transceiver apparatus is provided, comprising a communication interface configured to communicate with a further transceiver apparatus via a communication link using an adjustable transmission rate. The transceiver apparatus further comprises a processing circuitry configured to encode an adjustable number of a plurality of data symbols with a multidimensional multi-level code, MLC, wherein the MLC includes an outer FEC code and an inner FEC code. The outer FEC code is a Reed-Solomon, RS, code and the inner FEC code is a Bose, Chaudhuri, and Hocquenghem, BCH, code. The processing circuitry of the transceiver apparatus is further configured to modulate the encoded data symbols with a pulse-amplitude modulation, PAM. Moreover, the processing circuitry of the transceiver apparatus is configured to adjust the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols. Thus, advantageously, the transceiver apparatus according to the first aspect allows for a fine-grained adjustment of the data transmission rate.

In a further possible implementation form of the first aspect, the processing circuitry of the transceiver apparatus is configured to encode the adjustable number of the plurality of data symbols with the MLC by encoding an adjustable first portion of the adjustable number of the plurality of data symbols with the outer FEC code and an adjustable second portion of the adjustable number of the plurality of data symbols with the outer FEC code and the inner FEC code.

In a further possible implementation form of the first aspect, the communication link is an Ethernet link (as defined in one or more of the standards of the family of standards IEEE 802.3).

In a further possible implementation form of the first aspect, the BCH code, i.e. the inner FEC code, has a codeword length of 255 symbols with 199 data symbols.

In a further possible implementation form of the first aspect, the RS code, i.e. the outer FEC code, has a codeword length of 360 symbols with 326 data symbols.

In a further possible implementation form of the first aspect, the processing circuitry of the transceiver apparatus is configured to modulate the encoded data symbols using a PAM-4 scheme and/or a PAM-8 scheme. According to a second aspect a method of communicating with a transceiver apparatus via a communication link is provided. The method comprises the steps of: encoding an adjustable number of a plurality of data symbols with a multidimensional multi-level code, MLC, including an outer FEC code and an inner FEC code, wherein the outer FEC code is a Reed-Solomon, RS, code and the inner FEC code is a Bose, Chaudhuri, and Hocquenghem, BCH, code; modulating the encoded data symbols with a pulse-amplitude modulation, PAM, scheme; and adjusting the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols.

In a further possible implementation form of the second aspect, the step of encoding the adjustable number of the plurality of data symbols with the MLC comprises encoding an adjustable first portion of the adjustable number of the plurality of data symbols with the outer FEC code and an adjustable second portion of the adjustable number of the plurality of data symbols with the outer FEC code and the inner FEC code.

In a further possible implementation form of the second aspect, the communication link is an Ethernet link.

In a further possible implementation form of the second aspect, the BCH code, i.e. the inner FEC code, has a codeword length of 255 symbols with 199 data symbols.

In a further possible implementation form of the second aspect, the RS code, i.e. the outer FEC code, has a codeword length of 360 symbols with 326 data symbols.

In a further possible implementation form of the second aspect, the step of modulating the encoded data symbols comprises modulating the encoded data symbols with a PAM-4 scheme and/or a PAM-8 scheme.

According to a third aspect a computer program product is provided, comprising a computer-readable storage medium for storing program code which causes a computer or a processor to perform the method according to the second aspect when the program code is executed by the computer or the processor.

The different aspects of the present disclosure can be implemented in software and/or hardware. Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following embodiments of the present disclosure are described in more detail with reference to the attached figures and drawings, in which:

Fig. 1 is a schematic diagram illustrating a communication system including a transceiver apparatus according to an embodiment communicating with a further transceiver apparatus via a communication link;

Fig. 2 shows a table listing data rates for a plurality of exemplary modulation schemes;

Fig. 3 is a diagram illustrating aspects of a multi-dimensional multi-level code;

Fig. 4 is a schematic diagram illustrating processing blocks implemented by a transceiver apparatus;

Fig. 5 is a schematic diagram illustrating further aspects of the transceiver apparatus and the further transceiver apparatus of figure 1 ;

Figs. 6a-c are schematic diagrams illustrating in more detail processing blocks implemented by the transceiver apparatus according to different embodiments;

Fig. 7 shows a table listing data rates provided by a transceiver apparatus according to an embodiment;

Fig. 8 shows graphs illustrating the bit error rate as a function of the noise for different modulation schemes implemented by a transceiver apparatus according to an embodiment; and

Fig. 9 is a flow diagram illustrating a method of operating a transceiver apparatus according to an embodiment.

In the following identical reference signs refer to identical or at least functionally equivalent features. DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description, reference is made to the accompanying figures, which form part of the disclosure, and which show, by way of illustration, specific aspects of embodiments of the present disclosure or specific aspects in which embodiments of the present disclosure may be used. It is understood that embodiments of the present disclosure may be used in other aspects and comprise structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

For instance, it is to be understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if one or a plurality of specific method steps are described, a corresponding device may include one or a plurality of units, e.g. functional units, to perform the described one or plurality of method steps (e.g. one unit performing the one or plurality of steps, or a plurality of units each performing one or more of the plurality of steps), even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a specific apparatus is described based on one or a plurality of units, e.g. functional units, a corresponding method may include one step to perform the functionality of the one or plurality of units (e.g. one step performing the functionality of the one or plurality of units, or a plurality of steps each performing the functionality of one or more of the plurality of units), even if such one or plurality of steps are not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless specifically noted otherwise.

Figure 1 is schematic diagram illustrating a communication system 100 including a transceiver apparatus 110 according to an embodiment communicating with a further transceiver apparatus 160 via a communication link 150 (also referred to as communication channel 150). The communication link 150 may be a wireless communication link 150 or a wired communication link 150. In an embodiment, the communication link 150 may be an Ethernet link 150 according to one o more standards of the family of standards IEEE 802.3.

As illustrated in figure 1, the transceiver apparatus 110 according to an embodiment comprises a processing circuitry 120 for processing data and a communication interface 130 for transmitting and receiving data via the communication link 150. As will be described in more detail below, the communication interface 130 of the transceiver apparatus 110 is configured to communicate with the further transceiver apparatus 160 (i.e. its communication interface 180) via the communication link 150 using an adjustable transmission rate.

In an embodiment, the communication interface 130 may comprise one or more antennas for wireless communication or a network interface, in particular an Ethernet interface for communicating via the communication link 150. The processing circuitry 120 may be implemented in hardware and/or software. The hardware may comprise digital circuitry, or both analog and digital circuitry. Digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. The transceiver apparatus 110 may further comprise a memory 140, e.g. a Flash memory 140, configured to store executable program code which, when executed by the processing circuitry 110, causes the transceiver apparatus 110 to perform the functions and operations described herein.

Likewise, the further transceiver apparatus 160 may comprise a processing circuitry 170 for processing data, a communication interface 180 for transmitting and receiving data via the communication link 150. In an embodiment, the communication interface 180 may comprise one or more antennas for wireless communication or a network interface, in particular an Ethernet interface for communicating via the communication link 150. The processing circuitry 170 may be implemented in hardware and/or software. The hardware may comprise digital circuitry, or both analogue and digital circuitry. Digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field- programmable arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. The further transceiver apparatus 160 may further comprise a memory 190, e.g. a Flash memory 190, configured to store executable program code which, when executed by the processing circuitry 110, causes the transceiver apparatus 160 to perform the functions and operations described herein.

Before further describing different embodiments of the transceiver apparatus 110 in more detail, in the following some technical background will be introduced.

The data transmission rate, in particular bit rate R may be defined as

R = S (log₂ M) , where B denotes the Nyquist bandwidth, M denotes the order of modulation, k denotes the payload in bits, and n denotes number of bits to be transmitted through the channel 150, i.e. the code length.

For a BASE-T communication system it is known from Ken Naumann, Amrik Bains, “NBASE-T Downshift: Optimization of 2.5Gb/s and 5Gb/s Ethernet Data Rates Over Cat5e/Cat6 Cabling”, NBASE-T Alliance, December 2017 for reducing, i.e. downshifting the data transmission rate to reduce the bandwidth B twice for each step, i.e. 400 MHz, 200 MHz, 100 MHz. Thus, the reduction of the bandwidth B provide a coarse rate adaptation with fixed transmission rates. For providing a more fine-grained rate adaption it is known to either change the modulation order M or the code rate k/n. However, as in practice it is usually desirable to have a large code rate, e.g. larger than 0.8, often only the modulation order M may be adjusted for varying the transmission rate.

However, in a lot of case it is desirable to change the modulation order M between adjacent values thereof, such as from PAM-8 to PAM-16 and vice versa, but not from PAM-4 to PAM-16 or vice versa (which would skip PAM-8). As will be appreciated, the simple change of the modulation order from, for instance, PAM-4 to PAM-8 or from PAM-8 to PAM-16 achieves only one intermediate transmission rate. Thus, in this exemplary case, the series of possible transmission rates with normalized B would be 4, 3, 2, 3/2, 1 , 3/4, 1/2, 3/8, 1/4, and so on, which achieves respective intermediate rates between the conventional rates, namely 7.5 G between 10 G and 5G, 3.75 G between 5 G and 2.5 G, and so on.

An approach for further increasing the number of intermediate rates is disclosed in US 9,363,039 B1. Additional rates appear due to utilizing Double Square (DSQ) constellations, namely 32-DSQ and 128-DSQ in addition to PAM-8 and PAM-16. DSQ allows different mapping. For instance, good Euclidean distance properties allow to subdivide the constellation to cosets (regions). Indices (in bit representation) of these cosets remain uncoded. Points (bits) within cosets are encoded by a low-density parity- check (LDPC) code. The results are listed in the table shown in figure 2. As can be taken from figure 2, there a three intermediate rates between 400 and 200 Mbaud, namely 4.51, 3.92, and 3.23 Gbps with a distribution that is far from uniform.

As will be described in more detail below, embodiments disclosed herein make use of multidimensional coding. More specifically, embodiments disclosed herein make use of (i) concatenated forward error correction (FEC) codes; (ii) multilevel coding and (iii) generalized two-dimensional (2D) modulation.

Multilevel coding is a coded modulation in which each input to the constellation mapper is driven by an independent encoder. The common goal is to optimize the code in Euclidean space rather than dealing with Hamming distance as in classical coding schemes. Further details about multilevel coding can be found in Udo Wachsmann, Robert F. H. Fischer, and Johannes B. Huber, “Multilevel Codes: Theoretical Concepts and Practical Design Rules”, IEEE Trans on Info. Theory, Vol. 45, No. 5, July 1999, pp. 1361 - 1391 , which is herein fully incorporated by reference.

A classical approach to coded modulation is based on mapping by set partitioning, wherein the signal set (constellation) A = {a₀,a₁ of an M = 2^q-ary modulation scheme is successively binary partitioned in q steps defining a mapping of binary addresses x = { x °,x¹, ...,x^q~1} to signal points a_m. Often, the following set partitioning strategy is chosen: maximize the minimum intra-subset Euclidean distance. In the encoder, the binary addresses are usually divided into two parts: the least significant binary symbols (LSB) are FEC encoded and the most significant binary symbols (MSB) (if presented) remain uncoded.

Aharon Vargasl, Wolfgang H. Gerstacker, Marco Breiling, and Gokhan Gul, “Multidimensional Multilevel Coding for Satellite Broadcasting with Highly Flexible QoS”, 2010 IEEE Global Telecommunications Conference GLOBECOM 2010, Miami, FL, USA, 6-10 Dec. disclose a way how to increase the flexibility when designing the levels of a multilevel coding (MLC) system using block labelling (BL) partitioning, which is herein fully incorporated by reference.

A 2D partitioning that may be used for a transceiver apparatus 110 according to an embodiment for PAM 4 and PAM 8 is illustrated in figure 3 and disclosed in L.-F. Wei, ’’Trellis-coded modulation with multidimensional constellations”, IEEE Transaction on Information Theory, Vol.33, July 1987, pp. 483 - 501, which is herein fully incorporated by reference. As will be appreciated, the mapping shown in figure 3 follows from a successive partitioning of a channel-signal set into subsets with increasing minimum distances d₀ < d_t < d₂ < ··· between the signals of these subsets.

As will be described in more detail below, the transceiver apparatus 110 implements a Bose, Chaudhuri, and Hocquenghem (BCH) code as inner code, because these codes demonstrate better performance in comparison with a convolutional code of rate 2/3 (known as trellis coded modulation (TCM)), as illustrated in figure 4.

Figure 5 is a schematic diagram illustrating further aspects implemented by the processing circuitry 121 of the transceiver apparatus 110 and the processing circuitry 170 of the further transceiver apparatus 160 of figure 1. As will be described in more detail below, the processing circuitry 120 of the transceiver apparatus 110 is configured to encode an adjustable number of a plurality of data symbols with a multidimensional multi level code (MLC), including an outer FEC code 121 and an inner FEC code 123a. As illustrated in figure 5, the outer FEC code 121 is a Reed-Solomon code (implemented by the processing block 121) and the inner FEC code 123a is a Bose, Chaudhuri, and Hocquenghem, BCH, code (implemented by the processing block 123a). The multidimensional MLC mapping is illustrated by processing block 123a in figure 5.

The processing circuitry 120 of the transceiver apparatus 110 is further configured to modulate the encoded data symbols with a pulse-amplitude modulation, PAM (illustrated by the processing block 125 in figure 5). As illustrated in figure 5, in an embodiment, the processing circuitry 120 of the transceiver apparatus 110 is configured to modulate the encoded data symbols using PAM-4 and/or PAM-8.

As illustrated in figure 5, the processing circuitry 170 of the further transceiver apparatus 160 is configured to implement processing blocks for performing the "inverse" operations of the processing blocks implemented by the processing circuitry 120 of the transceiver apparatus 110. More specifically, the processing circuitry 170 of the further transceiver apparatus 160 is configured to (i) perform a demapping of the data received from the transceiver apparatus 110 using a PAM, in particular a PAM-4 or a PAM-8 (see processing block 175 of figure 5), and (ii) to decode the demodulated data symbols using the multidimensional MLC (see processing block 173b), including the outer RS code 171 and the inner BCH code 173a.

The processing circuitry 120 of the transceiver apparatus 110 is further configured to adjust the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols encoded by the multidimensional multi-level code. In the embodiment shown in figure 5, the processing circuitry 120 of the transceiver apparatus 110 is configured to encode the adjustable number of the plurality of data symbols with the MLC by encoding an adjustable first portion of the adjustable number of the plurality of data symbols with the outer RS code 121 and an adjustable second portion of the adjustable number of the plurality of data symbols with the outer RS code and the inner BCH code. For instance, as shown in figure 5, one uncoded and three encoded bits are consistent with a code rate of a BCH(255, 199) code and vice versa. As already mentioned above, by controlling the multilevel multidimensional modulation, i.e. the adjustable number of the plurality of data symbols encoded by the multidimensional multi-level code, the transceiver apparatus 110 is configured to obtain a uniform distribution of transmission rates. Due to the multidimensional multilevel coding different groups of bits have different resistances against noise, in particular additive white Gaussian noise (AWGN). In the example shown in figure 5, the MSB (most significant bit, i.e. the zero bit to the left) is quite resistant against AWGN (and therefore reliable) and can be directly provided to the PAM processing block 125. The LSBs (least significant bits, i.e. the three zero bits to the right) are not so well protected, thus they are additionally encoded by the inner (BCH) code 123a and only thereafter the resulting inner codeword (based on the LSBs) is provided to the PAM processing block 125.

Figures 6a-c are schematic diagrams illustrating in more detail processing blocks implemented by the transceiver apparatus 110 according to different embodiments for communication over an Ethernet link. In the embodiments shown in figures 6a-c the inner BCH FEC code has a codeword length of 255 symbols with 199 data symbols and the outer RS FEC code has a codeword length of 360 symbols with 326 data symbols. The embodiments shown in figures 6a-c are based on the standardized structure for BASE-T (where further details may be found). More specifically, figures 6a-c show the bit ordering in the Physical Coding Sublayer (PCS) and illustrate how the bit allocation (highlighted in gray for the LSBs and in white for the MSBs) provided by embodiments disclosed herein forms the IEEE standard frame and allows an improved rate adaptation.

In all of the embodiments shown in figures 6a-c the processing circuitry 120 of the transceiver apparatus 110 provides the elements already described above in the context of figure 5, namely a RS FEC encoder 121 (further including an interleaver), a BCH encoder 123a, a MLC mapping block 123b and the PAM mapping block 125. Furthermore, the processing circuitry 120 of the transceiver apparatus 110 may implement a scrambler 124 and a selectable precoder 126.

In the embodiment shown in figure 6a, two coded bits and two uncoded bits as well as PAM4 are used (referred to herein as 2D MLC PAM4 with scheme 2x2). As can be taken from figure 6a, the RS encoder 121 provides as output: 65x50 (blocks) + 10 OAM +340 (parity) = 3600 bits. The BCH encoder 123a processes: 31x50 (block) + 42 (parity) = 1592 bits. As output the BCH encoder 123a provides: 2040 bits (LSB). In order to obtain a LSB to MSB ratio of 1:1, 32 zero bits are added to the MSBs.

In the embodiment shown in figure 6b, three coded bits and 1 uncoded bit as well as PAM4 are used (referred to herein as 2D MLC PAM4 with scheme 3x1; as in figure 5). As can be taken from figure 6b, the RS encoder 121 provides as output: 65x50 (blocks) + 10 OAM +340 (parity) = 3600 bits. The BCH encoder 123a processes: 51x50 (block) + 37 (parity) = 2587 bits. As output the BCH encoder 123a provides: 3315 bits (LSB). In order to obtain a LSB to MSB ratio of 3:1 , 92 zero bits are added to the MSBs.

In the embodiment shown in figure 6c, four coded bits and 2 uncoded bits as well as PAM8 are used (referred to herein as 2D MLC PAM8 with scheme 4x2). As can be taken from figure 6c, the RS encoder 121 provides as output: 65x50 (blocks) + 10 OAM +340 (parity) = 3600 bits. The BCH encoder 123a processes: 47x50 (block) + 38 (parity) = 2388 bits. As output the BCH encoder 123a provides: 3060 bits (LSB). In order to obtain a LSB to MSB ratio of 2:1, 312 zero bits are added to the MSBs.

Figure 7 shows a table listing data rates provided by the transceiver apparatus 110 according to different embodiments (using the same "notation" as for the embodiments shown in figures 6a-c). As will be appreciated, from the bit rates listed in the table of figure 7 the transceiver apparatus 110 may provide uniformly distributed data rates.

Figure 8 shows graphs illustrating the bit error rate as a function of the noise for different modulation schemes implemented by the transceiver apparatus 110 according to an embodiment. The rates for (b), (d), and (e) are almost uniformly distributed and corresponding noise regions are almost uniformly distributed too. Curve (c) demonstrates a possibility of fine rate adaptation.

Figure 9 is a flow diagram illustrating a method 900 of operating the transceiver apparatus 110 according to an embodiment. The method 900 comprises the steps of: encoding 901 an adjustable number of a plurality of data symbols with a multidimensional multi-level code, MLC, including an outer FEC code and an inner FEC code, wherein the outer FEC code is a Reed-Solomon code and the inner FEC code is a Bose, Chaudhuri, and Hocquenghem, BCH, code; modulating 903 the encoded data symbols with a pulse-amplitude modulation, PAM; and adjusting 905 the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols encoded by the multidimensional multi-level code.

The person skilled in the art will understand that the "blocks" ("units") of the various figures (method and apparatus) represent or describe functionalities of embodiments of the present disclosure (rather than necessarily individual "units" in hardware or software) and thus describe equally functions or features of apparatus embodiments as well as method embodiments (unit = step).

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the described apparatus embodiment is merely exemplary. For example, the unit division is merely logical function division and may be other division in actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented by using some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit.

Claims

1. A transceiver apparatus (110), comprising: a communication interface (130) configured to communicate with a further transceiver apparatus (160) via a communication link (150) using an adjustable transmission rate; and a processing circuitry (120) configured to encode an adjustable number of a plurality of data symbols with a multidimensional multi-level code, MLC, including an outer FEC code (121) and an inner FEC code, wherein the outer FEC code (121) is a Reed-Solomon, RS, code (121) and the inner FEC code is a Bose, Chaudhuri, and Hocquenghem, BCH, code; wherein the processing circuitry (120) is further configured to modulate the encoded data symbols with a pulse-amplitude modulation, PAM (123); wherein the processing circuitry (120) is further configured to adjust the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols.

2. The transceiver apparatus (110) of claim 1 , wherein the processing circuitry ( 20) is configured to encode the adjustable number of the plurality of data symbols with the MLC by encoding an adjustable first portion of the adjustable number of the plurality of data symbols with the outer FEC code and an adjustable second portion of the adjustable number of the plurality of data symbols with the outer FEC code and the inner FEC code.

3. The transceiver apparatus (110) of any one of the preceding claims, wherein the communication link is an Ethernet link.

4. The transceiver apparatus (110) of any one of the preceding claims, wherein the BCH code has a codeword length of 255 symbols with 199 data symbols.

5. The transceiver apparatus (110) of any one of the preceding claims, wherein the RS code has a codeword length of 360 symbols with 326 data symbols.

6. The transceiver apparatus (110) of any one of the preceding claims, wherein the PAM comprises PAM-4 and/or PAM-8.

7. A method (900) of communicating with a transceiver apparatus (160) via a communication link (150), wherein the method (900) comprises: encoding (901) an adjustable number of a plurality of data symbols with a multidimensional multi-level code, MLC, including an outer FEC code and an inner FEC code, wherein the outer FEC code is a Reed-Solomon, RS, code and the inner FEC code is a Bose, Chaudhuri, and Hocquenghem, BCFI, code; modulating (903) the encoded data symbols with a pulse-amplitude modulation, PAM; and adjusting (905) the adjustable transmission rate by adjusting the adjustable number of the plurality of data symbols.

8. The method (900) of claim 7, wherein encoding the adjustable number of the plurality of data symbols with the MLC comprises encoding an adjustable first portion of the adjustable number of the plurality of data symbols with the outer FEC code and an adjustable second portion of the adjustable number of the plurality of data symbols with the outer FEC code and the inner FEC code.

9. The method (900) of claim 7 or 8, wherein the communication link (150) is an Ethernet link (150).

10. The method (900) of any one of claims 7 to 9, wherein the BCH code has a codeword length of 255 symbols with 199 data symbols.

11. The method (900) of any one of claims 7 to 10, wherein the RS code has a codeword length of 360 symbols with 326 data symbols.

12. The method (900) of any one of claims 7 to 11 , wherein the PAM comprises PAM- 4 and/or PAM-8.

13. A computer program product comprising a computer-readable storage medium for storing program code which causes a computer or a processor to perform the method (900) of any one of claims 7 to 12 when the program code is executed by the computer or the processor.