EP4315045A4 - Parallelverarbeitungsarchitektur mit spekulativer kodierung - Google Patents

Parallelverarbeitungsarchitektur mit spekulativer kodierung

Info

Publication number
EP4315045A4
EP4315045A4 EP22776686.2A EP22776686A EP4315045A4 EP 4315045 A4 EP4315045 A4 EP 4315045A4 EP 22776686 A EP22776686 A EP 22776686A EP 4315045 A4 EP4315045 A4 EP 4315045A4
Authority
EP
European Patent Office
Prior art keywords
speculative
coding
parallel processing
processing architecture
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP22776686.2A
Other languages
English (en)
French (fr)
Other versions
EP4315045A1 (de
Inventor
Peter Foley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ascenium Inc
Original Assignee
Ascenium Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascenium Inc filed Critical Ascenium Inc
Publication of EP4315045A1 publication Critical patent/EP4315045A1/de
Publication of EP4315045A4 publication Critical patent/EP4315045A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G06F8/4451—Avoiding pipeline stalls
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
EP22776686.2A 2021-03-26 2022-03-25 Parallelverarbeitungsarchitektur mit spekulativer kodierung Withdrawn EP4315045A4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163166298P 2021-03-26 2021-03-26
PCT/US2022/021838 WO2022204450A1 (en) 2021-03-26 2022-03-25 Parallel processing architecture using speculative encoding

Publications (2)

Publication Number Publication Date
EP4315045A1 EP4315045A1 (de) 2024-02-07
EP4315045A4 true EP4315045A4 (de) 2025-01-29

Family

ID=83397932

Family Applications (1)

Application Number Title Priority Date Filing Date
EP22776686.2A Withdrawn EP4315045A4 (de) 2021-03-26 2022-03-25 Parallelverarbeitungsarchitektur mit spekulativer kodierung

Country Status (3)

Country Link
EP (1) EP4315045A4 (de)
KR (1) KR20230159596A (de)
WO (1) WO2022204450A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11269642B2 (en) * 2019-09-20 2022-03-08 Microsoft Technology Licensing, Llc Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor
KR20250101126A (ko) 2023-12-27 2025-07-04 주식회사 지엠디소프트 로컬 컴퓨팅 환경에서 ai 모델 추론 스케줄링 장치 및 방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8949806B1 (en) * 2007-02-07 2015-02-03 Tilera Corporation Compiling code for parallel processing architectures based on control flow

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6059413B2 (ja) * 2005-04-28 2017-01-11 クアルコム，インコーポレイテッド 再構成可能命令セル・アレイ
GB201001621D0 (en) * 2010-02-01 2010-03-17 Univ Catholique Louvain A tile-based processor architecture model for high efficiency embedded homogenous multicore platforms
KR102070199B1 (ko) * 2012-05-11 2020-01-28 삼성전자주식회사 재구성가능 프로세서 및 재구성가능 프로세서의 코드 압축해제 방법
US20150268963A1 (en) * 2014-03-23 2015-09-24 Technion Research & Development Foundation Ltd. Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware
US20160246602A1 (en) * 2015-02-19 2016-08-25 Arizona Board Of Regents On Behalf Of Arizona State University Path selection based acceleration of conditionals in coarse grain reconfigurable arrays (cgras)

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8949806B1 (en) * 2007-02-07 2015-02-03 Tilera Corporation Compiling code for parallel processing architectures based on control flow

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2022204450A1 *
SOO-MOOK MOON ET AL: "Performance analysis of tree VLIW architecture for exploiting branch ILP in non-numerical code", PROCEEDINGS OF THE 1997 INTERNATIONAL CONFERENCE ON SUPERCOMPUTING. VIENNA, JULY 7 - 11, 1997; [PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SUPERCOMPUTING], NEW YORK, ACM, US, 11 July 1997 (1997-07-11), pages 301 - 308, XP058242361, ISBN: 978-0-89791-902-9, DOI: 10.1145/263580.263653 *

Also Published As

Publication number Publication date
WO2022204450A1 (en) 2022-09-29
EP4315045A1 (de) 2024-02-07
KR20230159596A (ko) 2023-11-21

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