Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
  • H02M1/007—Plural converter units in cascade
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
  • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J7/007—Regulation of charging or discharging current or voltage
  • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
  • H02J7/007182—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters in response to battery voltage
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0048—Circuits or arrangements for reducing losses
  • H02M1/0054—Transistor switching losses
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0083—Converters characterised by their input or output configuration
  • H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
  • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M3/00—Conversion of dc power input into dc power output
  • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
  • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
  • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
  • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J2207/20—Charging or discharging characterised by the power electronics converter
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J2207/30—Charge provided using DC bus or data bus of a computer

Definitions

• Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to methods and apparatus for converting power using a multioutput switched-mode power supply (SMPS) coupled to a multi-cell-in-series battery.
• SMPS switched-mode power supply
• a voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage.
• Voltage regulators may be classified as linear regulators or switching regulators. While linear regulators tend to be relatively compact, many applications may benefit from the increased efficiency of a switching regulator.
• a linear regulator may be implemented by a low-dropout (LDO) regulator, for example.
• LDO low-dropout
• a switching regulator also known as a “switching converter” or “switcher”
• SMPS switched-mode power supply
• a buck converter is a type of SMPS typically comprising: (1) a high-side switch coupled between a relatively higher voltage rail and a switching node, (2) a low-side switch coupled between the switching node and a relatively lower voltage rail, (3) and an inductor coupled between the switching node and a load (e.g., represented by a shunt capacitive element).
• the high-side and low-side switches are typically implemented with transistors, although the low-side switch may alternatively be implemented with a diode.
• a charge pump is a type of SMPS typically comprising at least one switching device to control the connection of a supply voltage across a load through a capacitor.
• a voltage doubler also referred to as a “multiply-by-two (X2) charge pump”
• the capacitor of the charge pump circuit may initially be connected across the supply, charging the capacitor to the supply voltage.
• the charge pump circuit may then be reconfigured to connect the capacitor in series with the supply and the load, doubling the voltage across the load. This two-stage cycle is repeated at the switching frequency for the charge pump.
• Charge pumps may be used to multiply or divide voltages by integer or fractional amounts, depending on the circuit topology.
• Power management integrated circuits are used for managing the power scheme of a host system and may include and/or control one or more voltage regulators (e.g., buck converters or charge pumps).
• a PMIC may be used in battery-operated devices, such as mobile phones, tablets, laptops, wearables, etc., to control the flow and direction of electrical power in the devices.
• the PMIC may perform a variety of functions for the device such as DC-to-DC conversion (e.g., using a voltage regulator as described above), battery charging, power-source selection, voltage scaling, power sequencing, etc.
• Certain aspects of the present disclosure generally relate to a multi-output switched-mode power supply (SMPS) circuit coupled to a multi-cell-in-series battery, such as a dual-output three-level buck converter coupled to a two-cell-in-series (2S) battery.
• SMPS switched-mode power supply
• Such a circuit may alternatively function in reverse as a multi-input SMPS circuit receiving power from a multi-cell-in-series battery, such as a 2S battery coupled to a dual-input two-level boost converter.
• the power supply circuit generally includes a switched-mode power supply circuit having an input node and an output node, a battery comprising multiple cells connected in series, a charge pump circuit having a first terminal and a second terminal, the second terminal of the charge pump circuit being coupled to the battery, a first switch coupled between the output node of the switched-mode power supply circuit and the first terminal of the charge pump circuit, and a second switch coupled between the output node of the switched-mode power supply circuit and the second terminal of the charge pump circuit.
• Certain aspects of the present disclosure provide a power management integrated circuit (PMIC) comprising at least a portion of the power supply circuit described above.
• PMIC power management integrated circuit
• Certain aspects of the present disclosure provide a battery charging circuit comprising the power supply circuit described above.
• the power supply circuit generally includes a switched-mode power supply circuit having an input node and an output node, a charge pump circuit having a first terminal and a second terminal, a first switch coupled between the output node of the switched-mode power supply circuit and the first terminal of the charge pump circuit, and a second switch coupled between the output node of the switched-mode power supply circuit and the second terminal of the charge pump circuit.
• Certain aspects of the present disclosure are directed to a method of supply power.
• the method generally includes operating a switched-mode power supply circuit and selectively routing a current through a first switch coupled between a first node of the switched-mode power supply circuit and a first terminal of a charge pump circuit or through a second switch coupled between the first node of the switched-mode power supply circuit and a second terminal of the charge pump circuit.
• FIG. 1 is a block diagram of an example device comprising a power management system that includes a switched-mode power supply (SMPS) circuit and a battery charging circuit, in which aspects of the present disclosure may be practiced.
• SMPS switched-mode power supply
• FIG. 2A is a block diagram of an example power supply circuit with a single-output SMPS and a charge pump for charging a two-cell-in-series (2S) battery.
• FIGs. 2B and 2C are block diagrams of an example power supply circuit with a dual-output SMPS and a charge pump for charging a 2S battery, illustrating different power paths, in accordance with certain aspects of the present disclosure.
• FIGs. 2D and 2E are block diagrams of the example power supply circuit of FIGs. 2B and 2C operating in reverse as a dual-input SMPS receiving power from the 2S battery with different power paths, in accordance with certain aspects of the present disclosure.
• FIG. 3 is an example graph of normalized current ripple versus duty cycle for a two-level buck converter and for a three-level buck converter.
• FIG. 4 is a flow diagram of example operations for supplying power, in accordance with certain aspects of the present disclosure.
• identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.
• Certain aspects of the present disclosure provide techniques and apparatus for converting power using a multi-output switched-mode power supply (SMPS) coupled to a multi-cell-in-series battery, such as charging a two-cell-in-series (2S) battery using a dual-output three-level buck converter coupled thereto.
• SMPS switched-mode power supply
• Such a power supply circuit may alternatively function in reverse as a multi-input SMPS circuit receiving power from a multi-cell-in-series battery, such as a dual-input two-level boost converter charging another device from a 2S battery.
• connection in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element ).
• connection may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).
• circuits disclosed herein may be used in any of various suitable apparatus, such as in the power supply, battery charging circuit, or power management circuit of a communication system, a video codec, audio equipment such as music players and microphones, a television, camera equipment, and test equipment such as an oscilloscope.
• Communication systems intended to be included within the scope of the present disclosure include, by way of example only, cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), and the like.
• FIG. 1 illustrates an example device 100 in which aspects of the present disclosure may be implemented.
• the device 100 may be a battery-operated device such as a cellular phone, a PDA, a handheld device, a wireless device, a laptop computer, a tablet, a smartphone, a wearable device, etc.
• the device 100 may include a processor 104 that controls operation of the device 100.
• the processor 104 may also be referred to as a central processing unit (CPU).
• Memory 106 which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 104.
• a portion of the memory 106 may also include non-volatile random access memory (NVRAM).
• the processor 104 typically performs logical and arithmetic operations based on program instructions stored within the memory 106.
• the device 100 may also include a housing 108 that may include a transmitter 110 and a receiver 112 to allow transmission and reception of data between the device 100 and a remote location.
• the transmitter 110 and receiver 112 may be combined into a transceiver 114.
• One or more antennas 116 may be attached or otherwise coupled to the housing 108 and electrically connected to the transceiver 114.
• the device 100 may also include (not shown) multiple transmitters, multiple receivers, and/or multiple transceivers.
• the device 100 may also include a signal detector 118 that may be used in an effort to detect and quantify the level of signals received by the transceiver 114.
• the signal detector 118 may detect such signal parameters as total energy, energy per subcarrier per symbol, and power spectral density, among others.
• the device 100 may also include a digital signal processor (DSP) 120 for use in processing signals.
• DSP digital signal processor
• the device 100 may further include a battery 122, which may be used to power the various components of the device 100 (e.g., when another power source — such as a wall adapter or a wireless power charger — is unavailable).
• the battery 122 may comprise a single cell or multiple cells connected in series.
• the device 100 may also include a power management system 123 for managing the power from the battery 122, a wall adapter, and/or a wireless power charger to the various components of the device 100.
• the power management system 123 may perform a variety of functions for the device such as DC-to-DC conversion, battery charging, power-source selection, voltage scaling, power sequencing, etc.
• the power management system 123 may include a power management integrated circuit (power management IC or PMIC) 124 and one or more power supply circuits, such as a battery charger 125, which may be controlled by the PMIC.
• a power management integrated circuit power management IC or PMIC
• PMIC power management integrated circuit
• the power supply circuits such as a battery charger 125, which may be controlled by the PMIC.
• at least a portion of one or more of the power supply circuits may be integrated in the PMIC 124.
• the PMIC 124 and/or the one or more power supply circuits may include at least a portion of a switched-mode power supply (SMPS) circuit, which may be implemented by any of various suitable SMPS circuit topologies, such as a buck converter, a buck-boost converter, a three-level buck converter, or a charge pump, such as a multiply-by-two (X2) or multiply-by-three (X3) charge pump.
• SMPS switched-mode power supply
• the various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.
• Battery charging systems e.g., the battery charger 125 of FIG. 1 are trending towards higher charging current, which leads to the desire for higher efficiency converters that can operate over a wider battery voltage range. To reduce thermal issues and/or conserve power, it may be desirable to operate such battery charging systems with higher efficiency.
• the master charger is implemented based on a buck converter topology.
• the master charger is capable of charging a battery (e.g., the battery 122) and providing power by itself or may be paralleled with one or more slave chargers.
• Each of the slave chargers may be implemented, for example, as a switched-capacitor converter (e.g., a divide-by-two (Div2) charge pump) or a switched-mode power supply (SMPS) topology using an inductor (e.g., a buck converter).
• a switched-capacitor converter e.g., a divide-by-two (Div2) charge pump
• SMPS switched-mode power supply
• Charge pump converters may provide a more efficient alternative than buck converters.
• a power supply system for charging a 2S battery may include, for example, a buck converter followed by a boost converter, or a buck converter followed by a charge pump capable of voltage multiplying by two (X2).
• An X2 charge pump may also be capable of dividing by two (Div2) when discharging the 2S battery in the opposite direction (i.e., in reverse).
• a battery charging circuit with this multiply-by-two and divide-by-two charge pump capability may be referred to as an “X2/D2” circuit.
• FIG. 2A is a block diagram of an example power supply circuit 200 with a single-output SMPS 210 and a charge pump 214 (e.g., an X2/D2 charge pump) for charging a multi-cell battery 230 (e.g., a 2S battery). While the charge pump 214 is generally described herein with the example of an X2/D2 charge pump, it is to be understood that the charge pump may be implemented with other configurations, such as an X3/D3 charge pump.
• a charge pump 214 e.g., an X2/D2 charge pump
• the power source for the charge pump 214 may come from a first power supply node 213 (labeled “VBATI”), which may come from the SMPS 210 (e.g., in a power management circuit, such as the PMIC 124), or from a second power supply node 215 (labeled “VBAT2”), which may come from the battery 230. As illustrated in FIG.
• a wall adapter or other power cable e.g., a Universal Serial Bus (USB) adapter 201
• USB Universal Serial Bus
• the USB source may supply a voltage VUSB of 5 V with a USB standard downstream port, charging downstream port, or dedicated charging port (SDP/CDP/DCP) or USB Type-C, 9 to 12 V with Quick Charge (QC) 2.0/3.0/4.0, or 15 to 20 V with a USB power delivery (PD) adapter.
• the wireless (WLS) source in transmit mode (Tx) may supply a voltage VWLS of 5 V with Qi Baseline Power Profile (BPP), 15 V with Qi Extended Power Profile (EPP), or 20 V with other modes, for instance.
• the SMPS 210 may include any of various suitable switching converters, such as a two-level buck converter or a three-level buck converter. To implement a three-level buck converter topology, as shown in FIG. 2A, the SMPS 210 may include a first transistor QI, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a flying capacitive element CFLY, an inductive element LI, and a shunt capacitive element Cour.
• Transistor Q2 may be coupled to transistor QI via a first node (labeled “CFH” for flying capacitor high node), transistor Q3 may be coupled to transistor Q2 via a second node (labeled “VSW” for voltage switching node), and transistor Q4 may be coupled to transistor Q3 via a third node (labeled “CFL” for flying capacitor low node).
• the transistors Q1-Q4 may be implemented as n-type metal-oxide- semiconductor (NMOS) transistors, as illustrated in FIG. 2A.
• the drain of transistor Q2 may be coupled to the source of transistor QI
• the drain of transistor Q3 may be coupled to the source of transistor Q2
• the drain of transistor Q4 may be coupled to the source of transistor Q3.
• the source of transistor Q4 may be coupled to a reference potential node (e.g., electric ground) for the power supply circuit 200.
• the flying capacitive element CFLY may have a first terminal coupled to the first node and a second terminal coupled to the third node.
• the inductive element LI may have a first terminal coupled to the second node and a second terminal coupled to an output voltage node (labeled “VPHI”).
• Certain aspects may include an optional transistor (labeled “QBAT1”) disposed between the VPHI node and the first power supply node (VBATI).
• the transistor QBAT1 may be implemented by an NMOS transistor, as shown, and may serve to control current flow and/or protect one or more elements in the power supply circuit 200.
• Control logic may control operation of the power supply circuit 200.
• the control logic may control operation of the transistors Q1-Q4 via output signals to the inputs of respective gate drivers 2061-2064 (collectively referred to as “gate drivers 206”).
• the outputs of the gate drivers 206 are coupled to respective gates of transistors Q1-Q4.
• the control logic may cycle through four different phases, which may differ depending on whether the duty cycle is less than 50% or greater than 50%.
• a first phase (referred to as a “charging phase”), transistors QI and Q3 are activated, and transistors Q2 and Q4 are deactivated, to charge the flying capacitive element CFLY and to energize the inductive element LI.
• a second phase (called a “holding phase”), transistor QI is deactivated, and transistor Q4 is activated, such that the VSW node is connected to the reference potential node, the flying capacitive element CFLY is disconnected (e.g., one of the CFLY terminals is floating), and the inductive element LI is deenergized.
• a third phase (referred to as a “discharging phase”), transistors Q2 and Q4 are activated, and transistor Q3 is deactivated, to discharge the flying capacitive element CFLY and to energize the inductive element LI.
• a fourth phase also referred to as a “holding phase”
• transistor Q3 is activated, and transistor Q2 is deactivated, such that the flying capacitive element CFLY is disconnected and the inductive element LI is deenergized.
• Operation of the three-level buck converter with a duty cycle greater than 50% is similar in the first and third phases, with the same transistor configurations.
• transistor Q3 is deactivated, and transistor Q2 is activated, such that the VSW node is coupled to an input voltage node (labeled “MID”) of the SMPS 210, the flying capacitive element CFLY is disconnected, and the inductive element LI is energized.
• transistor QI is activated
• transistor Q4 is deactivated, such that the flying capacitive element CFLY is disconnected and the inductive element LI is energized.
• the SMPS 210 may convert the input voltage of 5 to 20 V power at the input node to a range of 3 to 4.5 V, for example, at the SMPS output node (labeled “VPHI”).
• the charge pump 214 may then double this voltage to a range of 6 to 9 V (for an X2/D2 charge pump) to charge the battery 230.
• the SMPS 210 may also operate in reverse as a (two-level) boost converter to supply power from the battery 230 to the USB port 202 and/or wireless power loop 205 in a reverse charging mode (e.g., supplying 5 V to VUSB in USB On-the-Go (OTG) or 10 V to VWLS for reverse WLS charging).
• a reverse charging mode e.g., supplying 5 V to VUSB in USB On-the-Go (OTG) or 10 V to VWLS for reverse WLS charging).
• This power supply circuit architecture in FIG. 2A offers flexibility for IS battery charging (e.g., without or disabling the charge pump 214) or for 2S battery charging (e.g., with or enabling the X2/D2 charge pump).
• SMPS 210 as a three-level buck converter halves the amplitude of the switching node (labeled “VSW”) and doubles the effective switching frequency, which allows for using an inductor with a smaller inductance, and thus offers lower DC resistance (DCR) and higher efficiency.
• VSW switching node
• DCR DC resistance
• This architecture offers good efficiency with input voltages (at the MID node) of 5 to 9 V for an output voltage VPHI of 3 to 4.5 V (at or near 50% duty cycle), but may have lower efficiency with input voltages of 15 to 20 V.
• a three-level buck converter may operate with a 20-30% duty ratio, which results in higher inductor current ripple (as shown in the graph 300 of FIG. 3, compared to a 50% duty cycle) and lower efficiency.
• an optional parallel charger 216 may be enabled to provide power from the USB input node (labeled “USB IN”) at VUSB or the wireless power input node (labeled “WLS_IN”) at VWLS to the second power supply node 215 at VBAT2 in certain cases (e.g., with input voltages of 15 to 20 V). For some cases, however, the efficiency may be unacceptably low when no such parallel charger 216 is present.
• USB IN the USB input node
• WLS_IN wireless power input node
• the efficiency of charging a multi-cell-in-series battery with the power supply circuit 200 of FIG. 2A may not be as ideal as possible. Accordingly, certain aspects of the present disclosure provide techniques and apparatus for charging a multi-cell-in-series battery with higher efficiency.
• FIG. 2B is a block diagram of an example power supply circuit 250 with a dual-output SMPS 260 and the charge pump 214 for charging the battery 230.
• the power supply circuit 250 adds two switches (which may be implemented by transistors QPH1 and QPH2 as depicted) to the power supply circuit 200 of FIG. 2A.
• One path through a first switch (e.g., through transistor QPH1) provides a first output of the dualoutput SMPS 260, which is similar to the output of the SMPS 210 of FIG. 2A.
• the other path through a second switch (e.g., through transistor QPH2) provides a second output of the SMPS 260, which can selectively connect the output node 270 (labeled “VOUT”) to the second power supply node 215 with VBAT2, bypassing the charge pump
• VMID ⁇ VBAT2 e.g., with 5 V USB or WLS BPP Tx
• the first switch transistor QPH1
• the second switch transistor QPH2
• the SMPS 260 is operated in a forward mode to convert the input voltage VMID down to a lower voltage VBATI (e.g., 3 to 4.5 V) at the VPHI node and at the first power supply node 213, and the charge pump 214 is operated in X2 mode to double the voltage VBATI to a higher voltage VBAT2 (e.g., 6 to 9 V) at the second power supply node
• a lower voltage VBATI e.g., 3 to 4.5 V
• the charge pump 214 is operated in X2 mode to double the voltage VBATI to a higher voltage VBAT2 (e.g., 6 to 9 V) at the second power supply node
• the power supply circuit 250 of FIG. 2B can achieve significantly higher efficiency than the power supply circuit 200 of FIG. 2A with higher input voltages.
• the charge pump 214 is effectively bypassed, such that there is no 1 to 2% efficiency loss through the charge pump in charging the battery.
• the SMPS 260 can operate in a reverse mode as a dual-input (two- level) boost converter.
• current can be routed from the battery 230 via a third path 276 through the second switch (e.g., transistor QPH2) such that the voltage VBAT2 at the second power supply node 215 can be boosted by the SMPS 260 to supply the MID node for reverse charging of devices connected to the USB port 202 or inductively coupled to the wireless power loop 205.
• current can be routed from the battery 230 via a fourth path 278 through the first switch (e.g., transistor QPH1) such that the voltage VBATI at the first power supply node 213 can be boosted by the SMPS 260 to supply the MID node for reverse charging of devices.
• the efficiency can be greater than when boosting VBATI through the first switch, according to the conversion ratios (and associated inductor current ripple) of the examples provided herein.
• the example power supply circuit 250 is capable of charging a 2S battery, although it is to be understood that the scope of the present disclosure includes batteries with more than two cells (e.g., three-cell-in-series (3S), four-cell-in-series (4S) batteries, or //-cell-in-series, where n is an integer greater than 1).
• batteries with more than two cells e.g., three-cell-in-series (3S), four-cell-in-series (4S) batteries, or //-cell-in-series, where n is an integer greater than 1).
• the power supply circuit 250 has a dual-output SMPS 260 with a charge pump 214 between the two different outputs (e.g., between VBATI and VBAT2)
• a charge pump 214 between the two different outputs (e.g., between VBATI and VBAT2)
• the scope of the present disclosure includes a multi-output SMPS (e.g., a three-output SMPS for a 3S battery) with multiple switches for selecting between the different outputs (e.g., VBATI, VBAT2, and VBAT3 for a 3S battery) and a charge pump between each pair of outputs (e.g., a X1.5/D1.5 charge pump between VBAT2 and VBAT3 for a 3S battery).
• FIG. 4 is a flow diagram of example operations 400 for supplying power, in accordance with certain aspects of the present disclosure.
• the operations 400 may be performed by a power supply circuit (e.g., the power supply circuit 250 of FIGs. 2B- 2E).
• the operations 400 may begin, at block 402, by operating a switched-mode power supply circuit (e.g., the SMPS 260).
• the power supply circuit may selectively route a current through a first switch (e.g., transistor QPH1) coupled between a first node (e.g., the output node 270) of the switched-mode power supply circuit and a first terminal (e.g., coupled to the first power supply node 213) of a charge pump circuit (e.g., the charge pump 214) or through a second switch (e.g., transistor QPH2) coupled between the first node of the switched-mode power supply circuit and a second terminal (e.g., coupled to the second power supply node 215) of the charge pump circuit.
• a first switch e.g., transistor QPH1
• a first terminal e.g., coupled to the first power supply node 213
• a charge pump circuit e.g., the charge pump 214
• a second switch e.g., transistor Q
• the operations 400 may further involve charging a battery (e.g., the battery 230) at optional block 406.
• the operating at block 402 may include operating the switched-mode power supply circuit in a forward mode.
• the battery may comprise multiple cells connected in series.
• the battery may be coupled to the second switch and to the second terminal of the charge pump circuit.
• the selectively routing at block 404 involves closing the first switch and opening the second switch.
• the operations 400 may further include operating the charge pump circuit as a multiply-by-two charge pump from the first terminal to the second terminal of the charge pump circuit.
• the selectively routing at block 404 involves opening the first switch and closing the second switch.
• the operations 400 may further include operating the charge pump circuit as a divide-by-two charge pump from the second terminal to the first terminal of the charge pump circuit.
• the operations 400 may further involve receiving power to charge the battery via at least one of: a port (e.g., the USB port 202) designated for a wired connection and coupled to the switched-mode power supply circuit or a wireless power transceiver (e.g., the wireless power transceiver 204) coupled to the switched-mode power supply circuit.
• a port e.g., the USB port 202 designated for a wired connection and coupled to the switched-mode power supply circuit
• a wireless power transceiver e.g., the wireless power transceiver 204
• the operating at block 402 involves operating the switched-mode power supply circuit in a reverse mode
• the selectively routing at block 404 involves closing the first switch and opening the second switch to route the current from the charge pump circuit through the first switch to the switched-mode power supply circuit.
• the operations 400 further include operating the charge pump circuit as a divide-by-two charge pump from the second terminal to the first terminal of the charge pump circuit.
• the operations 400 further involve receiving power from a battery (e.g., the battery 230).
• the battery may include multiple cells connected in series. The battery may be coupled to the second switch and to the second terminal of the charge pump circuit.
• the operating at block 402 involves operating the switched-mode power supply circuit in a reverse mode
• the selectively routing at block 404 involves opening the first switch and closing the second switch to route the current from a battery through the second switch to the switched-mode power supply circuit.
• the battery may comprise multiple cells connected in series. The battery may be coupled to the second switch and to the second terminal of the charge pump circuit.
• a power supply circuit comprising: a switched-mode power supply circuit having an input node and an output node; a charge pump circuit having a first terminal and a second terminal; a first switch coupled between the output node of the switched-mode power supply circuit and the first terminal of the charge pump circuit; and a second switch coupled between the output node of the switched-mode power supply circuit and the second terminal of the charge pump circuit.
• Aspect 2 The power supply circuit of Aspect 1, further comprising a battery comprising multiple cells connected in series, wherein the second terminal of the charge pump circuit is coupled to the battery.
• Aspect 3 The power supply circuit of Aspect 2, wherein the first switch is configured to be closed and the second switch is configured to be open when an input voltage at the input node is less than a battery voltage of the battery.
• Aspect 4 The power supply circuit of Aspect 3, wherein the charge pump circuit is configured as a multiply-by-two charge pump from the first terminal to the second terminal of the charge pump circuit when the input voltage at the input node is less than the battery voltage of the battery.
• Aspect 5 The power supply circuit of Aspect 2, wherein the first switch is configured to be open and the second switch is configured to be closed when an input voltage at the input node is more than a battery voltage of the battery.
• Aspect 6 The power supply circuit of Aspect 5, wherein the charge pump circuit is configured as a divide-by-two charge pump from the second terminal to the first terminal of the charge pump circuit when the input voltage at the input node is more than the battery voltage of the battery.
• Aspect 7 The power supply circuit of any of the preceding Aspects, wherein the power supply circuit is configured to be operated in a reverse mode and wherein the first switch is configured to be closed and the second switch is configured to be open in the reverse mode.
• Aspect 8 The power supply circuit of any of Aspects 1-6, wherein the power supply circuit is configured to be operated in a reverse mode and wherein the first switch is configured to be open and the second switch is configured to be closed in the reverse mode.
• Aspect 9 The power supply circuit of any of the preceding Aspects, wherein the first switch and the second switch comprise n-type metal-oxide- semiconductor (NMOS) transistors.
• NMOS n-type metal-oxide- semiconductor
• Aspect 10 The power supply circuit of any of the preceding Aspects, wherein the switched-mode power supply circuit comprises: a first transistor coupled to the input node; a second transistor coupled to the first transistor via a first node; a third transistor coupled to the second transistor via a second node; a fourth transistor coupled to the third transistor via a third node; a capacitive element having a first terminal coupled to the first node and having a second terminal coupled to the third node; and an inductive element having a first terminal coupled to the second node and having a second terminal coupled to the output node of the switched-mode power supply circuit.
• Aspect 11 The power supply circuit of Aspect 10, wherein the first, second, third, and fourth transistors comprise n-type metal-oxide-semiconductor (NMOS) transistors.
• Aspect 12 The power supply circuit of any of the preceding Aspects, further comprising a parallel charger coupled between the input node of the switched- mode power supply circuit and the second terminal of the charge pump circuit.
• a power management integrated circuit comprising at least a portion of the power supply circuit of any preceding aspect.
• a method of supplying power comprising: operating a switched-mode power supply circuit; and selectively routing a current through a first switch coupled between a first node of the switched-mode power supply circuit and a first terminal of a charge pump circuit or through a second switch coupled between the first node of the switched-mode power supply circuit and a second terminal of the charge pump circuit.
• Aspect 15 The method of Aspect 14, further comprising charging a battery, wherein the operating comprises operating the switched-mode power supply circuit in a forward mode, wherein the battery comprises multiple cells connected in series, and wherein the battery is coupled to the second switch and to the second terminal of the charge pump circuit.
• Aspect 16 The method of Aspect 15, wherein when an input voltage at a second node of the switched-mode power supply circuit is less than a battery voltage of the battery, the selectively routing comprises closing the first switch and opening the second switch.
• Aspect 17 The method of Aspect 16, further comprising operating the charge pump circuit as a multiply-by-two charge pump from the first terminal to the second terminal of the charge pump circuit when the input voltage at the second node of the switched-mode power supply circuit is less than the battery voltage of the battery.
• Aspect 18 The method of Aspect 15, wherein when an input voltage at a second node of the switched-mode power supply circuit is more than a battery voltage of the battery, the selectively routing comprises opening the first switch and closing the second switch.
• Aspect 19 The method of Aspect 18, further comprising operating the charge pump circuit as a divide-by-two charge pump from the second terminal to the first terminal of the charge pump circuit when the input voltage at the second node of the switched-mode power supply circuit is more than the battery voltage of the battery.
• Aspect 20 The method of any of Aspects 15-19, further comprising receiving power to charge the battery via at least one of: a port designated for a wired connection and coupled to the switched-mode power supply circuit; or a wireless power transceiver coupled to the switched-mode power supply circuit.
• Aspect 21 The method of any of Aspects 14-20, wherein: the operating comprises operating the switched-mode power supply circuit in a reverse mode; and the selectively routing comprises closing the first switch and opening the second switch to route the current from the charge pump circuit through the first switch to the switched- mode power supply circuit.
• Aspect 22 The method of any of Aspects 14-21, further comprising operating the charge pump circuit as a divide-by-two charge pump from the second terminal to the first terminal of the charge pump circuit.
• Aspect 23 The method of any of Aspects 14-22e the battery comprises multiple cells connected in series; and the battery is coupled to the second switch and to the second terminal of the charge pump circuit.
• Aspect 24 The method of Aspect 14, wherein: the operating comprises operating the switched-mode power supply circuit in a reverse mode; the selectively routing comprises opening the first switch and closing the second switch to route the current from a battery through the second switch to the switched-mode power supply circuit; the battery comprises multiple cells connected in series; and the battery is coupled to the second switch and to the second terminal of the charge pump circuit.
• Aspect 25 A battery charging circuit comprising at least a portion of the power supply circuit of any of Aspects 1-12.
• the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions.
• the means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor.
• ASIC application-specific integrated circuit
• determining encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining, and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, “determining” may include resolving, selecting, choosing, establishing, and the like.
• a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members.
• “at least one of: a, b. or c” is intended to cover: a, b. c, a-b. a-c, b-c. and a-b-c, as well as any combination with multiples of the same element (e.g., a-a. a-a-a. a-a-b. a-a-c. a-b-b. a- c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b. and c).
• the methods disclosed herein comprise one or more steps or actions for achieving the described method.
• the method steps and/or actions may be interchanged with one another without departing from the scope of the claims.
• the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Computer Networks & Wireless Communication (AREA)
• Charge And Discharge Circuits For Batteries Or The Like (AREA)

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• 2022
  • 2022-01-13 WO PCT/US2022/070182 patent/WO2022159927A1/en active Application Filing
  • 2022-01-13 EP EP22703246.3A patent/EP4282061A1/de active Pending
  • 2022-01-13 KR KR1020237023601A patent/KR20230130646A/ko unknown
  • 2022-01-13 BR BR112023013660A patent/BR112023013660A2/pt unknown
  • 2022-01-14 TW TW111101652A patent/TW202249399A/zh unknown

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