EP4273905A1 - Technologies for transistors with a ferroelectric gate dielectric - Google Patents
Technologies for transistors with a ferroelectric gate dielectric Download PDFInfo
- Publication number
- EP4273905A1 EP4273905A1 EP23166327.9A EP23166327A EP4273905A1 EP 4273905 A1 EP4273905 A1 EP 4273905A1 EP 23166327 A EP23166327 A EP 23166327A EP 4273905 A1 EP4273905 A1 EP 4273905A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- gate dielectric
- transistor
- channel
- gate
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
Definitions
- Transistors are ubiquitous devices present in virtually all electronic devices. As the density of transistors continues to increase, the power dissipated by the transistors needs to be addressed. The power dissipated can be removed by heat sinks or cold plates. The power dissipation of a transistor can be reduced in several ways, such as reducing leakage current and reducing the threshold voltage of the transistor.
- a typical transistor can maintain its state when a voltage is maintained at a gate electrode.
- a ferroelectric field-effect transistor FEFET
- FEFET ferroelectric field-effect transistor
- FEFETs typically have a relatively high threshold voltage and a corresponding relatively high leakage current.
- Ferroelectric field-effect transistors can use the spontaneous polarization in a ferroelectric material to apply an electric displacement to raise or lower a gate voltage above or below a threshold voltage.
- the orientation of the spontaneous polarization in the ferroelectric material can be changed by the application of an electric field to a gate of the transistor, allowing the transistor to be used as a memory cell.
- a FEFET has a ferroelectric hafnium zirconium oxide (Hf x Zr 1-x O 2 ) over a silicon channel.
- the coercive voltage to change the electric field of the ferroelectric material is typically 3-5 volts.
- the gate dielectric of a transistor is a ferroelectric perovskite, such as lead zirconate titanate (or PZT).
- a dielectric material includes a linear dielectric material, a paraelectric material, or a ferroelectric material.
- the material of the channel is also a perovskite, with a lattice constant that matches that of the gate dielectric.
- the similarity of the gate dielectric and channel materials can reduce lattice defects, reduce trapped charges, reduce oxygen vacancies, and/or reduce polycrystalline or amorphous structure. As a result, the transistor performance can be increased, and the threshold voltage and leakage current can be reduced.
- the phrase "communicatively coupled” refers to the ability of a component to send a signal to or receive a signal from another component.
- the signal can be any type of signal, such as an input signal, an output signal, or a power signal.
- a component can send or receive a signal to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air).
- a wired or wireless communication medium e.g., conductive traces, conductive contacts, air.
- Examples of components that are communicatively coupled include integrated circuit dies located in the same package that communicate via an embedded bridge in a package substrate, and an integrated circuit component attached to a printed circuit board that send signals to or receives signals from other integrated circuit components or electronic devices attached to the printed circuit board.
- Some embodiments may have some, all, or none of the features described for other embodiments.
- First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner.
- Connected may indicate elements are in direct physical or electrical contact and “coupled” may indicate elements co-operate or interact, but they may or may not be in direct physical or electrical contact.
- the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure are synonymous.
- ⁇ include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term.
- the central axis of a magnetic plug that is substantially coaxially aligned with a through hole may be misaligned from a central axis of the through hole by several degrees.
- a substrate assembly feature, such as a through width, that is described as having substantially a listed dimension can vary within a few percent of the listed dimension.
- a transistor 100 has a substrate 102, a body 104, a source 106, and a drain 108.
- FIG. 1 shows a top-down view of the transistor 100
- FIG. 2 shows a cross-sectional view of the transistor 100.
- a channel 110 is between the source 106 and the drain 108.
- a source electrode 112 is in contact with the source 106, and a drain electrode 114 is in contact with the drain 108.
- a gate dielectric 116 is above the channel 110, and a gate electrode 118 is above the gate dielectric 116.
- a voltage can be applied to the gate electrode 118, which causes an electric field to be applied to the gate dielectric 116 and to the channel 110.
- the illustrative gate dielectric 116 is ferroelectric.
- the applied voltage causes an electric field above a coercive field, the direction of the spontaneous polarization of the ferroelectric material can switch.
- the electric displacement of the ferroelectric material is the spontaneous polarization of the ferroelectric when no electric field is applied by the gate electrode 118. Under the applied field from the voltage of the gate electrode 118, the electric displacement of the ferroelectric material increases.
- the electric displacement applied to the channel 110 is affected by the polarization state of the ferroelectric material of the gate dielectric 116, and, therefore, the current through the channel 110 is affected by the polarization state of the ferroelectric material of the gate dielectric 116.
- this property can be used to facilitate low-threshold switching, single transistor memory, and compute-in-memory.
- the transistor 100 is a planar transistor. More generally, the transistor 100 may be implemented as, e.g., FinFET, gate-all-around, and stacked gate-all-around transistors, as described in more detail below in regard to FIGS. 10A-10D .
- the substrate 102 supports the body 104 and the rest of the transistor 100.
- the substrate 102 is strontium titanium oxide (SrTiO 3 or STO or strontium titanate).
- the strontium titanium oxide may be supported by, e.g., silicon, silicon dioxide, or any other suitable material.
- the substrate 102 may be any suitable material that can interface with the body 104, such as WO 3 , NaTaOs, BaTiO 3 , KTaO 3 , LaAlO 3 , MgO, or Al 2 O 3 .
- the body 104 is a perovskite material.
- a perovskite material is any crystalline material with a crystal structure similar to calcium titanate (CaTiO 3 ), typically with the chemical formula of ABX 3 , where A is one element, B is a second element, and X is a third element. In some cases, some of one (or more) of element A, B, or X in a perovskite material may be replaced by a different element.
- Pb(Zr x Ti 1- x )O 3 i.e., lead zirconate titanate or PZT
- PZT lead zirconate titanate
- a perovskite material may have various cation pairings, such as A + B 2+ X - 3 , A 2+ B 4+ X 2- 3 , A 3+ B 3+ X 2- 3 , or A + B 5+ X 2- 3 .
- the body 104 may be any suitable perovskite material, such as barium tin oxide (BaSnO 3 , or barium stannate) La-doped STO, Pb(Zr 0.52 Ti 0.48 )O 3 , CaMnOs, and/or the like. In some embodiments, the body 104 may not be a perovskite.
- the body 104 may be indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO), indium gallium zinc oxide (IGZO), or any other suitable material, such as other materials that do not have interface oxide layers. Some or all of the body 104 may be n-doped or p-doped, depending on the transistor type.
- the channel 110 is the same material as the body 104. In some embodiments, the channel 110 may be any of the materials referenced above in regard to the body 104. In some embodiments, the channel 110 may be doped differently from the rest of the body 104.
- the channel 110 has a relatively high electron mobility, such as at least 50-500 cm 2 /(V ⁇ s). In the illustrative embodiment, the channel 110 is barium tin oxide with an electron mobility of about 100 cm 2 /(V ⁇ s).
- the channel 110 is lattice matched to the gate dielectric 116.
- a material in the channel 110 is lattice matched to the material in the gate dielectric 116 if the lattice constant for the channel 110 is within 1% of the lattice constant of the gate dielectric 116.
- the lattice mismatch between the channel 110 and the gate dielectric 116 may be lower, such as less than 0.1% or less than 0.01% of the lattice constant of the gate dielectric 116.
- Each of the source 106 and drain 108 may be any suitable material, such as any of the materials referenced above in regard to the body 104 or channel 110.
- each of the source 106 and drain 108 are the same material as the body 104 but with a different doping to make it more conductive.
- the source 106 and drain 108 may be n -doped
- the source 106 and drain 108 may be p -doped.
- the transistor 100 is symmetric, and there is no functional distinction between the source 106 and the drain 108.
- the source electrode 112 and drain electrode 114 may be any suitable material.
- the source electrode 112 and/or the drain electrode 114 may be platinum, iridium, or other metal, polysilicon, a metallic perovskite, etc.
- the illustrative gate dielectric 116 is lead zirconate titanate.
- the relative concentration or zirconium and titanium may be selected so that the gate dielectric 116 is lattice matched to the channel 110.
- the gate dielectric 116 may be any suitable perovskite or non-perovskite ferroelectric.
- the gate dielectric 116 may be barium titanate (BaTiO 3 or BTO), lead niobate zirconate titanate ((Pb 1-x Nb x )(Zr 1-y Ti y )O 3 or PNZT), lead lanthanum zirconate titanate ((Pb i-x La x )(Zr 1-y Ti y )O 3 or PLZT), bismuth ferrite (BiFeO 3 or BFO), lanthanum bismuth ferrite (La x Bi 1-x FeO 3 or LaBFO), etc.
- barium titanate BaTiO 3 or BTO
- lead niobate zirconate titanate ((Pb 1-x Nb x )(Zr 1-y Ti y )O 3 or PNZT)
- lead lanthanum zirconate titanate (Pb i-x La x )(Zr 1-y Ti y )O 3 or PLZT)
- the gate dielectric 116 has a relatively low coercive field of about 130 kV/cm, allowing the direction of the spontaneous polarization of the ferroelectric material of the gate dielectric 116 to be changed with a relatively low voltage applied to the gate electrode 118. More generally, the gate dielectric 116 may have any suitable coercive field, such as 50-500 kV/cm. The gate dielectric 116 may be any suitable thickness. In the illustrative embodiment, the gate dielectric 116 may have a thickness of about 20-230 nanometers. Properties of the gate dielectric 116, such as the coercive field, may depend on the crystal orientation. Any suitable crystal orientation may be used, which may depend on the particular material being used. For example, ferroelectric gate dielectric 116 of PZT may have a crystal orientation of, e.g., (111) or (001) pseudocubic indices.
- the threshold voltage of the transistor 100 depends on the gate dielectric 116 material as well as the channel 110 thickness and doping concentration. In the illustrative embodiment, the threshold voltage of the transistor 100 is about 250 millivolts applied to the gate electrode 118, with the polarization of the ferroelectric material of the gate dielectric 116 increasing the electric displacement applied to the channel 110. In other embodiments, the threshold voltage of the transistor 100 may be any suitable value, such as 0.2-5 volts, depending on the materials used.
- the polarization of the ferroelectric of the gate dielectric 116 switches all at once in a few picoseconds.
- the ferroelectric of the gate dielectric 116 may have multiple domains that may switch at different applied electric fields (and, therefore, at different times).
- the ferroelectric of the gate dielectric 116 may have multiple stable states that can be set by applying a particular voltage to the gate electrode 118.
- Such a transistor 100 can act as a multi-level memory or like an analog memory.
- the illustrative gate electrode 118 is a metallic perovskite, such as strontium ruthenate (SrRuO 3 or SRO), lanthanum strontium manganite (La 1-x Sr x MnO 3 or LMSO), lanthanum strontium cobalt oxide (La 1-x Sr x CoO 3 or LSCO), SrVO 3 , SrCrO 3 , SrFeO 3 , ReO 3 , CaRuO 3 , SrMoO 3 , SrNbO 3 , LaNiOs, etc.
- SrRuO 3 or SRO strontium ruthenate
- La 1-x Sr x MnO 3 or LMSO lanthanum strontium manganite
- La 1-x Sr x CoO 3 or LSCO lanthanum strontium cobalt oxide
- SrVO 3 SrCrO 3 , SrFeO 3 , ReO 3 , CaRuO 3 , SrMo
- the gate electrode 118 may be other materials, such as platinum, iridium, or other metal, oxides with high electric conductivity that do not have the perovskite structure including RuO 2 , IrO 2 , and ITO, polysilicon, etc.
- the work function of the gate electrode 118 is selected to shift the coercive voltage across the gate dielectric 116.
- FIG. 3 shows a curve of current from the source 106 to the drain 108, for a given voltage across the source 106 and drain 108, as voltage applied to the gate electrode 118 is increased and then decreased. As the gate voltage is increased, the current follows the curve 302, and as the gate voltage is decreased, the current follows the curve 304.
- the voltage increases past a first ferroelectric switching voltage to switch the spontaneous polarization of the gate dielectric 116 to a positive polarization (i.e., a polarization that applies an electric displacement in the direction of that caused by the gate dielectric 116).
- a positive polarization i.e., a polarization that applies an electric displacement in the direction of that caused by the gate dielectric 116.
- the voltage decreases past a second ferroelectric switching voltage to switch the spontaneous polarization of the gate dielectric 116 to a negative polarization (i.e., a polarization that applies an electric displacement opposite the direction of that caused by the gate dielectric 116).
- the difference 306 between the two ferroelectric switching voltages corresponds to 2 ⁇ E C ⁇ d FE , where E C is the coercive field of the gate dielectric 116 and d FE is the thickness of the gate dielectric 116.
- the position of the ferroelectric switching voltages depends on the gate electrode 118.
- the lower ferroelectric switching voltage is shifted to a positive voltage, allowing the polarization of the ferroelectric to be controlled without applying a negative voltage to the gate electrode 118.
- a transistor 100 may use a gate electrode 118, gate dielectric 116, channel 110, etc., that results in a gate voltage/drain current relationship as shown in FIG. 4 .
- the spontaneous polarization of the ferroelectric material of the gate dielectric 116 is flipped.
- the direction of the spontaneous polarization of the ferroelectric material of the gate dielectric 116 remains the same, effectively allowing the ferroelectric material of the gate dielectric 116 to turn the transistor 100 on with no external voltage applied.
- the polarization of the ferroelectric material of the gate dielectric 116 may be less than the threshold voltage of the transistor 100. In order to flip the ferroelectric material back to the first polarization, the voltage applied to the gate electrode 118 must go to a negative value.
- the transistor 100 has a gate voltage/drain current curve as shown in FIG. 3 , with a threshold voltage of 250 millivolts.
- the low threshold voltage reduces leakage current and reduces overall energy dissipation in the transistor.
- Such a transistor 100 can be used for general computing tasks such as adders, memory cells, etc.
- the transistor 100 has a gate voltage/drain current curve, as shown in FIG. 4 .
- Such a transistor 100 can be used as a one-transistor memory cell to store one bit.
- the transistor 100 can be set by increasing the voltage past a threshold to set the polarization of the ferroelectric material of the gate dielectric 116 one way, and the transistor 100 can be cleared by decreasing the voltage past a threshold to set the polarization of the ferroelectric material of the gate dielectric 116 the opposite way.
- the ferroelectric material of the gate dielectric 116 will maintain its polarization without a voltage applied to the gate electrode 118, allowing the transistor 100 to act as a non-volatile memory cell.
- the state of the ferroelectric material of the gate dielectric 116 can be probed by detecting the current that can pass between the source 106 and the drain 108 at a given voltage.
- the transistor 100 can be used in a compute-in-memory system. In such an embodiment, the transistor 100 can be used both to perform calculations and store data.
- a transistor 100 may be used to implement a machine-learning-based algorithm, such as a neural network.
- a transistor 100 may act as a neuron of a neural network and can hold a weight value that acts as an input to a level of a neural network.
- the transistor 100 can hold one of several possible weight values, not just 0 or 1.
- a transistor 500 includes a linear gate dielectric 502 between the ferroelectric gate dielectric 116 and the channel 110.
- the transistor 500 includes similar components to the transistor 100, such as the body 104, the source 106, the drain 108, etc., a description of which will not be repeated in the interest of clarity.
- the linear gate dielectric 502 can reduce leakage current from the gate electrode 118, such as by reducing charge traps and/or oxygen vacancies.
- the linear gate dielectric 502 may be any suitable material. In some embodiments, the linear gate dielectric 502 may be selected to be similar to the channel 110 and/or the gate dielectric 116.
- the linear gate dielectric 502 may be barium oxide, BaZrO 3 , SrZrO 3 , LaScO 3 , LaInO 3 , SrSnO 3 , or titanium oxide. It should be appreciated that the linear gate dielectric 502 may have a relatively high dielectric constant, leading to a high electric displacement applied to the channel 110.
- a flowchart for a method 700 for creating a transistor (such as transistor 100 or 500) is shown.
- the method 700 may be executed by a technician and/or by one or more automated machines.
- one or more machines may be programmed to do some or all of the steps of the method 700.
- Such a machine may include, e.g., a memory, a processor, data storage, etc.
- the memory and/or data storage may store instructions that, when executed by the machine, causes the machine to perform some or all of the steps of the method 700.
- the method 700 may use any suitable set of techniques that are used in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, pulsed laser deposition, layer transfer, photolithography, ion implantation, dry etching, wet etching, thermal treatments, etc.
- the method 700 begins in block 702, in which the body 104 is deposited.
- the body 104 is barium tin oxide.
- the body 104 is deposited on the substrate 102.
- the body 104 may be deposited in any suitable manner, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, pulsed laser deposition, etc.
- the body 104 is deposited using layer transfer.
- the body 104 is the same base structure as the source 106, drain 108, and channel 110.
- the source 106, drain 108, and channel 110 do not need to be separately deposited, and a variation in the doping of this same layer can be achieved during the deposition process, if desired.
- the source 106, drain 108, and/or channel 110 may be made from a different material as the body 104 and may be deposited separately.
- the source 106, drain 108, and channel 110 are doped, such as by using ion implantation.
- the source 106 and drain 108 are relatively heavily doped, and the channel 110 is relatively lightly doped.
- the channel 110 is doped with the same carrier type as the source 106 and drain 108.
- the channel 110 may be n -doped and the source 106 and drain 108 may be n -doped, or all three may be p -doped.
- a linear gate dielectric 502 is applied, such as barium oxide, BaZrO 3 , SrZrO 3 , LaScO 3 , LaInO 3 , SrSnO 3 , or titanium oxide.
- the linear gate dielectric 502 may be applied using, e.g., photolithography and chemical layer deposition. In some embodiments, a linear gate dielectric 502 may not be used.
- a dielectric with a polarization mismatch 502 is applied, such as LaScO 3 or LaInOs
- the carrier concentration of the channel layer 110 may be altered through a process commonly known as "electronic reconstruction.”
- This means of doping can be used in conjunction with doped (e.g., La-doped BaSnO 3 ) or even completely undoped (e.g., stoichiometric BaSnO 3 ) channel layers.
- the dielectric with a polarization mismatch 502 may be applied using an appropriate thin film growth technique in combination with patterning, e.g., photolithography and physical vapor deposition. In some embodiments a dielectric with a polarization mismatch 502 may not be used.
- a doped dielectric with a positive conduction band offset 502 is applied, such as La-doped SrSnO 3 .
- the purpose of the doped dielectric layer with positive conduction band offset is to alter the carrier concentration of the channel layer 110 through a process commonly known as "modulation doping." This means of doping can be used in conjunction with doped (e.g., La-doped BaSnO 3 ) or even completely undoped (e.g., stoichiometric BaSnO 3 ) channel layers.
- the doped dielectric with positive conduction band offset 502 may be applied using an appropriate thin film growth technique in combination with patterning, e.g., photolithography and physical vapor deposition. In some embodiments a doped dielectric with positive conduction band offset 502 may not be used.
- a ferroelectric gate dielectric 116 is applied.
- the gate dielectric 116 is BTO or PZT.
- the ferroelectric gate dielectric 116 may be applied using, e.g., photolithography and physical vapor deposition.
- the gate electrode 118 is applied.
- the gate electrode 118 is a metallic perovskite, such as SRO or LMSO.
- the gate electrode 118 may be selected based on its work function, which shifts the voltage at which the spontaneous polarization of the ferroelectric gate dielectric 116 changes.
- source electrode 112 and drain electrode 114 are applied.
- the source electrode 112 and drain electrode 114 may be any suitable material, such as platinum, iridium, or other metal, polysilicon, a metallic perovskite, etc.
- the source electrode 112 and drain electrode 114 may be applied using, e.g., photolithography and physical vapor deposition.
- the method 700 is one of many possible embodiments of manufacturing the transistor 100. Different approaches or orders of steps are envisioned as well.
- the ferroelectric gate dielectric 116 and gate electrode 118 may be applied before doping the source 106 and drain 108, creating a self-aligned gate.
- a complete manufacturing process of an integrated circuit that includes the transistor 100 may include steps not shown in the method 700, such as cleaning, surface passivation, creating interconnects, packaging, etc.
- FIG. 8 is a top view of a wafer 800 and dies 802 that may include one or more of any of the transistors 100, 500 disclosed herein.
- the wafer 800 may be composed of semiconductor material and may include one or more dies 802 having integrated circuit structures formed on a surface of the wafer 800.
- the individual dies 802 may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, the wafer 800 may undergo a singulation process in which the dies 802 are separated from one another to provide discrete "chips" of the integrated circuit product.
- the die 802 may include one or more transistors (e.g., some of the transistors 940 of FIG.
- the wafer 800 or the die 802 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 802.
- RAM random access memory
- SRAM static RAM
- MRAM magnetic RAM
- RRAM resistive RAM
- CBRAM conductive-bridging RAM
- a memory array formed by multiple memory devices may be formed on a same die 802 as a processor unit (e.g., the processor unit 1202 of FIG. 12 ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
- Various ones of the transistors 100, 500 disclosed herein may be manufactured using a die-to-wafer assembly technique in which some dies are attached to a wafer 800 that include others of the dies, and the wafer 800 is subsequently singulated.
- FIG. 9 is a cross-sectional side view of an integrated circuit device 900 that may include any of the transistors 100, 500 disclosed herein.
- One or more of the integrated circuit devices 900 may be included in one or more dies 802 ( FIG. 8 ).
- the integrated circuit device 900 may be formed on a die substrate 902 (e.g., the wafer 800 of FIG. 8 ) and may be included in a die (e.g., the die 802 of FIG. 8 ).
- the die substrate 902 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type orp-type materials systems (or a combination of both).
- the die substrate 902 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure.
- the die substrate 902 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate 902. Although a few examples of materials from which the die substrate 902 may be formed are described here, any material that may serve as a foundation for an integrated circuit device 900 may be used.
- the die substrate 902 may be part of a singulated die (e.g., the dies 802 of FIG. 8 ) or a wafer (e.g., the wafer 800 of FIG. 8 ).
- the integrated circuit device 900 may include one or more device layers 904 disposed on the die substrate 902.
- the device layer 904 may include features of one or more transistors 940 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 902.
- the transistors 940 may include, for example, one or more source and/or drain (S/D) regions 920, a gate 922 to control current flow between the S/D regions 920, and one or more S/D contacts 924 to route electrical signals to/from the S/D regions 920.
- the transistors 940 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like.
- the transistors 940 are not limited to the type and configuration depicted in FIG.
- Non- planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.
- FIGS. 10A-10D are simplified perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. Any of the transistors 100, 500 may be implemented as FinFET, gate-all-around, and stacked gate-all-around transistors.
- the transistors illustrated in FIGS. 10A-10D are formed on a substrate 1016 having a surface 1008. Isolation regions 1014 separate the source and drain regions of the transistors from other transistors and from a bulk region 1018 of the substrate 1016.
- FIG. 10A is a perspective view of an example planar transistor 1000 comprising a gate 1002 that controls current flow between a source region 1004 and a drain region 1006.
- the transistor 1000 is planar in that the source region 1004 and the drain region 1006 are planar with respect to the substrate surface 1008.
- FIG. 10B is a perspective view of an example FinFET transistor 1020 comprising a gate 1022 that controls current flow between a source region 1024 and a drain region 1026.
- the transistor 1020 is non-planar in that the source region 1024 and the drain region 1026 comprise "fins" that extend upwards from the substrate surface 1028.
- the transistor 1020 can be considered a tri-gate transistor.
- FIG. 10B illustrates one S/D fin extending through the gate 1022, but multiple S/D fins can extend through the gate of a FinFET transistor.
- FIG. 10C is a perspective view of a gate-all-around (GAA) transistor 1040 comprising a gate 1042 that controls current flow between a source region 1044 and a drain region 1046.
- the transistor 1040 is non-planar in that the source region 1044 and the drain region 1046 are elevated from the substrate surface 1028.
- FIG. 10D is a perspective view of a GAA transistor 1060 comprising a gate 1062 that controls current flow between multiple elevated source regions 1064 and multiple elevated drain regions 1066.
- the transistor 1060 is a stacked GAA transistor as the gate controls the flow of current between multiple elevated S/D regions stacked on top of each other.
- the transistors 1040 and 1060 are considered gate-all-around transistors as the gates encompass all sides of the semiconductor portions that extends from the source regions to the drain regions.
- the transistors 1040 and 1060 can alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors depending on the width (e.g., widths 1048 and 1068 of transistors 1040 and 1060, respectively) of the semiconductor portions extending through the gate.
- a transistor 940 may include a gate 922 formed of at least two layers, a gate dielectric and a gate electrode.
- the gate dielectric may include one layer or a stack of layers.
- the one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.
- the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, bismuth, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
- high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
- an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
- the gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 940 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor.
- the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
- metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning).
- metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
- the gate electrode when viewed as a cross-section of the transistor 940 along the source-channel-drain direction, may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 902 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 902.
- at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 902 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 902.
- the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
- the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
- a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack.
- the sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
- the S/D regions 920 may be formed within the die substrate 902 adjacent to the gate 922 of individual transistors 940.
- the S/D regions 920 may be formed using an implantation/diffusion process or an etching/deposition process, for example.
- dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ionimplanted into the die substrate 902 to form the S/D regions 920.
- An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 902 may follow the ion-implantation process.
- the die substrate 902 may first be etched to form recesses at the locations of the S/D regions 920.
- the S/D regions 920 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
- the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
- the S/D regions 920 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy.
- one or more layers of metal and/or metal alloys may be used to form the S/D regions 920.
- Electrical signals such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 940) of the device layer 904 through one or more interconnect layers disposed on the device layer 904 (illustrated in FIG. 9 as interconnect layers 906-910).
- interconnect layers 906-910 electrically conductive features of the device layer 904 (e.g., the gate 922 and the S/D contacts 924) may be electrically coupled with the interconnect structures 928 of the interconnect layers 906-910.
- the one or more interconnect layers 906-910 may form a metallization stack (also referred to as an "ILD stack") 919 of the integrated circuit device 900.
- the interconnect structures 928 may be arranged within the interconnect layers 906-910 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 928 depicted in FIG. 9 . Although a particular number of interconnect layers 906-910 is depicted in FIG. 9 , embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.
- the interconnect structures 928 may include lines 928a and/or vias 928b filled with an electrically conductive material such as a metal.
- the lines 928a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 902 upon which the device layer 904 is formed.
- the vias 928b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 902 upon which the device layer 904 is formed.
- the vias 928b may electrically couple lines 928a of different interconnect layers 906-910 together.
- the interconnect layers 906-910 may include a dielectric material 926 disposed between the interconnect structures 928, as shown in FIG. 9 .
- dielectric material 926 disposed between the interconnect structures 928 in different ones of the interconnect layers 906-910 may have different compositions; in other embodiments, the composition of the dielectric material 926 between different interconnect layers 906-910 may be the same.
- the device layer 904 may include a dielectric material 926 disposed between the transistors 940 and a bottom layer of the metallization stack as well.
- the dielectric material 926 included in the device layer 904 may have a different composition than the dielectric material 926 included in the interconnect layers 906-910; in other embodiments, the composition of the dielectric material 926 in the device layer 904 may be the same as a dielectric material 926 included in any one of the interconnect layers 906-910.
- a first interconnect layer 906 (referred to as Metal 1 or "M1") may be formed directly on the device layer 904.
- the first interconnect layer 906 may include lines 928a and/or vias 928b, as shown.
- the lines 928a of the first interconnect layer 906 may be coupled with contacts (e.g., the S/D contacts 924) of the device layer 904.
- the vias 928b of the first interconnect layer 906 may be coupled with the lines 928a of a second interconnect layer 908.
- the second interconnect layer 908 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 906.
- the second interconnect layer 908 may include via 928b to couple the lines 928 of the second interconnect layer 908 with the lines 928a of a third interconnect layer 910.
- the lines 928a and the vias 928b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 928a and the vias 928b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
- the third interconnect layer 910 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 908 according to similar techniques and configurations described in connection with the second interconnect layer 908 or the first interconnect layer 906.
- the interconnect layers that are "higher up” in the metallization stack 919 in the integrated circuit device 900 may be thicker that the interconnect layers that are lower in the metallization stack 919, with lines 928a and vias 928b in the higher interconnect layers being thicker than those in the lower interconnect layers.
- the integrated circuit device 900 may include a solder resist material 934 (e.g., polyimide or similar material) and one or more conductive contacts 936 formed on the interconnect layers 906-910.
- the conductive contacts 936 are illustrated as taking the form of bond pads.
- the conductive contacts 936 may be electrically coupled with the interconnect structures 928 and configured to route the electrical signals of the transistor(s) 940 to external devices.
- solder bonds may be formed on the one or more conductive contacts 936 to mechanically and/or electrically couple an integrated circuit die including the integrated circuit device 900 with another component (e.g., a printed circuit board).
- the integrated circuit device 900 may include additional or alternate structures to route the electrical signals from the interconnect layers 906-910; for example, the conductive contacts 936 may include other analogous features (e.g., posts) that route the electrical signals to external components.
- the integrated circuit device 900 may include another metallization stack (not shown) on the opposite side of the device layer(s) 904.
- This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 906-910, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 904 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 900 from the conductive contacts 936.
- the integrated circuit device 900 may include one or more through silicon vias (TSVs) through the die substrate 902; these TSVs may make contact with the device layer(s) 904, and may provide conductive pathways between the device layer(s) 904 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 900 from the conductive contacts 936.
- TSVs through silicon vias
- TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 900 from the conductive contacts 936 to the transistors 940 and any other components integrated into the die 900, and the metallization stack 919 can be used to route I/O signals from the conductive contacts 936 to transistors 940 and any other components integrated into the die 900.
- Multiple integrated circuit devices 900 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack.
- one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die.
- Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack.
- the conductive contacts can be fine-pitch solder bumps (microbumps).
- FIG. 11 is a cross-sectional side view of an integrated circuit device assembly 1100 that may include any of the transistors 100, 500 disclosed herein.
- the integrated circuit device assembly 1100 includes a number of components disposed on a circuit board 1102 (which may be a motherboard, system board, mainboard, etc.).
- the integrated circuit device assembly 1100 includes components disposed on a first face 1140 of the circuit board 1102 and an opposing second face 1142 of the circuit board 1102; generally, components may be disposed on one or both faces 1140 and 1142.
- the circuit board 1102 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias.
- the individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1102.
- the circuit board 1102 may be a non-PCB substrate.
- the integrated circuit device assembly 1100 illustrated in FIG. 11 includes a package-on-interposer structure 1136 coupled to the first face 1140 of the circuit board 1102 by coupling components 1116.
- the coupling components 1116 may electrically and mechanically couple the package-on-interposer structure 1136 to the circuit board 1102, and may include solder balls (as shown in FIG. 11 ), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
- solder balls as shown in FIG. 11
- pins e.g., as part of a pin grid array (PGA)
- contacts e.g., as part of a land grid array (LGA)
- male and female portions of a socket e.g., an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
- the package-on-interposer structure 1136 may include an integrated circuit component 1120 coupled to an interposer 1104 by coupling components 1118.
- the coupling components 1118 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1116. Although a single integrated circuit component 1120 is shown in FIG. 11 , multiple integrated circuit components may be coupled to the interposer 1104; indeed, additional interposers may be coupled to the interposer 1104.
- the interposer 1104 may provide an intervening substrate used to bridge the circuit board 1102 and the integrated circuit component 1120.
- the integrated circuit component 1120 may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die 802 of FIG. 8 , the integrated circuit device 900 of FIG. 9 ) and/or one or more other suitable components.
- a packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic.
- a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1104.
- the integrated circuit component 1120 can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller.
- processor units e.g., system-on-a-chip (SoC)
- SoC system-on-a-chip
- GPU graphics processor unit
- accelerator chipset processor
- I/O controller I/O controller
- memory or network interface controller.
- the integrated circuit component 1120 can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.
- ESD electrostatic discharge
- the integrated circuit component 1120 comprises multiple integrated circuit dies
- they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component).
- a multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
- the integrated circuit component 1120 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as "chiplets". In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel ® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
- EMIBs Intel ® embedded multi-die interconnect bridges
- the interposer 1104 may spread connections to a wider pitch or reroute a connection to a different connection.
- the interposer 1104 may couple the integrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of the coupling components 1116 for coupling to the circuit board 1102.
- BGA ball grid array
- the integrated circuit component 1120 and the circuit board 1102 are attached to opposing sides of the interposer 1104; in other embodiments, the integrated circuit component 1120 and the circuit board 1102 may be attached to a same side of the interposer 1104.
- three or more components may be interconnected by way of the interposer 1104.
- the interposer 1104 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias.
- the interposer 1104 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide.
- the interposer 1104 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
- the interposer 1104 may include metal interconnects 1108 and vias 1110, including but not limited to through hole vias 1110-1 (that extend from a first face 1150 of the interposer 1104 to a second face 1154 of the interposer 1104), blind vias 1110-2 (that extend from the first or second faces 1150 or 1154 of the interposer 1104 to an internal metal layer), and buried vias 1110-3 (that connect internal metal layers).
- through hole vias 1110-1 that extend from a first face 1150 of the interposer 1104 to a second face 1154 of the interposer 1104
- blind vias 1110-2 that extend from the first or second faces 1150 or 1154 of the interposer 1104 to an internal metal layer
- buried vias 1110-3 that connect internal metal layers.
- the interposer 1104 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer.
- TSV through silicon vias
- an interposer 1104 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 1104 to an opposing second face of the interposer 1104.
- the interposer 1104 may further include embedded devices 1114, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1104.
- the package-on-interposer structure 1136 may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board
- the integrated circuit device assembly 1100 may include an integrated circuit component 1124 coupled to the first face 1140 of the circuit board 1102 by coupling components 1122.
- the coupling components 1122 may take the form of any of the embodiments discussed above with reference to the coupling components 1116, and the integrated circuit component 1124 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1120.
- the integrated circuit device assembly 1100 illustrated in FIG. 11 includes a package-on-package structure 1134 coupled to the second face 1142 of the circuit board 1102 by coupling components 1128.
- the package-on-package structure 1134 may include an integrated circuit component 1126 and an integrated circuit component 1132 coupled together by coupling components 1130 such that the integrated circuit component 1126 is disposed between the circuit board 1102 and the integrated circuit component 1132.
- the coupling components 1128 and 1130 may take the form of any of the embodiments of the coupling components 1116 discussed above, and the integrated circuit components 1126 and 1132 may take the form of any of the embodiments of the integrated circuit component 1120 discussed above.
- the package-on-package structure 1134 may be configured in accordance with any of the package-on-package structures known in the art.
- FIG. 12 is a block diagram of an example electrical device 1200 that may include one or more of the transistors 100, 500 disclosed herein.
- any suitable ones of the components of the electrical device 1200 may include one or more of the integrated circuit device assemblies 1100, integrated circuit components 1120, integrated circuit devices 900, or integrated circuit dies 802 disclosed herein.
- a number of components are illustrated in FIG. 12 as included in the electrical device 1200, but any one or more of these components may be omitted or duplicated, as suitable for the application.
- some or all of the components included in the electrical device 1200 may be attached to one or more motherboards mainboards, or system boards.
- one or more of these components are fabricated onto a single system-on-a-chip (SoC) die.
- SoC system-on-a-chip
- the electrical device 1200 may not include one or more of the components illustrated in FIG. 12 , but the electrical device 1200 may include interface circuitry for coupling to the one or more components.
- the electrical device 1200 may not include a display device 1206, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1206 may be coupled.
- the electrical device 1200 may not include an audio input device 1224 or an audio output device 1208, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1224 or audio output device 1208 may be coupled.
- the electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor units).
- processor unit e.g., one or more processor units
- processor unit may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
- the processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units.
- DSPs digital signal processors
- ASICs application-specific integrated circuits
- CPUs central processing units
- GPUs graphics processing units
- GPUs general-purpose GPUs
- APUs accelerated processing units
- FPGAs field-programmable gate arrays
- NPUs neural network processing units
- DPUs data processor units
- accelerators e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator
- controller cryptoprocessors
- the electrical device 1200 may include a memory 1204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive.
- volatile memory e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)
- non-volatile memory e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories
- solid state memory e.g., solid state memory, and/or a hard drive.
- the memory 1204 may include memory that is located on the same integrated circuit die as the processor unit 1202.
- This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
- eDRAM embedded dynamic random access memory
- STT-MRAM spin transfer torque magnetic random access memory
- the electrical device 1200 can comprise one or more processor units 1202 that are heterogeneous or asymmetric to another processor unit 1202 in the electrical device 1200.
- processor units 1202 can be heterogeneous or asymmetric to another processor unit 1202 in the electrical device 1200.
- the electrical device 1200 may include a communication component 1212 (e.g., one or more communication components).
- the communication component 1212 can manage wireless communications for the transfer of data to and from the electrical device 1200.
- the term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium.
- the term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
- the communication component 1212 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
- IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards.
- the communication component 1212 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
- GSM Global System for Mobile Communication
- GPRS General Packet Radio Service
- UMTS Universal Mobile Telecommunications System
- High Speed Packet Access HSPA
- E-HSPA Evolved HSPA
- LTE LTE network.
- the communication component 1212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
- EDGE Enhanced Data for GSM Evolution
- GERAN GSM EDGE Radio Access Network
- UTRAN Universal Terrestrial Radio Access Network
- E-UTRAN Evolved UTRAN
- the communication component 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
- CDMA Code Division Multiple Access
- TDMA Time Division Multiple Access
- DECT Digital Enhanced Cordless Telecommunications
- EV-DO Evolution-Data Optimized
- the communication component 1212 may operate in accordance with other wireless protocols in other embodiments.
- the electrical device 1200 may include an antenna 1222 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
- the communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards).
- the communication component 1212 may include multiple communication components. For instance, a first communication component 1212 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1212 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
- GPS global positioning system
- EDGE EDGE
- GPRS long-range wireless communications
- CDMA Code Division Multiple Access
- WiMAX Code Division Multiple Access
- LTE Long Term Evolution
- EV-DO Evolution-DO
- the electrical device 1200 may include battery/power circuitry 1214.
- the battery/power circuitry 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1200 to an energy source separate from the electrical device 1200 (e.g., AC line power).
- the electrical device 1200 may include a display device 1206 (or corresponding interface circuitry, as discussed above).
- the display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
- the electrical device 1200 may include an audio output device 1208 (or corresponding interface circuitry, as discussed above).
- the audio output device 1208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
- the electrical device 1200 may include an audio input device 1224 (or corresponding interface circuitry, as discussed above).
- the audio input device 1224 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
- the electrical device 1200 may include a Global Navigation Satellite System (GNSS) device 1218 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device.
- GNSS device 1218 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1200 based on information received from one or more GNSS satellites, as known in the art.
- the electrical device 1200 may include an other output device 1210 (or corresponding interface circuitry, as discussed above).
- Examples of the other output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
- the electrical device 1200 may include an other input device 1220 (or corresponding interface circuitry, as discussed above).
- the other input device 1220 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
- an accelerometer e.g., a gyroscope, a compass
- an image capture device e.g., monoscopic or stereoscopic camera
- a trackball e.g., monoscopic or stereoscopic camera
- a trackball e.
- the electrical device 1200 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment).
- the electrical device 1200 may be any other electronic device that processes data.
- the electrical device 1200 may comprise multiple discrete physical components. Given the range of devices that the electrical device 1200 can be manifested as in various embodiments, in some embodiments, the electrical device 1200 can be referred to as a computing device or a computing system.
- An embodiment of the technologies disclosed herein may include any one or more, and any combination of, the examples described below.
- Example 1 includes a device comprising a source; a drain; a channel between the source and the drain; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric, wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- Example 2 includes the subject matter of Example 1, and wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the gate electrode is a metallic perovskite.
- Example 4 includes the subject matter of any of Examples 1-3, and wherein the channel has an electron mobility of at least 50 cm 2 /(V ⁇ s).
- Example 5 includes the subject matter of any of Examples 1-4, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 6 includes the subject matter of any of Examples 1-5, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 7 includes the subject matter of any of Examples 1-6, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 8 includes the subject matter of any of Examples 1-7, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- Example 9 includes the subject matter of any of Examples 1-8, and further including a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- Example 10 includes the subject matter of any of Examples 1-9, and wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- Example 11 includes the subject matter of any of Examples 1-10, and wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above a threshold voltage of the device to zero voltage.
- Example 12 includes an integrated circuit comprising the device of Example 1, wherein a polarization state of the gate dielectric stores a weight of a neuron of a neural network.
- Example 13 includes the subject matter of Example 12, and wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- Example 14 includes a memory device comprising the device in Example 13, wherein the two stable polarization states of the gate dielectric is used to store a memory bit.
- Example 15 includes the subject matter of Example 14, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.
- Example 16 includes a processor comprising the device of Example 1.
- Example 17 includes a system comprising the processor of Example 16 and one or more memory devices.
- a device comprising a source; a drain; a channel between the source and the drain; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric
- the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- Example 19 includes the subject matter of any of Examples 17 and 18, and wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- Example 20 includes the subject matter of any of Examples 17-19, and wherein the gate electrode is a metallic perovskite.
- Example 21 includes the subject matter of any of Examples 17-20, and wherein the channel has an electron mobility of at least 50 cm 2 /(V ⁇ s).
- Example 22 includes the subject matter of any of Examples 17-21, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 23 includes the subject matter of any of Examples 17-22, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 24 includes the subject matter of any of Examples 17-23, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 25 includes the subject matter of any of Examples 17-24, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- Example 26 includes the subject matter of any of Examples 17-25, and further including a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- Example 27 includes the subject matter of any of Examples 17-26, and wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- Example 28 includes the subject matter of any of Examples 17-27, and wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above a threshold voltage of the device to zero voltage.
- Example 29 includes an integrated circuit comprising the device of Example 18, wherein a polarization state of the gate dielectric stores a weight of a neuron of a neural network.
- Example 30 includes the subject matter of Example 29, and wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- Example 31 includes a memory device comprising the device in Example 30, wherein the two stable polarization states of the gate dielectric is used to store a memory bit.
- Example 32 includes the subject matter of Example 31, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.
- Example 33 includes a processor comprising the device of Example 18.
- Example 34 includes a system comprising the processor of Example 33 and one or more memory devices.
- Example 35 includes a device comprising a transistor comprising a source; a drain; a channel between the source and the drain; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric, wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 36 includes the subject matter of Example 35, and wherein the gate electrode is a metallic perovskite.
- Example 37 includes the subject matter of any of Examples 35 and 36, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 38 includes the subject matter of any of Examples 35-37, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 39 includes the subject matter of any of Examples 35-38, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- Example 40 includes the subject matter of any of Examples 35-39, and further including a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- Example 41 includes the subject matter of any of Examples 35-40, and wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- Example 42 includes the subject matter of any of Examples 35-41, and wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above the threshold voltage to zero voltage.
- Example 43 includes an integrated circuit comprising the device of Example 35, wherein a polarization state of the gate dielectric stores a weight of a neuron of a neural network.
- Example 44 includes the subject matter of Example 43, and wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- Example 45 includes a memory device comprising the device in Example 44, wherein the two stable polarization states of the gate dielectric is used to store a memory bit.
- Example 46 includes the subject matter of Example 45, and wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.
- Example 47 includes a processor comprising the device of Example 35.
- Example 48 includes a system comprising the processor of Example 47 and one or more memory devices.
- Example 49 includes a method comprising depositing a channel of a transistor; depositing a gate dielectric over the channel, wherein the gate dielectric is ferroelectric; and depositing a gate electrode over the gate dielectric, wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- Example 50 includes the subject matter of Example 49, and wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- Example 51 includes the subject matter of any of Examples 49 and 50, and wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 52 includes the subject matter of any of Examples 49-51, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 53 includes the subject matter of any of Examples 49-52, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 54 includes the subject matter of any of Examples 49-53, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
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Abstract
Description
- This invention was made with government support under Grant No. FA9550-20-1-0102 awarded by the Air Force Office of Scientific Research. The government has certain rights in the invention.
- Transistors are ubiquitous devices present in virtually all electronic devices. As the density of transistors continues to increase, the power dissipated by the transistors needs to be addressed. The power dissipated can be removed by heat sinks or cold plates. The power dissipation of a transistor can be reduced in several ways, such as reducing leakage current and reducing the threshold voltage of the transistor.
- A typical transistor can maintain its state when a voltage is maintained at a gate electrode. However, a ferroelectric field-effect transistor (FEFET) can maintain its state based on a state of a ferroelectric layer in the transistor. FEFETs typically have a relatively high threshold voltage and a corresponding relatively high leakage current.
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FIG. 1 is a top view of a transistor with a gate dielectric that is ferroelectric. -
FIG. 2 is a cross-sectional side view of the transistor ofFIG. 1 . -
FIG. 3 is a graph showing a voltage-current relationship for one embodiment of the transistor ofFIG. 1 . -
FIG. 4 is a graph showing a voltage-current relationship for one embodiment of the transistor ofFIG. 1 . -
FIG. 5 is a top view of a transistor with a gate dielectric that is ferroelectric. -
FIG. 6 is a cross-sectional side view of the transistor ofFIG. 5 . -
FIG. 7 is a simplified flow diagram of at least one embodiment of a method for creating a transistor with a gate dielectric that is ferroelectric. -
FIG. 8 is a top view of a wafer and dies that may be included in a microelectronic assembly, in accordance with any of the embodiments disclosed herein. -
FIG. 9 is a cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly, in accordance with any of the embodiments disclosed herein. -
FIGS. 10A-10D are perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. -
FIG. 11 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly, in accordance with any of the embodiments disclosed herein. -
FIG. 12 is a block diagram of an example electrical device that may include a microelectronic assembly, in accordance with any of the embodiments disclosed herein. - Ferroelectric field-effect transistors (FEFETs) can use the spontaneous polarization in a ferroelectric material to apply an electric displacement to raise or lower a gate voltage above or below a threshold voltage. The orientation of the spontaneous polarization in the ferroelectric material can be changed by the application of an electric field to a gate of the transistor, allowing the transistor to be used as a memory cell. In some cases, a FEFET has a ferroelectric hafnium zirconium oxide (Hf x Zr1-xO2) over a silicon channel. The coercive voltage to change the electric field of the ferroelectric material is typically 3-5 volts.
- In one embodiment disclosed herein, as described in more detail blow, the gate dielectric of a transistor is a ferroelectric perovskite, such as lead zirconate titanate (or PZT). As used herein, a dielectric material includes a linear dielectric material, a paraelectric material, or a ferroelectric material. The material of the channel is also a perovskite, with a lattice constant that matches that of the gate dielectric. The similarity of the gate dielectric and channel materials can reduce lattice defects, reduce trapped charges, reduce oxygen vacancies, and/or reduce polycrystalline or amorphous structure. As a result, the transistor performance can be increased, and the threshold voltage and leakage current can be reduced.
- As used herein, the phrase "communicatively coupled" refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive a signal to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of components that are communicatively coupled include integrated circuit dies located in the same package that communicate via an embedded bridge in a package substrate, and an integrated circuit component attached to a printed circuit board that send signals to or receives signals from other integrated circuit components or electronic devices attached to the printed circuit board.
- In the following description, specific details are set forth, but embodiments of the technologies described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. Phrases such as "an embodiment," "various embodiments," "some embodiments," and the like may include features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics.
- Some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner. "Connected" may indicate elements are in direct physical or electrical contact and "coupled" may indicate elements co-operate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. Terms modified by the word "substantially" include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, the central axis of a magnetic plug that is substantially coaxially aligned with a through hole may be misaligned from a central axis of the through hole by several degrees. In another example, a substrate assembly feature, such as a through width, that is described as having substantially a listed dimension can vary within a few percent of the listed dimension.
- It will be understood that in the examples shown and described further below, the figures may not be drawn to scale and may not include all possible layers and/or circuit components. In addition, it will be understood that although certain figures illustrate transistor designs with source/drain regions, electrodes, etc. having orthogonal (e.g., perpendicular) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within +/- 5 or 10 degrees of orthogonality) due to fabrication methods used to create such devices or for other reasons.
- Reference is now made to the drawings, which are not necessarily drawn to scale, wherein similar or same numbers may be used to designate the same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
- In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims.
- Referring now to
FIGS. 1 and 2 , in one embodiment, atransistor 100 has asubstrate 102, abody 104, asource 106, and adrain 108.FIG. 1 shows a top-down view of thetransistor 100, andFIG. 2 shows a cross-sectional view of thetransistor 100. Achannel 110 is between thesource 106 and thedrain 108. Asource electrode 112 is in contact with thesource 106, and adrain electrode 114 is in contact with thedrain 108. Agate dielectric 116 is above thechannel 110, and agate electrode 118 is above thegate dielectric 116. - In use, a voltage can be applied to the
gate electrode 118, which causes an electric field to be applied to thegate dielectric 116 and to thechannel 110. The illustrative gate dielectric 116 is ferroelectric. In the illustrative embodiment, if the applied voltage causes an electric field above a coercive field, the direction of the spontaneous polarization of the ferroelectric material can switch. The electric displacement of the ferroelectric material is the spontaneous polarization of the ferroelectric when no electric field is applied by thegate electrode 118. Under the applied field from the voltage of thegate electrode 118, the electric displacement of the ferroelectric material increases. As a result, the electric displacement applied to thechannel 110 is affected by the polarization state of the ferroelectric material of thegate dielectric 116, and, therefore, the current through thechannel 110 is affected by the polarization state of the ferroelectric material of thegate dielectric 116. As discussed in more detail below, this property can be used to facilitate low-threshold switching, single transistor memory, and compute-in-memory. - In the illustrative embodiment described in detail below, the
transistor 100 is a planar transistor. More generally, thetransistor 100 may be implemented as, e.g., FinFET, gate-all-around, and stacked gate-all-around transistors, as described in more detail below in regard toFIGS. 10A-10D . - The
substrate 102 supports thebody 104 and the rest of thetransistor 100. In the illustrative embodiment, thesubstrate 102 is strontium titanium oxide (SrTiO3 or STO or strontium titanate). The strontium titanium oxide, in turn, may be supported by, e.g., silicon, silicon dioxide, or any other suitable material. In other embodiments, thesubstrate 102 may be any suitable material that can interface with thebody 104, such as WO3, NaTaOs, BaTiO3, KTaO3, LaAlO3, MgO, or Al2O3. - In the illustrative embodiment, the
body 104 is a perovskite material. A perovskite material is any crystalline material with a crystal structure similar to calcium titanate (CaTiO3), typically with the chemical formula of ABX3, where A is one element, B is a second element, and X is a third element. In some cases, some of one (or more) of element A, B, or X in a perovskite material may be replaced by a different element. For example, in one embodiment, Pb(ZrxTi1-x )O3 (i.e., lead zirconate titanate or PZT) can have both zirconium and titanium as element B, with a varying amount of each depending on the value of x. A perovskite material may have various cation pairings, such as A+B2+X- 3, A2+B4+X2- 3, A3+B3+X2- 3, or A+B5+X2- 3. Thebody 104 may be any suitable perovskite material, such as barium tin oxide (BaSnO3, or barium stannate) La-doped STO, Pb(Zr0.52Ti0.48)O3, CaMnOs, and/or the like. In some embodiments, thebody 104 may not be a perovskite. For example, thebody 104 may be indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO), indium gallium zinc oxide (IGZO), or any other suitable material, such as other materials that do not have interface oxide layers. Some or all of thebody 104 may be n-doped or p-doped, depending on the transistor type. - In the illustrative embodiment, the
channel 110 is the same material as thebody 104. In some embodiments, thechannel 110 may be any of the materials referenced above in regard to thebody 104. In some embodiments, thechannel 110 may be doped differently from the rest of thebody 104. Thechannel 110 has a relatively high electron mobility, such as at least 50-500 cm2/(V∗s). In the illustrative embodiment, thechannel 110 is barium tin oxide with an electron mobility of about 100 cm2/(V∗s). - In the illustrative embodiment, the
channel 110 is lattice matched to thegate dielectric 116. As used herein, a material in thechannel 110 is lattice matched to the material in thegate dielectric 116 if the lattice constant for thechannel 110 is within 1% of the lattice constant of thegate dielectric 116. In other embodiments, the lattice mismatch between thechannel 110 and thegate dielectric 116 may be lower, such as less than 0.1% or less than 0.01% of the lattice constant of thegate dielectric 116. - Each of the
source 106 and drain 108 may be any suitable material, such as any of the materials referenced above in regard to thebody 104 orchannel 110. In the illustrative embodiment, each of thesource 106 and drain 108 are the same material as thebody 104 but with a different doping to make it more conductive. For example, for an n-dopedchannel 110, thesource 106 and drain 108 may be n-doped, and for a p-dopedchannel 110, thesource 106 and drain 108 may be p-doped. In the illustrative embodiment, thetransistor 100 is symmetric, and there is no functional distinction between thesource 106 and thedrain 108. - The
source electrode 112 anddrain electrode 114 may be any suitable material. For example, thesource electrode 112 and/or thedrain electrode 114 may be platinum, iridium, or other metal, polysilicon, a metallic perovskite, etc. - The illustrative gate dielectric 116 is lead zirconate titanate. The relative concentration or zirconium and titanium may be selected so that the
gate dielectric 116 is lattice matched to thechannel 110. In other embodiments, thegate dielectric 116 may be any suitable perovskite or non-perovskite ferroelectric. For example, thegate dielectric 116 may be barium titanate (BaTiO3 or BTO), lead niobate zirconate titanate ((Pb1-xNbx)(Zr1-yTiy)O3 or PNZT), lead lanthanum zirconate titanate ((Pbi-xLax)(Zr1-yTiy)O3 or PLZT), bismuth ferrite (BiFeO3 or BFO), lanthanum bismuth ferrite (LaxBi1-xFeO3 or LaBFO), etc. In the illustrative embodiment, thegate dielectric 116 has a relatively low coercive field of about 130 kV/cm, allowing the direction of the spontaneous polarization of the ferroelectric material of thegate dielectric 116 to be changed with a relatively low voltage applied to thegate electrode 118. More generally, thegate dielectric 116 may have any suitable coercive field, such as 50-500 kV/cm. Thegate dielectric 116 may be any suitable thickness. In the illustrative embodiment, thegate dielectric 116 may have a thickness of about 20-230 nanometers. Properties of thegate dielectric 116, such as the coercive field, may depend on the crystal orientation. Any suitable crystal orientation may be used, which may depend on the particular material being used. For example,ferroelectric gate dielectric 116 of PZT may have a crystal orientation of, e.g., (111) or (001) pseudocubic indices. - The threshold voltage of the
transistor 100 depends on thegate dielectric 116 material as well as thechannel 110 thickness and doping concentration. In the illustrative embodiment, the threshold voltage of thetransistor 100 is about 250 millivolts applied to thegate electrode 118, with the polarization of the ferroelectric material of thegate dielectric 116 increasing the electric displacement applied to thechannel 110. In other embodiments, the threshold voltage of thetransistor 100 may be any suitable value, such as 0.2-5 volts, depending on the materials used. - In some embodiments, the polarization of the ferroelectric of the
gate dielectric 116 switches all at once in a few picoseconds. In other embodiments, the ferroelectric of thegate dielectric 116 may have multiple domains that may switch at different applied electric fields (and, therefore, at different times). In such embodiments, the ferroelectric of thegate dielectric 116 may have multiple stable states that can be set by applying a particular voltage to thegate electrode 118. Such atransistor 100 can act as a multi-level memory or like an analog memory. - The
illustrative gate electrode 118 is a metallic perovskite, such as strontium ruthenate (SrRuO3 or SRO), lanthanum strontium manganite (La1-xSrxMnO3 or LMSO), lanthanum strontium cobalt oxide (La1-xSrxCoO3 or LSCO), SrVO3, SrCrO3, SrFeO3, ReO3, CaRuO3, SrMoO3, SrNbO3, LaNiOs, etc. In other embodiments, thegate electrode 118 may be other materials, such as platinum, iridium, or other metal, oxides with high electric conductivity that do not have the perovskite structure including RuO2, IrO2, and ITO, polysilicon, etc. In the illustrative embodiment, the work function of thegate electrode 118 is selected to shift the coercive voltage across thegate dielectric 116. For example, in one embodiment,FIG. 3 shows a curve of current from thesource 106 to thedrain 108, for a given voltage across thesource 106 and drain 108, as voltage applied to thegate electrode 118 is increased and then decreased. As the gate voltage is increased, the current follows thecurve 302, and as the gate voltage is decreased, the current follows thecurve 304. As the gate voltage is applied, the voltage increases past a first ferroelectric switching voltage to switch the spontaneous polarization of thegate dielectric 116 to a positive polarization (i.e., a polarization that applies an electric displacement in the direction of that caused by the gate dielectric 116). When the spontaneous polarization of thegate dielectric 116 switches, the electric displacement applied to thechannel 110 increases as well, effectively turning on thetransistor 100 at the same time as the spontaneous polarization of thegate dielectric 116 is switched. As the gate voltage is decreased, the voltage decreases past a second ferroelectric switching voltage to switch the spontaneous polarization of thegate dielectric 116 to a negative polarization (i.e., a polarization that applies an electric displacement opposite the direction of that caused by the gate dielectric 116). Thedifference 306 between the two ferroelectric switching voltages corresponds to 2∗EC ∗dFE, where EC is the coercive field of thegate dielectric 116 and dFE is the thickness of thegate dielectric 116. - It should be appreciated that the position of the ferroelectric switching voltages depends on the
gate electrode 118. InFIG. 3 , the lower ferroelectric switching voltage is shifted to a positive voltage, allowing the polarization of the ferroelectric to be controlled without applying a negative voltage to thegate electrode 118. - In another embodiment, a
transistor 100 may use agate electrode 118,gate dielectric 116,channel 110, etc., that results in a gate voltage/drain current relationship as shown inFIG. 4 . Following thecurve 402, as a positive voltage is applied to thegate electrode 118, the spontaneous polarization of the ferroelectric material of thegate dielectric 116 is flipped. Following thecurve 402, in one embodiment, as the voltage is reduced back to zero, the direction of the spontaneous polarization of the ferroelectric material of thegate dielectric 116 remains the same, effectively allowing the ferroelectric material of thegate dielectric 116 to turn thetransistor 100 on with no external voltage applied. In other embodiments, the polarization of the ferroelectric material of thegate dielectric 116 may be less than the threshold voltage of thetransistor 100. In order to flip the ferroelectric material back to the first polarization, the voltage applied to thegate electrode 118 must go to a negative value. - In the illustrative embodiment, the
transistor 100 has a gate voltage/drain current curve as shown inFIG. 3 , with a threshold voltage of 250 millivolts. The low threshold voltage reduces leakage current and reduces overall energy dissipation in the transistor. Such atransistor 100 can be used for general computing tasks such as adders, memory cells, etc. - In another embodiment, the
transistor 100 has a gate voltage/drain current curve, as shown inFIG. 4 . Such atransistor 100 can be used as a one-transistor memory cell to store one bit. Thetransistor 100 can be set by increasing the voltage past a threshold to set the polarization of the ferroelectric material of thegate dielectric 116 one way, and thetransistor 100 can be cleared by decreasing the voltage past a threshold to set the polarization of the ferroelectric material of thegate dielectric 116 the opposite way. The ferroelectric material of thegate dielectric 116 will maintain its polarization without a voltage applied to thegate electrode 118, allowing thetransistor 100 to act as a non-volatile memory cell. The state of the ferroelectric material of thegate dielectric 116 can be probed by detecting the current that can pass between thesource 106 and thedrain 108 at a given voltage. - In yet another embodiment, the
transistor 100 can be used in a compute-in-memory system. In such an embodiment, thetransistor 100 can be used both to perform calculations and store data. For example, in one embodiment, atransistor 100 may be used to implement a machine-learning-based algorithm, such as a neural network. Atransistor 100 may act as a neuron of a neural network and can hold a weight value that acts as an input to a level of a neural network. In some embodiments, such as embodiments in which the ferroelectric material of thegate dielectric 116 has multiple domains and can have multiple levels, thetransistor 100 can hold one of several possible weight values, not just 0 or 1. - Referring now to
FIGS. 5 and 6 , in one embodiment, atransistor 500 includes alinear gate dielectric 502 between theferroelectric gate dielectric 116 and thechannel 110. Thetransistor 500 includes similar components to thetransistor 100, such as thebody 104, thesource 106, thedrain 108, etc., a description of which will not be repeated in the interest of clarity. Thelinear gate dielectric 502 can reduce leakage current from thegate electrode 118, such as by reducing charge traps and/or oxygen vacancies. Thelinear gate dielectric 502 may be any suitable material. In some embodiments, thelinear gate dielectric 502 may be selected to be similar to thechannel 110 and/or thegate dielectric 116. For example, if thegate dielectric 116 is barium titanate, thelinear gate dielectric 502 may be barium oxide, BaZrO3, SrZrO3, LaScO3, LaInO3, SrSnO3, or titanium oxide. It should be appreciated that thelinear gate dielectric 502 may have a relatively high dielectric constant, leading to a high electric displacement applied to thechannel 110. - Referring now to
FIG. 7 , in one embodiment, a flowchart for amethod 700 for creating a transistor (such astransistor 100 or 500) is shown. Themethod 700 may be executed by a technician and/or by one or more automated machines. In some embodiments, one or more machines may be programmed to do some or all of the steps of themethod 700. Such a machine may include, e.g., a memory, a processor, data storage, etc. The memory and/or data storage may store instructions that, when executed by the machine, causes the machine to perform some or all of the steps of themethod 700. Themethod 700 may use any suitable set of techniques that are used in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, pulsed laser deposition, layer transfer, photolithography, ion implantation, dry etching, wet etching, thermal treatments, etc. - The
method 700 begins inblock 702, in which thebody 104 is deposited. In the illustrative embodiment, thebody 104 is barium tin oxide. Thebody 104 is deposited on thesubstrate 102. Thebody 104 may be deposited in any suitable manner, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, molecular beam epitaxy, pulsed laser deposition, etc. In some embodiments, thebody 104 is deposited using layer transfer. In the illustrative embodiment, thebody 104 is the same base structure as thesource 106, drain 108, andchannel 110. As such, thesource 106, drain 108, andchannel 110 do not need to be separately deposited, and a variation in the doping of this same layer can be achieved during the deposition process, if desired. In other embodiments, thesource 106, drain 108, and/orchannel 110 may be made from a different material as thebody 104 and may be deposited separately. - In
block 704, thesource 106, drain 108, andchannel 110 are doped, such as by using ion implantation. Thesource 106 and drain 108 are relatively heavily doped, and thechannel 110 is relatively lightly doped. Thechannel 110 is doped with the same carrier type as thesource 106 and drain 108. For example, thechannel 110 may be n-doped and thesource 106 and drain 108 may be n-doped, or all three may be p-doped. - In some embodiments, in
block 706, alinear gate dielectric 502 is applied, such as barium oxide, BaZrO3, SrZrO3, LaScO3, LaInO3, SrSnO3, or titanium oxide. Thelinear gate dielectric 502 may be applied using, e.g., photolithography and chemical layer deposition. In some embodiments, alinear gate dielectric 502 may not be used. - Depending upon the details of the atomic termination of the
channel layer 110, when, inblock 706, a dielectric with apolarization mismatch 502 is applied, such as LaScO3 or LaInOs, the carrier concentration of thechannel layer 110 may be altered through a process commonly known as "electronic reconstruction." This means of doping can be used in conjunction with doped (e.g., La-doped BaSnO3) or even completely undoped (e.g., stoichiometric BaSnO3) channel layers. The dielectric with apolarization mismatch 502 may be applied using an appropriate thin film growth technique in combination with patterning, e.g., photolithography and physical vapor deposition. In some embodiments a dielectric with apolarization mismatch 502 may not be used. - In some embodiments, in
block 706, a doped dielectric with a positive conduction band offset 502 is applied, such as La-doped SrSnO3. The purpose of the doped dielectric layer with positive conduction band offset is to alter the carrier concentration of thechannel layer 110 through a process commonly known as "modulation doping." This means of doping can be used in conjunction with doped (e.g., La-doped BaSnO3) or even completely undoped (e.g., stoichiometric BaSnO3) channel layers. The doped dielectric with positive conduction band offset 502 may be applied using an appropriate thin film growth technique in combination with patterning, e.g., photolithography and physical vapor deposition. In some embodiments a doped dielectric with positive conduction band offset 502 may not be used. - In
block 708, aferroelectric gate dielectric 116 is applied. In the illustrative embodiment, thegate dielectric 116 is BTO or PZT. Theferroelectric gate dielectric 116 may be applied using, e.g., photolithography and physical vapor deposition. - In
block 710, thegate electrode 118 is applied. In the illustrative embodiment, thegate electrode 118 is a metallic perovskite, such as SRO or LMSO. As discussed in more detail above, thegate electrode 118 may be selected based on its work function, which shifts the voltage at which the spontaneous polarization of the ferroelectric gate dielectric 116 changes. - In
block 712,source electrode 112 anddrain electrode 114 are applied. Thesource electrode 112 anddrain electrode 114 may be any suitable material, such as platinum, iridium, or other metal, polysilicon, a metallic perovskite, etc. Thesource electrode 112 anddrain electrode 114 may be applied using, e.g., photolithography and physical vapor deposition. - It should be appreciated that the
method 700 is one of many possible embodiments of manufacturing thetransistor 100. Different approaches or orders of steps are envisioned as well. For example, theferroelectric gate dielectric 116 andgate electrode 118 may be applied before doping thesource 106 and drain 108, creating a self-aligned gate. It should be appreciated that a complete manufacturing process of an integrated circuit that includes thetransistor 100 may include steps not shown in themethod 700, such as cleaning, surface passivation, creating interconnects, packaging, etc. -
FIG. 8 is a top view of awafer 800 and dies 802 that may include one or more of any of thetransistors wafer 800 may be composed of semiconductor material and may include one or more dies 802 having integrated circuit structures formed on a surface of thewafer 800. The individual dies 802 may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the fabrication of the semiconductor product is complete, thewafer 800 may undergo a singulation process in which the dies 802 are separated from one another to provide discrete "chips" of the integrated circuit product. Thedie 802 may include one or more transistors (e.g., some of thetransistors 940 ofFIG. 9 , discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other integrated circuit components. In some embodiments, thewafer 800 or thedie 802 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on asingle die 802. For example, a memory array formed by multiple memory devices may be formed on asame die 802 as a processor unit (e.g., theprocessor unit 1202 ofFIG. 12 ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. Various ones of thetransistors wafer 800 that include others of the dies, and thewafer 800 is subsequently singulated. -
FIG. 9 is a cross-sectional side view of anintegrated circuit device 900 that may include any of thetransistors integrated circuit devices 900 may be included in one or more dies 802 (FIG. 8 ). Theintegrated circuit device 900 may be formed on a die substrate 902 (e.g., thewafer 800 ofFIG. 8 ) and may be included in a die (e.g., thedie 802 ofFIG. 8 ). Thedie substrate 902 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type orp-type materials systems (or a combination of both). Thedie substrate 902 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, thedie substrate 902 may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form thedie substrate 902. Although a few examples of materials from which thedie substrate 902 may be formed are described here, any material that may serve as a foundation for anintegrated circuit device 900 may be used. Thedie substrate 902 may be part of a singulated die (e.g., the dies 802 ofFIG. 8 ) or a wafer (e.g., thewafer 800 ofFIG. 8 ). - The
integrated circuit device 900 may include one or more device layers 904 disposed on thedie substrate 902. Thedevice layer 904 may include features of one or more transistors 940 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on thedie substrate 902. Thetransistors 940 may include, for example, one or more source and/or drain (S/D)regions 920, agate 922 to control current flow between the S/D regions 920, and one or more S/D contacts 924 to route electrical signals to/from the S/D regions 920. Thetransistors 940 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. Thetransistors 940 are not limited to the type and configuration depicted inFIG. 9 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non- planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors. -
FIGS. 10A-10D are simplified perspective views of example planar, FinFET, gate-all-around, and stacked gate-all-around transistors. Any of thetransistors FIGS. 10A-10D are formed on asubstrate 1016 having asurface 1008.Isolation regions 1014 separate the source and drain regions of the transistors from other transistors and from abulk region 1018 of thesubstrate 1016. -
FIG. 10A is a perspective view of anexample planar transistor 1000 comprising agate 1002 that controls current flow between asource region 1004 and adrain region 1006. Thetransistor 1000 is planar in that thesource region 1004 and thedrain region 1006 are planar with respect to thesubstrate surface 1008. -
FIG. 10B is a perspective view of anexample FinFET transistor 1020 comprising agate 1022 that controls current flow between asource region 1024 and adrain region 1026. Thetransistor 1020 is non-planar in that thesource region 1024 and thedrain region 1026 comprise "fins" that extend upwards from the substrate surface 1028. As thegate 1022 encompasses three sides of the semiconductor fin that extends from thesource region 1024 to thedrain region 1026, thetransistor 1020 can be considered a tri-gate transistor.FIG. 10B illustrates one S/D fin extending through thegate 1022, but multiple S/D fins can extend through the gate of a FinFET transistor. -
FIG. 10C is a perspective view of a gate-all-around (GAA)transistor 1040 comprising agate 1042 that controls current flow between asource region 1044 and adrain region 1046. Thetransistor 1040 is non-planar in that thesource region 1044 and thedrain region 1046 are elevated from the substrate surface 1028. -
FIG. 10D is a perspective view of aGAA transistor 1060 comprising agate 1062 that controls current flow between multipleelevated source regions 1064 and multipleelevated drain regions 1066. Thetransistor 1060 is a stacked GAA transistor as the gate controls the flow of current between multiple elevated S/D regions stacked on top of each other. Thetransistors transistors widths transistors - Returning to
FIG. 9 , atransistor 940 may include agate 922 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. - The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, bismuth, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
- The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the
transistor 940 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. - For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
- In some embodiments, when viewed as a cross-section of the
transistor 940 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of thedie substrate 902 and two sidewall portions that are substantially perpendicular to the top surface of thedie substrate 902. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of thedie substrate 902 and does not include sidewall portions substantially perpendicular to the top surface of thedie substrate 902. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. - In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
- The S/
D regions 920 may be formed within thedie substrate 902 adjacent to thegate 922 ofindividual transistors 940. The S/D regions 920 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ionimplanted into thedie substrate 902 to form the S/D regions 920. An annealing process that activates the dopants and causes them to diffuse farther into thedie substrate 902 may follow the ion-implantation process. In the latter process, thedie substrate 902 may first be etched to form recesses at the locations of the S/D regions 920. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 920. In some implementations, the S/D regions 920 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 920 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 920. - Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 940) of the
device layer 904 through one or more interconnect layers disposed on the device layer 904 (illustrated inFIG. 9 as interconnect layers 906-910). For example, electrically conductive features of the device layer 904 (e.g., thegate 922 and the S/D contacts 924) may be electrically coupled with theinterconnect structures 928 of the interconnect layers 906-910. The one or more interconnect layers 906-910 may form a metallization stack (also referred to as an "ILD stack") 919 of theintegrated circuit device 900. - The
interconnect structures 928 may be arranged within the interconnect layers 906-910 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration ofinterconnect structures 928 depicted inFIG. 9 . Although a particular number of interconnect layers 906-910 is depicted inFIG. 9 , embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted. - In some embodiments, the
interconnect structures 928 may includelines 928a and/orvias 928b filled with an electrically conductive material such as a metal. Thelines 928a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of thedie substrate 902 upon which thedevice layer 904 is formed. Thevias 928b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of thedie substrate 902 upon which thedevice layer 904 is formed. In some embodiments, thevias 928b may electrically couplelines 928a of different interconnect layers 906-910 together. - The interconnect layers 906-910 may include a
dielectric material 926 disposed between theinterconnect structures 928, as shown inFIG. 9 . In some embodiments,dielectric material 926 disposed between theinterconnect structures 928 in different ones of the interconnect layers 906-910 may have different compositions; in other embodiments, the composition of thedielectric material 926 between different interconnect layers 906-910 may be the same. Thedevice layer 904 may include adielectric material 926 disposed between thetransistors 940 and a bottom layer of the metallization stack as well. Thedielectric material 926 included in thedevice layer 904 may have a different composition than thedielectric material 926 included in the interconnect layers 906-910; in other embodiments, the composition of thedielectric material 926 in thedevice layer 904 may be the same as adielectric material 926 included in any one of the interconnect layers 906-910. - A first interconnect layer 906 (referred to as Metal 1 or "M1") may be formed directly on the
device layer 904. In some embodiments, thefirst interconnect layer 906 may includelines 928a and/orvias 928b, as shown. Thelines 928a of thefirst interconnect layer 906 may be coupled with contacts (e.g., the S/D contacts 924) of thedevice layer 904. The vias 928b of thefirst interconnect layer 906 may be coupled with thelines 928a of asecond interconnect layer 908. - The second interconnect layer 908 (referred to as
Metal 2 or "M2") may be formed directly on thefirst interconnect layer 906. In some embodiments, thesecond interconnect layer 908 may include via 928b to couple thelines 928 of thesecond interconnect layer 908 with thelines 928a of athird interconnect layer 910. Although thelines 928a and thevias 928b are structurally delineated with a line within individual interconnect layers for the sake of clarity, thelines 928a and thevias 928b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments. - The third interconnect layer 910 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the
second interconnect layer 908 according to similar techniques and configurations described in connection with thesecond interconnect layer 908 or thefirst interconnect layer 906. In some embodiments, the interconnect layers that are "higher up" in themetallization stack 919 in the integrated circuit device 900 (i.e., farther away from the device layer 904) may be thicker that the interconnect layers that are lower in themetallization stack 919, withlines 928a and vias 928b in the higher interconnect layers being thicker than those in the lower interconnect layers. - The
integrated circuit device 900 may include a solder resist material 934 (e.g., polyimide or similar material) and one or moreconductive contacts 936 formed on the interconnect layers 906-910. InFIG. 9 , theconductive contacts 936 are illustrated as taking the form of bond pads. Theconductive contacts 936 may be electrically coupled with theinterconnect structures 928 and configured to route the electrical signals of the transistor(s) 940 to external devices. For example, solder bonds may be formed on the one or moreconductive contacts 936 to mechanically and/or electrically couple an integrated circuit die including the integratedcircuit device 900 with another component (e.g., a printed circuit board). Theintegrated circuit device 900 may include additional or alternate structures to route the electrical signals from the interconnect layers 906-910; for example, theconductive contacts 936 may include other analogous features (e.g., posts) that route the electrical signals to external components. - In some embodiments in which the
integrated circuit device 900 is a double-sided die, theintegrated circuit device 900 may include another metallization stack (not shown) on the opposite side of the device layer(s) 904. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 906-910, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 904 and additional conductive contacts (not shown) on the opposite side of theintegrated circuit device 900 from theconductive contacts 936. - In other embodiments in which the
integrated circuit device 900 is a double-sided die, theintegrated circuit device 900 may include one or more through silicon vias (TSVs) through thedie substrate 902; these TSVs may make contact with the device layer(s) 904, and may provide conductive pathways between the device layer(s) 904 and additional conductive contacts (not shown) on the opposite side of theintegrated circuit device 900 from theconductive contacts 936. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of theintegrated circuit device 900 from theconductive contacts 936 to thetransistors 940 and any other components integrated into thedie 900, and themetallization stack 919 can be used to route I/O signals from theconductive contacts 936 totransistors 940 and any other components integrated into thedie 900. - Multiple
integrated circuit devices 900 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps). -
FIG. 11 is a cross-sectional side view of an integratedcircuit device assembly 1100 that may include any of thetransistors circuit device assembly 1100 includes a number of components disposed on a circuit board 1102 (which may be a motherboard, system board, mainboard, etc.). The integratedcircuit device assembly 1100 includes components disposed on afirst face 1140 of thecircuit board 1102 and an opposingsecond face 1142 of thecircuit board 1102; generally, components may be disposed on one or bothfaces - In some embodiments, the
circuit board 1102 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to thecircuit board 1102. In other embodiments, thecircuit board 1102 may be a non-PCB substrate. The integratedcircuit device assembly 1100 illustrated inFIG. 11 includes a package-on-interposer structure 1136 coupled to thefirst face 1140 of thecircuit board 1102 bycoupling components 1116. Thecoupling components 1116 may electrically and mechanically couple the package-on-interposer structure 1136 to thecircuit board 1102, and may include solder balls (as shown inFIG. 11 ), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. - The package-on-
interposer structure 1136 may include anintegrated circuit component 1120 coupled to aninterposer 1104 bycoupling components 1118. Thecoupling components 1118 may take any suitable form for the application, such as the forms discussed above with reference to thecoupling components 1116. Although a singleintegrated circuit component 1120 is shown inFIG. 11 , multiple integrated circuit components may be coupled to theinterposer 1104; indeed, additional interposers may be coupled to theinterposer 1104. Theinterposer 1104 may provide an intervening substrate used to bridge thecircuit board 1102 and theintegrated circuit component 1120. - The
integrated circuit component 1120 may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., thedie 802 ofFIG. 8 , theintegrated circuit device 900 ofFIG. 9 ) and/or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate with the integrated circuit dies and package substrate encapsulated in a casing material, such as a metal, plastic, glass, or ceramic. In one example of an unpackagedintegrated circuit component 1120, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to theinterposer 1104. Theintegrated circuit component 1120 can comprise one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I/O controller, memory, or network interface controller. In some embodiments, theintegrated circuit component 1120 can comprise one or more additional active or passive devices such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. - In embodiments where the
integrated circuit component 1120 comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM). - In addition to comprising one or more processor units, the
integrated circuit component 1120 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as "chiplets". In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof. - Generally, the
interposer 1104 may spread connections to a wider pitch or reroute a connection to a different connection. For example, theinterposer 1104 may couple theintegrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of thecoupling components 1116 for coupling to thecircuit board 1102. In the embodiment illustrated inFIG. 11 , theintegrated circuit component 1120 and thecircuit board 1102 are attached to opposing sides of theinterposer 1104; in other embodiments, theintegrated circuit component 1120 and thecircuit board 1102 may be attached to a same side of theinterposer 1104. In some embodiments, three or more components may be interconnected by way of theinterposer 1104. - In some embodiments, the
interposer 1104 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, theinterposer 1104 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, theinterposer 1104 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. Theinterposer 1104 may includemetal interconnects 1108 and vias 1110, including but not limited to through hole vias 1110-1 (that extend from afirst face 1150 of theinterposer 1104 to asecond face 1154 of the interposer 1104), blind vias 1110-2 (that extend from the first orsecond faces interposer 1104 to an internal metal layer), and buried vias 1110-3 (that connect internal metal layers). - In some embodiments, the
interposer 1104 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, aninterposer 1104 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of theinterposer 1104 to an opposing second face of theinterposer 1104. - The
interposer 1104 may further include embeddeddevices 1114, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on theinterposer 1104. The package-on-interposer structure 1136 may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board - The integrated
circuit device assembly 1100 may include anintegrated circuit component 1124 coupled to thefirst face 1140 of thecircuit board 1102 bycoupling components 1122. Thecoupling components 1122 may take the form of any of the embodiments discussed above with reference to thecoupling components 1116, and theintegrated circuit component 1124 may take the form of any of the embodiments discussed above with reference to theintegrated circuit component 1120. - The integrated
circuit device assembly 1100 illustrated inFIG. 11 includes a package-on-package structure 1134 coupled to thesecond face 1142 of thecircuit board 1102 bycoupling components 1128. The package-on-package structure 1134 may include anintegrated circuit component 1126 and anintegrated circuit component 1132 coupled together by couplingcomponents 1130 such that theintegrated circuit component 1126 is disposed between thecircuit board 1102 and theintegrated circuit component 1132. Thecoupling components coupling components 1116 discussed above, and theintegrated circuit components integrated circuit component 1120 discussed above. The package-on-package structure 1134 may be configured in accordance with any of the package-on-package structures known in the art. -
FIG. 12 is a block diagram of an exampleelectrical device 1200 that may include one or more of thetransistors electrical device 1200 may include one or more of the integratedcircuit device assemblies 1100, integratedcircuit components 1120, integratedcircuit devices 900, or integrated circuit dies 802 disclosed herein. A number of components are illustrated inFIG. 12 as included in theelectrical device 1200, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in theelectrical device 1200 may be attached to one or more motherboards mainboards, or system boards. In some embodiments, one or more of these components are fabricated onto a single system-on-a-chip (SoC) die. - Additionally, in various embodiments, the
electrical device 1200 may not include one or more of the components illustrated inFIG. 12 , but theelectrical device 1200 may include interface circuitry for coupling to the one or more components. For example, theelectrical device 1200 may not include adisplay device 1206, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which adisplay device 1206 may be coupled. In another set of examples, theelectrical device 1200 may not include anaudio input device 1224 or anaudio output device 1208, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which anaudio input device 1224 oraudio output device 1208 may be coupled. - The
electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor units). As used herein, the terms "processor unit", "processing unit" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Theprocessor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU). - The
electrical device 1200 may include amemory 1204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, thememory 1204 may include memory that is located on the same integrated circuit die as theprocessor unit 1202. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). - In some embodiments, the
electrical device 1200 can comprise one ormore processor units 1202 that are heterogeneous or asymmetric to anotherprocessor unit 1202 in theelectrical device 1200. There can be a variety of differences between theprocessing units 1202 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among theprocessor units 1202 in theelectrical device 1200. - In some embodiments, the
electrical device 1200 may include a communication component 1212 (e.g., one or more communication components). For example, thecommunication component 1212 can manage wireless communications for the transfer of data to and from theelectrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they might not. - The
communication component 1212 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Thecommunication component 1212 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Thecommunication component 1212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Thecommunication component 1212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Thecommunication component 1212 may operate in accordance with other wireless protocols in other embodiments. Theelectrical device 1200 may include anantenna 1222 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). - In some embodiments, the
communication component 1212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, thecommunication component 1212 may include multiple communication components. For instance, afirst communication component 1212 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and asecond communication component 1212 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, afirst communication component 1212 may be dedicated to wireless communications, and asecond communication component 1212 may be dedicated to wired communications. - The
electrical device 1200 may include battery/power circuitry 1214. The battery/power circuitry 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of theelectrical device 1200 to an energy source separate from the electrical device 1200 (e.g., AC line power). - The
electrical device 1200 may include a display device 1206 (or corresponding interface circuitry, as discussed above). Thedisplay device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. - The
electrical device 1200 may include an audio output device 1208 (or corresponding interface circuitry, as discussed above). Theaudio output device 1208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds. - The
electrical device 1200 may include an audio input device 1224 (or corresponding interface circuitry, as discussed above). Theaudio input device 1224 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). Theelectrical device 1200 may include a Global Navigation Satellite System (GNSS) device 1218 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. TheGNSS device 1218 may be in communication with a satellite-based system and may determine a geolocation of theelectrical device 1200 based on information received from one or more GNSS satellites, as known in the art. - The
electrical device 1200 may include an other output device 1210 (or corresponding interface circuitry, as discussed above). Examples of theother output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. - The
electrical device 1200 may include an other input device 1220 (or corresponding interface circuitry, as discussed above). Examples of theother input device 1220 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader. - The
electrical device 1200 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, theelectrical device 1200 may be any other electronic device that processes data. In some embodiments, theelectrical device 1200 may comprise multiple discrete physical components. Given the range of devices that theelectrical device 1200 can be manifested as in various embodiments, in some embodiments, theelectrical device 1200 can be referred to as a computing device or a computing system. - Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
- Example 1 includes a device comprising a source; a drain; a channel between the source and the drain; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric, wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- Example 2 includes the subject matter of Example 1, and wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the gate electrode is a metallic perovskite.
- Example 4 includes the subject matter of any of Examples 1-3, and wherein the channel has an electron mobility of at least 50 cm2/(V∗s).
- Example 5 includes the subject matter of any of Examples 1-4, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 6 includes the subject matter of any of Examples 1-5, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 7 includes the subject matter of any of Examples 1-6, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 8 includes the subject matter of any of Examples 1-7, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- Example 9 includes the subject matter of any of Examples 1-8, and further including a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- Example 10 includes the subject matter of any of Examples 1-9, and wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- Example 11 includes the subject matter of any of Examples 1-10, and wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above a threshold voltage of the device to zero voltage.
- Example 12 includes an integrated circuit comprising the device of Example 1, wherein a polarization state of the gate dielectric stores a weight of a neuron of a neural network.
- Example 13 includes the subject matter of Example 12, and wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- Example 14 includes a memory device comprising the device in Example 13, wherein the two stable polarization states of the gate dielectric is used to store a memory bit.
- Example 15 includes the subject matter of Example 14, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.
- Example 16 includes a processor comprising the device of Example 1.
- Example 17 includes a system comprising the processor of Example 16 and one or more memory devices.
- 18. A device comprising a source; a drain; a channel between the source and the drain; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric,
- wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- Example 19 includes the subject matter of any of Examples 17 and 18, and wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- Example 20 includes the subject matter of any of Examples 17-19, and wherein the gate electrode is a metallic perovskite.
- Example 21 includes the subject matter of any of Examples 17-20, and wherein the channel has an electron mobility of at least 50 cm2/(V∗s).
- Example 22 includes the subject matter of any of Examples 17-21, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 23 includes the subject matter of any of Examples 17-22, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 24 includes the subject matter of any of Examples 17-23, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 25 includes the subject matter of any of Examples 17-24, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- Example 26 includes the subject matter of any of Examples 17-25, and further including a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- Example 27 includes the subject matter of any of Examples 17-26, and wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- Example 28 includes the subject matter of any of Examples 17-27, and wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above a threshold voltage of the device to zero voltage.
- Example 29 includes an integrated circuit comprising the device of Example 18, wherein a polarization state of the gate dielectric stores a weight of a neuron of a neural network.
- Example 30 includes the subject matter of Example 29, and wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- Example 31 includes a memory device comprising the device in Example 30, wherein the two stable polarization states of the gate dielectric is used to store a memory bit.
- Example 32 includes the subject matter of Example 31, and wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.
- Example 33 includes a processor comprising the device of Example 18.
- Example 34 includes a system comprising the processor of Example 33 and one or more memory devices.
- Example 35 includes a device comprising a transistor comprising a source; a drain; a channel between the source and the drain; a gate electrode; and a gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric, wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 36 includes the subject matter of Example 35, and wherein the gate electrode is a metallic perovskite.
- Example 37 includes the subject matter of any of Examples 35 and 36, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 38 includes the subject matter of any of Examples 35-37, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 39 includes the subject matter of any of Examples 35-38, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- Example 40 includes the subject matter of any of Examples 35-39, and further including a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- Example 41 includes the subject matter of any of Examples 35-40, and wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- Example 42 includes the subject matter of any of Examples 35-41, and wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above the threshold voltage to zero voltage.
- Example 43 includes an integrated circuit comprising the device of Example 35, wherein a polarization state of the gate dielectric stores a weight of a neuron of a neural network.
- Example 44 includes the subject matter of Example 43, and wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- Example 45 includes a memory device comprising the device in Example 44, wherein the two stable polarization states of the gate dielectric is used to store a memory bit.
- Example 46 includes the subject matter of Example 45, and wherein the transistor is a FinFET, a gate-all-around transistor, or a stacked gate-all-around-transistor.
- Example 47 includes a processor comprising the device of Example 35.
- Example 48 includes a system comprising the processor of Example 47 and one or more memory devices.
- Example 49 includes a method comprising depositing a channel of a transistor; depositing a gate dielectric over the channel, wherein the gate dielectric is ferroelectric; and depositing a gate electrode over the gate dielectric, wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- Example 50 includes the subject matter of Example 49, and wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- Example 51 includes the subject matter of any of Examples 49 and 50, and wherein a threshold voltage of the transistor is less than 0.5 volts.
- Example 52 includes the subject matter of any of Examples 49-51, and wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- Example 53 includes the subject matter of any of Examples 49-52, and wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- Example 54 includes the subject matter of any of Examples 49-53, and wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
Claims (15)
- A device comprising:a source;a drain;a channel between the source and the drain;a gate electrode; anda gate dielectric between the gate electrode and the channel, wherein the gate dielectric is ferroelectric,wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- The device of claim 1, wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
- The device of claim 2, wherein the gate electrode is a metallic perovskite.
- The device of claim 2, wherein the channel has an electron mobility of at least 50 cm2/(V∗s).
- The device of claim 1, wherein the device comprises a transistor, wherein the transistor comprises the source, the drain, the channel, the gate dielectric, and the gate electrode, wherein a threshold voltage of the transistor is less than 0.5 volts.
- The device of claim 1, wherein the gate dielectric comprises lead, zirconium, titanium, and oxygen, wherein the channel comprises barium, tin, and oxygen.
- The device of claim 6, wherein the gate electrode comprises strontium, ruthenium, and oxygen.
- The device of claim 6, wherein the gate electrode comprises lanthanum, strontium, manganese, and oxygen.
- The device of claim 1, further comprising a linear gate dielectric between the ferroelectric gate dielectric and the channel.
- The device of claim 9, wherein the ferroelectric gate dielectric comprises barium, titanium, and oxygen, wherein the linear gate dielectric comprises (i) barium and oxygen or (ii) titanium and oxygen.
- The device of claim 1, wherein the gate electrode has a work function such that the gate dielectric switches polarization in response to a change of voltage applied to the gate electrode from above a threshold voltage of the device to zero voltage.
- The device of claim 1, wherein the gate electrode has a work function such that the gate dielectric has two stable polarization states when zero voltage is applied to the gate electrode.
- A processor comprising the device of claim 1.
- A method comprising:depositing a channel of a transistor;depositing a gate dielectric over the channel, wherein the gate dielectric is ferroelectric; anddepositing a gate electrode over the gate dielectric,wherein the gate dielectric has a lattice constant that is matched to a lattice constant of the channel.
- The method of claim 14, wherein the gate dielectric is a first perovskite material, wherein the channel is a second perovskite material.
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