EP4211803A1

EP4211803A1 - Wideband low phase noise digitally controlled oscillator using switched inductors

Info

Publication number: EP4211803A1
Application number: EP21725671.8A
Authority: EP
Inventors: Michael Bushman; Lawrence Connell; Daniel Mccarthy; James Caldwell
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-09-28
Filing date: 2021-01-22
Publication date: 2023-07-19
Also published as: EP4211803A4; CN116210151A; WO2021097493A1

Abstract

A digitally-controlled oscillator (DCO) is provided. In one aspect, the DCO includes a resonant tank that can include multiple inductors and multiple metal-oxide-semiconductor (MOS) transistors. The resonant tank can include a first circuit connected between a first pair of inductors, a second circuit connected between a second pair of inductors, a third circuit connected between a third pair of inductors, and a fourth circuit connected between a fourth pair. Each of the third and fourth circuits can include a capacitor and a switching element. Each of the first and second pair of circuits include an inductor arranged in parallel with a respective switching element. Each of the third and fourth pair of inductors can include an inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors. The fourth pair of inductors can be different from the third pair of inductors.

Description

WIDEBAND LOW PHASE NOISE DIGITALLY CONTROLLED OSCILLATOR

USING SWITCHED INDUCTORS

BACKGROUND

In a wireless/wired terminal, such as a cellular phone or Wi-Fi device, a digitally- controlled oscillator (DCO) is part of the phase locked loop (PLL) that provides the local oscillator signal used for radio frequency (RF) transmission and reception.

SUMMARY

By operating with low phase noise and a broad frequency range, the components that provide the local oscillator signal can enable such a terminal to communicate on a wide spectrum of cellular frequencies. However, current DCO designs generally cannot cover the entire spectrum of cellular frequencies with a single DCO with sufficiently low phase noise. As such, in order to support communication on the entire spectrum of cellular frequencies, many terminals employ two or more DCOs per PLL. The inductors of each DCO occupy a relatively large die area and often must be spaced relatively far apart from one another to attenuate magnetic coupling effects, which adds to the cost of the integrated circuit (IC).

The subject matter described in this specification can be implemented in particular embodiments to realize one or more of the following advantages. The objective of one or more of the systems and techniques disclosed herein is to increase the frequency range of a DCO to allow it to cover enough range that a second DCO is not required for a PLL to cover all cellular frequencies. In this way, such systems and techniques may provide both size and cost savings.

In general, one innovative aspect of the subject matter described in this specification can be embodied in a digitally-controlled oscillator (DCO) that can include a resonant tank, which can include a plurality of inductors; a plurality of metal-oxide-semiconductor (MOS) transistors, wherein a terminal of each MOS transistor in the plurality of MOS transistors is coupled to a tapping point of a respective inductor in the plurality of inductors; a first circuit connected between a first pair of inductors in the plurality of inductors, wherein the first circuit comprises a first inductor arranged in parallel with a first switching element; a second circuit connected between a second pair of inductors in the plurality of inductors, wherein the second circuit comprises a second inductor arranged in parallel with a second switching element; a third circuit connected between a third pair of inductors in the plurality of inductors, the third pair of inductors having one inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors, wherein the third circuit comprises a capacitor and a switching element; and a fourth circuit connected between a fourth pair of inductors in the plurality of inductors, the fourth pair of inductors having one inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors, wherein the fourth circuit comprises a capacitor and a switching element and wherein the fourth pair of inductors are different from the third pair of inductors.

The foregoing and other embodiments can each optionally include one or more of the features described herein, alone or in combination. In particular, one embodiment includes all the following features in combination.

In some implementations, each inductor in the plurality of inductors has a same inductance.

In some implementations, the DCO can include a control circuit communicatively coupled to each of the first circuit and the second circuit, the control circuit configured to control the first and second circuits to switch between a first mode and a second mode. In the first mode, both the first and second switching elements can be open and in the second mode, both the first and second switching elements are closed.

In some implementations, in the first mode, the resonant tank can be configured to generate signals in a first range of frequencies; and in the second mode, the resonant tank can be configured to generate signals in a second range of frequencies different from the first range of frequencies.

In some implementations, the control circuit can be communicatively coupled to each of the third circuit and the fourth circuit, such that in the first mode, the control circuit is configured to selectively control the switching element in the third circuit, the switching element in the fourth circuit, or both, to tune the resonant tank to a specific frequency in the first range of frequencies; and in the second mode, the control circuit is configured to selectively control the switching element in the third circuit, the switching element in the fourth circuit, or both, to tune the resonant tank to a specific frequency in the second range of frequencies.

In some implementations, each of the first and second inductors can have a same inductance, and the inductance of each of the first and second inductors can be different from an inductance of each of the plurality of inductors. In some implementations, the resonant tank can be formed on a single semiconductor substrate.

In some implementations, each of the third and fourth circuits can include a plurality of capacitors and a plurality of switching elements.

In some implementations, the terminal of each MOS transistor in the plurality of MOS transistors can include a drain terminal.

In some implementations, a gate terminal of each MOS transistor in the plurality of MOS transistors can be coupled to a respective point in a plurality of points within the resonant tank.

In some implementations, the plurality of points within the resonant tank can include (i) a point between the first pair of inductors and the third circuit, (ii) a point between the first pair of inductors and the fourth circuit, (iii) a point between the second pair of inductors and the third circuit, and (iv) a point between the second pair of inductors and the fourth circuit.

The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example wireless communication system.

FIG. 2 is a block diagram of an example wireless device that may implement the methods and teachings according to this disclosure.

FIGS. 3A-3B are schematics of example DCOs.

FIG. 4 shows a layout of the example DCO of FIG. 3B, according to some implementations.

FIG. 5 is a schematic of example DCO of FIG. 3B, according to some implementations.

FIG. 6 shows a table of specifications.

FIGs. 7A-B show various plots of inductance as a function of resonant frequency for the DCO. DETAILED DESCRIPTION

FIG. 1 shows a block diagram of an example wireless communication system 100 that includes a wireless device 110 capable of communicating with one or more wireless communication networks. The one or more wireless communication networks with which the wireless device 110 is capable of communicating can include but is not limited to one or more cellular or wireless wide area networks (WWANs), one or more wireless local area networks (WLANs), one or more wireless personal area networks (WPANs), or a combination thereof.

In the example of FIG. 1, the wireless device 110 is depicted as being capable of communicating with at least one WWAN by way of at least one base station 120 and at least one WLAN by way of at least one access point 130. The at least one base station 120 can support bi-directional communication with wireless devices that are within its corresponding area of coverage 122. Similarly, the at least one access point 130 can support bi-directional communication with wireless devices that are within its corresponding area of coverage 132.

In some implementations, the at least one WWAN with which the at least one base station 120 is associated can be a fifth generation (5G) network among other generations and types of networks. In these implementations, the at least one base station 120 can be a 5G base station that employs orthogonal frequency-division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g. 100 or 200 microseconds), to communicate with wireless devices, such as wireless device 110. For example, the at least one base station 120 can take the form of one of several devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point, or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network. In addition, and as shown in FIG. 1, wireless device 110 is configured to communicate with one or more personal area network (PAN) devices/systems 130 (e.g., Bluetooth® or radio frequency identification (RFID) systems and devices) over one or more WPANs.

System 100 can use multiple channel access functionality, including for example schemes in which the at least one base station 120 and the wireless device 110 are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other implementations, the at least one base stations 120 and wireless device 110 are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols can be utilized. Wireless device 110 can include one or more transmitters and receivers similar to those described below with reference to FIG. 2 to support multiple communications with different types of access points, base stations, and other wireless communications devices.

Examples of transmitter components and RF power amplifiers that can be employed in wireless device 110 and other similar devices are described in further detail below with reference to FIGS. 2-6. Although FIG. 1 illustrates one example of a communication system, various changes can be made to FIG. 1. For example, the communication system 100 could include any number of wireless devices, base stations, access points, networks, or other components in any suitable configuration.

FIG. 2 is a block diagram of an example wireless device 110 that may implement the methods and teachings according to this disclosure. The wireless device 110 can, for example, be a mobile telephone, but can be other devices in further examples such as a desktop computer, laptop computer, tablet, hand-held computing device, automobile computing device and/or other computing devices. As shown in FIG. 2, the wireless device 110 is shown as including at least one transmitter 210, at least one receiver 220, at least one memory 230, at least one processor 240, and at least one input/output device 260. Here, only one transmitter and one receiver are shown, but in many embodiments multiple transmitters and receivers are included to support multiple communications of different types at the same time. Each transmitter may employ the innovations of the present disclosure.

The processor 240 can implement various processing operations of the wireless device 110. For example, the processor 240 can perform signal coding, data processing, power control, input/output processing, or any other functionality enabling the wireless device 110 to operate in the system 100 (FIG. 1). The processor 240 can include any suitable processing or computing device configured to perform one or more operations. For example, the processor 240 can include a microprocessor, microcontroller, digital signal processor, field programmable gate array, application specific integrated circuit, or a combination of these devices.

The transmitter 210 is configured to modulate data or other content for transmission by at least one antenna 250A. The transmitter 210 can also be configured to amplify, filter, and upconvert baseband or intermediate frequency signals to radio frequency (RF) signals before such signals are provided to a power amplifier and then antenna 250A for transmission. The transmitter 210 can include any suitable structure for generating signals for wireless transmission. Additional aspects of the transmitter 210 are described in further detail below with reference to components 212-218 as depicted in FIG. 2.

The receiver 220 can be configured to demodulate data or other content received by at least one antenna 250B. The receiver 220 can also be configured to amplify, filter, and frequency convert RF signals received via the antenna 250B. The receiver 220 can include any suitable structure for processing signals received wirelessly.

Each of the antennas 250A and 250B can include any suitable structure for transmitting and/or receiving wireless signals. In some implementations, the antennas 250A and 250B can be implemented as a single antenna that can be used for both transmitting and receiving RF signals.

It is appreciated that one or multiple transmitters 210 could be used in the wireless device 110, one or multiple receivers 220 could be used in the wireless device 110, and one or multiple antennas 250 could be used in the wireless device 110. Although shown as separate blocks or components, at least one transmitter 210 and at least one receiver 220 could be combined into a transceiver. Accordingly, rather than showing a separate block for the transmitter 210 and a separate block for the receiver 220 in FIG. 2, a single block for a transceiver could have been shown.

The wireless device 110 further includes one or more input/output devices 260. The input/output devices 260 facilitate interaction with a user. Each input/output device 260 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.

In addition, the wireless device 110 includes at least one memory 230. The memory 230 stores instructions and data used, generated, or collected by the wireless device 110. For example, the memory 230 could store software or firmware instructions executed by the processor(s) 240 and data used to reduce or eliminate interference in incoming signals. Each memory 230 includes any suitable volatile and/or non-volatile storage and retrieval device(s). Any suitable type of memory may be used, such as random access memory (RAM), read only memory (ROM), hard disk, optical disc, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, and the like.

In some implementations, the transmitter 210 can include signal processing circuitry 212, modulation circuitry 214, a power amplifier 216, and at least one filter 218. The signal processing circuitry 212 may include one or more circuits that are configured to process signals received as input (e.g. from processor 240). For example, the signal processing circuitry 212 may include a digital-to-analog converter (D/A), which converts a digital input (e.g. from processor 240) into an analog RF signal and provides the RF signal to a low pass filter, which filters the RF signal and provides the filtered RF signal to the modulation circuitry 214.

The modulation circuitry 214, in addition to receiving the filtered RF signal from the signal processing circuitry 212, also receives a signal from a local oscillator 215 and modulates or adjusts the frequency of the an outgoing signal, e.g., from a first frequency such as a baseband or intermediate frequency (IF) signals to a second frequency that is higher than the first frequency for upconverting an outgoing signal to RF and to a third frequency that is lower than the first frequency when down converting an ingoing RF signal to an IF or a baseband frequency signal. Moreover, as shown in FIG. 2, transmitter 210 includes an RF front end 217, which includes amplification and filtering circuits that filter and amplify the RF signal before providing the RF signal to the power amplifier 216.

The RF signal produced from the RF front end 217 is amplified by the power amplifier 216 and filtered by the at least one filter 218 before being provided as output of the transmitter 210 to the at least one antenna 250A for wireless transmission. In some examples, the transmitter 210 can further include a pre-power amplifier or other circuitry that connects the modulation circuitry 214 to the power amplifier 216. Although FIG. 2 shows the filter 218 as downstream from the power amplifier 216, in some implementations, the filter 218 can be upstream from the power amplifier 216 in which case the RF signal from the RF front end 217 is first filtered by the at least one filter 218 and then amplified by the power amplifier 216 before being provided as output of the transmitter 210 to the at least one antenna 250A for wireless transmission. In some implementations, the local oscillator 215 includes a phase locked loop (PLL) 219 and/or a digitally-controlled oscillator (DCO) 213, similar to one or more of those described in further detail below. In some examples, the local oscillator 215 may also provide a signal to modulation (or demodulation) circuitry of the receiver 220. In other examples, a separate local oscillator that is similar or equivalent to that of the local oscillator 215 may be employed at the receiver 220 for purposes of providing such a signal to modulation (or demodulation) circuitry of the receiver 220. As such, in some implementations, the local oscillator that provides a signal to modulation (or demodulation) circuitry of the receiver 220 includes a PLL 219 and/or a DCO 213, similar to one or more of those described in further detail below. Other configurations are possible. As mentioned above, one or more of the systems and techniques disclosed herein can increase the frequency range of a DCO to allow it to cover enough range that a second DCO is not required for a PLL to cover all cellular frequencies. In this way, such systems and techniques may provide both size and cost savings. Examples of such systems and techniques are provided below.

In some implementations, to extend the range of a DCO, additional inductance is added to the inductor/capacitor (LC) resonator of the DCO. In some examples, a variable inductor size is employed to increase the range of the DCO beyond one octave and thereby eliminate the need for two DCOs per PLL.

FIGS. 3A and 3B are schematics of example DCOs 300A and 300B, respectively. DCOs 300B and 300A represent DCOs without and with the aforementioned additional inductance, respectively.

DCO 300A can include a single inductor value resonator and a Capacitive Digital to Analog Converter (CAPDAC) for frequency adjustment. On the other hand, DCO 300B can include switchable inductance values for the resonator with the same CAPDAC. The additional inductance in the LC resonator(s) of DCO 300B provides for two distinct LC resonator frequency ranges, giving it two bands of operation. The frequency range, based on the mean geometric frequency of the DCO, is 40.8% for DCO 300A and 75.8% for DCO 300B, where a 70.7% range represents one octave.

The frequency range of DCO 300A may be given as: where L is the inductance value of the resonator loop, C is the fixed capacitance of the CAPDAC, and AC is the variable capacitance of the CAPDAC.

DCO 300B is a resonant tank including a plurality of inductors 302. Each inductor in the plurality of inductors 302 may have the same inductance.

DCO 300B further includes a plurality of metal-oxide-semiconductor (MOS) transistors 304, wherein a terminal 306 of each MOS transistor in the plurality of MOS transistors is coupled to a tapping point 308 of a respective inductor in the plurality of inductors. The terminal 306 of each of MOS transistor in the plurality of MOS transistors 304 that is coupled to a tapping point 308 of a respective inductor is the drain terminal. The tap points reduce the voltage seen by the transistors 304 and allow the resonator voltage to be higher to maintain signal power. The gate terminal 310 of each MOS transistor in the plurality of MOS transistors may be coupled to a respective point in a plurality of points within the resonant tank.

The center point of an inductor of the plurality of inductors 302 is a virtual AC ground. Smaller process technologies have higher gate breakdown voltages v_gs and v_gd than drain to source voltages v_ds, which allows greater voltage swing than the supply rails. The non-linearities of the MOS transistors are dominated at the output rather than the input and the voltage swing at the gate doesn’t significantly impact up-converted flicker noise levels. This allows a larger tap voltage at the inputs of the inverters than at the outputs.

DCO 300B includes a first circuit connected between a first pair of inductors in the plurality of inductors 302. This first circuit includes a first inductor 312 arranged in parallel with a first switching element 314.

DCO 300 B also includes a second circuit connected between a second pair of inductors in the plurality of inductors 302. This second circuit includes a second inductor 316 arranged in parallel with a second switching element 318.

When at least one of switching element 314 and/or switching element 318 is open, a second inductance L₂ is added in series to the primary inductance L_t (given by the plurality of inductors 302). The second inductance includes first inductor 312 and/or second inductor 316. Both inductances are altered by their mutual inductance affecting the resonant frequency w₀. In addition to the mutual inductance, any parasitic capacitance C_s in the switching element 314 and / or switching element 318 creates a parasitic resonant frequency with L₂ , which increases its added inductance as frequency increases. The second resonance creates a high impedance in the resonator’s loop decreasing the Q. The switching element size is such that it balances the added resistance in the primary inductive loop when closed with the parasitic resonant frequency when the switching element is open.

The lower frequency band range may be given as: where L_t is a first fixed inductance, L₂ is a second switchable inductance, C_p is the parasitic capacitance of the switching element, C is the fixed capacitance of the CAPDAC, and AC is the variable capacitance of the CAPDAC. For DCO 300B, when the inductor is shorted by the closing switching element 314 and/or switching element 318, the Q of the primary inductance L 1 is degraded by the switch resistance and the higher frequency band range may be given as: where L_tis a first fixed inductance (the inductance of the plurality of inductors 302), C is the fixed capacitance of the CAPDAC, and AC is the variable capacitance of the CAPDAC.

A single DCO 300B is not subject to magnetic coupling to an adjacent DCO which, while not operating, can shift the DCO’s frequency when two DCOs are required to cover the full cellular frequency spectrum.

DCO 300B further includes a third circuit 320 connected between a third pair of inductors in the plurality of inductors 302. The third pair of inductors have one inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors. The third circuit includes a capacitor and a switching element.

DCO 300B also includes a fourth circuit 322 connected between a fourth pair of inductors in the plurality of inductors 302. The fourth pair of inductors have one inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors. The fourth circuit includes a capacitor and a switching element. In some implementations, the fourth pair of inductors are different from the third pair of inductors.

The respective point in the plurality of points that gate terminal 310 of each MOS transistor (in the plurality of MOS transistors 304) may be coupled to within the resonant tank may include (i) a point between the first pair of inductors and the third circuit, (ii) a point between the first pair of inductors and the fourth circuit, (iii) a point between the second pair of inductors and the third circuit, and (iv) a point between the second pair of inductors and the fourth circuit. The plurality of MOS transistors can be supplied by an AGC circuit (not shown) or, alternatively, a simple voltage or current source. In some embodiments the plurality of MOS transistors are “self-biased” — i.e., a low input voltage produces a high output voltage and vice versa. The gate terminal of each of the plurality of MOS transistors is connected to the drain (output) via the inductor, which causes the inputs and outputs to settle at the minimum supply voltage. In such an implementation, a bias circuit may not be implemented.

In some implementations, the plurality of MOS transistors 304 may be two pairs of cross-coupled CMOS inverters 324. The inverters 324 are connected to both ends of the inductor to retain matching of the capacitance. The inverters 324 are self-biased through the DC connection of the inductor for low noise. The inputs are on the opposite sides of the inductor’s main loop for correct phase. The inverters 324 are placed close to their gate connection and the outputs routed radially through the center of the main loop of the inductor to minimize inductive coupling. The outputs can be connected to any point on the inductor after the virtual ground to form a tapped inductor.

Each of the third circuit 320 and fourth circuit 322 may include a plurality of capacitors and a plurality of switching elements. The switching elements shown are shown as open in the figures for illustrative purposes, but may be either open or closed. Each of the third circuit 320 and fourth circuit 322 may include a plurality of capacitors and a plurality of switching elements, such as, e.g., the CAPDAC described above. The third circuit 320 and fourth circuit 322 can include a plurality of weighted capacitors. For example, each of third circuit 320 and fourth circuits 322 may include a 5 -bit coarse tuning CAPDAC; however, a 5-bit fine tuning CAPDAC may also or alternatively be used. The rows of capacitors in the CAPDAC are constructed from unit capacitor cells. Active pull- up and pull-down devices are used for DC biasing and optimal switch resistance.

The distributed nature of capacitance results in Differential Discontinuity (DD), which means step-to-step variation in the digitally controlled capacitance in the resonant frequency if all capacitors are equally weighted due to additional inductance in the CAPDAC connections. The farther a capacitor of the plurality of capacitors is from the plurality of inductors, the greater the effective capacitance. The plurality of capacitors may be binary weighted capacitors. The binary weighted capacitors may be distributed to minimize the DD.

FIG. 4 shows a layout 400 of the example DCO of FIG. 3B, according to some implementations. That is, in some implementations, the DCO 300B employs an inductor layout 400 that includes a main inductor loop and side inductor lobes. The side lobes are connected to the main inductor loop at virtual alternating current (AC) grounds in the LC resonator to minimize capacitive coupling to ground.

An approximately 50% area reduction may be achieved by replacing two DCOs with a single DCO that is similar or equivalent to that of DCO 300B. Given that DCOs often take up a reasonably large portion of a transceiver IC’s area, with as many as 2 TX PLLs and 5 RX PLLs on a single chip, this area reduction may translate to a significant reduction in the size and cost of the IC. FIG. 5 is a schematic of an example DCO 500, which in some implementations may represent a detailed schematic of example DCO 300B of FIG. 3B.

The DCO 500 includes a resonant tank including a first circuit 510, a second circuit 520, a third circuit 530, a fourth circuit 540, and multiple inductors 551A-551D. In some implementations, the resonant tank is formed on a single semiconductor substrate. The first circuit 510 is connected between a first pair of inductors, e.g., inductors 551A and 51 IB, and includes a first inductor arranged in parallel with a first switching element. The second circuit 520 is connected between a second pair of inductors, e.g., inductors 551C and 551D, and includes a second inductor arranged in parallel with a second switching element. The third circuit 530 is connected between a third pair of inductors, e.g., inductors 551B and 551 C, and includes a capacitor and a switching element. The third pair of inductors has one inductor in common with the first pair of inductors, e.g., inductor 551B, and another inductor in common with the second pair of inductors, e.g., inductor 551C. The fourth circuit 540 is connected between a fourth pair of inductors, e.g., inductors 551D and 551 A, and includes a capacitor and a switching element. The fourth pair of inductors has one inductor in common with the first pair of inductors, e.g., inductor 551 A, and another inductor in common with the second pair of inductors, e.g., inductor 551D. In some implementations, each of one or both of the first and second circuits can include a parasitic capacitor C_P, a parasitic resistor R_P, or both.

In some implementations, the DCO 500 further includes a control circuit 570 communicatively coupled to each of the first circuit 510 and the second circuit 520. The control circuit can be configured to control the first and second circuits 510, 520 to switch between (i) a first mode in which both the first and second switching elements are open, and (ii) a second mode in which both the first and second switching elements are closed. In some examples, the first and second modes can cause the resonant tank to generate signals in first and second ranges of frequencies, respectively. For example, the first mode can correspond to the resonant tank being tuned to a frequency in the low frequency band range described above, and the second mode can correspond to the resonant tank being tuned to a frequency in the high frequency band range described above. In some examples, the control circuit is configured to control the first and second switching elements in unison such that the first and second switching elements are maintained in the same state.

In the first mode, the control circuit can be configured to selectively control the switching element in the third circuit 530, the switching element in the fourth circuit 540, or both, to tune the resonant tank to a specific frequency in the first range of frequencies, e.g., the low frequency band range described above. Similarly, in the second mode, the control circuit can be configured to selectively control the switching element in the third circuit 530, the switching element in the fourth circuit 540, or both, to tune the resonant tank to a specific frequency in the second range of frequencies, e.g., the high frequency band range described above.

In some implementations, inductors 551A-551D all have a same inductance. For example, the inductance of each of inductors 551A-551D can be ½ L . where L_t is the first fixed inductance described above. Similarly, in some implementations, the first and second inductors of the first and second circuits 510 and 520, respectively, both have a same inductance. For example, the inductance of each of the first and second inductors can be L₂, where L₂ is the second switchable inductance described above. In addition, L₂ and ½ L can differ in value.

FIG. 6 shows computer simulation results for the resonant frequency of the DCO under different operating conditions. Fmin band 0 is the lowest operating frequency when the CAPDAC has the maximum capacitance and the inductor switch is open. Fmax band 0 is the highest operating frequency when the CAPDAC has the minimum capacitance and the inductor switch is open. Fmin band 1 is the lowest operating frequency when the CAPDAC has the maximum capacitance and the inductor switch is closed. Fmax band 1 is the highest operating frequency when the CAPDAC has the minimum capacitance and the inductor switch is closed. Range is the overall frequency range of the DCO relative to its geometric mean frequency. The columns NOMINAL, FFH RCMIN, and FFC RCMIN represent different component tolerance values and temperatures. FF indicates fast CMOS transistors, SS represents slow CMOS transistors, H represents hot temperature and C represents cold temperature, RCMIN represents minimum tolerance valued capacitors and resistors, and RCMAX represents maximum tolerance valued capacitors and resistors. For example, FFH RCMIN is a device where the production tolerances have skewed the transistor in such a way that they are faster than nominal, the device is operating at hot temperature, and the production tolerances have skewed the capacitors in such a way as to make the capacitors smaller than nominal. The table shows how the frequency ranges are skewed when production tolerances affect the manufacturing of the IC.

In some implementations, the range of resonant frequency of the DCO as simulated is 4.517GHz-10.469GHz. The low band (switching element open) is 4.517 GHz to 7.448GHz and the high band (switching element closed) range is 5.791 GHz to 10.469 GHz. A definitive split may be implemented, for example, at 6.732 GHz. An overall tuning range of 79.4%, with an overlap of 22.3% of the low and high bands can be achieved.

FIGS. 7A and 7B shows plots of inductance as a function of resonant frequency for the DCO. These plots collectively reflect the impact that the parasitic components of the switch (e.g., capacitance C_p and/or resistance R_P discussed above) have on the inductors when the switch is open and closed. The yellow plot shows the effects of an ideal switch where there are no parasitic components, and the red plot shows the effects when there are one or more parasitic components.

The FIG. 7A plots show the inductance value and Q when the switch is open. The top left shows that the inductance without parasitic components is relatively constant (yellow), but exhibits a resonance (the peak and dip in red) when there is parasitic capacitance. The bottom left shows the quality factor, Q, of the inductor increasing with frequency without parasitic components (yellow) but degrading as the frequency nears the resonance due to one or more parasitic components (red).

The FIG. 7B plots show the inductance value and Q when the switch is closed. The top right shows the inductance which does not change significantly either without parasitic components (yellow) or with one or more parasitic components (red). The bottom right shows the inductor Q is degraded with parasitic resistance (red) vs without parasitic resistance (yellow).

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A digitally-controlled oscillator (DCO), comprising: a resonant tank comprising: a plurality of inductors; a plurality of metal-oxide-semiconductor (MOS) transistors, wherein a terminal of each MOS transistor in the plurality of MOS transistors is coupled to a tapping point of a respective inductor of the plurality of inductors; a first circuit connected between a first pair of inductors in the plurality of inductors, wherein the first circuit comprises a first inductor arranged in parallel with a first controllable switching element; a second circuit connected between a second pair of inductors in the plurality of inductors, wherein the second circuit comprises a second inductor arranged in parallel with a second controllable switching element; a third circuit connected between a third pair of inductors in the plurality of inductors, the third pair of inductors having one inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors, wherein the third circuit comprises a capacitor and a switching element; and a fourth circuit connected between a fourth pair of inductors in the plurality of inductors, the fourth pair of inductors having one inductor in common with the first pair of inductors and another inductor in common with the second pair of inductors, wherein the fourth circuit comprises a capacitor and a switching element and wherein the fourth pair of inductors are different from the third pair of inductors.

2. The DCO of claim 1, wherein each inductor in the plurality of inductors has a same inductance.

3. The DCO of any one of claims 1-2, further comprising: a control circuit communicatively coupled to each of the first circuit and the second circuit, the control circuit configured to control the first and second circuits to switch between a first mode and a second mode, wherein: in the first mode, both the first and second switching elements are open; and in the second mode, both the first and second switching elements are closed.

4. The DCO of claim 3, wherein: in the first mode, the resonant tank is configured to generate signals in a first range of frequencies; and in the second mode, the resonant tank is configured to generate signals in a second range of frequencies different from the first range of frequencies.

5. The DCO of claim 4, wherein the control circuit is communicatively coupled to each of the third circuit and the fourth circuit, wherein: in the first mode, the control circuit is configured to selectively control the switching element in the third circuit, the switching element in the fourth circuit, or both, to tune the resonant tank to a specific frequency in the first range of frequencies; and in the second mode, the control circuit is configured to selectively control the switching element in the third circuit, the switching element in the fourth circuit, or both, to tune the resonant tank to a specific frequency in the second range of frequencies.

6. The DCO of any one of claims 1-5, wherein each of the first and second inductors has a same inductance, the inductance of each of the first and second inductors being different from an inductance of each of the plurality of inductors.

7. The DCO of any one of claims 1-6, wherein the resonant tank is formed on a single semiconductor substrate.

8. The DCO of any one of claims 1-7, wherein each of the third and fourth circuits comprises a plurality of capacitors and a plurality of switching elements.

9. The DCO of any one of claims 1-8, wherein the terminal of each MOS transistor in the plurality of MOS transistors comprises a drain terminal.

10. The DCO of any one of claims 1-9, wherein a gate terminal of each MOS transistor in the plurality of MOS transistors is coupled to a respective point in a plurality of points within the resonant tank.

11. The DCO of claim 10, wherein the plurality of points within the resonant tank comprise (i) a point between the first pair of inductors and the third circuit, (ii) a point between the first pair of inductors and the fourth circuit, (iii) a point between the second pair of inductors and the third circuit, and (iv) a point between the second pair of inductors and the fourth circuit.

12. A device, comprising: at least one processor; an antenna; communication circuitry coupled to the at least one processor and the antenna, wherein communication circuitry includes a local oscillator, the local oscillator comprising a DCO according to any of claims 1-11.

13. The device of claim 12, wherein the local oscillator is a phase locked loop (PLL).

14. The device of claim 12 or claim 13, wherein the communication circuitry comprises a transmitter, a receiver, or both.