EP4173033A1 - Transistor with interdigital electrodes, comprising a gate terminal connected by a plurality of vertical vias to the gate electrodes - Google Patents

Transistor with interdigital electrodes, comprising a gate terminal connected by a plurality of vertical vias to the gate electrodes

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Publication number
EP4173033A1
EP4173033A1 EP21737725.8A EP21737725A EP4173033A1 EP 4173033 A1 EP4173033 A1 EP 4173033A1 EP 21737725 A EP21737725 A EP 21737725A EP 4173033 A1 EP4173033 A1 EP 4173033A1
Authority
EP
European Patent Office
Prior art keywords
transistor
gate
electrodes
gate terminal
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21737725.8A
Other languages
German (de)
French (fr)
Inventor
Robin Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics France SAS
Original Assignee
Exagan SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exagan SAS filed Critical Exagan SAS
Publication of EP4173033A1 publication Critical patent/EP4173033A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present invention relates to the field of semiconductors and microelectronic devices, including devices capable of operating reliably at radio frequencies and above, while being capable of handling high power loads.
  • It relates in particular to a field effect transistor based on a structure of interdigitated electrodes, defining a plurality of elementary transistor cells arranged in parallel, each elementary cell including a source electrode, a gate electrode and a drain electrode, and the gate terminal of the transistor being connected to the gate electrodes of the elementary cells by a plurality of vertical vias.
  • a field effect transistor 90 (FET for “field effect transistor”) based on a lateral diffused metal-oxide-semiconductor technology (LD-MOS for “lateral diffused metal-oxide-semiconductor”) generally has an electrode structure interdigitated (figure la). Such a structure corresponds to the placing in parallel of several elementary transistor cells 50 (or elementary transistors), each comprising a source electrode 1, a drain electrode 3 and a gate electrode 2 interposed between the aforementioned two. These electrodes 1,2,3 take the form of lines elongated (or fingers) which extend over the active region 40 of transistor 90.
  • Each elementary cell 50 has the same electrical characteristics (such as in particular the threshold voltage (VTH), the drain-source breakdown voltage (BVDSS) and the resistance in the on state (R DS (on >)) defined by the properties of the semiconductor substrate of the active region 40 and of the electrodes 1,2,3 placed on the latter.
  • VTH threshold voltage
  • BVDSS drain-source breakdown voltage
  • R DS on >
  • the source 1, gate 2 and drain 3 electrodes are respectively connected to source 10, gate 20 and drain 30 terminals.
  • a source terminal 10 and a drain terminal 30 extend at the periphery of the active region 40 along an axis perpendicular to the axis of the electrodes 1,2,3, and away from each other; they are directly connected to one end of the source 1 and drain 3 electrodes respectively.
  • two gate terminals 20 are arranged in the periphery of the active region 40 and connected to the plurality of gate electrodes 2 of the elementary cells 50 via a connection line 21 connected to one end of said electrodes 2.
  • connection line 21 which is related to the resistivity of the material used and to the line length between each gate electrode 2 and a gate terminal 20, directly affects the switching delays of the transistor 90.
  • FIG. 1b qualitatively illustrates the increase in the switching delay with the distance between a gate electrode 2 and the gate terminal 20.
  • this delay can induce a current focusing in the elementary cells 50 which are closest to the gate terminals 20: in fact, when switching to the on state of the transistor 90, these 50 elementary cells are the first to be switched and see a very large quantity of current flow over a short period of time, linked to the delay in switching elementary cells 50 further away from the gate terminals 20.
  • This high current coupled with the strong electric field involved during switching, generates a significant stress on the elementary transistors 50, liable to damage them.
  • the present invention proposes a solution overcoming all or part of the aforementioned drawbacks. It relates in particular to a field effect transistor having an interdigitated structure in which several elementary transistor cells are arranged in parallel, each comprising a source electrode, a gate electrode and a drain electrode; the gate electrodes are all connected to a gate terminal by vertical conductive vias, said gate terminal being placed directly above the elementary cells.
  • the present invention relates to a field effect transistor having an interdigitated structure and comprising: several elementary transistor cells arranged in parallel, each elementary cell comprising a source electrode, a drain electrode and a gate electrode interposed between the source electrodes and drain, a source terminal and a drain terminal respectively connected to the source electrodes and to the drain electrodes of the elementary cells,
  • the field effect transistor is remarkable in that it includes only vertical conductive vias for connecting the gate electrodes to the gate terminal.
  • a plurality of conductive vias distributed along each gate electrode connects each gate electrode to the gate terminal; and the gate terminal is placed directly above all or part of the elementary cells.
  • the gate terminal is arranged on a front face of the transistor, and the conductive vias pass through a dielectric layer interposed between the gate electrodes of the elementary cells and the gate terminal;
  • the gate terminal is arranged on a rear face of the transistor, and the conductive vias pass through a semiconductor substrate of the transistor;
  • the gate terminal is formed by a copper film bonded to a ceramic support, on which the rear face of the transistor is assembled by means of an electrically conductive adhesive; • the conductive vias are uniformly distributed along each gate electrode;
  • each via conductor has a section, of circular, square, rectangle or polygonal shape, between 1 and 100 square microns;
  • the conductive vias comprise an electrically conductive material chosen from copper and aluminum;
  • the field effect transistor comprises a semi-conducting surface layer comprising a stack based on III-N materials, in particular based on GaN and AlGaN material, in which the conduction channel consists of a layer of electron gas two-dimensional.
  • FIG. 2 shows a top view of a transistor according to the present invention
  • FIGS. 3a and 3b respectively show a sectional view of an elementary cell of a transistor, and a top view of said transistor according to a first embodiment of the invention
  • FIG. 4 shows a transistor according to the first embodiment of the invention (i), compared with a transistor with interdigitated structure according to the state of the art (ii), and locates, on each transistor, the elementary cell for which the resistance R G , between its gate electrode and a pad contacting the gate terminal, has been evaluated;
  • FIGS. 5a and 5b respectively show a sectional view of an elementary cell of a transistor, and a top view of said transistor according to a second embodiment of the invention
  • FIG. 6 shows a transistor according to the second embodiment of the invention (i), compared with a transistor with interdigitated structure according to the state of the art (ii), and locates, on each transistor, the elementary cell for which the resistance R G , between its gate electrode and a pad contacting the gate terminal, was evaluated.
  • the figures are schematic representations which, for the sake of readability, are not to scale.
  • the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes.
  • the invention relates to a field effect transistor (FET) 100 comprising a semiconductor substrate, at least one surface layer of which forms the active region of the transistor 100.
  • the active region defines a source region, a source region. drain region and a conduction channel between these two regions.
  • the transistor is based on LD-MOS technology, the source and drain regions are therefore included in the surface layer and conduction between them takes place laterally, in the principal plane (x, y) of said layer.
  • the source and drain semiconductor regions are in ohmic contact with the source and drain electrodes, respectively.
  • a gate electrode is disposed between the source and drain electrodes, above the conduction channel of the active region. The voltage applied to the gate electrode makes it possible to manage the on or off state of transistor 100.
  • the transistor 100 according to the invention has a structure of interdigitated electrodes as is apparent in top view in FIG. 2. It is formed by several elementary cells of transistor 50 arranged in parallel in the main plane (x, y). Each elementary cell 50 comprises a source electrode 1, a drain electrode 3 and a gate electrode 2 interposed between the source 1 and drain 3 electrodes.
  • the source 1, gate 2 and drain 3 electrodes are made of aluminum. They typically have a length (along the x axis in the figures) between 1mm and 2mm and a width (along the y axis in the figures) between 1 and 10 microns.
  • All the source electrodes 1 of the elementary cells 50 are electrically connected to the source terminal 10 of the transistor 100.
  • the drain electrodes 3 are for their part electrically connected to the drain terminal 30 of the transistor 100.
  • the source 10 and drain 30 terminals advantageously extend at the periphery of the active region 40, perpendicular to the axis of the electrodes 1, 3 and are electrically connected to one end of the respectively source 1 and drain 3 electrodes.
  • the terminals 10, 30 are arranged in a plane above the plane (x, y) in which the electrodes 1, 3 extend: vertical interconnections (c ' that is to say along the axis z in the figures) between one end of the source 1 and drain 3 electrodes provide their electrical connection respectively with the source terminal 10 and the drain terminal 30. These interconnections are not shown. in the figures.
  • the source 10 and drain 30 terminals are typically formed from the same material as the electrodes 1, 3.
  • the transistor 100 further comprises conductive and vertical vias 22, to connect the gate electrodes 2 to the gate terminal 20.
  • the gate terminal 20 is placed in line with all or part of the elementary cells 50, that is, it is not in the same plane (x, y) as the electrodes 1,2,3, and not necessarily in the same plane as the source 10 and drain 30 terminals.
  • the gate terminal 20 is according to a first embodiment (FIGS. 3a, 3b), on the front face of the transistor 100, above the electrodes 1,2,3 and separated from them by a dielectric layer 6.
  • a second embodiment FIGS. 5a, 5b
  • the gate terminal 20 is arranged on the rear face of the transistor 100, below the electrodes 1,2,3 and of the semiconductor substrate 4 of said transistor 100.
  • the gate terminal 20 does not consume any useful surface area of the active region 40 because it is located directly above all or part of the elementary cells 50; it is not adjacent to the elementary cells 50, unlike the source 10 and drain 30 terminals which are located at the periphery of said cells 50 in the main plane (x, y) or in a higher plane.
  • Such a configuration therefore allows optimization of the active region surface 40.
  • the arrangement of the gate terminal 20 on the front face or on the rear face of the transistor 100 allows a great degree of freedom as to the dimensions (lateral and thickness) of said terminal 20.
  • the choice of a metallic material which is very good electrical conductor (for example, copper or aluminum) and an extended surface area for the gate terminal 20 allows its resistance to be greatly reduced.
  • the conductive vias 22 are preferably formed from a very good conductive material, for example copper. This also helps to reduce the grid resistance.
  • each conductive vias 22 has a section of between 1 and 100 square microns.
  • a plurality of conductive vias 22 connects each gate electrode 2 to the gate terminal 20, as illustrated in FIG. 2.
  • Each via 22 vertically connects a gate electrode 2 in its length, and not to a end or on an extension specifically designed for this purpose.
  • the plurality of conductive vias 22 directly connected between each gate electrode 2 and the gate terminal 20 makes it possible to significantly reduce the gate resistance.
  • FIG. 3a illustrates a sectional view of an elementary cell 50 of the transistor 100 in accordance with the invention.
  • the semiconductor substrate comprises the surface layer 5 and a lower support part 4 (referred to as support substrate 4 hereinafter).
  • the source 1 and drain 3 electrodes are in ohmic contact with the surface layer
  • the conduction channel (not shown) extends between source and drain, in the (x, y) plane.
  • the semi-conducting surface layer 5 comprises a stack of III-N materials, in particular based on GaN, AlGaN, AIN, etc. material.
  • the conduction channel then consists of a two-dimensional electron gas layer (2DEG), and the source 1 and drain 3 electrodes are in ohmic contact with said 2DEG layer.
  • the transistor 100 is then a power transistor, suitable for high voltage applications.
  • a gate oxide 2a separates the gate electrode 2 and the surface layer 5.
  • the gate oxide 2a is typically formed from silicon oxide and has a thickness of a few tens of nanometers.
  • the gate electrode 2 is connected to a field plate 2b, separated from the surface layer 5 by an insulating layer of thickness greater than or equal to the thickness of the gate oxide 2a.
  • the electrodes 1,2,3 are covered by a dielectric layer
  • the dielectric layer 6 preferably comprises silicon oxide, silicon nitride, or even alumina.
  • Conductive vias 22 pass through the dielectric layer 6 so as to reach the gate electrode 2.
  • a conventional method involving steps of lithography, of etching of the dielectric layer 6, then of deposition to fill the vias 22, can be used.
  • An insulating film 22b and / or forming a diffusion barrier can be deposited on the walls of the trench corresponding to each via 22, before it is filled with an electrically conductive material.
  • the gate terminal 20 is then formed by depositing a conductive metallic material on the dielectric layer 6, in electrical contact with the vias 22.
  • the gate terminal 20 is disposed above all or part of the active region 40 of elementary cell 50, and more generally above all or part of active region 40 of transistor 100, as illustrated in FIG. 3b.
  • the contacts 200 to connect the transistor 100 to another electronic device or to a box, can be done either by wired contact or by means of pads or balls implemented in known packaging techniques.
  • the calculation of the gate resistor R G is made for the least favorable zone of the transistor, namely, for the elementary cell 50 furthest from the contact pick-up pads 200.
  • the calculation of R G is carried out between the gate electrode 2 of the elementary cell 50 furthest to the left in FIG. 4 and two contact pads 200 located at right on transistor 100; the contact pads 200 are balls deposited on the gate terminal 20.
  • the latter is formed by a layer of copper of 10 microns thick with a resistance of about 5 mohm.
  • the conductive vias 22 have a square section with side 8 microns in the (x, y) plane and extend over a height of 50 microns (along the z axis), between gate electrodes 2 and gate terminal 20.
  • the dielectric layer 6 therefore has a thickness of the order of 50 microns.
  • the conductive vias 22 are made of copper.
  • the associated resistance is about 13 mohm.
  • the gate resistance R G between the gate electrode 2 of the elementary cell 50 studied and the contact pad 200 is therefore evaluated at approximately 18 mohm.
  • the calculation of R G is carried out between the gate electrode 2 of a central elementary cell 50 and two pads contact 200 formed by wire connections connected to gate terminals 20 located at the periphery of the active region 40 of transistor 90; remember that each gate electrode 2 of the elementary cells 50 is connected to the gate terminals 20 via a connection line 21.
  • the gate structure (gate electrodes 2, connection line 21 and gate terminals 20) is developed on two levels of metal and tungsten interconnects connect these two levels, as is conventionally done.
  • the gate resistance R G between the gate electrode 2 of the elementary cell 50 studied and the contact pad 200 is then of the order of 2 to 3 ohms.
  • the transistor 100 according to the invention therefore provides a net reduction of about a factor of 100 in the gate resistance R G , greatly limiting the problem of current focusing in certain elementary cells during the switching to the on state of the transistor.
  • the gate terminal 20 is arranged on the rear face of the transistor 100, below the electrodes 1,2,3 and of the semiconductor substrate of said transistor 100.
  • FIG. 5a illustrates a sectional view of an elementary cell 50 of transistor 100 in accordance with the invention.
  • the semiconductor substrate comprising the surface layer 5 and the support substrate 4.
  • the source 1 and drain 3 electrodes are in ohmic contact with the surface layer 5.
  • the conduction channel (not shown) extends between source and drain, in the (x, y) plane.
  • the surface semiconductor layer 5 advantageously comprises a stack based on III-N materials, in particular based on GaN, AlGaN, AIN, etc. material.
  • the conduction channel then consists of a two-dimensional electron gas layer (2DEG), and the source 1 and drain 3 electrodes are in ohmic contact with said 2DEG layer.
  • a gate oxide separates the gate electrode 2 and the surface layer 5.
  • the gate oxide is typically formed from silicon oxide and has a thickness of a few tens of nanometers.
  • the gate electrode 2 can be connected to a field plate, separated from the surface layer 5 by an insulating layer of thickness greater than or equal to the thickness of the gate oxide.
  • the conductive vias 22 can be produced according to two variants: the first variant provides for the formation of the vias 22 by etching and deposition from the front face of the semiconductor substrate of the transistor 100; the second variant provides for the formation of vias 22 by its rear face. According to the first variant, the vias 22 are produced prior to the formation of the gate electrodes 2.
  • a process of photolithography and deep etching (for example by reactive ion etching - RIE) through the surface layer 5 and through everything or part of the support substrate 4, first of all makes it possible to form trenches from the front face 100a.
  • An insulating film is deposited on the walls of the trenches, so as to isolate the conductive vias 22 from the semiconductor materials of the surface layer 5 and of the support substrate 4.
  • a metal deposit is then operated to fill the trenches and form the vias. 22.
  • the gate electrodes 2 can then be produced; it should be noted that the source 1 and drain 3 electrodes may be formed before or after all or part of the development of the vias
  • the conductive vias 22 are produced after the formation of the electrodes 1, 2, 3, or even after the production of the source 10 and drain 30 terminals.
  • An insulating film is deposited on the walls of the trenches, so as to isolate the conductive vias 22 from the semiconductor materials passed through.
  • a metal deposit is then operated to fill the trenches and form the vias 22.
  • the gate terminal 20 is formed in contact with the conductive vias 22 opening out at the rear face 100b of the transistor 100 (FIG. 5a (ii)).
  • the gate terminal 20 can be produced by depositing a conductive metallic material on the support substrate 4.
  • the gate terminal 20 can also be formed by a copper film bonded to a ceramic support (DBC for “direct bond copper”), on which the rear face 100b of the transistor 100 is assembled by means of an electrically conductive adhesive (FIG. 5b).
  • DBC ceramic support
  • This configuration provides the additional advantage of polarizing the support substrate 4 at the gate potential, that is to say at a potential very close to that of the source. This bias is generally useful for the correct operation of the transistor 100 and is authorized without an additional step by the second embodiment of the invention.
  • the gate terminal 20 is placed below all or part of the active region 40 of the elementary cell 50, and more generally below all or part of the active region 40 of the transistor 100. .
  • the contact resumptions, to connect the transistor 100 to another electronic device or to a box, can be done either by wired contact or by means of pads or balls.
  • FIG. 6 (i) A comparison has been made between a transistor 100 according to the second embodiment of the invention (FIG. 6 (i)) and the transistor 90 of the state of the art (FIG. 6 (ii) already described with reference to first embodiment.
  • the resistance R G is evaluated between the gate electrode 2 of the elementary cell 50 most to the left of the transistor 100 and two pads contact 200 located to the right of transistor 100; the contact pads 200 are here wire connections integral with the copper film (gate terminal 20 in electrical contact with the conductive vias 22) of a DBC.
  • the copper film has a thickness of 90 microns.
  • the resistance associated with the gate terminal 20 and wire connections is approximately 0.7 mohm.
  • the associated resistance is of the order of 14 mohm.
  • the conductive vias 22 have a square section of 8 microns per side in the (x, y) plane and extend over a height (along the z axis) of 300 microns, between gate electrodes 2 and rear face 100b of the substrate support 4.
  • the conductive vias 22 are made of copper.
  • the associated resistance is about 80 mohm.
  • the gate resistance R G between the gate electrode 2 of the elementary cell 50 studied and the contact pad 200 is therefore evaluated at approximately 95 mohm.
  • the transistor 100 according to the second embodiment of the invention provides a gate resistance R G less than order 10, and capable of reducing the problem of current focusing in certain elementary cells during the switching to the on state of the transistor.

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Abstract

The invention relates to a field-effect transistor (100) having an interdigital structure and comprising: several elementary transistor cells (50) arranged in parallel, each elementary cell comprising a source electrode (1), a drain electrode (3) and a gate electrode (2) interposed between the source and drain electrodes, a source terminal (10) and a drain terminal (30) respectively connected to the source electrodes (1) and to the drain electrodes (3) of the elementary cells (50), a gate terminal (20) connected to the gate electrodes (2) of the elementary cells. The field-effect transistor (100) comprises only vertical conductive vias for connecting the gate electrodes to the gate terminal, and the gate terminal (20) is arranged vertically in line with all or part of the elementary cells (50).

Description

TRANSISTOR A ELECTRODES INTERDIGITEES, COMPRENANT UN TERMINAL DE GRILLE CONNECTE PAR UNE PLURALITE DE VIAS VERTICAUX AUX TRANSISTOR WITH PROHIBITED ELECTRODES, INCLUDING A GRID TERMINAL CONNECTED BY A PLURALITY OF VERTICAL VIAS TO THE
ELECTRODES DE GRILLE GRID ELECTRODES
DOMAINE DE L' INVENTION FIELD OF THE INVENTION
La présente invention concerne le domaine des semi-conducteurs et des dispositifs microélectroniques, notamment les dispositifs capables de fonctionner de manière fiable aux fréquences radio et au-dessus, tout en étant capable de gérer des charges de puissance élevées. The present invention relates to the field of semiconductors and microelectronic devices, including devices capable of operating reliably at radio frequencies and above, while being capable of handling high power loads.
Elle concerne en particulier un transistor à effet de champ basé sur une structure d'électrodes interdigitées, définissant une pluralité de cellules élémentaires de transistor disposées en parallèle, chaque cellule élémentaire incluant une électrode de source, une électrode de grille et une électrode de drain, et le terminal de grille du transistor étant connecté aux électrodes de grille des cellules élémentaires par une pluralité de vias verticaux. It relates in particular to a field effect transistor based on a structure of interdigitated electrodes, defining a plurality of elementary transistor cells arranged in parallel, each elementary cell including a source electrode, a gate electrode and a drain electrode, and the gate terminal of the transistor being connected to the gate electrodes of the elementary cells by a plurality of vertical vias.
ARRIERE PLAN TECHNOLOGIQUE DE L' INVENTION TECHNOLOGICAL BACKGROUND OF THE INVENTION
Un transistor à effet de champ 90 (FET pour « field effect transistor ») basé sur une technologie métal-oxyde-semi conducteur diffusée latérale (LD-MOS pour « latéral diffused metal-oxide-semiconductor ») présente généralement une structure d'électrodes interdigitées (figure la). Une telle structure correspond à la mise en parallèle de plusieurs cellules élémentaires de transistor 50 (ou transistors élémentaires), comprenant chacune une électrode de source 1, une électrode de drain 3 et une électrode de grille 2 intercalée entre les deux précitées. Ces électrodes 1,2,3 prennent la forme de lignes allongées (ou doigts) qui s'étendent sur la région active 40 du transistor 90. Chaque cellule élémentaire 50 présente les mêmes caractéristiques électriques (telles que notamment la tension de seuil (VTH), la tension de claquage Drain-Source (BVDSS) et la résistance à l'état passant (RDS(on>)) définies par les propriétés du substrat semi-conducteur de la région active 40 et des électrodes 1,2,3 disposées sur cette dernière. A field effect transistor 90 (FET for “field effect transistor”) based on a lateral diffused metal-oxide-semiconductor technology (LD-MOS for “lateral diffused metal-oxide-semiconductor”) generally has an electrode structure interdigitated (figure la). Such a structure corresponds to the placing in parallel of several elementary transistor cells 50 (or elementary transistors), each comprising a source electrode 1, a drain electrode 3 and a gate electrode 2 interposed between the aforementioned two. These electrodes 1,2,3 take the form of lines elongated (or fingers) which extend over the active region 40 of transistor 90. Each elementary cell 50 has the same electrical characteristics (such as in particular the threshold voltage (VTH), the drain-source breakdown voltage (BVDSS) and the resistance in the on state (R DS (on >)) defined by the properties of the semiconductor substrate of the active region 40 and of the electrodes 1,2,3 placed on the latter.
Les électrodes de source 1, de grille 2 et de drain 3 sont respectivement connectées à des terminaux de source 10, de grille 20 et de drain 30. Dans l'exemple de la figure la, un terminal de source 10 et un terminal de drain 30 s'étendent en périphérie de la région active 40 selon un axe perpendiculaire à l'axe des électrodes 1,2,3, et à l'opposé l'un de l'autre ; ils sont directement connectés à une extrémité des électrodes respectivement de source 1 et de drain 3. Toujours dans cet exemple, deux terminaux de grille 20 sont disposés dans la périphérie de la région active 40 et connectés à la pluralité d'électrodes de grille 2 des cellules élémentaires 50 par l'intermédiaire d'une ligne de connexion 21 reliée à une extrémité desdites électrodes 2. The source 1, gate 2 and drain 3 electrodes are respectively connected to source 10, gate 20 and drain 30 terminals. In the example of FIG. 1a, a source terminal 10 and a drain terminal 30 extend at the periphery of the active region 40 along an axis perpendicular to the axis of the electrodes 1,2,3, and away from each other; they are directly connected to one end of the source 1 and drain 3 electrodes respectively. Still in this example, two gate terminals 20 are arranged in the periphery of the active region 40 and connected to the plurality of gate electrodes 2 of the elementary cells 50 via a connection line 21 connected to one end of said electrodes 2.
La résistance de la ligne de connexion 21, qui est liée à la résistivité du matériau utilisé et à la longueur de ligne entre chaque électrode de grille 2 et un terminal de grille 20, affecte directement les retards de commutation du transistor 90. La figure lb illustre qualitativement l'augmentation du retard de commutation avec la distance entre une électrode de grille 2 et le terminal de grille 20. The resistance of the connection line 21, which is related to the resistivity of the material used and to the line length between each gate electrode 2 and a gate terminal 20, directly affects the switching delays of the transistor 90. FIG. 1b qualitatively illustrates the increase in the switching delay with the distance between a gate electrode 2 and the gate terminal 20.
Dans un transistor LD-MOSFET à structure interdigitée, ce retard peut induire une focalisation de courant dans les cellules élémentaires 50 qui sont les plus proches des terminaux de grille 20 : en effet, lors de la commutation à l'état passant du transistor 90, ces cellules élémentaires 50 sont les premières à commuter et voient passer une très grande quantité de courant pendant un faible laps de temps, lié au retard de commutation des cellules élémentaires 50 plus éloignées des terminaux de grille 20. Ce courant élevé, couplée au fort champ électrique impliqué lors de la commutation, génère une contrainte importante sur les transistors élémentaires 50, susceptible de les détériorer. In an LD-MOSFET transistor with interdigitated structure, this delay can induce a current focusing in the elementary cells 50 which are closest to the gate terminals 20: in fact, when switching to the on state of the transistor 90, these 50 elementary cells are the first to be switched and see a very large quantity of current flow over a short period of time, linked to the delay in switching elementary cells 50 further away from the gate terminals 20. This high current, coupled with the strong electric field involved during switching, generates a significant stress on the elementary transistors 50, liable to damage them.
Pour limiter ce problème, il est possible de former plusieurs terminaux de grille 20 indépendants, connectant chacun une partie des électrodes de grille 2 des cellules élémentaires 50 : la longueur de ligne de connexion 21 peut être réduite et le retard de commutation diminué. Ce type de solution présente néanmoins l'inconvénient de consommer une plus grande surface de la région active 40 pour disposer les terminaux indépendants, et donc de dégrader la résistance du transistor 90 à l'état passant (RDS(on))· To limit this problem, it is possible to form several independent gate terminals 20, each connecting a part of the gate electrodes 2 of the elementary cells 50: the length of the connection line 21 can be reduced and the switching delay reduced. This type of solution nevertheless has the drawback of consuming a larger area of the active region 40 to have the independent terminals, and therefore of degrading the resistance of the transistor 90 in the on state (RDS (on)).
OBJET DE L' INVENTION OBJECT OF THE INVENTION
La présente invention propose une solution remédiant à tout ou partie des inconvénients précités. Elle concerne en particulier un transistor à effet de champ présentant une structure interdigitée dans laquelle plusieurs cellules élémentaires de transistor sont disposées en parallèle, chacune comprenant une électrode de source, une électrode de grille et une électrode de drain ; les électrodes de grille sont toutes connectées à un terminal de grille par des vias conducteurs verticaux, ledit terminal de grille étant disposé à l'aplomb des cellules élémentaires. The present invention proposes a solution overcoming all or part of the aforementioned drawbacks. It relates in particular to a field effect transistor having an interdigitated structure in which several elementary transistor cells are arranged in parallel, each comprising a source electrode, a gate electrode and a drain electrode; the gate electrodes are all connected to a gate terminal by vertical conductive vias, said gate terminal being placed directly above the elementary cells.
BREVE DESCRIPTION DE L' INVENTION La présente invention concerne un transistor à effet de champ présentant une structure interdigitée et comprenant : plusieurs cellules élémentaires de transistor disposées en parallèle, chaque cellule élémentaire comprenant une électrode de source, une électrode de drain et une électrode de grille intercalée entre les électrodes de source et de drain, un terminal de source et un terminal de drain respectivement connectés aux électrodes de sources et aux électrodes de drain des cellules élémentaires, BRIEF DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor having an interdigitated structure and comprising: several elementary transistor cells arranged in parallel, each elementary cell comprising a source electrode, a drain electrode and a gate electrode interposed between the source electrodes and drain, a source terminal and a drain terminal respectively connected to the source electrodes and to the drain electrodes of the elementary cells,
- un terminal de grille connecté aux électrodes de grille des cellules élémentaires. a gate terminal connected to the gate electrodes of the elementary cells.
Le transistor à effet de champ est remarquable en ce qu'il comprend uniquement des vias conducteurs verticaux pour connecter les électrodes de grille au terminal de grille. Une pluralité de vias conducteurs répartis le long de chaque électrode de grille relie chaque électrode de grille au terminal de grille ; et le terminal de grille est disposé à l'aplomb de tout ou partie des cellules élémentaires. The field effect transistor is remarkable in that it includes only vertical conductive vias for connecting the gate electrodes to the gate terminal. A plurality of conductive vias distributed along each gate electrode connects each gate electrode to the gate terminal; and the gate terminal is placed directly above all or part of the elementary cells.
Selon des caractéristiques avantageuses de l'invention, prises seules ou selon toute combinaison réalisable : According to advantageous characteristics of the invention, taken alone or in any feasible combination:
• le terminal de grille est disposé sur une face avant du transistor, et les vias conducteurs traversent une couche diélectrique intercalée entre les électrodes de grille des cellules élémentaires et le terminal de grille ; • the gate terminal is arranged on a front face of the transistor, and the conductive vias pass through a dielectric layer interposed between the gate electrodes of the elementary cells and the gate terminal;
• le terminal de grille est disposé sur une face arrière du transistor, et les vias conducteurs traversent un substrat semi-conducteur du transistor ; • the gate terminal is arranged on a rear face of the transistor, and the conductive vias pass through a semiconductor substrate of the transistor;
• le terminal de grille est formé par un film de cuivre collé sur un support en céramique, sur lequel est assemblée la face arrière du transistor par l'intermédiaire d'une colle conductrice électrique ; • les vias conducteurs sont uniformément répartis le long de chaque électrode de grille ; • the gate terminal is formed by a copper film bonded to a ceramic support, on which the rear face of the transistor is assembled by means of an electrically conductive adhesive; • the conductive vias are uniformly distributed along each gate electrode;
• chaque via conducteur présente une section, de forme circulaire, carré, rectangle ou polygonale, comprise entre 1 et 100 microns carrés ; • each via conductor has a section, of circular, square, rectangle or polygonal shape, between 1 and 100 square microns;
• les vias conducteurs comprennent un matériau conducteur électrique choisi parmi le cuivre et l'aluminium ; • the conductive vias comprise an electrically conductive material chosen from copper and aluminum;
• le transistor à effet de champ comprend une couche superficielle semi-conductrice comprenant un empilement à base de matériaux III-N, en particulier à base de matériau GaN et AlGaN, dans laquelle le canal de conduction consiste en une couche de gaz d'électrons à deux dimensions. • the field effect transistor comprises a semi-conducting surface layer comprising a stack based on III-N materials, in particular based on GaN and AlGaN material, in which the conduction channel consists of a layer of electron gas two-dimensional.
BREVE DESCRIPTION DES DESSINS BRIEF DESCRIPTION OF THE DRAWINGS
D'autres caractéristiques et avantages de l'invention ressortiront de la description détaillée qui va suivre en référence aux figures annexées sur lesquelles : Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:
- Les figures la et lb présentent un transistor à structure interdigitée selon l'état de la technique ; - Figures la and lb show a transistor with interdigitated structure according to the state of the art;
- La figure 2 présente une vue de dessus d'un transistor conforme à la présente invention ; - Figure 2 shows a top view of a transistor according to the present invention;
- Les figures 3a et 3b présentent respectivement une vue en coupe d'une cellule élémentaire d'un transistor, et une vue de dessus dudit transistor selon un premier mode de réalisation de l'invention ; FIGS. 3a and 3b respectively show a sectional view of an elementary cell of a transistor, and a top view of said transistor according to a first embodiment of the invention;
La figure 4 présente un transistor selon le premier mode de réalisation de l'invention (i), comparé à un transistor à structure interdigitée selon l'état de la technique (ii), et localise, sur chaque transistor, la cellule élémentaire pour laquelle la résistance RG, entre son électrode de grille et un plot contactant le terminal de grille, a été évaluée ; FIG. 4 shows a transistor according to the first embodiment of the invention (i), compared with a transistor with interdigitated structure according to the state of the art (ii), and locates, on each transistor, the elementary cell for which the resistance R G , between its gate electrode and a pad contacting the gate terminal, has been evaluated;
Les figures 5a et 5b présentent respectivement une vue en coupe d'une cellule élémentaire d'un transistor, et une vue de dessus dudit transistor selon un deuxième mode de réalisation de l'invention ; FIGS. 5a and 5b respectively show a sectional view of an elementary cell of a transistor, and a top view of said transistor according to a second embodiment of the invention;
La figure 6 présente un transistor selon le deuxième mode de réalisation de l'invention (i), comparé à un transistor à structure interdigitée selon l'état de la technique (ii), et localise, sur chaque transistor, la cellule élémentaire pour laquelle la résistance RG, entre son électrode de grille et un plot contactant le terminal de grille, a été évaluée. FIG. 6 shows a transistor according to the second embodiment of the invention (i), compared with a transistor with interdigitated structure according to the state of the art (ii), and locates, on each transistor, the elementary cell for which the resistance R G , between its gate electrode and a pad contacting the gate terminal, was evaluated.
Les mêmes références sur les figures pourront être utilisées pour des éléments de même nature. The same references in the figures could be used for elements of the same nature.
Les figures sont des représentations schématiques qui, dans un objectif de lisibilité, ne sont pas à l'échelle. En particulier, les épaisseurs des couches selon l'axe z ne sont pas à l'échelle par rapport aux dimensions latérales selon les axes x et y. The figures are schematic representations which, for the sake of readability, are not to scale. In particular, the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes.
DESCRIPTION DETAILLEE DE L' INVENTION DETAILED DESCRIPTION OF THE INVENTION
L'invention concerne un transistor à effet de champ (FET) 100 comprenant un substrat semi-conducteur dont au moins une couche superficielle forme la région active du transistor 100. Comme cela est bien connu, la région active définit une région de source, une région de drain et un canal de conduction entre ces deux régions. Le transistor est basé sur une technologie LD-MOS, les régions de source et de drain sont donc incluses dans la couche superficielle et la conduction entre elles se fait latéralement, dans le plan principal (x,y) de ladite couche.The invention relates to a field effect transistor (FET) 100 comprising a semiconductor substrate, at least one surface layer of which forms the active region of the transistor 100. As is well known, the active region defines a source region, a source region. drain region and a conduction channel between these two regions. The transistor is based on LD-MOS technology, the source and drain regions are therefore included in the surface layer and conduction between them takes place laterally, in the principal plane (x, y) of said layer.
Les régions semi-conductrices de source et de drain sont en contact ohmique avec des électrodes respectivement de source et de drain. Une électrode de grille est disposée entre les électrodes de source et de drain, au-dessus du canal de conduction de la région active. La tension appliquée à l'électrode de grille permet de gérer l'état passant ou bloqué du transistor 100. The source and drain semiconductor regions are in ohmic contact with the source and drain electrodes, respectively. A gate electrode is disposed between the source and drain electrodes, above the conduction channel of the active region. The voltage applied to the gate electrode makes it possible to manage the on or off state of transistor 100.
Le transistor 100 selon l'invention présente une structure d'électrodes interdigitées comme cela est apparent en vue de dessus sur la figure 2. Il est formé par plusieurs cellules élémentaires de transistor 50 disposées en parallèle dans le plan principal (x,y). Chaque cellule élémentaire 50 comprend une électrode de source 1, une électrode de drain 3 et une électrode de grille 2 intercalée entre les électrodes de source 1 et de drain 3. The transistor 100 according to the invention has a structure of interdigitated electrodes as is apparent in top view in FIG. 2. It is formed by several elementary cells of transistor 50 arranged in parallel in the main plane (x, y). Each elementary cell 50 comprises a source electrode 1, a drain electrode 3 and a gate electrode 2 interposed between the source 1 and drain 3 electrodes.
Préférentiellement, les électrodes de source 1, de grille 2 et de drain 3 sont formées en aluminium. Elles présentent typiquement une longueur (selon l'axe x sur les figures) comprise entre 1mm et 2mm et une largeur (selon l'axe y sur les figures) comprise entre 1 et 10 microns. Preferably, the source 1, gate 2 and drain 3 electrodes are made of aluminum. They typically have a length (along the x axis in the figures) between 1mm and 2mm and a width (along the y axis in the figures) between 1 and 10 microns.
Toutes les électrodes de source 1 des cellules élémentaires 50 sont électriquement connectées au terminal de source 10 du transistor 100. Les électrodes de drain 3 sont quant à elles électriquement connectées au terminal de drain 30 du transistor 100. Comme cela est illustré sur la figure 2, les terminaux de source 10 et de drain 30 s'étendent avantageusement en périphérie de la région active 40, perpendiculairement à l'axe des électrodes 1,3 et sont électriquement reliés à une extrémité des électrodes respectivement de source 1 et de drain 3. En général, les terminaux 10,30 sont disposés dans un plan au-dessus du plan (x,y) dans lequel s'étendent les électrodes 1,3 : des interconnexions verticales (c'est-à-dire selon l'axe z sur les figures) entre une extrémité des électrodes de source 1 et de drain 3 assurent leur liaison électrique respectivement avec le terminal de source 10 et le terminal de drain 30. Ces interconnexions ne sont pas représentées sur les figures. All the source electrodes 1 of the elementary cells 50 are electrically connected to the source terminal 10 of the transistor 100. The drain electrodes 3 are for their part electrically connected to the drain terminal 30 of the transistor 100. As illustrated in FIG. 2 , the source 10 and drain 30 terminals advantageously extend at the periphery of the active region 40, perpendicular to the axis of the electrodes 1, 3 and are electrically connected to one end of the respectively source 1 and drain 3 electrodes. In general, the terminals 10, 30 are arranged in a plane above the plane (x, y) in which the electrodes 1, 3 extend: vertical interconnections (c ' that is to say along the axis z in the figures) between one end of the source 1 and drain 3 electrodes provide their electrical connection respectively with the source terminal 10 and the drain terminal 30. These interconnections are not shown. in the figures.
Les terminaux de source 10 et de drain 30 sont typiquement formés dans le même matériau que les électrodes 1,3. The source 10 and drain 30 terminals are typically formed from the same material as the electrodes 1, 3.
Le transistor 100 selon l'invention comprend en outre des vias 22 conducteurs et verticaux, pour connecter les électrodes de grille 2 au terminal de grille 20. Le terminal de grille 20 est disposé à l'aplomb de tout ou partie des cellules élémentaires 50, c'est-à-dire qu'il ne se trouve pas dans le même plan (x,y) que les électrodes 1,2,3, et pas nécessairement dans le même plan que les terminaux de source 10 et de drain 30. Le terminal de grille 20 est selon un premier mode de réalisation (figures 3a, 3b), en face avant du transistor 100, au-dessus des électrodes 1,2,3 et séparé de celles-ci par une couche diélectrique 6. Selon une deuxième mode de réalisation (figures 5a, 5b), le terminal de grille 20 est disposé en face arrière du transistor 100, en-dessous des électrodes 1,2,3 et du substrat semi-conducteur 4 dudit transistor 100. The transistor 100 according to the invention further comprises conductive and vertical vias 22, to connect the gate electrodes 2 to the gate terminal 20. The gate terminal 20 is placed in line with all or part of the elementary cells 50, that is, it is not in the same plane (x, y) as the electrodes 1,2,3, and not necessarily in the same plane as the source 10 and drain 30 terminals. The gate terminal 20 is according to a first embodiment (FIGS. 3a, 3b), on the front face of the transistor 100, above the electrodes 1,2,3 and separated from them by a dielectric layer 6. According to a second embodiment (FIGS. 5a, 5b), the gate terminal 20 is arranged on the rear face of the transistor 100, below the electrodes 1,2,3 and of the semiconductor substrate 4 of said transistor 100.
Selon l'un ou l'autre des modes de réalisation, le terminal de grille 20 ne consomme pas de surface utile de la région active 40 car il est situé à l'aplomb de tout ou partie des cellules élémentaires 50 ; il n'est pas adjacent aux cellules élémentaires 50, au contraire des terminaux de source 10 et de drain 30 qui se situent à la périphérie desdites cellules 50 dans le plan principal (x,y) ou dans un plan supérieur. Une telle configuration permet donc une optimisation de la surface de région active 40. According to one or the other of the embodiments, the gate terminal 20 does not consume any useful surface area of the active region 40 because it is located directly above all or part of the elementary cells 50; it is not adjacent to the elementary cells 50, unlike the source 10 and drain 30 terminals which are located at the periphery of said cells 50 in the main plane (x, y) or in a higher plane. Such a configuration therefore allows optimization of the active region surface 40.
Par ailleurs, la disposition du terminal de grille 20 en face avant ou en face arrière du transistor 100 autorise un grand degré de liberté quant aux dimensions (latérales et épaisseur) dudit terminal 20. Le choix d'un matériau métallique très bon conducteur électrique (par exemple, le cuivre ou l'aluminium) et d'une superficie étendue pour le terminal de grille 20 permet de diminuer grandement sa résistance. Furthermore, the arrangement of the gate terminal 20 on the front face or on the rear face of the transistor 100 allows a great degree of freedom as to the dimensions (lateral and thickness) of said terminal 20. The choice of a metallic material which is very good electrical conductor ( for example, copper or aluminum) and an extended surface area for the gate terminal 20 allows its resistance to be greatly reduced.
Les vias conducteurs 22 sont préférentiellement formés en un matériau très bon conducteur, par exemple le cuivre. Cela participe également à diminuer la résistance de grille. Préférentiellement, chaque vias conducteur 22 présente une section comprise entre 1 et 100 microns carrés. The conductive vias 22 are preferably formed from a very good conductive material, for example copper. This also helps to reduce the grid resistance. Preferably, each conductive vias 22 has a section of between 1 and 100 square microns.
Selon l'invention, une pluralité de vias conducteurs 22 relie chaque électrode de grille 2 au terminal de grille 20, comme illustré sur la figure 2. Chaque via 22 vient connecter verticalement une électrode de grille 2 dans sa longueur, et non pas à une extrémité ou sur une extension spécifiquement aménagée à cet effet. According to the invention, a plurality of conductive vias 22 connects each gate electrode 2 to the gate terminal 20, as illustrated in FIG. 2. Each via 22 vertically connects a gate electrode 2 in its length, and not to a end or on an extension specifically designed for this purpose.
La pluralité de vias conducteurs 22 directement connectée entre chaque électrode de grille 2 et le terminal de grille 20 permet de diminuer significativement la résistance de grille. The plurality of conductive vias 22 directly connected between each gate electrode 2 and the gate terminal 20 makes it possible to significantly reduce the gate resistance.
A titre d'exemple, pour des électrodes de grille 2 présentant une longueur (selon l'axe x) de l'ordre de 1mm, on pourra réaliser entre quatre et huit vias conducteurs 22, répartis sur toute la longueur. En particulier, dans le deuxième mode de réalisation, le nombre de vias 22 par électrode de grille 2 est défini par le compromis entre la densité de courant d'appel de grille et la surface de zone active empiétée par la traversée des vias 22. Revenant à la description du premier mode de réalisation de l'invention, le terminal de grille 20 est donc disposé sur la face avant 100a du transistor 100, c'est-à-dire celle au niveau de laquelle on trouve la couche superficielle semi-conductrice 5 et la région active 40. La figure 3a illustre une vue en coupe d'une cellule élémentaire 50 du transistor 100 conforme à l'invention. Le substrat semi-conducteur comprend la couche superficielle 5 et une partie support inférieure 4 (appelée substrat support 4 par la suite). Les électrodes de source 1 et de drain 3 sont en contact ohmique avec la couche superficielleBy way of example, for grid electrodes 2 having a length (along the x axis) of the order of 1 mm, between four and eight conductive vias 22, distributed over the entire length, can be produced. In particular, in the second embodiment, the number of vias 22 per gate electrode 2 is defined by the compromise between the gate inrush current density and the surface area of the active zone encroached by the crossing of the vias 22. Returning to the description of the first embodiment of the invention, the gate terminal 20 is therefore arranged on the front face 100a of the transistor 100, that is to say that at which the semi-surface layer is found. conductor 5 and the active region 40. FIG. 3a illustrates a sectional view of an elementary cell 50 of the transistor 100 in accordance with the invention. The semiconductor substrate comprises the surface layer 5 and a lower support part 4 (referred to as support substrate 4 hereinafter). The source 1 and drain 3 electrodes are in ohmic contact with the surface layer
5. Le canal de conduction (non représenté) s'étend entre source et drain, dans le plan (x,y). 5. The conduction channel (not shown) extends between source and drain, in the (x, y) plane.
Avantageusement, la couche superficielle semi-conductrice 5 comprend un empilement de matériaux III-N, en particulier à base de matériau GaN, AlGaN, AIN, etc. Le canal de conduction consiste alors en une couche de gaz d'électrons à deux dimensions (2DEG), et les électrodes de source 1 et de drain 3 sont en contact ohmique avec ladite couche 2DEG. Le transistor 100 est alors un transistor de puissance, adapté aux applications haute tension. Advantageously, the semi-conducting surface layer 5 comprises a stack of III-N materials, in particular based on GaN, AlGaN, AIN, etc. material. The conduction channel then consists of a two-dimensional electron gas layer (2DEG), and the source 1 and drain 3 electrodes are in ohmic contact with said 2DEG layer. The transistor 100 is then a power transistor, suitable for high voltage applications.
Dans l'exemple de la figure 3a, un oxyde de grille 2a sépare l'électrode de grille 2 et la couche superficielle 5. L'oxyde de grille 2a est typiquement formé en oxyde de silicium et présente une épaisseur de quelques dizaines de nanomètres. In the example of FIG. 3a, a gate oxide 2a separates the gate electrode 2 and the surface layer 5. The gate oxide 2a is typically formed from silicon oxide and has a thickness of a few tens of nanometers.
De manière avantageuse, l'électrode de grille 2 est connectée à une plaque de champ 2b, séparée de la couche superficielle 5 par une couche isolante d'épaisseur supérieure ou égale à l'épaisseur de l'oxyde de grille 2a. Advantageously, the gate electrode 2 is connected to a field plate 2b, separated from the surface layer 5 by an insulating layer of thickness greater than or equal to the thickness of the gate oxide 2a.
Les électrodes 1,2,3 sont couvertes par une couche diélectriqueThe electrodes 1,2,3 are covered by a dielectric layer
6, formée au moins en partie par une couche dite de passivation. La couche diélectrique 6 comprend préférentiellement de l'oxyde de silicium, du nitrure de silicium, ou encore de l'alumine. Des vias conducteurs 22 traversent la couche diélectrique 6 de manière à atteindre l'électrode de grille 2. Un procédé classique impliquant des étapes de lithographie, de gravure de la couche diélectrique 6, puis de dépôt pour le remplissage des vias 22, peut être mis en œuvre. Un film isolant 22b et/ou formant une barrière de diffusion peut être déposé sur les parois de la tranchée correspondant à chaque via 22, avant son remplissage par un matériau conducteur électrique. 6, formed at least in part by a so-called passivation layer. The dielectric layer 6 preferably comprises silicon oxide, silicon nitride, or even alumina. Conductive vias 22 pass through the dielectric layer 6 so as to reach the gate electrode 2. A conventional method involving steps of lithography, of etching of the dielectric layer 6, then of deposition to fill the vias 22, can be used. implemented. An insulating film 22b and / or forming a diffusion barrier can be deposited on the walls of the trench corresponding to each via 22, before it is filled with an electrically conductive material.
Le terminal de grille 20 est ensuite formé par dépôt d'un matériau métallique conducteur sur la couche diélectrique 6, en contact électrique avec les vias 22. Le terminal de grille 20 est disposé au-dessus de tout ou partie de la région active 40 de la cellule élémentaire 50, et plus généralement au-dessus de tout ou partie de la région active 40 du transistor 100, comme illustré sur la figure 3b. The gate terminal 20 is then formed by depositing a conductive metallic material on the dielectric layer 6, in electrical contact with the vias 22. The gate terminal 20 is disposed above all or part of the active region 40 of elementary cell 50, and more generally above all or part of active region 40 of transistor 100, as illustrated in FIG. 3b.
Les reprises de contact 200, pour connecter le transistor 100 à un autre dispositif électronique ou à un boitier, peuvent se faire soit par contact filaire ou par l'intermédiaire de plots ou billes mis en œuvre dans les techniques connues de packaging. The contacts 200, to connect the transistor 100 to another electronic device or to a box, can be done either by wired contact or by means of pads or balls implemented in known packaging techniques.
Une comparaison a été faite entre un transistor 100 selon le premier mode de mise en œuvre de l'invention et un transistor 90 de l'état de la technique, respectivement référencés (i) et (ii) sur la figure 4. Le calcul de la résistance de grille RG est fait pour la zone la moins favorable du transistor, à savoir, pour la cellule élémentaire 50 la plus éloignée des plots de reprise de contact 200. A comparison has been made between a transistor 100 according to the first embodiment of the invention and a transistor 90 of the state of the art, respectively referenced (i) and (ii) in FIG. 4. The calculation of the gate resistor R G is made for the least favorable zone of the transistor, namely, for the elementary cell 50 furthest from the contact pick-up pads 200.
Dans l'exemple (i) de transistor 100 selon l'invention, le calcul de RG est effectué entre l'électrode de grille 2 de la cellule élémentaire 50 la plus à gauche sur la figure 4 et deux plots de contact 200 situés à droite sur le transistor 100 ; les plots de contact 200 sont des billes déposées sur le terminal de grille 20. Ce dernier est formé par une couche de cuivre de 10 microns d'épaisseur dont la résistance est d'environ 5 mohm. Les vias conducteurs 22 présentent une section carrée de 8 microns de côté dans le plan (x,y) et s'étendent sur une hauteur de 50 microns (selon l'axe z), entre électrodes de grille 2 et terminal de grille 20. La couche diélectrique 6 présente donc une épaisseur de l'ordre de 50 microns. Les vias conducteurs 22 sont en cuivre. La résistance associée est d'environ 13 mohm. On évalue donc à environ 18 mohm la résistance de grille RG entre l'électrode de grille 2 de la cellule élémentaire 50 étudiée et le plot de contact 200. In example (i) of transistor 100 according to the invention, the calculation of R G is carried out between the gate electrode 2 of the elementary cell 50 furthest to the left in FIG. 4 and two contact pads 200 located at right on transistor 100; the contact pads 200 are balls deposited on the gate terminal 20. The latter is formed by a layer of copper of 10 microns thick with a resistance of about 5 mohm. The conductive vias 22 have a square section with side 8 microns in the (x, y) plane and extend over a height of 50 microns (along the z axis), between gate electrodes 2 and gate terminal 20. The dielectric layer 6 therefore has a thickness of the order of 50 microns. The conductive vias 22 are made of copper. The associated resistance is about 13 mohm. The gate resistance R G between the gate electrode 2 of the elementary cell 50 studied and the contact pad 200 is therefore evaluated at approximately 18 mohm.
Toujours en référence à la figure 4, dans l'exemple (ii) de transistor de l'état de l'art, le calcul de RG est effectué entre l'électrode de grille 2 d'une cellule élémentaire 50 centrale et deux plots de contact 200 constitués par des connexions filaires connectées aux terminaux de grille 20 situés en périphérie de la région active 40 du transistor 90 ; rappelons que chaque électrode de grille 2 des cellules élémentaires 50 est reliée aux terminaux de grille 20 via une ligne de connexion 21. La structure de grille (électrodes de grille 2, ligne de connexion 21 et terminaux de grille 20) est élaborée sur deux niveaux de métal et des interconnexions en tungstène connectent ces deux niveaux, comme cela est classiquement réalisé. La résistance de grille RG entre l'électrode de grille 2 de la cellule élémentaire 50 étudiée et le plot de contact 200 est alors de l'ordre de 2 à 3 ohms. Still with reference to FIG. 4, in example (ii) of a state-of-the-art transistor, the calculation of R G is carried out between the gate electrode 2 of a central elementary cell 50 and two pads contact 200 formed by wire connections connected to gate terminals 20 located at the periphery of the active region 40 of transistor 90; remember that each gate electrode 2 of the elementary cells 50 is connected to the gate terminals 20 via a connection line 21. The gate structure (gate electrodes 2, connection line 21 and gate terminals 20) is developed on two levels of metal and tungsten interconnects connect these two levels, as is conventionally done. The gate resistance R G between the gate electrode 2 of the elementary cell 50 studied and the contact pad 200 is then of the order of 2 to 3 ohms.
Le transistor 100 selon l'invention procure donc une nette diminution d'environ un facteur 100 de la résistance de grille RG, limitant grandement la problématique de focalisation de courant dans certaines cellules élémentaires lors de la commutation à l'état passant du transistor. Selon un deuxième mode de réalisation de l'invention, le terminal de grille 20 est disposé en face arrière du transistor 100, en- dessous des électrodes 1,2,3 et du substrat semi-conducteur dudit transistor 100. The transistor 100 according to the invention therefore provides a net reduction of about a factor of 100 in the gate resistance R G , greatly limiting the problem of current focusing in certain elementary cells during the switching to the on state of the transistor. According to a second embodiment of the invention, the gate terminal 20 is arranged on the rear face of the transistor 100, below the electrodes 1,2,3 and of the semiconductor substrate of said transistor 100.
La figure 5a illustre une vue en coupe d'une cellule élémentaire 50 du transistor 100 conforme à l'invention. On retrouve le substrat semi-conducteur, comprenant la couche superficielle 5 et le substrat support 4. Les électrodes de source 1 et de drain 3 sont en contact ohmique avec la couche superficielle 5. Le canal de conduction (non représenté) s'étend entre source et drain, dans le plan (x,y). FIG. 5a illustrates a sectional view of an elementary cell 50 of transistor 100 in accordance with the invention. We find the semiconductor substrate, comprising the surface layer 5 and the support substrate 4. The source 1 and drain 3 electrodes are in ohmic contact with the surface layer 5. The conduction channel (not shown) extends between source and drain, in the (x, y) plane.
Comme dans le premier mode de réalisation, la couche superficielle semi-conductrice 5 comprend avantageusement un empilement à base de matériaux III-N, en particulier à base de matériau GaN, AlGaN, AIN, etc. Le canal de conduction consiste alors en une couche de gaz d'électrons à deux dimensions (2DEG), et les électrodes de source 1 et de drain 3 sont en contact ohmique avec ladite couche 2DEG. As in the first embodiment, the surface semiconductor layer 5 advantageously comprises a stack based on III-N materials, in particular based on GaN, AlGaN, AIN, etc. material. The conduction channel then consists of a two-dimensional electron gas layer (2DEG), and the source 1 and drain 3 electrodes are in ohmic contact with said 2DEG layer.
Un oxyde de grille sépare l'électrode de grille 2 et la couche superficielle 5. L'oxyde de grille est typiquement formé en oxyde de silicium et présente une épaisseur de quelques dizaines de nanomètres. L'électrode de grille 2 peut être connectée à une plaque de champ, séparée de la couche superficielle 5 par une couche isolante d'épaisseur supérieure ou égale à l'épaisseur de l'oxyde de grille. A gate oxide separates the gate electrode 2 and the surface layer 5. The gate oxide is typically formed from silicon oxide and has a thickness of a few tens of nanometers. The gate electrode 2 can be connected to a field plate, separated from the surface layer 5 by an insulating layer of thickness greater than or equal to the thickness of the gate oxide.
Les vias conducteurs 22 peuvent être élaborés selon deux variantes : la première variante prévoit la formation des vias 22 par gravure et dépôt à partir de la face avant du substrat semi-conducteur du transistor 100 ; la deuxième variante prévoit la formation des vias 22 par sa face arrière. Selon la première variante, les vias 22 sont réalisées préalablement à la formation des électrodes de grille 2. Un procédé de photolithographie et de gravure profonde (par exemple par gravure par ions réactifs - RIE) à travers la couche superficielle 5 et à travers tout ou partie le substrat support 4, permet en premier lieu de former des tranchées à partir de la face avant 100a. Un film isolant est déposé sur les parois des tranchées, de manière à isoler les vias conducteurs 22 des matériaux semi-conducteurs de la couche superficielle 5 et du substrat support 4. Un dépôt de métal est ensuite opéré pour remplir les tranchées et former les vias 22. Les électrodes de grille 2 peuvent ensuite être élaborées ; notons que les électrodes de source 1 et de drain 3 pourront être formées avant ou après tout ou partie de l'élaboration des vias 22. The conductive vias 22 can be produced according to two variants: the first variant provides for the formation of the vias 22 by etching and deposition from the front face of the semiconductor substrate of the transistor 100; the second variant provides for the formation of vias 22 by its rear face. According to the first variant, the vias 22 are produced prior to the formation of the gate electrodes 2. A process of photolithography and deep etching (for example by reactive ion etching - RIE) through the surface layer 5 and through everything or part of the support substrate 4, first of all makes it possible to form trenches from the front face 100a. An insulating film is deposited on the walls of the trenches, so as to isolate the conductive vias 22 from the semiconductor materials of the surface layer 5 and of the support substrate 4. A metal deposit is then operated to fill the trenches and form the vias. 22. The gate electrodes 2 can then be produced; it should be noted that the source 1 and drain 3 electrodes may be formed before or after all or part of the development of the vias 22.
Dans le cas particulier où il est prévu d'amincir le substrat support 4 en fin de fabrication du transistor 100, il est avantageux de ne pas faire déboucher les vias conducteurs 22 du substrat support 4 lors de leur réalisation (figure 5a (i)) ; elles déboucheront à l'issue de l'amincissement du substrat support 4. In the particular case where provision is made to thin the support substrate 4 at the end of manufacture of the transistor 100, it is advantageous not to open the conductive vias 22 of the support substrate 4 during their production (FIG. 5a (i)). ; they will emerge at the end of the thinning of the support substrate 4.
Selon la deuxième variante, les vias conducteur 22 sont élaborés après la formation des électrodes 1,2,3, voire après la réalisation des terminaux de source 10 et de drain 30. Un procédé impliquant des étapes de photolithographie et de gravure profonde (par exemple par gravure par ions réactifs - RIE) à travers le substrat support 4 et à travers la couche superficielle 5, permet en premier lieu de former des tranchées, depuis la face arrière 100b jusqu'à l'électrode de grille 2. Un film isolant est déposé sur les parois des tranchées, de manière à isoler les vias conducteurs 22 des matériaux semi-conducteurs traversés. Un dépôt de métal est ensuite opéré pour remplir les tranchées et former les vias 22. Dans l'une et l'autre des variantes précitées, le terminal de grille 20 est formé en contact avec les vias conducteurs 22 débouchant au niveau de la face arrière 100b du transistor 100 (figure 5a (ii)). According to the second variant, the conductive vias 22 are produced after the formation of the electrodes 1, 2, 3, or even after the production of the source 10 and drain 30 terminals. A method involving steps of photolithography and deep etching (for example by reactive ion etching - RIE) through the support substrate 4 and through the surface layer 5, first of all makes it possible to form trenches, from the rear face 100b to the gate electrode 2. An insulating film is deposited on the walls of the trenches, so as to isolate the conductive vias 22 from the semiconductor materials passed through. A metal deposit is then operated to fill the trenches and form the vias 22. In both of the aforementioned variants, the gate terminal 20 is formed in contact with the conductive vias 22 opening out at the rear face 100b of the transistor 100 (FIG. 5a (ii)).
Il peut être élaboré par dépôt d'un matériau métallique conducteur sur le substrat support 4. Le terminal de grille 20 peut aussi être formé par un film de cuivre collé sur un support en céramique (DBC pour « direct bond copper »), sur lequel est assemblée la face arrière 100b du transistor 100 par l'intermédiaire d'une colle conductrice électrique (figure 5b). Cette configuration apporte l'avantage supplémentaire de polariser le substrat support 4 au potentiel de grille, c'est- à-dire à un potentiel très proche de celui de la source. Cette polarisation est généralement utile au bon fonctionnement du transistor 100 et est autorisée sans étape supplémentaire par le deuxième mode de réalisation de l'invention. It can be produced by depositing a conductive metallic material on the support substrate 4. The gate terminal 20 can also be formed by a copper film bonded to a ceramic support (DBC for “direct bond copper”), on which the rear face 100b of the transistor 100 is assembled by means of an electrically conductive adhesive (FIG. 5b). This configuration provides the additional advantage of polarizing the support substrate 4 at the gate potential, that is to say at a potential very close to that of the source. This bias is generally useful for the correct operation of the transistor 100 and is authorized without an additional step by the second embodiment of the invention.
Quelle que soit la variante de réalisation implémentée, le terminal de grille 20 est disposé en dessous de tout ou partie de la région active 40 de la cellule élémentaire 50, et plus généralement en dessous de tout ou partie de la région active 40 du transistor 100. Whatever the variant embodiment implemented, the gate terminal 20 is placed below all or part of the active region 40 of the elementary cell 50, and more generally below all or part of the active region 40 of the transistor 100. .
Les reprises de contact, pour connecter le transistor 100 à un autre dispositif électronique ou à un boitier, peuvent se faire soit par contact filaire ou par l'intermédiaire de plots ou billes. The contact resumptions, to connect the transistor 100 to another electronic device or to a box, can be done either by wired contact or by means of pads or balls.
Une comparaison a été faite entre un transistor 100 selon le deuxième mode de mise en œuvre de l'invention (figure 6 (i)) et le transistor 90 de l'état de la technique (figure 6 (ii) déjà décrit en référence au premier mode de réalisation. A comparison has been made between a transistor 100 according to the second embodiment of the invention (FIG. 6 (i)) and the transistor 90 of the state of the art (FIG. 6 (ii) already described with reference to first embodiment.
Dans l'exemple (i) de transistor 100 selon l'invention, on évalue la résistance RG, entre l'électrode de grille 2 de la cellule élémentaire 50 la plus à gauche du transistor 100 et deux plots de contact 200 situés à droite du transistor 100 ; les plots de contact 200 sont ici des connexions filaires solidaires du film de cuivre (terminal de grille 20 en contact électrique avec les vias conducteurs 22) d'un DBC. Le film de cuivre présente une épaisseur de 90 microns. La résistance associée au terminal de grille 20 et aux connexions filaires est d'environ 0,7 mohm.In example (i) of transistor 100 according to the invention, the resistance R G is evaluated between the gate electrode 2 of the elementary cell 50 most to the left of the transistor 100 and two pads contact 200 located to the right of transistor 100; the contact pads 200 are here wire connections integral with the copper film (gate terminal 20 in electrical contact with the conductive vias 22) of a DBC. The copper film has a thickness of 90 microns. The resistance associated with the gate terminal 20 and wire connections is approximately 0.7 mohm.
Une couche de colle conductrice, par exemple une colle à base d'argent avec une résistivité p=6e-6 Q.cm, assure l'assemblage entre le film de cuivre du DBC et la face arrière du transistor 100. La résistance associée est de l'ordre de 14 mohm. A layer of conductive glue, for example a silver-based glue with a resistivity p = 6e-6 Q.cm, ensures the assembly between the copper film of the DBC and the rear face of the transistor 100. The associated resistance is of the order of 14 mohm.
Les vias conducteurs 22 présentent une section carrée de 8 microns de côté dans le plan (x,y) et s'étendent sur une hauteur (selon l'axe z) de 300 microns, entre électrodes de grille 2 et face arrière 100b du substrat support 4. Les vias conducteurs 22 sont en cuivre. La résistance associée est d'environ 80 mohm. On évalue donc à environ 95 mohm la résistance de grille RG entre l'électrode de grille 2 de la cellule élémentaire 50 étudiée et le plot de contact 200. The conductive vias 22 have a square section of 8 microns per side in the (x, y) plane and extend over a height (along the z axis) of 300 microns, between gate electrodes 2 and rear face 100b of the substrate support 4. The conductive vias 22 are made of copper. The associated resistance is about 80 mohm. The gate resistance R G between the gate electrode 2 of the elementary cell 50 studied and the contact pad 200 is therefore evaluated at approximately 95 mohm.
Comparée au transistor 90 de l'état de l'art (RG de l'ordre de 2 à 3 ohms), le transistor 100 selon le deuxième mode de réalisation de l'invention procure une résistance de grille RG inférieure d'un ordre 10, et apte à réduire la problématique de focalisation de courant dans certaines cellules élémentaires lors de la commutation à l'état passant du transistor. Compared with the transistor 90 of the state of the art (R G of the order of 2 to 3 ohms), the transistor 100 according to the second embodiment of the invention provides a gate resistance R G less than order 10, and capable of reducing the problem of current focusing in certain elementary cells during the switching to the on state of the transistor.
Bien-sûr, l'invention n'est pas limitée aux modes de réalisation décrits et on peut y apporter des variantes de réalisation sans sortir du cadre de l'invention tel que défini par les revendications . Of course, the invention is not limited to the embodiments described and it is possible to provide variant embodiments without departing from the scope of the invention as defined by the claims.

Claims

REVENDICATIONS
1. Transistor à effet de champ (100) présentant une structure interdigitée et comprenant : plusieurs cellules élémentaires de transistor (50) disposées en parallèle, chaque cellule élémentaire comprenant une électrode de source (1), une électrode de drain (3) et une électrode de grille (2) intercalée entre les électrodes de source (1) et de drain (3), 1. Field effect transistor (100) having an interdigitated structure and comprising: several elementary transistor cells (50) arranged in parallel, each elementary cell comprising a source electrode (1), a drain electrode (3) and a gate electrode (2) interposed between the source (1) and drain (3) electrodes,
- un terminal de source (10) et un terminal de drain (30) respectivement connectés aux électrodes de sources (1) et aux électrodes de drain (3) des cellules élémentaires (50),- a source terminal (10) and a drain terminal (30) respectively connected to the source electrodes (1) and to the drain electrodes (3) of the elementary cells (50),
- un terminal de grille (20) connecté aux électrodes de grille (2) des cellules élémentaires (50), le transistor à effet de champ (100) étant caractérisé en ce qu'il comprend uniquement des vias conducteurs (22) verticaux pour connecter les électrodes de grille (2) au terminal de grille (20), une pluralité de vias conducteurs (22) répartis le long de chaque électrode de grille (2) reliant chaque électrode de grille (2) au terminal de grille (20), et le terminal de grille (20) étant disposé à l'aplomb de tout ou partie des cellules élémentaires (50). - a gate terminal (20) connected to the gate electrodes (2) of the elementary cells (50), the field effect transistor (100) being characterized in that it only comprises vertical conductive vias (22) for connecting the gate electrodes (2) to the gate terminal (20), a plurality of conductive vias (22) distributed along each gate electrode (2) connecting each gate electrode (2) to the gate terminal (20), and the gate terminal (20) being arranged in line with all or part of the elementary cells (50).
2. Transistor à effet de champ (100) selon la revendication précédente, dans lequel : 2. Field effect transistor (100) according to the preceding claim, wherein:
- le terminal de grille (20) est disposé sur une face avant (100a) du transistor (100), et les vias conducteurs (22) traversent une couche diélectrique (6) intercalée entre les électrodes de grille (2) des cellules élémentaires (50) et le terminal de grille (20). - the gate terminal (20) is arranged on a front face (100a) of the transistor (100), and the conductive vias (22) pass through a dielectric layer (6) interposed between the gate electrodes (2) of the elementary cells ( 50) and the gate terminal (20).
3. Transistor à effet de champ (100) selon la revendication 1, dans lequel : - le terminal de grille (20) est disposé sur une face arrière (100b) du transistor (100), et 3. A field effect transistor (100) according to claim 1, wherein: - the gate terminal (20) is arranged on a rear face (100b) of the transistor (100), and
- les vias conducteurs (22) traversent un substrat semi- conducteur (4,5) du transistor (100). - The conductive vias (22) pass through a semiconductor substrate (4,5) of the transistor (100).
4. Transistor à effet de champ (100) selon la revendication précédente, dans lequel le terminal de grille (20) est formé par un film de cuivre collé sur un support en céramique, sur lequel est assemblée la face arrière (100b) du transistor (100) par l'intermédiaire d'une colle conductrice électrique. 4. Field effect transistor (100) according to the preceding claim, wherein the gate terminal (20) is formed by a copper film bonded to a ceramic support, on which is assembled the rear face (100b) of the transistor. (100) by means of an electrically conductive adhesive.
5. Transistor à effet de champ (100) selon l'une des revendications précédentes, dans lequel les vias conducteurs (22) sont uniformément répartis le long de chaque électrode de grille (2). 5. Field effect transistor (100) according to one of the preceding claims, wherein the conductive vias (22) are uniformly distributed along each gate electrode (2).
6. Transistor à effet de champ (100) selon l'une des revendications précédentes, dans lequel chaque via conducteur (22) présente une section, de forme circulaire, carré, rectangle ou polygonale, comprise entre 1 et 100 microns carrés. 6. Field effect transistor (100) according to one of the preceding claims, wherein each conductor via (22) has a section, of circular, square, rectangle or polygonal shape, between 1 and 100 square microns.
7. Transistor à effet de champ (100) selon l'une des revendications précédentes, dans lequel les vias conducteurs (22) comprennent un matériau conducteur électrique choisi parmi le cuivre et l'aluminium. 7. Field effect transistor (100) according to one of the preceding claims, wherein the conductive vias (22) comprise an electrically conductive material selected from copper and aluminum.
8. Transistor à effet de champ (100) selon l'une des revendications précédentes, comprenant une couche superficielle semi-conductrice (5) comprenant un empilement à base de matériaux III-N, en particulier à base de matériau GaN et AlGaN, dans laquelle le canal de conduction consiste en une couche de gaz d'électrons à deux dimensions. 8. Field effect transistor (100) according to one of the preceding claims, comprising a semiconductor surface layer (5) comprising a stack based on III-N materials, in particular based on GaN and AlGaN material, in in which the conduction channel consists of a two-dimensional layer of electron gas.
EP21737725.8A 2020-06-30 2021-06-15 Transistor with interdigital electrodes, comprising a gate terminal connected by a plurality of vertical vias to the gate electrodes Pending EP4173033A1 (en)

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FR2006863A FR3112025B1 (en) 2020-06-30 2020-06-30 TRANSISTOR WITH INTERDIGITED ELECTRODES, INCLUDING A GRID TERMINAL CONNECTED BY A PLURALITY OF VERTICAL VIAS TO THE GRID ELECTRODES
PCT/FR2021/051069 WO2022003265A1 (en) 2020-06-30 2021-06-15 Transistor with interdigital electrodes, comprising a gate terminal connected by a plurality of vertical vias to the gate electrodes

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US9029866B2 (en) * 2009-08-04 2015-05-12 Gan Systems Inc. Gallium nitride power devices using island topography
US9362267B2 (en) * 2012-03-15 2016-06-07 Infineon Technologies Americas Corp. Group III-V and group IV composite switch
TWI577022B (en) * 2014-02-27 2017-04-01 台達電子工業股份有限公司 Semiconductor device and semiconductor device package using the same
US10128377B2 (en) * 2017-02-24 2018-11-13 International Business Machines Corporation Independent gate FinFET with backside gate contact
US10103233B1 (en) * 2017-09-29 2018-10-16 Nxp Usa, Inc. Transistor die with drain via arrangement, and methods of manufacture thereof

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FR3112025B1 (en) 2023-04-21
US20230253401A1 (en) 2023-08-10
FR3112025A1 (en) 2021-12-31

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