EP4158774A1

EP4158774A1 - Cascode amplifier with a feedback circuit for providing a bias voltage

Info

Publication number: EP4158774A1
Application number: EP20734502.6A
Authority: EP
Inventors: Luca Romano; Federico VECCHI
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-22
Filing date: 2020-06-22
Publication date: 2023-04-05
Also published as: WO2021259442A1

Abstract

The present disclosure relates to a cascode amplifier (1), CA, for amplifying an input voltage (Vin) to an output voltage (Vout), wherein the CA (1) comprises at least one circuit branch (CB1) comprising a load resistor (RL), a first transistor (Ql) and a second transistor (Q2) in series to each other. The CA further comprises a feedback circuit (2) and a reference voltage generation circuit (3). The feedback circuit (2) is configured to provide a bias voltage (Vbias) to the first transistor (Ql) by comparing a cascode voltage (Vcasc) sensed at a terminal of the first transistor (Ql) with a reference voltage (Vref). The reference voltage generation circuit (3) is configured to generate the reference voltage (Vref) using a voltage divider, such that the ratio between a transistor voltage (Vcel) of the first transistor (Ql) and a transistor voltage (Vce2) of the second transistor (Q2) is kept constant.

Description

CASCODE AMPLIFIER WITH A FEEDBACK CIRCUIT FOR PROVIDING A BIAS

VOLTAGE

TECHNICAL FIELD

The present disclosure relates to a cascode amplifier (CA) for amplifying an input voltage to an output voltage, wherein the CA comprises a feedback circuit for providing a bias voltage. The present disclosure further relates to a cascode amplifier circuit (CAC) comprising such a CA and to an amplifier circuit comprising one or more such CAs and/or one or more such CACs.

BACKGROUND

The present disclosure is in the field of cascode amplifiers (CAs) with one or more circuit branches, each branch comprising a load resistor, first transistor and second transistor electrically connected in series to each other. Such CAs have many advantages, such as high bandwidth, high linearity, high output impedance, and reduced input capacitive loading. CAs are especially used in applications where a good linearity is required. For example, they may be used in broadband driver amplifiers for optical communications, broadband transimpedance amplifiers for optical communications, broadband amplifiers for wideband RF transceivers and broadband amplifiers for narrowband RF transceivers.

SUMMARY

The inventors have made the following considerations.

Figures 1A and IB each show an example of a cascode amplifier (CA).

The CA of Figure 1A is a single ended amplifier comprising one circuit branch. The CA of Figure IB comprises two circuit branches which are electrically connected in parallel to each other. The term “electrically connected” may be referred to by only the term “connected”. Each of the two circuit branches of the differential CA of Figure IB is identical to the single circuit branch of the single ended CA of Figure 1A. Thus, in the following only the circuit branch of Figure 1 A is described, wherein this description is also valid for each of the two circuit branches of Figure IB. The circuit branch comprises a load resistor RL, a first transistor Ql, a second transistor Q2 and an optional degeneration resistor Rdeg that are connected in series to each other. The first transistor Ql and the second transistor Q2 are each a bipolar junction transistor (BJT).

The series connection of the load resistor RL, first transistor Ql, second transistor Q2 and the optional degeneration resistor Rdeg is connected between a supply terminal of the CA (for providing a supply voltage Vcc to the CA) and ground (GND). Ground is a reference potential of the circuit and optionally may correspond to the earth potential. In case the circuit branch of the CA comprises the degeneration resistor Rdeg, the CA may also be referred to as degenerated cascode amplifier (degenerated CA).

A bias voltage Vbias may be supplied to the base terminal (control terminal) of the first transistor Ql for biasing the first transistor Ql. The base terminal (control terminal) of the second transistor Q2 is connected to an input terminal of the CA. The node between the load resistor RL and the collector terminal (first terminal) of the first transistor Ql is connected to an output terminal of the CA.

In case of the single ended amplifier topology shown in Figure 1A an input voltage (input signal) Vin may be supplied via the input terminal to the base terminal of the second transistor Q2. The input voltage may be amplified by the CA and, thus, an output voltage (output signal) Vout corresponding to the amplified input voltage Vin may be provided at the node between the load resistor RL and the collector terminal of the first transistor QL

In case of the differential amplifier topology shown in Figure IB, the base terminal of each second transistor Q2 of the two circuit branches is connected to an input terminal of the CA. Thus, an input differential voltage (input differential signal) Vin,p - Vin,n may be supplied via these two input terminals to the base terminals of the two second transistors Q2, as shown in Figure IB, wherein the input differential voltage is to be amplified by the CA. The node between the load resistor RL and the first transistor Ql of each circuit branch is connected to an output terminal of the CA. These two output terminals of the CA may provide an output differential voltage (output differential signal), e.g. Vout,p - Vout,n, which corresponds to the amplified input differential voltage. As indicated in Figure IB, the two first transistors Q1 may be biased by the same bias voltage Vbias. Further, an optional current source for providing a bias current may be connected between ground and the node at which the two optional degeneration resistors Rdeg of the two circuit branches are connected. In case one or both degeneration resistors Rdeg is omitted, the optional current source may be connected between ground and the emitter terminal (second terminal) of one or both second transistors Q2.

The most significant performance parameters (typically in trade-off) of a CA are: linearity, voltage headroom, gain, output swing, and current consumption.

As a measure of linearity of the CA distortion of the CA may be equivalently used, which is often measured as Total Harmonic Distortion (THD). That is, the higher the THD of the CA the lower the linearity and vice versa.

The voltage headroom Vh corresponds to the supply voltage across the transistors of a circuit branch of a CA (such as the first and second transistors Q1 and Q2 of the circuit branch(es) of the CA of Figure 1A or IB) for a given current consumption and given load resistor RL and optional degeneration resistor Rdeg. That is, in case the circuit branch only comprises the load resistor RL, the voltage headroom Vh of the circuit branch corresponds to a supply voltage Vcc, which may be supplied to the supply terminal of the CA, subtracted by the voltage drop VRL across the load resistor RL (Vh = Vcc - (IRL X RL) = Vcc - VRL). In case the circuit branch comprises the load resistor RL and the optional degeneration resistor Rdeg, the voltage headroom Vh of the circuit branch corresponds to the supply voltage Vcc, which may be supplied to the supply terminal of the CA, subtracted by the voltage drop VRL across the load resistor RL and the voltage drop VRdeg across the degeneration resistor Rdeg (Vh = Vcc - (IRL x RL) - (iRdeg x Rdeg) = Vcc - (VRL + VRdeg)).

In other words, the voltage headroom Vh corresponds to the sum of the transistor voltages (collector emitter voltages) of the transistors of the circuit branch. That is, in case of the circuit branch of the CA of Figure 1 A, the voltage headroom Vh corresponds to the sum of the collector emitter voltage (transistor voltage) Vcel of the first transistor Q1 and the collector emitter voltage (transistor voltage) Vce2 of the second transistor Q2 (Vh = Vcel + Vce2), as shown in Figure 1A.

Process, supply voltage and temperature variations (PVT variations) may limit the achievable linearity performance of the CA.

In order to increase the linearity for a given total voltage headroom Vh, both transistors of the circuit branch, i.e. the first transistor Q1 and the second transistor Q2, need to be properly biased.

Usually the bias of the second transistor Q2 is fixed. This is done either because the second transistor Q2 is used to set a bias current of the circuit branch, in case of a single ended topology such as the CA of Figure 1 A, or because the second transistor Q2 needs to leave enough voltage in order for the optional current source connected to the two circuit branches to work properly providing a bias current, in case of a differential topology such as the CA of Figure IB.

Therefore, the linearity performance of the CA may be maximized by choosing respectively setting the bias voltage Vbias of the first transistor Q1 accordingly. In other words, the bias voltage Vbias provided to the base terminal (control terminal) of the first transistor Q1 has to be carefully chosen in order to maximize the linearity performance of the CA.

Figures 2A, 2B and 2C each show an example of a circuit for generating a bias voltage for a cascode amplifier (CA). In particular, Figures 2A, 2B and 2C show examples of circuits for generating the bias voltage Vbias that is provided to the first transistor Q1 of the circuit branch of the CA in order to improve the linearity performance of the CA by biasing the first transistor Q1 accordingly.

The circuit of Figure 2 A corresponds to a voltage divider formed by four resistors that are connected in series between ground and a supply terminal of the CA for supplying a supply voltage Vcc to the CA. The bias voltage Vbias may be provided at the middle node of the voltage divider (as shown in Figure 2A) or any other node between two resistors of the voltage divider. The biasing using the circuit of Figure 2A has the disadvantage that it is sensitive to supply voltage Vcc variations and temperature variations, as it does not comprise a temperature compensation.

The circuit of Figure 2B corresponds to a series connection formed by a current source and two resistors that are electrically connected between a supply terminal of the CA and ground. The current source is connected between the supply terminal of the CA and one of the resistors, and the basis voltage is provided at the node between the current source and the one resistor. The biasing using the circuit Figure 2B may include a temperature compensation (PTAT current/resistor temperature coefficient/VBE temperature variation), but has the disadvantage that it is sensitive to current/resistors mismatches.

The circuit of Figure 2C corresponds to a series connection formed by two resistors and a current source that are electrically connected between a supply terminal of the CA and ground. The current source is connected between ground and one of the resistors, and the basis voltage is provided at the node between the current source and the one resistor. The biasing using the circuit of Figure 2C can track the voltage drop from the supply voltage Vcc including load resistor RL temperature variation but has the disadvantage that it is sensitive to current/resistors mismatches.

Therefore, all of the circuits of Figures 2A, 2B and 2C need at least process calibration to ensure good linearity performance over process variations.

Some of the open loop biasing schemes shown in Figure 2, e.g. the circuits of Figures 2B and 2C, may partially track process, supply voltage and temperature variations (PVT variations). However, device mismatches of the elements of the respective circuit limit the effectiveness of the circuits of Figure 2. Thus, a calibration of the elements of the circuits is required in order to ensure proper operation, which adds complexity and, thus, is disadvantageous.

Figures 3 and 4 exemplarily show the ratio of the transistor voltage (collector emitter voltage) Vcel of the first transistor Q1 and the transistor voltage (collector emitter voltage) Vce2 of the second transistor Q2 of one or more circuit branches of a CA, such as the CA of Figure 1A or IB, for the open loop biasing scheme using the circuit of Figure 2B (shown in Figure 3) and the open loop biasing scheme using the circuit of Figure 2C (shown in Figure 5) versus temperature, process and supply voltage variations. Figure 3 shows the relationship between temperature and the ratio of the transistor voltage Vcel of the first transistor Q1 of one or more circuit branches of a CA, such as the CA of Figure 1A or IB, and the transistor voltage Vce2 of the second transistor Q2 of the one or more circuit branches of the CA for different supply voltages and different values of the load resistor and optional degeneration resistor of the one or more circuit branches of the CA, in case the circuit of Figure 2B provides a bias voltage to the first transistor Ql. Figure 4 shows the relationship between temperature and the ratio of the transistor voltage Vcel of the first transistor Ql of one or more circuit branches of a CA, such as the CA of Figure 1A or IB, and the transistor voltage Vce2 of the second transistor Q2 of the one or more circuit branches of the CA for different supply voltages and different values of the load resistor and optional degeneration resistor of the one or more circuit branches of the CA, in case the circuit of Figure 2C provides a bias voltage to the first transistor.

In Figures 3 and 4, the process variations are shown for two cases of the resistance value R of the one or more circuit branches of the CA, wherein the resistance value R (measured in ohm) is the sum of the resistance value of the load resistor and the resistance value of the optional degeneration resistor. The term “resistor value” may be used as a synonym for the term “resistance value”. In the first case the resistance value R corresponds to a typical resistance value Rtyp. In the second case the resistance value R corresponds to a maximum resistance value Rmax that is greater than the typical resistance value Rtyp (Rmax > Rtyp). The supply voltage variations are shown for two cases of the supply voltage Vcc. In the first case the supply voltage is a first supply voltage Vccl and in the second case the supply voltage is a second supply voltage Vcc2, wherein the second supply voltage Vcc2 is greater than the first supply voltage Vccl. The first supply voltage Vccl may be e.g. 2.9 Volt. The second supply voltage Vcc2 may be e.g. 3.3 Volt. The temperature variation is shown for temperatures between 0 and 100 degrees Celsius (°C).

The dashed line LI shows the variation of the transistor voltage ratio of the first transistor Ql and second transistor Q2 (Vce2/Vcel) for a varying temperature in the temperature range between 0°C and 100°C in case the resistance value R of the circuit branch corresponds to the maximum resistance value Rmax (R = Rmax) and the supply voltage Vcc corresponds to the first supply voltage Vccl (Vcc = Vccl). The dashed line L2 shows the variation of the transistor voltage ratio of the first transistor Q1 and second transistor Q2 (Vce2/Vcel) for a varying temperature in the temperature range between 0°C and 100°C in case the resistance value R of the circuit branch corresponds to the typical resistance value Rtyp (R = Rtyp) and the supply voltage Vcc corresponds to the first supply voltage Vccl (Vcc = Vccl). That is, for the dashed lines LI and L2 the supply voltage Vcc corresponds to the first supply voltage Vccl (Vcc = Vccl).

The solid line L3 shows the variation of the transistor voltage ratio of the first transistor Q1 and second transistor Q2 (Vce2/V cel) for a varying temperature in the temperature range between 0°C and 100°C in case the resistance value R of the circuit branch corresponds to the maximum resistance value Rmax (R = Rmax) and the supply voltage V cc corresponds to the second supply voltage Vcc2 (Vcc = Vcc2).

The solid line L4 shows the variation of the transistor voltage ratio of the first transistor Q1 and second transistor Q2 (Vce2/V cel) for a varying temperature in the temperature range between 0°C and 100°C in case the resistance value R of the circuit branch corresponds to the typical resistance value Rtyp (R = Rtyp) and the supply voltage Vcc corresponds to the second supply voltage Vcc2 (Vcc = Vcc2). That is, for the solid lines L3 and L4 the supply voltage Vcc corresponds to the second supply voltage Vcc2 (Vcc = Vcc2).

As can be seen from lines LI, L2, L3 and L4 of Figures 3 and 4 the ratio between the transistor voltages (collector emitter voltages) of the first and second transistors (Vce2/Vcel) changes with temperature variations. Moreover, as can be seen from dashed lines LI and L2 or from solid lines L3 and L4 for a given supply voltage Vcc and a given temperature, the ratio between the transistor voltages of the first and second transistors (Vce2/Vcel) changes with process variations, that is with a variation of the resistance value R of the circuit branch of the CA. Furthermore, as can be seen from the lines LI and L3 or from lines L2 and L4 for a given resistance value R of the circuit branch of the CA and a given temperature, the ratio of the transistor voltages of the first and second transistors (Vce2/Vcel) changes with supply voltage variations.

Figure 5 and 6 exemplarily show the linearity performance in terms of THD for the open loop biasing scheme using the circuit of Figure 2B (shown in Figure 5) and the open loop biasing scheme using the circuit of Figure 2C (shown in Figure 6) versus temperature, process and supply voltage variations. The linearity performance in terms of THD shown in Figure 5 is caused by the variation of the ratio of the transistor voltages of the first and second transistors of one or more circuit branches of a CA, such as the CA of Figure 1 A or IB, due to temperature, process and supply voltage variations shown in Figure 3. The linearity performance in terms of THD shown in Figure 6 is caused by the variation of the ratio of the transistor voltages of the first and second transistors of one or more circuit branches of a CA, such as the CA of Figure 1 A or IB, due to temperature, process and supply voltage variations shown in Figure 4.

In other words, Figure 5 shows with regard to Figure 3 the corresponding relationship between the temperature and total harmonic distortion (THD) of a cascode amplifier (CA) for different supply voltages and different values of the load resistor and optional degeneration resistor, in case the circuit of Figure 2B provides a bias voltage to the first transistor of one or more circuit branches of the CA. Figure 6 shows with regard to Figure 4 the corresponding relationship between the temperature and Total Harmonic Distortion (THD) of a cascode amplifier (CA) for different supply voltages and different values of the load resistor and optional degeneration resistor, in case the circuit of Figure 2C provides a bias voltage to the first transistor of one or more circuit branches of the CA.

The lines LI, L2, L3 and L4 of Figures 5 and 6 show the same cases as shown by the lines LI, L2, L3 and L4 of Figures 3 and 4. As can be seen from the dashed line LI of Figures 5 and 6, in case the supply voltage Vcc corresponds to the first supply voltage Vccl (Vcc = Vccl) and the resistance value R of the one or more circuit branches of the CA corresponds to the maximum resistance value Rmax (R = Rmax), the THD increases with increasing temperature at least up to 80°C and, thus, the linearity performance of the CA worsens with increasing temperature.

For providing the simulation result shown in Figures 3, 4, 5 and 6 a commercial, state-of-the- art BiCMOS technology CA may be employed. Further, a gain of around 12 dB may be assumed in the typical case (i.e. R = Rtyp), with a fixed differential output swing in case of a differential CA. The fixed differential output swing may be a differential output swing of e.g. 650 mVpp.

In view of the above-mentioned problems and disadvantages, it is an objective to provide a cascode amplifier (CA) with an improved linearity performance. The objective is achieved by the embodiments of the invention as described in the enclosed independent claims. Advantageous implementations of the embodiments of the invention are further defined in the dependent claims.

A first aspect of the present disclosure provides a cascode amplifier (CA) for amplifying an input voltage to an output voltage. The CA comprises one or more circuit branches, wherein each circuit branch comprises a load resistor, a first transistor and a second transistor that are electrically connected in series to each other. The load resistor is electrically connected between a supply terminal of the CA and a first terminal of the first transistor. A second terminal of the first transistor is electrically connected to a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to ground. A control terminal of the second transistor is electrically connected to an input terminal of the CA. The node between the load resistor and the first terminal of the first transistor is electrically connected to an output terminal of the CA. The CA further comprises a feedback circuit and a reference voltage generation circuit. The feedback circuit is configured to provide a bias voltage to a control terminal of each first transistor by comparing a cascode voltage sensed at the second terminal of each first transistor with a reference voltage. The reference voltage generation circuit comprises a voltage divider and is configured to generate for the feedback circuit the reference voltage using the voltage divider, such that the ratio between a transistor voltage of each first transistor and a transistor voltage of each second transistor is kept constant.

That is, the present disclosure proposes a CA with a closed loop biasing circuit which ensures that the ratio between the transistor voltages of the first transistor and the second transistor of each circuit branch of the one or more circuit branches of the CA is kept constant. In other words, the CA according to the first aspect is based on a closed loop biasing scheme. This design reduces total harmonic distortion (THD) variations over process, supply voltage variations, and temperature variations (PVT variations), and thus improves the CA’s linearity. The ratio between the transistor voltages of transistors may also be referred to as the transistor voltage ratio of the transistors.

The terms “feedback” and “closed loop” may be used as synonyms. Thus, the closed loop biasing circuit may be referred to as feedback biasing circuit and the feedback circuit may be referred to as closed loop circuit. The CA according to the first aspect may be referred to as “cascode amplifier with a closed loop biasing scheme” or “cascode amplifier with a feedback biasing scheme”.

The closed loop biasing circuit is implemented by the feedback circuit and the reference voltage generation circuit of the CA. That is, the closed loop biasing circuit comprises the feedback circuit and the reference voltage generation circuit.

The cascode voltage of a respective transistor of a circuit branch corresponds to the voltage drop between the second terminal of the respective transistor and ground, which may be sensed at the second terminal of the respective transistor. Thus, the cascode voltage of each first transistor corresponds to the voltage drop between the second terminal of the respective first transistor and ground, which may be sensed at the second terminal of the respective first transistor.

The transistor voltage of a respective transistor of a circuit branch corresponds to the voltage drop between the first and second terminal of the respective transistor. Thus, the transistor voltage of each first transistor corresponds to the voltage drop between the first and second terminal of the respective first transistor, and the transistor voltage of each second transistor corresponds to the voltage drop between the first and second terminal of the respective second transistor.

The terms “include” and “comprise” are used as synonyms.

A supply voltage may be supplied to the CA via the supply terminal of the CA.

In an implementation form of the first aspect, the second terminal of the first transistor of each circuit branch is directly electrically connected to the first terminal of the respective second transistor.

In an implementation form of the first aspect, each circuit branch further comprises one or more third transistors electrically connected in series between the second terminal of the respective first transistor and the first terminal of the respective second transistor, so that the second terminal of the respective first transistor is electrically connected via the one or more third transistors to the first terminal of the respective second transistor. A first terminal of each third transistor is electrically connected to a second terminal of a respective transistor of the respective circuit branch. A second terminal of each third transistor is electrically connected to a first terminal of a respective transistor of the respective circuit branch. The CA comprises, for each third transistor of one circuit branch, a further feedback circuit configured to provide a bias voltage to a control terminal of each respective third transistor of the one or more circuit branches by comparing a cascode voltage sensed at the second terminal of each respective third transistor with a respective reference voltage. The reference voltage generation circuit is configured to generate for each feedback circuit the respective reference voltage using the voltage divider, such that the ratio between the transistor voltage of each first transistor, the transistor voltage of each second transistor, and a transistor voltage of each third transistor is kept constant.

That is, the present disclosure may propose a CA with a closed loop biasing circuit which ensures that the ratio between the transistor voltages of the transistors of each circuit branch of the one or more circuit branches of the CA is kept constant. As a result, the linearity performance of the CA is improved by reducing total harmonic distortion (THD) variations over process, supply voltage and temperature variations (PVT variations).

The closed loop biasing circuit is implemented by the feedback circuits and the reference voltage generation circuit of the CA. That is, the closed loop biasing circuit comprises the feedback circuits and the reference voltage generation circuit.

In an implementation form of the first aspect, the voltage divider of the reference voltage generation circuit is electrically connected to the one or more circuit branches such that the voltage at the first terminal of each first transistor is provided to one end of the voltage divider, and the voltage at the second terminal of each second transistor is provided to the other end of the voltage divider.

That is, the voltage divider of the reference voltage generation circuit may be electrically connected to the one or more circuit branches such that the voltage sensed at the first terminal of each first transistor is provided to one end of the voltage divider, and the voltage sensed at the second terminal of each second transistor is provided to the other end of the voltage divider.

In an implementation form of the first aspect, the voltage divider comprises two or more resistors electrically connected in series to each other, wherein the number of resistors of the voltage divider corresponds to the number of transistors of each circuit branch of the CA. For each transistor of one circuit branch, which is supplied with a respective bias voltage by a respective feedback circuit, a terminal of the respective resistor of the voltage divider, wherein the terminal is electrically connected to another resistor of the voltage divider, provides the respective reference voltage to the respective feedback circuit.

Thus, the voltage divider may be implemented by cheap means, which reduces costs for implementing the closed loop biasing circuit of the CA.

The respective resistor of the voltage divider for a transistor being supplied with a respective bias voltage by a respective feedback circuit of one circuit branch is at the same position in the series connection of resistors of the voltage divider as the position of the transistor in the series connections of transistors of the one circuit branch. That is a transistor at a position in the series connection of transistors of a circuit branch and a resistor at the same position in the series connection of resistors of the voltage divider are respective components respectively corresponding components.

The terminal of the respective resistor providing the respective reference voltage to the respective feedback circuit may be the terminal of lower potential (lower potential terminal) of the two terminals of the respective resistor.

In an implementation form of the first aspect, one or more of the two or more resistors are variable resistors.

Thus, the ratio between the transistor voltages of the transistors of each circuit branch of the one or more circuit branches of the CA may be easily set by setting respectively adjusting the one or more variable resistors. That is, by setting respectively adjusting the variable resistance value of the one or more variable resistors. The term variable resistor corresponds to a resistor with a variable resistance value. The other resistors of the voltage divider are resistors with a fixed resistance value, in particular ohmic resistors with a fixed resistance value.

A variable resistor may comprise or correspond to one or more transistors, such as one or more field effect transistors (FET). In particular, the one or more transistors may be one or more metal oxide semiconductor field effect transistors (MOSFET).

In an implementation form of the first aspect, each resistor of the voltage divider is a variable resistor and, thus, the ratio between the resistors of the voltage divider is programmable respectively variable.

In an implementation form of the first aspect, the resistors of the voltage divider may have the same resistance value.

In an implementation form of the first aspect, the second terminal of the second transistor of each circuit branch may be directly electrically connected to ground. Alternatively, each circuit branch may further comprise a degeneration resistor that is electrically connected between the second terminal of the second transistor and ground.

In case, each circuit branch comprises a degeneration resistor, the CA may also be referred to as degenerated cascode amplifier (degenerated CA). The degeneration resistor further improves the linearity performance of the CA.

Additionally or alternatively, the second terminal of the one or more second transistors may be connected via a current source to ground.

In an implementation form of the first aspect, each transistor of the one or more circuit branches may comprises or correspond to a bipolar junction transistor (BJT) wherein the control terminal of the respective transistor is the base terminal of the BJT, the first terminal of the respective transistor is the collector terminal of the BJT and the second terminal of the respective terminal is the emitter terminal of the BJT. Alternatively, each transistor of the one or more circuit branches may comprise or correspond to a field effect transistor (FET), such as a metal oxide semiconductor FET (MOSFET) wherein the control terminal of the respective transistor is the gate terminal of the FET, the first terminal of the respective transistor is the drain terminal of the FET and the second terminal of the respective transistor is the source terminal of the FET. Alternatively, one or more transistors of the one or more circuit branches each comprise or correspond to a BJT and the other transistors of the one or more circuit branches each comprises or corresponds to a FET.

That is, the transistors of the one or more circuit branches may be of the same transistor type or the transistors of the one or more circuit branches may be of different transistor types.

According to an implementation form, the transistors of a circuit branch are of the same transistor type. For example, each transistor of a circuit branch comprises or corresponds to a BJT. Alternatively, each transistor of a circuit branch may comprise or correspond to a FET.

According to a further implementation form, the transistors of a circuit branch may be of different transistor types. In case, a circuit branch comprises two transistors, one transistor may be of one transistor type, such as a BJT or a FET, and the other transistor may be of another transistor type, such as a FET or a BJT, respectively. In case, a circuit branch comprises three or more transistors, one or more transistors may be of one transistor type, such as a BJT or a FET, and the other one or more transistors may be of another transistor type, such as a FET or a BJT, respectively.

In an implementation form of the first aspect, a topology of the CA is configured to be integrated on different IC technologies, such as BiCMOS technologies,

CMOS technologies, and/or

III-V compound technologies, e.g. InP technologies and/or GaAs technologies.

In an implementation form of the first aspect, the CA is a single ended amplifier comprising one circuit branch.

In an implementation form of the first aspect, the CA is a differential amplifier comprising two circuit branches, wherein the two circuit branches are electrically connected in parallel to each other. In an implementation form of the first aspect, each feedback circuit of the CA comprises an operational amplifier. The output terminal of the operational amplifier is electrically connected to the control terminal of the respective one or more transistors. The reference voltage for the respective one or more transistors is provided to the non-inverting input of the operational amplifier. The cascode voltage of the respective one or more transistors is provided to the inverting input of the operational amplifier. The operational amplifier is configured to provide via the output terminal the bias voltage to the control terminal of the respective one or more transistors.

That is, the output terminal of the operational amplifier of the feedback circuit for the one or more first transistors is electrically connected to the control terminal of the one or more first transistors. In case, each circuit branch comprises the one or more third transistors, the output terminal of the operational amplifier of each feedback circuit for the one or more third transistors of one circuit branch is electrically connected to the control terminal of the respective one or more third transistors.

Thus, for comparing the respective cascode voltage and the respective reference voltage each feedback circuit may comprise an operational amplifier. This is advantageous, because the bias voltage provided by a feedback circuit may be buffered by the respective operational amplifier. This may compensate a base current in case the transistor supplied with the bias voltage (i.e. either the first transistor or a third transistor) is a bipolar junction transistor.

The terms “inverting input terminal” and “inverting terminal” may be used as synonyms for the inverting input of an operational amplifier. The terms “non-inverting input terminal” and “non inverting terminal” may be used as synonyms for the non-inverting input of an operational amplifier.

In an implementation form of the first aspect, in case the CA is a single ended amplifier, one or more feedback circuits further comprise a sensing resistor that is electrically connected between the inverting input of the operational amplifier of the respective feedback circuit and the second terminal of the respective transistor of the one circuit branch for sensing the cascode voltage of the respective transistor. In an implementation form of the first aspect, in case the CA is a differential amplifier, each feedback circuit further comprises two sensing resistors, wherein one sensing resistor is electrically connected between the inverting input of the operational amplifier of the respective feedback circuit and the second terminal of the respective transistor of one circuit branch, and the other sensing resistor is electrically connected between the inverting input of the operational amplifier of the respective feedback circuit and the second terminal of the respective transistor of the other circuit branch.

In case the CA is a single ended amplifier and each feedback circuit of the CA comprises an operational amplifier, the inverting input of the operational amplifier of each feedback circuit may be directly connected to the second terminal of the respective transistor of the one circuit branch for sensing the cascode voltage of the respective transistor.

Alternatively, one or more feedback circuits may comprise a sensing resistor and the inverting input of the operational amplifier of each feedback circuit of the one or more feedback circuits is electrically connected via the respective sensing resistor to the second terminal of the respective transistor of the one circuit branch for sensing the cascode voltage of the respective transistor. The inverting input of the operational amplifier of each feedback circuit of the other feedback circuits is directly connected to the second terminal of the respective transistor of the one circuit branch for sensing the cascode voltage of the respective transistor.

Alternatively, each feedback circuit may comprise a sensing resistor that is electrically connected between the inverting input of the operational amplifier of the respective feedback circuit and the second terminal of the respective transistor of the one circuit branch for sensing the cascode voltage of the respective transistor.

In an implementation form of the first aspect, in case the CA is a single ended amplifier, the voltage divider of the reference voltage generation circuit is electrically connected to the circuit branch such that the first terminal of the first transistor is electrically connected via a buffer to one end of the voltage divider, and the second terminal of the second transistor is electrically connected via a further buffer to the other end of the voltage divider. In an implementation form of the first aspect, in case the CA is a differential amplifier, the voltage divider of the reference voltage generation circuit is electrically connected to the two circuit branches such that the first terminals of the first transistors are electrically connected via a buffer to one end of the voltage divider, wherein the first terminal of each first transistor is electrically connected via a sense resistor to the buffer, and the second terminals of the second transistors are electrically connected via a further buffer to the other end of the voltage divider, wherein the second terminal of each second transistor is electrically connected via a further sense resistor to the further buffer.

That is, in case the CA is a differential amplifier, the first terminal of each first transistor is electrically connected via the respective sense resistor to the input of the buffer and the output of the buffer is electrically connected to the one end of the voltage divider, and the second terminal of each second transistor is electrically connected via a further sense resistor to the input of the further buffer and the output of the further buffer is electrically connected to the other end of the voltage divider.

The buffer may comprise or correspond to an operational amplifier. In case the CA is a single ended amplifier, the first terminal of the first transistor is electrically connected to the non inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the one end of the voltage divider. In case the CA is a differential amplifier, the first terminal of each first transistor is electrically connected via the respective sense resistor to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the one end of the voltage divider.

Additionally or alternatively, the further buffer may comprise or correspond to an operational amplifier. In case the CA is a single ended amplifier, the second terminal of the second transistor is electrically connected to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the other end of the voltage divider. In case the CA is a differential amplifier, the second terminal of each second transistor is electrically connected via the respective further sense resistor to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the other end of the voltage divider.

The terms “unity gain buffer” and “unity gain amplifier” may be used as synonyms for the term “buffer”. In an implementation form of the first aspect, in case the CA is a single ended amplifier, the first terminal of the first transistor is electrically connected via a sense resistor to the input of the buffer and the output of the buffer is electrically connected to the one end of the voltage divider. Additionally or alternatively the second terminal of the second transistor is electrically connected via a further sense resistor to the input of the further buffer and the output of the further buffer is electrically connected to the other end of the voltage divider.

In case the CA is a single ended amplifier, the buffer may comprise or correspond to an operational amplifier, wherein the first terminal of the first transistor may be electrically connected via the sense resistor to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the one end of the voltage divider. Additionally or alternatively, in case the CA is a single ended amplifier, the further buffer may comprise or correspond to an operational amplifier, wherein the second terminal of the second transistor is electrically connected via the further sense resistor to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the other end of the voltage divider.

In order to achieve the CA according to the first aspect of the present disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

A second aspect of the present disclosure provides a cascode amplifier circuit (CAC). The CAC comprises a cascode amplifier (CA) according to the first aspect or any of its implementation forms, and a scaled replica of a circuit branch of the one or more circuit branches of the CA, wherein the control terminal of each scaled transistor except of the scaled second transistor of the scaled replica is supplied with a bias voltage maintaining the respective scaled transistor in the active region.

That is, the CAC comprises a scaled replica of the CA with a scaled replica of a circuit branch of the one or more circuit branches of the CA, but without the one or more feedback circuits and the reference voltage generation circuit of the CA. In case the CA is a differential amplifier, the scaled replica corresponds to a scaled replica of a circuit branch of the two circuit branches of the differential amplifier. In case the CA is a single ended amplifier, the scaled replica corresponds to a scaled replica of the circuit branch of the single ended amplifier.

The term “scaled replica circuit” may be used as a synonym for the term “scaled replica”.

The scaled replica may be a scaled down replica of the circuit branch or a scaled up replica of the circuit branch.

In an implementation form of the second aspect, one or more scaled transistors except of the scaled second transistor of the scaled replica are diode connected.

In an implementation form of the second aspect, each scaled transistor except of the scaled second transistor of the scaled replica is diode connected.

In case of a BJT, the term “diode connected” means that the base terminal and the collector terminal of the BJT are electrically connected with each other. In case of a MOSFET, the term “diode connected” means that the gate terminal and the drain terminal of the MOSFET are electrically connected with each other.

The reference voltage generation circuit of the CA is adapted to the scaled replica of the circuit branch. That is, the elements of the reference voltage generation circuit of the CA are adapted to the scaled elements of the scaled replica of the circuit branch.

In an implementation form of the second aspect, the voltage divider of the reference voltage generation circuit of the CA is electrically connected to the scaled replica of the circuit branch such that the voltage at the first terminal of the scaled first transistor of the scaled replica is provided to one end of the voltage divider, and the voltage at the second terminal of the scaled second transistor of the scaled replica is provided the other end of the voltage divider. That is, the voltage divider of the reference voltage generation circuit of the CA may be electrically connected to the scaled replica of the circuit branch such that the voltage sensed at the first terminal of the scaled first transistor of the scaled replica is provided to one end of the voltage divider, and the voltage sensed at the second terminal of the scaled second transistor of the scaled replica is provided the other end of the voltage divider.

In an implementation form of the second aspect, the voltage divider of the reference voltage generation circuit of the CA is electrically connected to the scaled replica of the circuit branch such that the first terminal of the scaled first transistor of the scaled replica is electrically connected via a buffer to one end of the voltage divider, and the second terminal of the scaled second transistor of the scaled replica is electrically connected via a further buffer to the other end of the voltage divider.

The buffer may comprise or correspond to an operational amplifier, wherein the first terminal of the scaled first transistor is electrically connected to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the one end of the voltage divider. Additionally or alternatively, the further buffer may comprise or correspond to an operational amplifier, wherein the second terminal of the scaled second transistor is electrically connected to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the other end of the voltage divider.

In an implementation form of the second aspect, the first terminal of the scaled first transistor of the scaled replica is electrically connected via a sense resistor to the input of the buffer and the output of the buffer is electrically connected to the one end of the voltage divider. Additionally or alternatively, the second terminal of the scaled second transistor of the scaled replica is electrically connected via a further sense resistor to the input of the further buffer and the output of the further buffer is electrically connected to the other end of the voltage divider.

The buffer may comprise or correspond to an operational amplifier, wherein the first terminal of the scaled first transistor is electrically connected via the sense resistor to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the one end of the voltage divider. Additionally or alternatively, the further buffer may comprise or correspond to an operational amplifier, wherein the second terminal of the scaled second transistor is electrically connected via the further sense resistor to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier is electrically connected to the inverting input of the operational amplifier and to the other end of the voltage divider.

The CAC of the second aspect and its implementation forms and optional features achieve the same advantages as the CA of the first aspect and its respective implementation forms and respective optional features.

In order to achieve the CAC according to the second aspect of the present disclosure, some or all of the implementation forms and optional features of the second aspect, as described above, may be combined with each other.

A third aspect of the present disclosure provides an amplifier circuit. The amplifier circuit comprises one or more cascode amplifiers (CAs) according to the first aspect or any of its implementation forms, and/or one or more cascode amplifier circuits (CACs) according to the second aspect or any of its implementation forms as one or more amplifier stages forming an amplifier chain to amplify an input voltage of the amplifier circuit to an output voltage of the amplifier circuit.

The amplifier circuit of the third aspect and its implementation forms and optional features achieve the same advantages as the CA of the first aspect and its respective implementation forms and respective optional features and/or as the CAC of the second aspect and its respective implementation forms and respective optional features.

It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which

Figures 1 A and IB each show an example of a cascode amplifier (CA).

Figures 2A, 2B and 2C each show an example of a circuit for generating a bias voltage for a cascode amplifier (CA).

Figure 3 shows the relationship between temperature and the ratio of the transistor voltage Vcel of the first transistor of one or more circuit branches of a cascode amplifier (CA), such as the CA of Figure 1A or IB, and the transistor voltage Vce2 of the second transistor of the one or more circuit branches of the CA for different supply voltages and different values of the load resistor and optional degeneration resistor of the one or more circuit branches of the CA, in case the circuit of Figure 2B provides a bias voltage to the first transistor.

Figure 4 shows the relationship between temperature and the ratio of the transistor voltage Vcel of the first transistor of one or more circuit branches of a cascode amplifier (CA), such as the CA of Figure 1A or IB, and the transistor voltage Vce2 of the second transistor of the one or more circuit branches of the CA for different supply voltages and different values of the load resistor and optional degeneration resistor of the one or more circuit branches of the CA, in case the circuit of Figure 2C provides a bias voltage to the first transistor. Figure 5 shows with regard to Figure 3 the corresponding relationship between the temperature and total harmonic distortion (THD) of a cascode amplifier (CA) for different supply voltages and different values of the load resistor and optional degeneration resistor, in case the circuit of Figure 2B provides a bias voltage to the first transistor of one or more circuit branches of the CA.

Figure 6 shows with regard to Figure 4 the corresponding relationship between the temperature and Total Harmonic Distortion (THD) of a cascode amplifier (CA) for different supply voltages and different values of the load resistor and optional degeneration resistor, in case the circuit of Figure 2C provides a bias voltage to the first transistor of one or more circuit branches of the CA.

Figure 7 shows a cascode amplifier (CA) according to an embodiment of the invention. Figure 8 shows a cascode amplifier (CA) according to an embodiment of the invention. Figure 9 shows a cascode amplifier (CA) according to an embodiment of the invention. Figure 10 shows a cascode amplifier circuit (CAC) according to an embodiment of the invention.

Figure 11 shows the relationship between the temperature and the ratio of the transistor voltage Vce2 of the second transistor of one or more circuit branches of a cascode amplifier (CA) according to the first aspect or any of its implementation forms and the transistor voltage Vcel of the first transistor of the one or more circuit branches of the CA for different supply voltages and different values of the load resistor and optional degeneration resistor.

Figure 12 shows with regard to Figure 11 the corresponding relationship between the temperature and Total Harmonic Distortion (THD) of a cascode amplifier (CA) according to the first aspect or any of its implementation forms for different supply voltages and different values of the load resistor and optional degeneration resistor. Figure 13 shows an amplifier circuit according to an embodiment of the invention. Corresponding elements in the Figures are marked by the same reference sign.

DETAILED DESCRIPTION OF EMBODIMENTS

Figure 7 shows a cascode amplifier (CA) according to an embodiment of the invention.

Thus, Figure 7 shows an implementation form of the CA according to the first aspect. The above description of the CA according to the first aspect or any of its implementation forms is correspondingly valid for the CA 1 of Figure 7.

The CA 1 of Figure 7 is a single ended amplifier comprising one circuit branch CB1.

The circuit branch CB1 comprises a load resistor RL, a first transistor Ql, a second transistor Q2 and an optional degeneration resistor Rdeg that are connected in series to each other.

The series connection of the load resistor RL, first transistor Ql, second transistor Q2 and the optional degeneration resistor Rdeg is connected between a supply terminal of the CA 1 (for providing a supply voltage Vcc to the CA 1) and ground (GND). Ground is a reference potential of the circuit and optionally may correspond to the earth potential.

As apparent from Figure 7, the first transistor Ql and the second transistor Q2 are each a bipolar junction transistor (BJT). This is only by way of example for describing the embodiment of Figure 7 and does not limit the present disclosure. As outlined already above, the first transistor Ql and/or the second transistor Q2 may be of a different transistor type, such as a field effect transistor (FET), e.g. a metal oxide semiconductor field effect transistor (MOSFET). In other words, the first transistor Ql and second transistor Q2 may be of the same transistor type (e.g. each being a bipolar junction transistor as shown in Figure 7) or the first transistor Ql and second transistor Q2 may be of a different transistor type.

The load resistor RL is electrically connected between the supply terminal of the CA 1 and the collector terminal (first terminal) of the first transistor Ql. The emitter terminal (second terminal) of the first transistor Q1 is electrically connected to the collector terminal (first terminal) of the second transistor Q2.

The emitter terminal (second terminal) of the second transistor Q2 is electrically connected to the optional degeneration resistor Rdeg, wherein the optional degeneration resistor Rdeg is connected between the emitter terminal of the second transistor Q2 and ground. In case the optional degeneration resistor Rdeg is omitted, the emitter terminal of the second transistor Q2 is connected to ground.

The base terminal (control terminal) of the second transistor Q2 is connected to an input terminal of the CA. The node between the load resistor RL and the collector terminal of the first transistor Q1 is connected to an output terminal of the CA. An input voltage (input signal) Vin may be supplied via the input terminal to the base terminal of the second transistor Q2. The input voltage Vin may be amplified by the CA and, thus, an output voltage (output signal) Vout corresponding to the amplified input voltage Vin may be provided at the node between the load resistor RL and the collector terminal of the first transistor Ql. The output voltage Vout corresponds to the collector voltage (voltage at the first terminal) of the first transistor Ql.

As shown in Figure 7, the CA 1 further comprises a feedback circuit 2 and a reference voltage generation circuit 3.

The feedback circuit 2 is configured to provide a bias voltage Vbias to the base terminal (control terminal) of the first transistor Ql by comparing a cascode voltage Vcasc sensed at the emitter terminal of the first transistor Ql with a reference voltage Vref. The reference voltage generation circuit 3 comprises a voltage divider and is configured to generate for the feedback circuit 2 the reference voltage Vref using the voltage divider, such that the ratio between the collector emitter voltage (transistor voltage) Vcel of the first transistor Ql and the collector emitter voltage (transistor voltage) Vce2 of the second transistor Q2 is kept constant.

As shown in Figure 7, the feedback circuit 2 may comprises an operational amplifier 2a for comparing the cascode voltage Vcasc sensed at the emitter terminal of the first transistor Ql and the reference voltage Vref with each other. The feedback circuit 2 may comprise an optional sense resistor Rs for sensing the cascode voltage Vcasc. As shown in Figure 7, the output terminal of the operational amplifier 2a of the feedback circuit 2 is connected to the base terminal (control terminal) of the first transistor Q1 for providing the bias voltage Vbias to the base terminal of the first transistor Ql. The reference voltage Vref is provided to the non inverting input of the operational amplifier 2a and the cascode voltage Vcasc is provided to the inverting input of the operational amplifier 2a. The optional sense resistor Rs may be connected between the inverting input of the operational amplifier 2a and the emitter terminal of the first transistor Ql.

As shown in Figure 7, the voltage divider of the reference voltage generation circuit 3 comprises two resistors R1 and R2, because the circuit branch CB1 comprises two transistors, namely the first transistor Ql and the second transistor Q2. The number of resistors of the voltage divider corresponds to the number of transistors of the circuit branch CB1. Therefore, the number of resistors of the voltage divider of the reference voltage generation circuit 3 is only by way of example for describing the embodiment of Figure 7 and is does not limit the present disclosure. According to Figure 7, the two resistors R1 and R2 of the voltage divider are variable resistors. Alternatively, one or more of the resistors of the voltage divider may be a resistor with a fixed resistance value (not shown in Figure 7).

At the node between the two resistors R1 and R2 of the voltage divider the reference voltage Vref is provided for the feedback circuit 2. The node between the two resistors R1 and R2 of the voltage divider may be connected to the non-inverting input of the operational amplifier 2a of the feedback circuit 2. According to Figure 7, the resistor R1 at the top of the series connection of resistors of the voltage divider of the reference voltage generation circuit 3 corresponds to the first transistor Ql at the top of the series connection of transistors of the circuit branch CB1. The resistor R2 at the bottom of the series connection of resistors of the voltage divider of the reference voltage generation circuit 3 corresponds to the second transistor Q2 at the bottom of the series connection of transistors of the circuit branch CB1. Therefore, for the first transistor Ql, which is supplied with the bias voltage Vbias by the respective/corresponding feedback circuit 2, a terminal of the respective/corresponding resistor R1 of the voltage divider of the reference voltage generation circuit 3, wherein the terminal is electrically connected to another resistor of the voltage divider (in the case of Figure 7 to the resistor R2), provides the respective/corresponding reference voltage Vref to the respective/corresponding feedback circuit 2. The voltage divider of the reference voltage generation circuit 3 is connected to the circuit branch CB1 such that the voltage Vout at the collector terminal (first terminal) of the first transistor Q1 is provided to one end of the voltage divider and the voltage Ve at the emitter terminal (second terminal) of the second transistor Q2 is provided to the other end of the voltage divider.

As shown in Figure 7, optionally, the voltage divider is connected to the circuit branch CB1 such that the collector terminal (first terminal) of the first transistor Q1 is connected via an optional buffer 3a to one end of the voltage divider (according to Figure 7 to the end at which the resistor R1 is arranged) and that the emitter terminal (second terminal) of the second transistor Q2 is connected via an optional further buffer 3b to the other end of the voltage divider (according to Figure 7 to the end at which the resistor R2 is arranged).

According to Figure 7, the optional buffer 3a of the reference voltage generation circuit 3 may comprise or correspond to an operational amplifier. In this case, the collector terminal of the first transistor Q1 may be directly connected (not shown in Figure 7) or connected via an optional sense resistor Rs (shown in Figure 7) to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier may be connected to the one end of the voltage divider (according to Figure 7 to the end at which the resistor R1 is arranged) and to the inverting input of the operational amplifier. In addition or alternatively, the optional further buffer 3b of the reference voltage generation circuit 3 may comprise or correspond to an operational amplifier. In this case, the emitter terminal of the second transistor Q2 may be directly connected (not shown in Figure 7) or connected via an optional sense resistor Rs (shown in Figure 7) to the non-inverting input of the operational amplifier and the output terminal of the operational amplifier may be connected to the other end of the voltage divider (according to Figure 7 to the end at which the resistor R2 is arranged) and to the inverting input of the operational amplifier.

According to the present disclosure, the output voltage Vout provided at the collector terminal (first terminal) of the first transistor Q1 and the emitter voltage Ve, i.e. the voltage at the emitter terminal (second terminal), of the second transistor Q2 are sensed by the reference voltage generation circuit in order to determine the total available voltage headroom Vh for the transistors Q1 and Q2 of the circuit branch CB1. In particular, as shown in Figure 7, the output voltage Vout and the emitter voltage Ve each may be sensed by a respective sense resistor Rs. It is assumed that the input voltage Vin is fixed (either from the previous amplifier stage of an amplifier chain comprising two or more amplifier stages in the case of DC coupling or by a biasing circuit in the case of AC coupling). Therefore, the bias voltage Vbias provided to the base terminal (control terminal) of the first transistor Q1 may be adjusted in order to maximize the voltage headroom Vh for the transistors Q1 and Q2 of the circuit branch CB1, in particular for the collector emitter voltage (transistor voltage) Vcel of the first transistor Q1 and the collector emitter voltage (transistor voltage) Vce2 of the second transistor Q2, and thus ensure proper operation for the transistors of the circuit branch CB1.

Therefore, starting from the voltage headroom Vh (which always equals to the sum of the transistor voltages (in case of Figure 7 collector emitter voltages) of the transistors of the circuit branch CB1) it is possible to generate, by the reference voltage generation circuit 3, the reference voltage Vref for the feedback circuit 2 of the first transistor Q1 using the voltage divider so that the reference voltage Vref equals to the sum of the emitter voltage Ve at the emitter terminal of the second transistor Q2 and the product of the voltage headroom Vh with a factor a, wherein a is smaller than 1 :

Vref = Ve + (ax Vh) with a < 1.

By comparing the cascode voltage Vcasc sensed at the emitter terminal (second terminal) of the first transistor Q1 with the reference voltage Vref (provided by the reference voltage generation circuit 3 to the feedback circuit 2) and by providing the bias voltage Vbias based on that comparison result to the base terminal (control terminal) of the first transistor Q1 using the feedback circuit 2, it is possible to make the cascode voltage Vcasc equal to Vref, thus ensuring a constant ratio between the collector emitter voltage (transistor voltage) Vce2 of the second transistor Q2 and the collector emitter voltage (transistor voltage) Vcel of the first transistor Ql. In particular, as shown in Figure 7, the operational amplifier 2a of the feedback circuit is used for comparing the cascode voltage Vcasc of the first transistor Ql with the reference voltage Vref.

Therefore, by using a closed loop biasing circuit (i.e. the feedback circuit 2 and the reference voltage generation circuit 3) it is possible to make the cascode voltage Vcasc of the first transistor Ql equal to the reference voltage Vref, thus ensuring a constant ratio between the collector emitter voltage (transistor voltage) Vce2 of the second transistor Q2 and the collector emitter voltage (transistor voltage) Vcel of the first transistor Ql.

This also ensures that a constant ratio between the base collector junctions of the first transistor Ql and the second transistor Q2 respectively that a constant ratio between the base collector voltage Vbcl of the first transistor Ql and the base collector voltage Vbc2 of the second transistor Q2 is maintained. In case the transistors of the circuit branch CB1 are bipolar junction transistors (as it is the case in Figure 7), this also prevents the base collector junctions of the transistors of the circuit branch CB1 (first transistor Ql and second transistor Q2) forward biasing as much as possible for a given voltage headroom Vh.

In the light of the above, the emitter voltage Ve of the second transistor Q2 and the collector voltage Vout of the first transistor Ql may be sensed by means of two optional sense resistors Rs. The emitter voltage Ve of the second transistor Q2 and the collector voltage Vout of the first transistor Ql may be buffered by optional buffers 3a, 3b or may not be buffered and may be used as references for the voltage divider of the reference voltage generation circuit 3. The ratio of the resistance values of the resistors (i.e. the ratio of the resistors) of the voltage divider may be made programmable by making one or more resistors of the resistors of the voltage divider to variable resistors. The ratio of the resistance values of the resistors of the voltage divider selects respectively sets the reference voltage Vref, which is used to control the ratio between the collector emitter voltage Vcel of the first transistor Ql and the collector emitter voltage Vce2 of the second transistor Q2 (i.e. the collector emitter voltage ratio of the transistors of the circuit branch CB1). The optional operational amplifier 2a of the feedback circuit 2 may be used to ensure that the cascode voltage Vcasc, sensed at the emitter terminal of the first transistor Ql, equals to the reference voltage Vref.

The closed loop biasing circuit of the CA 1 implemented by the feedback circuit 2 and the reference voltage generation circuit 3 ensures that the ratio between the transistor voltages of the transistors of the circuit branch CB1 is kept constant. In the case of Figure 7, the closed loop biasing circuit of the CA 1 ensures that the ratio between the collector emitter voltage Vcel of the first transistor Ql and the collector emitter voltage Vce2 of the second transistor Q2 is kept constant. In particular, this is achieved by the voltage divider of the reference voltage generation circuit 3. Namely, the ratio between the transistor voltages of the transistors of the circuit branch CB1 may be set by the ratio between the resistance values of the resistors of the voltage divider. Thus, the reference voltage generation circuit 3 is configured to generate for the feedback circuit 2 the reference voltage Vref using the voltage divider, such that the ratio between the transistor voltages of the transistors of the circuit branch CB1 is kept constant.

Figure 8 shows a cascode amplifier (CA) according to an embodiment of the invention.

Thus, Figure 8 shows an implementation form of the CA according to the first aspect.

The above description of the CA according to the first aspect or any of its implementation forms is correspondingly valid for the CA 1 of Figure 8.

The CA 1 according to Figure 8 differs from the CA according to Figure 7 in that the CA 1 of Figure 8 is a differential amplifier, whereas the CA of Figure 7 is a single ended amplifier. Thus, the closed loop biasing topology of a CA proposed by the present disclosure is suitable for both single-ended (Figure 7) and differential (Figure 8) configurations. The CA 1 of Figure 8 comprises two circuit branches CB1 and CB2 that are connected in parallel to each other, wherein each circuit branch of the two circuit branches CB1 and CB2 corresponds to the single circuit branch CB1 of the single ended CA of Figure 7. In the following mainly the differences between the CA of Figure 7 and CA of Figure 8 are described. The above description of the CA of Figure 7 is correspondingly valid for the CA of Figure 8.

For describing each circuit branch of the two circuit branches CB1 and CB2 of the CA 1 of Figure 8 reference is made to the above description of the single circuit branch CB1 of the CA of Figure 7.

As shown in Figure 8, each first transistor of the two first transistors Q1 of the two circuit branches CB1 and CB2 is provided with the bias voltage Vbias by the feedback circuit 2. That is, the feedback circuit 2 is configured to provide the bias voltage Vbias to the base terminal (control terminal) of each first terminal Q1 by comparing the cascode voltage Vcasc sensed at the emitter terminal (second terminal) of each first transistor Q1 with the reference voltage Vref provided by the reference voltage generation circuit 3.

For describing the feedback circuit 2 and the reference voltage generation circuit 3 of the CA 1 of Figure 8 reference is made to the above description of the feedback circuit 2 and the reference voltage generation circuit 3 of the CA 1 of Figure 7. As shown in Figure 8, the emitter terminal of the second transistor Q2 of each circuit branch CB1, CB2 is connected via a sense resistor Rs to the reference voltage generation circuit 3, in particular to the non-inverting input of the optional operational amplifier of the optional further buffer 3b. Therefore, the emitter voltage Ve, i.e. the voltage at the emitter terminal, of each second transistor Q2 may be sensed by a respective sense resistor Rs. Further, as shown in Figure 8, the collector terminal of the first transistor Q1 of each circuit branch CB1, CB2 is connected via a sense resistor Rs to the reference voltage generation circuit 3, in particular to the non-inverting input of the optional operational amplifier of the optional buffer 3a. Therefore, the collector voltage of each first transistor Q1 may be sensed by a respective sense resistor Rs.

Thus, the voltage divider of the reference voltage generation circuit 3 may be connected to the two circuit branches CB1 and CB2 such that the collector terminals of the first transistors Q1 are connected via the optional buffer 3 a to the one end of the voltage divider, wherein the collector terminal of each first transistor Q1 is connected via a sense resistor to the optional buffer 3 a and that the emitter terminals of the second transistors Q2 are connected via the further optional buffer 3b to the other end of the voltage divider, wherein the emitter terminal of each second transistor Q2 is connected via a further sense resistor Rs to the further optional buffer 3b.

Furthermore, as shown in Figure 8, the feedback circuit 2 comprises two sensing resistors Rs for sensing the cascode voltage Vcasc at the emitter terminal of each first transistor Ql. One sensing resistor Rs of the two sensing resistors Rs of the feedback circuit 2 is connected between the emitter terminal of the first transistor Ql of one circuit branch CB1 and the feedback circuit 2, in particular the inverting input of the optional operational amplifier 2a of the feedback circuit 2. The other sensing resistor Rs of the feedback circuit 2 is connected between the emitter terminal of the first transistor Ql of the other circuit branch CB2 and the feedback circuit 2, in particular the inverting input of the optional operational amplifier 2a of the feedback circuit 2.

As indicated in Figure 8, an optional current source for providing a bias current may be connected between ground and the node at which the two optional degeneration resistors Rdeg of the two circuit branches CB1 and CB2 are connected. In case one or both degeneration resistors Rdeg is omitted, the optional current source may be connected between ground and the emitter terminal of one or both second transistors Q2.

Figure 9 shows a cascode amplifier (CA) according to an embodiment of the invention.

Thus, Figure 9 shows an implementation form of the CA according to the first aspect. The above description of the CA according to the first aspect or any of its implementation forms is correspondingly valid for the CA 1 of Figure 9.

The CA 1 according to Figure 9 differs from the CA according to Figure 7 in that the circuit branch CB1 of the CA 1 of Figure 9 comprises more than two transistors, whereas the circuit branch CB1 of the CA 1 of Figure 7 comprise two transistors, namely the first transistor Q1 and the second transistor Q2. The CA 1 of Figure 9 comprises besides the first transistor Q1 and the second transistor Q2 one or more third transistors Q3_n. In the following mainly the differences between the CA of Figure 7 and CA of Figure 9 are described. The above description of the CA of Figure 7 is correspondingly valid for the CA of Figure 9.

For describing the load resistor RL, the first transistor Ql, the second transistor Q2 and the optional degeneration resistor Rdeg of the CA 1 of Figure 9 reference is made to the above description of the corresponding elements of the CA of Figure 7.

As shown in Figure 9 the circuit branch CB1 comprises N third transistors Q3_n (n = 1, 2, ... , N- 1, N), wherein N is greater or equal to 1. That is, the circuit branch CB1 comprises one or more third transistors Q3_n. The one or more third transistors Q3_n are bipolar junction transistors according to Figure 9. This is only by way of example for describing the embodiment of Figure 9 and does not limit the present disclosure. As outlined already above, the transistors of the circuit branch CB1 may be of a different transistor type, such as a field effect transistor (FET), e.g. a metal oxide semiconductor field effect transistor (MOSFET). In other words, the transistors of the circuit branch CB1 may be of the same transistor type (e.g. each being a bipolar junction transistor as shown in Figure 9) or of a different transistor type. The transistors of the circuit branch CB1 correspond to the first transistor Ql, the second transistor Q2 and the one or more third transistors Q3_n. The one or more third transistors Q3_n are connected in series between the emitter terminal (second terminal) of the first transistor Q1 and the collector terminal (first terminal) of the second transistor Q2, so that the emitter terminal of the first transistor Q1 is electrically connected via the one or more third transistors Q3_n to the collector terminal of the second transistor Q2. The collector terminal (first terminal) of each third transistor is electrically connected to the emitter terminal (second terminal) of a respective transistor (the first transistor Q1 or a further third transistor), and the emitter terminal (second terminal) of each third transistor is connected to the collector terminal (first terminal) of a respective transistor (second transistor Q2 or a further third transistor).

For example, in case the CA 1 of Figure 9 comprises only one third transistor Q3_n, then the collector terminal of the one third transistor is connected to the emitter terminal of the first transistor Q1 and the emitter terminal of the one third transistor is connected to the collector terminal of the second transistor Q2. In case the CA 1 of Figure 9 comprises more than one third transistor, the third transistor Q3_n shown in Figure 9 is connected such, that the collector terminal of the third transistor Q3_n is connected to the emitter terminal of a further third transistor (not shown in Figure 9) and the emitter terminal of the third transistor Q3_n is connected to the collector terminal of the second transistor Q2.

As indicated in Figure 9, the CA 1 comprises for each third transistor Q3_n of the circuit branch CB1 a further feedback circuit 2_n configured to provide a bias voltage Vbiasn to the base terminal (control terminal) of the respective third transistor Q3_n of the circuit branch CB1 by comparing a cascode voltage Vcascn sensed at the emitter terminal of the respective third transistor Q3_n with a respective reference voltage Vrefn.

For describing each further feedback circuit 2_n reference is made to the above description of the feedback circuit 2 of the CA of Figure 7.

The reference voltage generation circuit 3 is configured to generate for each feedback circuit, i.e for the feedback circuit 2 of the first transistor Q1 and the one or more further feedback circuits 2_n of the one or more third transistors Q3_n, the respective reference voltage, e.g. the reference voltage Vref for the feedback circuit 2, using the voltage divider, such that the ratio between the collector emitter voltage (transistor voltage) Vcel of the first transistor Ql, collector emitter voltage (transistor voltage) Vce2 of the second transistor Q2, and the collector emitter voltage (transistor voltage) Vce3_n of each third transistor Q3_n is kept constant. In other words, the reference voltage generation circuit 3 is configured to generate for each feedback circuit 2, 2_n the respective reference voltage Vref, Vrefn using the voltage divider, such that the ratio between the collector emitter voltages (transistor voltages) of the transistors of the circuit branch CB1 is kept constant.

For describing the reference voltage generation circuit 3 of the CA 1 of Figure 9 reference is made to the above description of the reference voltage generation circuit 3 of the CA of Figure 7.

The ratio of the resistance values of the resistors of the voltage divider of the reference voltage generation circuit 3 selects respectively sets the reference voltages (e.g. Vref and Vrefn) for the two or more feedback circuits (i.e. the feedback circuit 2 for the first transistor Q1 and the one or more further feedback circuits 2n for the one or more third transistors Q3n), which are used to control the ratio between the collector emitter voltages (transistor voltages) of the transistors of the circuit branch CB1 (i.e. the collector emitter voltage ratio (transistor voltage ratio) of the transistors of the circuit branch CB1). The optional operational amplifier 2a of each feedback circuit 2, 2_n may be used to ensure that the respective cascode voltage Vcasc, Vcascn, sensed at the emitter terminal of the first transistor Q1 or at the emitter terminal of the respective third transistor Q3_n, equals to the respective reference voltage Vref, Vrefn.

The closed loop biasing circuit of the CA 1 of Figure 9 implemented by the feedback circuits 2, 2_n and the reference voltage generation circuit 3 ensures that the ratio between the transistor voltages of the transistors of the circuit branch CB1 is kept constant. In particular, this is achieved by the voltage divider of the reference voltage generation circuit 3. Namely, the ratio between the transistor voltages of the transistors of the circuit branch CB1 may be set by the ratio between the resistance values of the resistors of the voltage divider. Thus, the reference voltage generation circuit 3 is configured to generate for each feedback circuit 2, 2_n the respective reference voltage Vref, Vrefn using the voltage divider, such that the ratio between the transistor voltages of the transistors of the circuit branch CB1 is kept constant.

The single ended CA 1 shown in Figure 9 may also be implemented as a differential amplifier (not shown in Figure 9). In such a case, the CA comprises two circuit branches that are connected in parallel to each other, wherein each circuit branch corresponds to the circuit branch CB1 shown in Figure 9. The number of feedback circuits 2, 2_n is the same as described above with respect to the single ended CA 1 shown in Figure 9. For the description of the two circuit branches reference is made to the above description of the single circuit branch CB1 of the CA 1 shown in Figure 9. In addition, in case the CA shown in Figure 9 is implemented as a differential amplifier, for the description of the two circuit branches, the feedback circuits 2, 2_n and the reference voltage generation circuit 3 reference is made to the description of the differential CA of Figure 8.

Figure 10 shows a cascode amplifier circuit (CAC) according to an embodiment of the invention.

Thus, Figure 10 shows an implementation form of the CAC according to the second aspect. The above description of the CAC according to the second aspect or any of its implementation forms is correspondingly valid for the CAC 4 of Figure 10.

As shown in Figure 10, the CAC 4 comprises a cascode amplifier (CA) 1, which corresponds to the cascode amplifier of Figure 7. Therefore, for describing the CA 1 of the CAC 4 reference is made to the above description of the CA of Figure 7 and only differences with respect to the CA of Figure 7 are described below. The CAC 4 further comprises a scaled replica 5 of the circuit branch CB1 of the CA 1. That is, the CAC 4 further comprises a scaled replica of the CA 1 with a scaled replica of the circuit branch CB1, but without the feedback circuit 2 and the reference voltage generation circuit 3. The scaled replica 5 of the circuit branch CB1 differs from the circuit branch CB1 of the CA 1 in that the elements of the scaled replica 5 of the circuit branch CB1 are scaled up or scaled down with respect to the corresponding elements of the circuit branch CB 1 of the C A 1.

The CA 1 of the CAC 4 shown in Figure 10 is only by way of example and does not limit the present disclosure. The CA 1 of the CAC 4 may be any other implementation form of the CA according to the first aspect, wherein the scaled replica 5 is a scaled replica of one circuit branch of the one or more circuit branches of the respective implementation form of the CA. For example, the CA 1 of the CAC 4 may alternatively correspond to the CA according to Figure 8. In such a case, the CAC 4 comprises a scaled replica 5 of one circuit branch of the two circuit branches CB1 and CB2 of the CA of Figure 8. Alternatively, the CA 1 of the CAC 4 may correspond to the CA according to Figure 9. In such a case, the CAC 4 comprises a scaled replica 5 of the circuit branch CB1 of the CA of Figure 9.

The base terminal (control terminal) of each scaled transistor except of the scaled second transistor Q2/N of the scaled replica 5 is supplied with a bias voltage maintaining the respective scaled transistor in the active region. That is, according to Figure 10, the scaled first transistor Ql/N of the scaled replica 5 is supplied with a bias voltage Vbias,r maintaining the scaled first transistor Ql/N in the active region. The scaled replica 5 may be a scaled down replica of the circuit branch CB1 or a scaled up replica of the circuit branch CB1.

The connection of the reference voltage generation circuit 3 of the CA 1 of the CAC 4 of Figure 10 differs from the connection of the corresponding reference voltage generation circuit 3 of the CA 1 of Figure 7. Namely, according to Figure 10, the voltage divider of the reference voltage generation circuit 3 of the CA 1 is electrically connected to the scaled replica 5 of the circuit branch CB1 such that the collector terminal (first terminal) of the scaled first transistor Ql/N of the scaled replica 5 is electrically connected via the optional buffer 3a to the one end of the voltage divider (the end at which the resistor R1 is arranged), and the emitter terminal (second terminal) of the scaled second transistor Q2/N of the scaled replica 5 is electrically connected via the optional further buffer 3b to the other end of the voltage divider (the end at which the resistor R2 is arranged).

The elements of the reference voltage generation circuit 3 of the CA 1 are adapted to the scaled elements of the scaled replica 5 of the circuit branch CB1.

As shown in Figure 10, the collector terminal of the scaled first transistor Ql/N of the scaled replica 5 may be connected via a sense resistor Rs to the input of the optional buffer 3 a and the output of the buffer 3a is electrically connected to the one end of the voltage divider. Further, the emitter terminal of the scaled second transistor Q2/N of the scaled replica 5 may be electrically connected via a further sense resistor Rs to the input of the optional further buffer 3b and the output of the further buffer 3b is electrically connected to the other end of the voltage divider.

Furthermore, as shown in Figure 10, the input voltage Vin is provided to the base terminal (control terminal) of the second transistor Q2 of the CA 1 and to the base terminal (control terminal) of the scaled second transistor Q2/N of the scaled replica 5. The input voltage Vin may be provided to the scaled second transistor Q2/N via an optional sense resistor Rs and an optional buffer 6 comprising an operational amplifier, as shown in Figure 10. According to Figure 10, the output of the operational amplifier of the optional buffer 6 is connected to the base terminal of the scaled second transistor Q2/N and to its inverting input. The input voltage Vin may be provided via the optional sense resistor Rs to the non-inverting input of the operational amplifier of the optional buffer 6.

The main difference between the reference voltage generation circuit 3 of the CA 1 of Figure 7 and the reference voltage generation circuit 3 of the CA 1 of the CAC 4 of Figure 10 is that instead of sensing the emitter voltage Ve of the second transistor Q2 and the collector voltage Vout of the first transistor Q1 of the CA 1 of the CAC 4, the emitter voltage Ve,r of the scaled second transistor Q2/N of the scaled replica 5 and the collector voltage Vout,r of the scaled first transistor Ql/N of the scaled replica 5 are sensed for generating the reference voltage Vref provided to the feedback circuit 2 of the CA 1 of the CAC 4.

In order to ensure proper operation of the replica circuit 5, the amplifier DC input voltage Vin may be sensed through the optional sense resistor Rs and provided via the optional buffer 6 to the base terminal of the scaled second transistor Q2/N.

Figure 11 shows the relationship between the temperature and the ratio of the transistor voltage Vce2 of the second transistor of one or more circuit branches of a cascode amplifier (CA) according to the first aspect or any of its implementation forms and the transistor voltage Vcel of the first transistor of the one or more circuit branches of the CA for different supply voltages and different values of the load resistor and optional degeneration resistor. Figure 12 shows with regard to Figure 11 the corresponding relationship between the temperature and Total Harmonic Distortion (THD) of a cascode amplifier (CA) according to the first aspect or any of its implementation forms for different supply voltages and different values of the load resistor and optional degeneration resistor.

The lines LI, L2, L3 and L4 of Figures 11 and 12 show the same cases as shown by the lines LI, L2, L3 and L4 of Figures 3 to 6. As can be seen from the lines LI, L2, L3 and L4 of Figure 11 the ratio between the transistor voltages of the first and second transistor Ql, Q2 (Vce2/V cel) of an CA according to the present disclosure, such as the CA 1 of Figure 7, is kept constant (if anything negligible changes) regardless of temperature, process and supply voltage variations. Thus, the CA of the present disclosure results in an improved linearity performance by reducing total harmonic distortion (THD) variations over process, supply voltage and temperature variations (PVT variations). This is shown in Figure 12. For all lines LI, L2, L3 and L4 the THD variation over process, supply voltage and temperature variations (PVT variations) is within a range of about 0.25 and 0.68 %. In contrast thereto, the THD variations shown in Figures 5 and 6 for open loop biasing schemes are in the range of 0.3 and 6.0 %. In particular, the line LI of Figure 12 shows a THD variation over temperature variations in a range of about 0.25 and 0.68 %. In contrast thereto, the line LI of Figure 5 shows a THD variation over temperature variations in a range of about 0.3 and 6.0 % and the line LI of Figure 6 shows a THD variation over temperature variations in a range of about 0.3 and 3.6 %.

Therefore the cascode amplifier (CA) according to the first aspect or any of its implementation forms and the cascode amplifier circuit (CAC) according to the second aspect or any of its implementation forms significantly improve the linearity performance stability over process, supply voltage and temperature variation; compared with CA topologies using an open loop biasing, as described above with respect to Figures 1 to 6. The CA according to the present disclosure has the possibility to automatically tune its bias voltage in order to ensure maximum linearity performance without requiring additional calibrations.

The cascode amplifier (CA) according to the first aspect or any of its implementation forms and the cascode amplifier circuit (CAC) according to the second aspect or any of its implementation forms are suitable for fully -integrated broadband and narrowband amplifiers requiring high linearity over process, supply voltage and temperature variation, and can be integrated on many different IC technologies, including (but not limited to) BiCMOS, CMOS, and III-V compound technologies (InP, GaAs).

Figure 13 shows an amplifier circuit according to an embodiment of the invention.

The amplifier circuit 7 of Figure 13 comprises two amplifier stages 7a forming an amplifier chain to amplify an input voltage (input signal) Vin of the amplifier circuit 7 to an output voltage (output signal) Vout of the amplifier circuit 7. The number of amplifier stages 7a of the amplifier circuit 7 shown in Figure 13 is only by way of example and does not limit the present disclosure. That is, the amplifier circuit 7 may comprise one or more amplifier stages 7a. The one or more amplifier stages 7a of the amplifier circuit 7 may correspond to one or more cascode amplifier (CA) according to the first aspect or any of its implementation forms, such as one or more CAs according to Figure 7, 8 or 9, and/or to one or more cascode amplifier circuits (CAC) according to the second aspect or any of its implementation forms, such as one or more CAC according to Figure 10. The one or more amplifier stages 7a may be single ended amplifiers and/or differential amplifiers. The amplifier circuit 7 is a high linearity, wide- bandwidth amplifier circuit.

The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed embodiments of the invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A cascode amplifier (1), CA, for amplifying an input voltage (Vin) to an output voltage (Vout), wherein the CA (1) comprises one or more circuit branches (CB1, CB2), wherein each circuit branch (CB1, CB2) comprises a load resistor (RL), a first transistor (Ql) and a second transistor (Q2) that are electrically connected in series to each other, wherein the load resistor (RL) is electrically connected between a supply terminal of the CA (1) and a first terminal of the first transistor (Ql), a second terminal of the first transistor (Ql) is electrically connected to a first terminal of the second transistor (Q2), a second terminal of the second transistor (Q2) is electrically connected to ground, a control terminal of the second transistor (Q2) is electrically connected to an input terminal of the CA (1), and the node between the load resistor (RL) and the first terminal of the first transistor (Ql) is electrically connected to an output terminal of the CA (1); a feedback circuit (2) configured to provide a bias voltage (Vbias) to a control terminal of each first transistor (Ql) by comparing a cascode voltage (Vcasc) sensed at the second terminal of each first transistor (Ql) with a reference voltage (Vrel); and a reference voltage generation circuit (3) including a voltage divider configured to generate for the feedback circuit (2) the reference voltage (Vrel) using the voltage divider, such that the ratio between a transistor voltage (Vcel) of each first transistor (Ql) and a transistor voltage (Vce2) of each second transistor (Q2) is kept constant.

2. The CA (1) according to claim 1, wherein the second terminal of the first transistor (Ql) of each circuit branch is directly electrically connected to the first terminal of the respective second transistor (Q2).

3. The CA (1) according to claim 1, wherein each circuit branch (CB1, CB2) further comprises one or more third transistors (Q3_n) electrically connected in series between the second terminal of the respective first transistor (Ql) and the first terminal of the respective second transistor (Q2), so that the second terminal of the respective first transistor (Ql) is electrically connected via the one or more third transistors (Q3_n) to the first terminal of the respective second transistor (Q2), wherein a first terminal of each third transistor (Q3_n) is electrically connected to a second terminal of a respective transistor of the respective circuit branch, and a second terminal of each third transistor (Q3_n) is electrically connected to a first terminal of a respective transistor of the respective circuit branch, the CA (1) comprises, for each third transistor (Q3n) of one circuit branch, a further feedback circuit (2_n) configured to provide a bias voltage (Vbiasn) to a control terminal of each respective third transistor (Q3_n) of the one or more circuit branches (CB1, CB2) by comparing a cascode voltage (Vcascn) sensed at the second terminal of each respective third transistor (Q3_n) with a respective reference voltage (Vrefn); wherein the reference voltage generation circuit (3) is configured to generate for each feedback circuit (2, 2_n) the respective reference voltage (Vref, Vrefn) using the voltage divider, such that the ratio between the transistor voltage (Vcel) of each first transistor (Ql), the transistor voltage (Vce2) of each second transistor (Q2), and a transistor voltage (Vce3_n) of each third transistor (Q3_n) is kept constant.

4. The CA (1) according to any one of the previous claims, wherein the voltage divider comprises two or more resistors (Rl, R2, R3_n) electrically connected in series to each other, the number of resistors (Rl, R2, R3n) of the voltage divider corresponds to the number of transistors (Ql, Q2, Q3_n) of each circuit branch (CB1, CB2) of the CA (1), and for each transistor (Ql, Q3_n) of one circuit branch, which is supplied with a respective bias voltage (Vbias, Vbiasn) by a respective feedback circuit (2, 2_n), a terminal of the respective resistor (Rl, R3_n) of the voltage divider, wherein the terminal is electrically connected to another resistor of the voltage divider, provides the respective reference voltage (Vref, Vrefn) to the respective feedback circuit (2, 2_n).

5. The CA (1) according to claim 4, wherein one or more of the two or more resistors (Rl, R2, R3_n) are variable resistors.

6. The CA (1) according to any one of the previous claims, wherein the second terminal of the second transistor (Q2) of each circuit branch (CB1, CB2) is directly electrically connected to ground, or each circuit branch further comprises a degeneration resistor (Rdeg) that is electrically connected between the second terminal of the second transistor (Q2) and ground.

7. The CA (1) according to any one of the previous claims, wherein each transistor (Ql, Q2, Q3_n) of the one or more circuit branches (CB1, CB2) comprises or corresponds to a bipolar junction transistor, BJT, wherein the control terminal of the respective transistor is the base terminal of the BJT, the first terminal of the respective transistor is the collector terminal of the BJT and the second terminal of the respective terminal is the emitter terminal of the BJT; or each transistor (Ql, Q2, Q3_n) of the one or more circuit branches (CB1, CB2) comprises or corresponds to a field effect transistor, FET, such as a metal oxide semiconductor FET, MOSFET, wherein the control terminal of the respective transistor is the gate terminal of the FET, the first terminal of the respective transistor is the drain terminal of the FET and the second terminal of the respective transistor is the source terminal of the FET; or one or more transistors of the one or more circuit branches (CB1, CB2) each comprise or correspond to a BJT and the other transistors of the one or more circuit branches (CB1, CB2) each comprises or corresponds to a FET.

8. The CA (1) according to any one of the previous claims, wherein a topology of the CA (1) is configured to be integrated on different IC technologies, such as

BiCMOS technologies,

CMOS technologies, and/or

III-V compound technologies, e.g. InP technologies and/or GaAs technologies.

9. The CA (1) according to any one of the previous claims, wherein the CA (1) is a single ended amplifier comprising one circuit branch (CB1).

10. The CA (1) according to any one of the previous claims, wherein the CA (1) is a differential amplifier comprising two circuit branches (CB1, CB2), and the two circuit branches (CB1, CB2) are electrically connected in parallel to each other.

11. The CA (1) according to any one of the previous claims, wherein each feedback circuit (2, 2_n) of the CA (1) comprises an operational amplifier (2a), the output terminal of the operational amplifier (2a) is electrically connected to the control terminal of the respective one or more transistors (Ql, Q3_n), the reference voltage (Vref, Vrefn) for the respective one or more transistors (Ql, Q3_n) is provided to the non-inverting input of the operational amplifier (2a), and the cascode voltage (Vcasc, Vcascn) of the respective one or more transistors (Ql, Q3_n) is provided to the inverting input of the operational amplifier (2a), wherein the operational amplifier (2a) is configured to provide via the output terminal the bias voltage (Vbias, Vbiasn) to the control terminal of the respective one or more transistors

(Ql, Q3n).

12. The CA (1) according to claim 11, wherein in case the CA (1) is a single ended amplifier, one or more feedback circuits (2, 2_n) further comprise a sensing resistor (Rs) that is electrically connected between the inverting input of the operational amplifier (2a) of the respective feedback circuit (2, 2_n) and the second terminal of the respective transistor (Ql, Q3_n) of the one circuit branch (CB1) for sensing the cascode voltage (Vcasc, Vcascn) of the respective transistor (Ql, Q3_n), and in case the CA (1) is a differential amplifier, each feedback circuit (2, 2_n) further comprises two sensing resistors (Rs), wherein one sensing resistor (Rs) is electrically connected between the inverting input of the operational amplifier (2a) of the respective feedback circuit (2, 2_n) and the second terminal of the respective transistor (Ql, Q3_n) of one circuit branch (CB1), and the other sensing resistor (Rs) is electrically connected between the inverting input of the operational amplifier (2a) of the respective feedback circuit (2, 2_n) and the second terminal of the respective transistor (Ql, Q3_n) of the other circuit branch (CB2).

13. The CA (1) according to any one of the previous claims, wherein in case the C A (1 ) is a single ended amplifier, the voltage divider of the reference voltage generation circuit (3) is electrically connected to the circuit branch (CB1) such that the first terminal of the first transistor (Ql) is electrically connected via a buffer (3 a) to one end of the voltage divider, and the second terminal of the second transistor (Q2) is electrically connected via a further buffer (3b) to the other end of the voltage divider; and in case the CA (1) is a differential amplifier, the voltage divider of the reference voltage generation circuit (3) is electrically connected to the two circuit branches (CB1, CB2) such that the first terminals of the first transistors (Ql) are electrically connected via a buffer (3 a) to one end of the voltage divider, wherein the first terminal of each first transistor (Ql) is electrically connected via a sense resistor (Rs) to the buffer (3 a), and the second terminals of the second transistors (Q2) are electrically connected via a further buffer (3b) to the other end of the voltage divider, wherein the second terminal of each second transistor (Q2) is electrically connected via a further sense resistor (Rs) to the further buffer (3b).

14. The CA (1) according to claim 13, wherein in case the CA (1) is a single ended amplifier, the first terminal of the first transistor (Ql) is electrically connected via a sense resistor (Rs) to the input of the buffer (3a) and the output of the buffer (3a) is electrically connected to the one end of the voltage divider, and/or the second terminal of the second transistor (Q2) is electrically connected via a further sense resistor (Rs) to the input of the further buffer (3b) and the output of the further buffer (3b) is electrically connected to the other end of the voltage divider.

15. A cascode amplifier circuit (4), CAC, comprising a cascode amplifier (1), CA, according to any one of claims 1 to 14, and a scaled replica (5) of a circuit branch of the one or more circuit branches (CB1, CB2) of the CA (1), wherein the control terminal of each scaled transistor (Ql/N) except of the scaled second transistor (Q2/N) of the scaled replica (5) is supplied with a bias voltage (Vbias,r) maintaining the respective scaled transistor (Ql/N) in the active region.

16. The CAC (4) according to claim 15, wherein the scaled replica (5) is a scaled down replica of the circuit branch or a scaled up replica of the circuit branch.

17. The CAC (5) according to claim 15 or 16, wherein one or more scaled transistors except of the scaled second transistor (Q2/N) of the scaled replica (5) are diode connected.

18. The CAC (4) according to any one of claims 15 to 17, wherein the voltage divider of the reference voltage generation circuit (3) of the CA (1) is electrically connected to the scaled replica (5) of the circuit branch such that the first terminal of the scaled first transistor (Ql/N) of the scaled replica (5) is electrically connected via a buffer (3a) to one end of the voltage divider, and the second terminal of the scaled second transistor (Q2/N) of the scaled replica (5) is electrically connected via a further buffer (3b) to the other end of the voltage divider.

19. The CAC (4) according to claim 18, wherein the first terminal of the scaled first transistor (Ql/N) of the scaled replica (5) is electrically connected via a sense resistor (Rs) to the input of the buffer (3a) and the output of the buffer (3 a) is electrically connected to the one end of the voltage divider, and/or the second terminal of the scaled second transistor (Q2/N) of the scaled replica (5) is electrically connected via a further sense resistor (Rs) to the input of the further buffer (3b) and the output of the further buffer (3b) is electrically connected to the other end of the voltage divider.

20. An amplifier circuit (7), comprising one or more cascode amplifiers (1), CAs, according to any one of claims 1 to 14, and/or one or more cascode amplifier circuits (4), CACs, according to any of claims 15 to 19, as one or more amplifier stages (7a) forming an amplifier chain to amplify an input voltage (Yin) of the amplifier circuit (7) to an output voltage (Vout) of the amplifier circuit (7).