Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
  • G06F17/10—Complex mathematical operations
  • G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06G—ANALOGUE COMPUTERS
  • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
  • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor
  • G06G7/122—Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor for optimisation, e.g. least square fitting, linear programming, critical path analysis, gradient method
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N5/00—Computing arrangements using knowledge-based models
  • G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound

Definitions

• This invention relates to Ising machines. Particularly, this invention relates to Ising machines implemented with a network of resistively coupled circuit nodes where a node has a capacitor connected in parallel with an active electronics element.
• Ising machines In general, these systems can be thought of as optimizing an objective function (in the form of the Ising formula) due to the physics. Hence, they are generally referred to as Ising machines. Clearly, unlike in a von Neumann machine, there is no explicit algorithm to follow. Instead, nature is effectively carrying out the computation. Ising machines have been implemented in a variety of ways with very different (and often complex) physics principles involved. It may not be clear whether some Ising machine form has a fundamental advantage that will manifest in a very large scale.
• Ising machines use physics to naturally guide a dynamical system towards an optimal state which can be read out as a heuristical solution to a combinational optimization problem. Such designs that use nature as a computing mechanism can lead to higher performance and/or lower operation costs. Quantum annealers are a prominent existing example of such machines. However, existing Ising machines are generally bulky and energy intensive. Such disadvantages might lead to intrinsic advantages at some larger scale in the future. But for now, integrated circuit designs allow more immediate applications. Embodiments of the present invention are directed to a design that uses bistable nodes, coupled with programmable and variable strength. The design is fully CMOS compatible for on-chip applications and demonstrate competitive metrics in performance, area, and energy.
• An exemplary embodiment of the invention can comprise a network of resistively coupled circuit nodes having at least one node including a capacitor where a voltage across the capacitor represents a state variable of the node and the voltage is resistively coupled to at least one other node in the network and an active electronics element having two terminals connected in parallel with the capacitor supplying energy to the node, the active electronics element having an odd-symmetric current-voltage characteristic exhibiting: a negative current gradient for voltages across the two terminals that are below a predetermined threshold value in magnitude, and a positive gradient otherwise; and zero current for three voltage instances: zero volts, +Vi volts, and -Vi volts, where Vi is a constant greater than the predetermined threshold.
• Further embodiments can include a programmable resistor connected in parallel with the active electronics element to adjust the negative current gradient and the positive current gradient in the odd-symmetric current-voltage characteristic and Vi.
• Further embodiments can include a bipolar junction transistor connected in parallel with the active electronics element to adjust the negative current gradient and the positive current gradient in the odd-symmetric current-voltage characteristic and Vi by changing a base current of the bipolar junction transistor.
• Further embodiments can include a field-effect transistor connected in parallel with the active electronics element to adjust the negative current gradient and the positive current gradient in the odd-symmetric current-voltage characteristic and Vi by changing a gate voltage of the field-effect transistor.
• Another embodiment of the invention can comprise a network of coupled circuit nodes having at least one node including a capacitor where a voltage across the capacitor represents a state variable of the node and the voltage is converted to current before being coupled to at least one other node in the network and an active electronics element having two terminals connected in parallel with the capacitor supplying energy to the node, and the element having an odd-symmetric current-voltage characteristic exhibiting: a negative current gradient for voltages across the two terminals that are below a predetermined threshold value in magnitude, and a positive gradient otherwise; and zero current for three voltage instances: zero volts, +Vi volts, and -Vi volts, where Vi is a constant greater than the predetermined threshold.
• This embodiment of the invention can be further modified consistent with any other networks, devices or methods described herein.
• An exemplary method for solving maximum-cut problems on a graph can comprise mapping vertices of the graph are to nodes in a network of resistively coupled circuit nodes; and mapping edge weights of the graph to coupling resistors of the network, the network having: at least one node including:a capacitor where a voltage across the capacitor represents a state variable of the node and the voltage is resistively coupled to at least one other node in the network; and an active electronics element having two terminals connected in parallel with the capacitor supplying energy to the node, and the active electronics element having an odd-symmetric current-voltage characteristic exhibiting: a negative current gradient for voltages across its terminals that are below a predetermined threshold value in magnitude, and a positive gradient otherwise; and zero current for three voltage instances: zero volts, +Vi volts, and -Vi volts, where Vi is a constant greater than the predetermined threshold.
• the method can further include a coupling resistor between any two nodes in the network corresponding to two vertices on the graph is inversely proportional to the edge weight between the two vertices, any two nodes in the network corresponding to positively connected vertices on the graph (i.e., positive edge weight) are cross-coupled connecting the terminals of the capacitors of the two corresponding nodes with the opposite polarity through the coupling resistor(s), and any two nodes in the network corresponding to negatively connected vertices on the graph (i.e., negative edge weight) are coupled in parallel connecting the terminals of the capacitors of the two corresponding nodes with the same polarity through the coupling resistor(s).
• This embodiment of the invention can be further modified consistent with any other networks, devices or methods described herein.
• Another exemplary method for solving maximum-cut problems on a graph can comprise: mapping vertices of the graph to nodes in a network of coupled circuit nodes; and mapping edge weights of the graph to coupling currents of the network, the network having: at least one node including: a capacitor where a voltage across the capacitor represents a state variable of the node and the voltage is converted to current before coupled to at least one other node in the network; and an active electronics element having two terminals connected in parallel with the capacitor supplying energy to the node, and the element having an odd-symmetric current-voltage characteristic exhibiting: a negative current gradient for voltages across its terminals that are below a predetermined threshold value in magnitude, and a positive gradient otherwise; and zero current for three voltage instances: zero volts, + Vi volts, and -Vi volts, where Vi is a constant greater than the predetermined threshold.
• a coupling current between any two nodes in the network corresponding to two vertices on the graph is proportional to the edge weight between the two vertices; any two nodes in the network corresponding to positively connected vertices on the graph (i.e., positive edge weight) are cross-coupled such that the coupling current charges the capacitors of the two corresponding nodes with the opposite polarity; and any two nodes in the network corresponding to negatively connected vertices on the graph (i.e., negative edge weight) are coupled in parallel such that the coupling current charges the capacitors of the two corresponding nodes with the same polarity.
• This embodiment of the invention can be further modified consistent with any other networks, devices or methods described herein.
• Another exemplary embodiment of the invention can comprise a device for solving maximum-cut problems on a graph, where vertices of the graph correspond to nodes in a network of resistively coupled circuit nodes and edge weights of the graph correspond to coupling resistors of the network, the network comprising: at least one node including: a capacitor where voltage across the capacitor represents a state variable of the node and the voltage is resistively coupled to at least one other node in the network; and an active electronics element having two terminals connected in parallel with the capacitor supplying energy to the node, and the element having an odd- symmetric current-voltage characteristic exhibiting: a negative current gradient for voltages across its terminals that are below a predetermined threshold value in magnitude, and a positive gradient otherwise; and zero current for three voltage instances: zero volts, + Vi volts, and -Vi volts, where Vi is a constant greater than the predetermined threshold; a coupling resistor between any two nodes in the network corresponding to two vertices on the graph is inverse
• Yet another embodiment of the invention can comprise a device for solving maximum-cut problems on a graph where vertices of the graph correspond to nodes in a network of coupled circuit nodes and edge weights of the graph are correspond to coupling currents of the network, the network comprising: at least one node including: a capacitor where voltage across the capacitor represents a state variable of the node and the voltage is converted to current before coupled to at least one other node in the network; and a two-terminal active electronics element connected in parallel with the capacitor supplying energy to the node, and the element having an odd-symmetric current-voltage characteristic exhibiting: a negative current gradient for voltages across its terminals that are below a predetermined threshold value in magnitude, and a positive gradient otherwise; and zero current for three voltage instances: zero volts, + Vi volts, and -Vi volts, where Vi is a constant greater than the predetermined threshold; a coupling current between any two nodes in the network corresponding to two vertices on the graph is proportional to the edge
• FIG. 1 illustrates architecture of the exemplary bistable, resistively-coupled Ising machine (BRIM);
• FIG. 2 illustrates an exemplary Ni balanced BRIM node depicting connection between the N, node to two other nodes (Nj and Nk)
• FIG. 3 illustrates an exemplary balanced ZIV diode implemented with discrete components with polarity of the diode’s terminals arbitrarily chosen
• FIG. 4 illustrates exemplary I-V curves of the balanced ZIV diode loaded with various load resistances RL where the curves are obtained from the ZIV diode in FIG. 3;
• FIG. 5 shows exemplary 6-nodes discrete BRIM implementation with LF412 opamps
• FIG. 6 shows exemplary voltage waveforms at the output of the nodes in the discrete BRIM of FIG. 5;
• FIG. 7 illustrates a block diagram showing components of an exemplary BRIM having nodes N, and coupling units CUy ;
• FIG 8 illustrates a balanced structure of an exemplary integrated circuit BRIM node which conceives to apply both the negative to positive coupling coefficients on the circuit
• FIG. 9 illustrates an exemplary coupling unit circuit diagram.
• the Ising model is used to describe the Hamiltonian (the sum of the energies of a given system, e.g., kinetics and potential) of a system of spin.
• the model itself existed before Ernst Ising solved analytically a one-dimensional system.
• the model is a general one that describes a system with many nodes (e.g., atoms), each with a spin represented as s ; which takes only two values of +1 and -1.
• the energy of the system is a function of pair-wise coupling of the spins (Jy) and the interaction of some external field with each spin (hi).
• the resulting Hamiltonian is as follows:
• a physical system with such a Hamiltonian naturally tends towards low-energy states and thus serves as a convenient machine to solve a problem with a formulation equivalent to the Ising Hamiltonian - provided parameters (e.g., Jy ) can be configured to match that of the problem.
• the max-cut is found.
• To find out the max-cut of an arbitrary graph is an NP-hard problem. Practical algorithms only operate to find a good answer.
• existing Ising machines including some present embodiments of the invention are all Ising sampling machines that attempt to find a good answer with no guarantee of optimality.
• Max-Cut is NP- complete and thus all other NP-complete problems can be transformed as a Max-Cut problem with polynomial complexity. (See Karp, “Reducibility among Combinatorial Problems,” pages 85-103. Springer US, Boston, MA, 1972, which is incorporated by reference herein.) This means other NP-complete problems can be solved with either additional pre- and post-processing time or with additional nodes for mapping. Both time and space overheads are bound by a polynomial complexity.
• Quantum mechanical and optical Ising machines There are many natural systems that can be described by the Ising model. Take two existing systems with relatively large footprints for example. D-Wave’s machine is a different style of quantum computers. Recent theoretical works have claimed the equivalence between quantum annealers and the more traditional circuit model quantum computing.
• minor embedding In practice, an abstract problem has to go through a transformation (called minor embedding) to ensure that it can be mapped to the machine. This process involves mapping a logical node onto multiple physical nodes that are themselves coupled together strongly. In this way, in solutions found they are almost always spinning in the same direction that they can be considered as one logical node. It will be shown that this limits the number of effective nodes (spins) that a machine can offer. Considering an extreme example of fully connected graph, the number of nodes needed in the minor embedded version grows quadratically with the number of logical nodes. Another disadvantage of the system is the cryogenic operating condition (at 15mK) needed for the quantum annealer. This requirement consumes a significant portion of the 25KW power of the machine.
• Coherent Ising machines are another recent example of Ising sampling machines.
• CIMs Coherent Ising machines
• OPO optical parametric oscillator
• the coupling between nodes is - at least in the current incarnation - implemented via computation external to the optical cavity. Every pulse’s amplitude and phase are detected and its interaction with all other pulses calculated on an auxiliary computer (FPGA) and in turn used to modulate new pulses that are injected into the cavity. Strictly speaking, the current implementation is a nature- simulation hybrid Ising machine. Thus, beyond the challenge of constructing the cavity, CIM also requires a significant supporting structure that involves fast conversions between optical signal and electrical signals and a rather intensive computational demand (e.g. 100s of GFLOPS).
• a network of coupled oscillators is another physical implementation of an Ising machine. Take a network of coupled oscillators as an example. After sufficient time, the oscillators will synchronize forming stable relative phase relationship. (The observation of such synchronization dates back to at least the 17 th century when Huygens observed synchronization of two pendulums. See Rosenblum et ah, “Phase synchronization of chaotic oscillators,” Physical review letters, 76(11): 1804, March 1996, incorporated by reference herein. Synchronization phenomenon is the subject of research efforts in a wide variety of fields.
• a large-scale Ising machine necessarily contains many nodes spread over long distances with concomitant parasitics of the interconnect lines. Proper coupling at such high operating frequencies while preserving phase coherence presents a real engineering challenge, if possible at all. In addition, it might be difficult to achieve purely resistive coupling of oscillator at GHz operating frequencies. Hence, it is desirable to explore an IC-focused designs that have good performance characteristics and easy for CMOS integration.
• Example Ising Machine Design with Discrete Electronics An exemplary implementation of the BRIM in discrete electronics with operational amplifiers is described here with passive components such as capacitors as well as resistors.
• the exemplary BRIM of Ising machine can employ a design using nodes with a single state variable (e.g., voltage on a capacitor) whose trajectories obey first order ordinary differential equations.
• a Lyapunov function can be used of the form shown in Eq. (7), where 3 ⁇ 4 ⁇ ' )) is a double-well potential energy term (e.g., a differentiable function having two equal minima at '7 1 and
• the Lyapunov function in Eq. (7) is a continuous function in an N-dimensional space whose global minimum might not map to the global minimum of the discrete N- dimensional space Ising Hamiltonian
• the second term in Eq. (7) will force the continuous states to bifurcate into one of the stable equilibrium points (e.g., -IV and +IV ) corresponding to the two spin values in the Ising Hamiltonian and collapsing the continuous Lyapunov function in Eq. (7) into a ground energy state of the corresponding Ising Hamiltonian form.
• FIG. 1 shows the topology overview of a discrete BRIM.
• At the heart of the present discrete implementation system is an array of bi-stable nodes (e.g., , i 1;
• Each bistable node provides a differential output (e.g., v, and vf) to the mesh of coupling units.
• Each coupling unit CUi j has a pair of resistors Ry connecting the differential outputs from two nodes (e.g., and Nj). For positive coupling coefficients ./ /, the positive output vC from node is coupled to the positive node v , ⁇ + from node Nj and the negative output vf is coupled to v/. Alternatively, for negative coupling coefficients Jy, the differential outputs from nodes and Nj are crosscoupled.
• FIG. 2 illustrates an examplary circuit for a bi-stable node implemented with discrete electronic components for use under the topology of FIG. 1.
• the balanced BRIM node has connection between the node to two other nodes (Nj and Nk).
• the circuit comprises one energy storage element (capacitor C) giving rise to a state variable Vi(t) whose trajectory is described by an ordinary differential equation as shown in Eq. 9.
• FIG. 3 shows an exemplary balanced ZIV diode implemented with two operational amplifiers which can be incorporated in to the examplary circuit of FIG. 2.
• the balanced ZIV diode can be implemented with discrete components with polarity of the diode’s terminals arbitrarily chosen.
• FIG. 4 shows example I-V curves of the ZIV diode’s ' ⁇ ⁇ / ⁇ 1 V.
• the I-V curves of the balanced ZIV diode are shown loaded with various load resistances RL.
• FIG. 5. illustrates an example discrete BRIM prototype implementing six bistable nodes from the described circuit elements of FIGS 2 and 3.
• FIG. 6 shows voltages Vi(t) converge to one of the stable states after the circuit is powered up, depicting voltages from the exemplary embodiment of FIG. 5.
• the exemplary voltage waveforms of FIG. 6 are shown at the output of the nodes in the discrete BRIM of FIG. 5.
• the output voltages from nodes Ni , N2, N3, and Ns converge to +1.15 V representing an “UP” spin, while voltages from nodes N4, and Ne converge to -1.15V representing “DOWN” spin.
• the voltages are compared against a threshold of 0V to measure a polarity and the results is presented as “spin” values to the user to determine the maximum-cut solution of the corresponding graph.
• An exemplary implementation of the BRIM in CMOS integrated circuit technologies is described here.
• FIG. 7 illustrates an exemplary BRIM system (having nodes Ni and coupling units CUij), which can be implemented in CMOS, defined by a group of components as follows:
• Nodes and couplers At the left of FIG. 7 are the bistable nodes, Ni, N2, N3, and N4. Each of the bistable nodes Ni, N2, N3, and N4 contains a pair of capacitors, two resistors, and a special diode to form a bi-stable, differential Ising node with two differential terminals (EC and Vi), across terminals Out+ 102 and In+ 104 and Out- 106 and In- 108, respectively.
• FIG. 8 shows an exemplary transistor level implementation of an integrated bistable node with the four terminals, Out+ 102 and In+ 104 and Out- 106 and In- 108.
• the coupling is directed/unidirectional: this is achieved with a buffer (e.g., transistors M5 to M9 in FIG. 8).
• a buffer e.g., transistors M5 to M9 in FIG. 8
• an undirected/bidirectional coupling has similar effects. But empirically, directed coupling produces better solution quality at the expense of increased circuit area.
• FIG. 9 shows an exemplary coupling unit circuit diagram using a transistor with adjustable gate voltage to achieve programmable resistance.
• the programming array coupled to each string of i coupling units CUy.
• This array comprises digital memory (MEM for storing the weights which drives an array of digital-to-analog converters (DACs) through multiplexors MUXi to MUX4.
• MEM digital memory
• DACs digital-to-analog converters
• MUXi multiplexors
• MUXi multiplexors
• N DACs are shown programming the N x (N -1) coupling units. In such a configuration, corresponding column selectors 110 and pulldown logic 112 are needed which are shown above and below the coupling units CU ij.
• Annealing scheduler The coupling strength is adjustable over time for annealing. Exponential annealing is used both because it can be conveniently achieved using a discharging capacitor as the global annealing scheduler.
• the annealing operation in this example IC design is achieved by the transistors Ml 0 and M21 in FIG. 8 whose gate biasing voltage sets their channel resistance which then loads the buffers and reduces the buffer’s gain and the overall coupling strength. For example, setting Vanmai to high value will lower the gain of the buffer to almost zero, therefore, eliminating coupling to other nodes altogether. Conversely, setting Vanneai to zero volts will allow maximum gain from the buffers and maximum coupling strength limited only by the coupling units.
• the state of the nodes will be read out from the nodes. With the stable voltage adjusted appropriately, the read out can be achieved with a simple flip- flop.
• Perturbation unit Finally, it is useful to have the ability to flip the state of a selected node. This gives the system the ability to escape the current basin of attraction. Note that this is a form of introducing perturbation. An alternative is to add circuit level noise. While both can achieve similar results, introducing analog noise is more difficult to control and leads to more discrepancies between simulation and actual hardware.
• the described exemplary BRIM can be used similarly to other Ising machines: first programming the weights; then selecting the annealing length; and finally reading out the state of the nodes.
• the system can be used in a number of different ways: e.g. the annealing time can be adjusted; the perturbation unit can be turned on with different frequency; the machine can be used with a software-based search algorithm (e.g., simulated annealing).

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Data Mining & Analysis (AREA)
• Software Systems (AREA)
• Pure & Applied Mathematics (AREA)
• Mathematical Optimization (AREA)
• Mathematical Analysis (AREA)
• Computational Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Operations Research (AREA)
• Algebra (AREA)
• Databases & Information Systems (AREA)
• Computer Hardware Design (AREA)
• Artificial Intelligence (AREA)
• Computational Linguistics (AREA)
• Evolutionary Computation (AREA)
• Computing Systems (AREA)
• Semiconductor Integrated Circuits (AREA)
• Management, Administration, Business Operations System, And Electronic Commerce (AREA)
• Control Of Voltage And Current In General (AREA)
• Control Of Electrical Variables (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=76797186

Family Applications (1)

Country Status (4)

Families Citing this family (2)

Family Cites Families (3)

• 2021
  • 2021-04-16 JP JP2022562672A patent/JP7654270B2/ja active Active
  • 2021-04-16 EP EP21737953.6A patent/EP4136562A2/de not_active Withdrawn
  • 2021-04-16 US US17/996,283 patent/US20230229727A1/en active Pending
  • 2021-04-16 WO PCT/US2021/070402 patent/WO2021212145A2/en not_active Ceased

Also Published As

Similar Documents

Legal Events