EP4099373A1 - Gate-ausgerichteter rippenschnitt zur herstellung fortschrittlicher integrierter schaltkreisstrukturen - Google Patents

Gate-ausgerichteter rippenschnitt zur herstellung fortschrittlicher integrierter schaltkreisstrukturen Download PDF

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Publication number
EP4099373A1
EP4099373A1 EP22169877.2A EP22169877A EP4099373A1 EP 4099373 A1 EP4099373 A1 EP 4099373A1 EP 22169877 A EP22169877 A EP 22169877A EP 4099373 A1 EP4099373 A1 EP 4099373A1
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EP
European Patent Office
Prior art keywords
fin
gate
segment
layer
integrated circuit
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EP22169877.2A
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English (en)
French (fr)
Inventor
Leonard P. GULER
Mohammad Hasan
William Hsu
Biswajeet Guha
Charles H. Wallace
Tahir Ghani
Sean PURSEL
Tsuan-Chung CHANG
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Intel Corp
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Intel Corp
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Publication of EP4099373A1 publication Critical patent/EP4099373A1/de
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    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, gate aligned fin cut for advanced integrated circuit structure fabrication.
  • tri-gate transistors In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication.
  • Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures.
  • FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer.
  • FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).
  • Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures.
  • BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers.
  • BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections.
  • contacts pads
  • interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.
  • Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures.
  • an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing.
  • an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.
  • Embodiments described herein are directed to gate aligned fin cut isolation integration schemes.
  • Embodiments may include performing fin cut after gate patterning.
  • Embodiments may include implementing a cut self-aligned to a gate and in order improve one or more of isolation uniformity, fin etch uniformity, gate etch uniformity, gate polish uniformity, and/or reduce issues associated with gate line collapse or gate line bending.
  • a fin is first cut following gate patterning.
  • Figures 1A-1D illustrate top-down angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a gate aligned fin cut, in accordance with an embodiment of the present disclosure.
  • a starting structure 100 includes sub-fins 104 extending from a substrate 102, such as silicon sub-fins extending from a silicon substrate.
  • the sub-fins 104 protrude through a shallow trench isolation (STI) structure 106, such as a silicon oxide structure.
  • Fins 108 are above corresponding ones of the sub-fins 104.
  • each fin 108 includes alternating sacrificial layers 110 and nanowires 112.
  • the nanowires 112 may be referred to as a vertical arrangement of horizontally stacked nanowires.
  • a protective cap 114 may be formed above the alternating sacrificial layers 110 and nanowires 112, as is depicted.
  • a lowermost sacrificial layer has been removed from beneath the fin to provide a gap 109 between the fins 108 and the corresponding sub-fins 104, as is also depicted. It is to be appreciated that the example illustrated in Figure 1A is merely one example of a fin and sub-fin pairing.
  • gate stacks 116 are over the fins 108.
  • Each gate stack may include a dummy gate material 118, such as polysilicon, and a hardmask 120, such as a silicon nitride hardmask.
  • a dummy gate material 118 such as polysilicon
  • a hardmask 120 such as a silicon nitride hardmask.
  • the gate stacks 116 may be fabricated using a direct patterning, a pitch-halving approach (spacer-based), a pitch quartering approach, etc.
  • a spacer material 122 is formed over the gate stacks 116, over the fins 108, and in the gaps 109, as is depicted.
  • each fin segment 108A can include, in one embodiment, a patterned protective cap 114A, and alternating patterned sacrificial layers 110A and nanowires 112A.
  • a mask is formed and then opened in the locations selected for fin cut.
  • the fins 108 are cut at the two locations between the three gate stacks 116, but not on either side of the grouping of three gate stacks 116. Cutting the fins 108 forms gaps 124 between fin segments 108A, as is depicted.
  • spacer 122 can be added to with additional spacer material to form thicker spacer material 122A.
  • a mask 126 can be formed in all remaining gaps, as is depicted. The mask 126 can ultimately be patterned to define regions where source and drain structures are to be formed, and regions where source and drain structures are not to be formed.
  • mask 126 is patterned to expose regions of the fin segments 108A on either side of the grouping of three gate stacks 116, and to mask the two locations between the three gate stacks 116.
  • the exposed regions of the fin segments 108A on either side of the grouping of three gate stacks 116 are subjected to a recess of the patterned sacrificial layers 110A to formed recessed sacrificial layers 110B.
  • An internal spacer 130 can then be deposited, followed by epitaxial source or drain structure 128 formation.
  • source or drain formation is blocked in the three gate stacks 116, e.g., by retained portions of mask 126.
  • insulating material 132 is formed over the structure to provide fin isolation structures 132A, such as silicon oxide structures.
  • subsequent processing can involve planarization of the insulating material 132 and the upper spacer material 122A to expose gate structures 116 and to confine fin isolation structures 132A in the two locations between the three gate stacks 116.
  • the gate stacks 116 are then removed and replaced with permanent gate stacks, such as gate stacks including a high-k dielectric layer and a metal gate electrode.
  • the recessed sacrificial layers 110B are removed to release the patterned nanowires 112B.
  • Figure 2 illustrates a top-down angled cross-sectional view representing an operation in a method of fabricating an integrated circuit structure having a gate aligned fin cut, in accordance with an embodiment of the present disclosure.
  • an integrated circuit structure 200 includes epitaxial source or drain structure 202 for active fin/nanowire portions, and a gate 204.
  • the structure 200 also includes "plugged" source or drain regions 206 where source and drain regions are not formed.
  • a fin edge is normally centered on a gate, in the structure 200, a fin edge 208 is aligned to the edge of the gate 204.
  • a dummy fin 210 is present between two active fins, with intervening "plugged" source or drain regions 206 there between. It is to be appreciated that dummy fin 210 would not normally in a case that initial fin cut is performed prior to gate line patterning. In one such embodiment, the dummy fin 210 is an electrically isolated feature.
  • an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment (e.g., left and center fin segments 108A).
  • a first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment.
  • a second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment.
  • An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.
  • the second fin segment is a dummy fin segment.
  • the first fin segment includes an epitaxial source or drain structure at a second fin end of the first fin segment, and the second fin segment does not include an epitaxial source or drain structure at a second fin end of the second fin segment.
  • the fin includes a plurality of horizontally stacked nanowires (with "fin” referring to a structure with or without intervening sacrificial material). In another embodiment, the fin is a unitary body.
  • a method of fabricating an integrated circuit structure includes forming a fin along a first direction, forming a plurality of gate structures over the fins, individual ones of the plurality of gate structures along a second direction orthogonal to the first direction, etching portions of the fin between the individual ones of the plurality of gate structures to form a plurality of fin segments, and forming an isolation structure between a first fin segment and a second fin segment of the plurality of fin segments.
  • the method further includes forming an epitaxial source or drain structure between and coupling the second fin segment and a third fin segment of the plurality of fin segments, e.g., such as a third fin segment to the far left of the left fin segment 108A of Figure 1D .
  • Non-planar transistors which utilize a fin of semiconductor material protruding from a substrate surface employ a gate electrode that wraps around two, three, or even all sides of the fin (i.e., dual-gate, tri-gate, nanowire transistors). Source and drain regions are typically then formed in the fin, or as re-grown portions of the fin, on either side of the gate electrode.
  • a gap or space may be formed between two adjacent fins.
  • Such an isolation gap generally requires a masked etch of some sort, and is typically performed immediately following fin formation. Once isolated, a gate stack is then patterned over the individual fins, again typically with a masked etch of some sort (e.g., a line etch or an opening etch depending on the specific implementation).
  • a masked etch of some sort e.g., a line etch or an opening etch depending on the specific implementation.
  • non-planar transistors in a microelectronic device such as an integrated circuit (IC) are isolated from one another in a manner that is self-aligned to gate electrodes of the transistors.
  • exemplary ICs include, but are not limited to, microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front end modules), and power ICs.
  • two ends of adjacent semiconductor fin portions are electrically isolated from each other with an isolation region that is positioned relative to gate electrodes with the use of only one patterning mask level.
  • One or more through-gate isolation embodiments described herein may, for example, enable higher transistor densities and higher levels of advantageous transistor channel stress.
  • isolation With isolation defined after placement or definition of the gate electrode, a greater transistor density can be achieved because fin isolation dimensioning and placement can be made perfectly on-pitch with the gate electrodes.
  • the semiconductor fin has a lattice mismatch with a substrate on which the fin is disposed, greater degrees of strain are maintained by defining the isolation after placement or definition of the gate electrode.
  • other features of the transistor such as the gate electrode and, possibly, added source or drain materials) that are formed before ends of the fin are defined help to mechanically maintain fin strain after an isolation cut is made into the fin.
  • transistor scaling can benefit from a denser packing of cells within the chip.
  • most cells are separated from their neighbors by two or more dummy gates, which have buried fins.
  • the cells are isolated by etching the fins beneath these two or more dummy gates, which connect one cell to the other.
  • Scaling can benefit significantly if the number of dummy gates that separate neighboring cells can be reduced from two or more down to one.
  • one solution requires two or more dummy gates.
  • the fins under the two or more dummy gates are etched during fin patterning.
  • a potential issue with such an approach is that dummy gates consume space on the chip which can be used for cells.
  • approaches described herein enable the use of, at most, only a single dummy or unused gate to separate neighboring cells.
  • Figures 3A and 3B illustrate plan views representing various operations in a method of patterning of fins with multi-gate spacing.
  • a plurality of fins 302 is shown having a length along a first direction 304.
  • a grid 306, having spacings 307 there between, defining locations for ultimately forming a plurality of gate lines is shown along a second direction 308 orthogonal to the first direction 304 as a reference.
  • a portion of the plurality of fins 302 is cut (e.g., removed by an etch process) to leave fins 310 having a cut 312 therein.
  • An isolation structure ultimately formed in the cut 312 therefore has a dimension of more than a single gate line, e.g., a dimension of three gate lines 306. Accordingly, gate structures ultimately formed along the locations of the gate lines 306 will be formed at least partially over an isolation structure formed in cut 312.
  • cut 312 is a relatively wide fin cut.
  • Figures 3C-3D illustrate plan views representing various operations in a method of patterning of fins with single gate spacing, in accordance with another embodiment of the present disclosure.
  • a method of fabricating an integrated circuit structure includes forming a plurality of fins 322, individual ones of the plurality of fins 322 having a longest dimension along a first direction 324.
  • a plurality of gate structures 326 is over the plurality of fins 322, individual ones of the gate structures 326 having a longest dimension along a second direction 328 orthogonal to the first direction 324.
  • the gate structures 326 are sacrificial or dummy gate lines, e.g., fabricated from polycrystalline silicon.
  • the plurality of fins 322 are silicon fins and are continuous with a portion of an underlying silicon substrate.
  • the plurality of fins 322 include alternating sacrificial layers and nanowire layers.
  • a mask 330 is formed between adjacent ones of the plurality of gate structures 326, but is removed and/or not formed in some locations.
  • the fins can be cut at locations "X" 332 to form a cut region 340.
  • the exposed portion of each of the plurality of fins 322 is removed/cut using a dry or plasma etch process.
  • the cut region is ultimately filled with an insulating layer, e.g., in locations of the removed portions of each of the plurality of fins 322 to form a fin cut isolation structure.
  • a fin structure for use in a gate aligned fin cut isolation approach includes a plurality of horizontal nanowires (which can refer generally to nanowires and/or nanoribbons).
  • the fin may include intervening sacrificial material between the plurality of horizontal nanowires.
  • nanowires or nanoribbons, or sacrificial intervening layers may be composed of silicon.
  • a silicon layer may be used to describe a silicon material composed of a very substantial amount of, if not all, silicon.
  • 100% pure Si may be difficult to form and, hence, could include a tiny percentage of carbon, germanium or tin.
  • Such impurities may be included as an unavoidable impurity or component during deposition of Si or may "contaminate" the Si upon diffusion during post deposition processing.
  • embodiments described herein directed to a silicon layer may include a silicon layer that contains a relatively small amount, e.g., "impurity" level, non-Si atoms or species, such as Ge, C or Sn. It is to be appreciated that a silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic.
  • nanowires or nanoribbons, or sacrificial intervening layers may be composed of silicon germanium.
  • a silicon germanium layer may be used to describe a silicon germanium material composed of substantial portions of both silicon and germanium, such as at least 5% of both.
  • the amount of germanium is greater than the amount of silicon.
  • a silicon germanium layer includes approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 ).
  • the amount of silicon is greater than the amount of germanium.
  • a silicon germanium layer includes approximately 30% germanium and approximately 70% silicon (Si 70 Ge 30 ).
  • SiGe silicon germanium
  • Such impurities may be included as an unavoidable impurity or component during deposition of SiGe or may "contaminate" the SiGe upon diffusion during post deposition processing.
  • embodiments described herein directed to a silicon germanium layer may include a silicon germanium layer that contains a relatively small amount, e.g., "impurity" level, non-Ge and non-Si atoms or species, such as carbon or tin.
  • a silicon germanium layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorous or arsenic.
  • embodiments described herein can also include other implementations such as nanowires and/or nanoribbons with various widths, thicknesses and/or materials including but not limited to Si and SiGe.
  • group III-V materials may be used.
  • nanowire or nanoribbon processing schemes may be used to fabricate a device that can be integrated with a gate aligned fin cut isolation approach, such as described in association with Figures 1A-1D and 2 .
  • the exemplary embodiments need not necessarily require all features described, or may include more features than are described.
  • nanowire release processing may be performed through a replacement gate trench. Examples of such release processes are described below.
  • backend (BE) interconnect scaling can result in lower performance and higher manufacturing cost due to patterning complexity.
  • Embodiments described herein may be implemented to enable front-side and back-side interconnect integration for nanowire transistors.
  • Embodiments described herein may provide an approach to achieve a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs.
  • Embodiments may be implemented to enable robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.
  • One or more embodiments described herein are directed dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth.
  • an integrated circuit structure is fabricated by forming source-drain openings of nanowire/nanoribbon transistors which are partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain side enables direct contact to a back-side interconnect level.
  • Figures 4A-4J illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure.
  • a method of fabricating an integrated circuit structure includes forming a starting stack which includes alternating sacrificial layers 404 and nanowires 406 above a fin 402, such as a silicon fin.
  • the nanowires 406 may be referred to as a vertical arrangement of nanowires.
  • a protective cap 408 may be formed above the alternating sacrificial layers 404 and nanowires 406, as is depicted.
  • a relaxed buffer layer 452 and a defect modification layer 450 may be formed beneath the alternating sacrificial layers 404 and nanowires 406, as is also depicted.
  • a gate stack 410 is formed over the vertical arrangement of horizontal nanowires 406. Portions of the vertical arrangement of horizontal nanowires 406 are then released by removing portions of the sacrificial layers 404 to provide recessed sacrificial layers 404' and cavities 412, as is depicted in Figure 4C .
  • a fabrication process involves use of a process scheme that provides a gate-all-around integrated circuit structure having epitaxial nubs, which may be vertically discrete source or drain structures.
  • upper gate spacers 414 are formed at sidewalls of the gate structure 410.
  • Cavity spacers 416 are formed in the cavities 412 beneath the upper gate spacers 414.
  • a deep trench contact etch is then optionally performed to form trenches 418 and to form recessed nanowires 406'.
  • a patterned relaxed buffer layer 452' and a patterned defect modification layer 450' may also be present, as is depicted.
  • a sacrificial material 420 is then formed in the trenches 418, as is depicted in Figure 4E .
  • an isolated trench bottom or silicon trench bottom may be used.
  • a first epitaxial source or drain structure (e.g., left-hand features 422) is formed at a first end of the vertical arrangement of horizontal nanowires 406'.
  • a second epitaxial source or drain structure (e.g., right-hand features 422) is formed at a second end of the vertical arrangement of horizontal nanowires 406'.
  • the epitaxial source or drain structures 422 are vertically discrete source or drain structures and may be referred to as epitaxial nubs.
  • An inter-layer dielectric (ILD) material 424 is then formed at the sides of the gate electrode 410 and adjacent the source or drain structures 422, as is depicted in Figure 4G .
  • ILD inter-layer dielectric
  • a replacement gate process is used to form a permanent gate dielectric 428 and a permanent gate electrode 426.
  • the ILD material 424 is then removed, as is depicted in Figure 41.
  • the sacrificial material 420 is then removed from one of the source drain locations (e.g., right-hand side) to form trench 432, but is not removed from the other of the source drain locations to form trench 430.
  • a first conductive contact structure 434 is formed coupled to the first epitaxial source or drain structure (e.g., left-hand features 422).
  • a second conductive contact structure 436 is formed coupled to the second epitaxial source or drain structure (e.g., right-hand features 422).
  • the second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434.
  • the method further includes forming an exposed surface of the second conductive contact structure 436 at a bottom of the fin 402.
  • Conductive contacts may include a contact resistance reducing layer and a primary contact electrode layer, where examples can include Ti, Ni, Co (for the former and W, Ru, Co for the latter.)
  • the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434, as is depicted. In one such embodiment, the first conductive contact structure 434 is not along the fin 402, as is depicted. In another such embodiment, not depicted, the first conductive contact structure 434 is partially along the fin 402.
  • the second conductive contact structure 436 is along an entirety of the fin 402. In an embodiment, although not depicted, in the case that the bottom of the fin 402 is exposed by a back-side substrate removal process, the second conductive contact structure 436 has an exposed surface at a bottom of the fin 402.
  • the structure of Figure 4J is formed using a gate aligned fin cut isolation approach, such as described in association with Figures 1A-1D and 2 .
  • integrated circuit structures described herein may be fabricated using a back-side reveal of front-side structures fabrication approach.
  • reveal of the back-side of a transistor or other device structure entails wafer-level back-side processing.
  • a reveal of the back-side of a transistor as described herein may be performed at the density of the device cells, and even within sub-regions of a device.
  • such a reveal of the back-side of a transistor may be performed to remove substantially all of a donor substrate upon which a device layer was disposed during front-side device processing.
  • a microns-deep TSV becomes unnecessary with the thickness of semiconductor in the device cells following a reveal of the back-side of a transistor potentially being only tens or hundreds of nanometers.
  • Reveal techniques described herein may enable a paradigm shift from “bottom-up” device fabrication to "center-out” fabrication, where the "center” is any layer that is employed in front-side fabrication, revealed from the back-side, and again employed in back-side fabrication. Processing of both a front-side and revealed back-side of a device structure may address many of the challenges associated with fabricating 3D ICs when primarily relying on front-side processing.
  • a reveal of the back-side of a transistor approach may be employed for example to remove at least a portion of a carrier layer and intervening layer of a donor-host substrate assembly.
  • the process flow begins with an input of a donor-host substrate assembly.
  • a thickness of a carrier layer in the donor-host substrate is polished (e.g., CMP) and/or etched with a wet or dry (e.g., plasma) etch process.
  • Any grind, polish, and/or wet/dry etch process known to be suitable for the composition of the carrier layer may be employed.
  • the carrier layer is a group IV semiconductor (e.g., silicon)
  • a CMP slurry known to be suitable for thinning the semiconductor may be employed.
  • any wet etchant or plasma etch process known to be suitable for thinning the group IV semiconductor may also be employed.
  • the above is preceded by cleaving the carrier layer along a fracture plane substantially parallel to the intervening layer.
  • the cleaving or fracture process may be utilized to remove a substantial portion of the carrier layer as a bulk mass, reducing the polish or etch time needed to remove the carrier layer.
  • a carrier layer is 400-900 ⁇ m in thickness
  • 100-700 ⁇ m may be cleaved off by practicing any blanket implant known to promote a wafer-level fracture.
  • a light element e.g., H, He, or Li
  • H, He, or Li is implanted to a uniform target depth within the carrier layer where the fracture plane is desired.
  • the thickness of the carrier layer remaining in the donor-host substrate assembly may then be polished or etched to complete removal.
  • the grind, polish and/or etch operation may be employed to remove a greater thickness of the carrier layer.
  • Detection is used to identify a point when the back-side surface of the donor substrate has advanced to nearly the device layer. Any endpoint detection technique known to be suitable for detecting a transition between the materials employed for the carrier layer and the intervening layer may be practiced.
  • one or more endpoint criteria are based on detecting a change in optical absorbance or emission of the back-side surface of the donor substrate during the polishing or etching performance. In some other embodiments, the endpoint criteria are associated with a change in optical absorbance or emission of byproducts during the polishing or etching of the donor substrate back-side surface.
  • absorbance or emission wavelengths associated with the carrier layer etch byproducts may change as a function of the different compositions of the carrier layer and intervening layer.
  • the endpoint criteria are associated with a change in mass of species in byproducts of polishing or etching the back-side surface of the donor substrate.
  • the byproducts of processing may be sampled through a quadrupole mass analyzer and a change in the species mass may be correlated to the different compositions of the carrier layer and intervening layer.
  • the endpoint criteria is associated with a change in friction between a back-side surface of the donor substrate and a polishing surface in contact with the back-side surface of the donor substrate.
  • Detection of the intervening layer may be enhanced where the removal process is selective to the carrier layer relative to the intervening layer as non-uniformity in the carrier removal process may be mitigated by an etch rate delta between the carrier layer and intervening layer. Detection may even be skipped if the grind, polish and/or etch operation removes the intervening layer at a rate sufficiently below the rate at which the carrier layer is removed. If an endpoint criteria is not employed, a grind, polish and/or etch operation of a predetermined fixed duration may stop on the intervening layer material if the thickness of the intervening layer is sufficient for the selectivity of the etch.
  • the carrier etch rate: intervening layer etch rate is 3:1-10:1, or more.
  • the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be removed uniformly by a polish, for example. Alternatively, a thickness of the intervening layer may be removed with a masked or blanket etch process. The process may employ the same polish or etch process as that employed to thin the carrier, or may be a distinct process with distinct process parameters. For example, where the intervening layer provides an etch stop for the carrier removal process, the latter operation may employ a different polish or etch process that favors removal of the intervening layer over removal of the device layer.
  • the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled than that employed for removal of the carrier layer.
  • a CMP process employed may, for example employ a slurry that offers very high selectively (e.g., 100:1-300:1, or more) between semiconductor (e.g., silicon) and dielectric material (e.g., SiO) surrounding the device layer and embedded within the intervening layer, for example, as electrical isolation between adjacent device regions.
  • back-side processing may commence on an exposed back-side of the device layer or specific device regions there in.
  • the back-side device layer processing includes a further polish or wet/dry etch through a thickness of the device layer disposed between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region.
  • such an etch may be a patterned etch or a materially selective etch that imparts significant non-planarity or topography into the device layer back-side surface.
  • the patterning may be within a device cell (i.e., "intra-cell” patterning) or may be across device cells (i.e., "inter-cell” patterning).
  • at least a partial thickness of the intervening layer is employed as a hard mask for back-side device layer patterning.
  • a masked etch process may preface a correspondingly masked device layer etch.
  • the above described processing scheme may result in a donor-host substrate assembly that includes IC devices that have a back-side of an intervening layer, a back-side of the device layer, and/or back-side of one or more semiconductor regions within the device layer, and/or front-side metallization revealed. Additional back-side processing of any of these revealed regions may then be performed during downstream processing.
  • Figure 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure.
  • a semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including protruding fin portion 504 and sub-fin region 505) within a trench isolation region 506.
  • the non-planar active region is separated into nanowires (such as nanowires 504A and 504B) above sub-fin region 505, as is represented by the dashed lines.
  • a non-planar active region 504 is referenced below as a protruding fin portion.
  • the sub-fin region 505 also includes a relaxed buffer layer 542 and a defect modification layer 540, as is depicted.
  • a gate line 508 is disposed over the protruding portions 504 of the non-planar active region (including, if applicable, surrounding nanowires 504A and 504B), as well as over a portion of the trench isolation region 506.
  • gate line 508 includes a gate electrode 550 and a gate dielectric layer 552.
  • gate line 508 may also include a dielectric cap layer 554.
  • a gate contact 514, and overlying gate contact via 516 are also seen from this perspective, along with an overlying metal interconnect 560, all of which are disposed in inter-layer dielectric stacks or layers 570.
  • the gate contact 514 is, in one embodiment, disposed over trench isolation region 506, but not over the non-planar active regions. In another embodiment, the gate contact 514 is over the non-planar active regions.
  • the semiconductor structure or device 500 is a non-planar device such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device.
  • a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body.
  • the gate electrode stacks of gate lines 508 surround at least a top surface and a pair of sidewalls of the three-dimensional body.
  • an interface 580 exists between a protruding fin portion 504 and sub-fin region 505.
  • the interface 580 can be a transition region between a doped sub-fin region 505 and a lightly or undoped upper fin portion 504.
  • each fin is approximately 10 nanometers wide or less, and sub-fin dopants are optionally supplied from an adjacent solid state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.
  • source or drain regions of or adjacent to the protruding fin portions 504 are on either side of the gate line 508, i.e., into and out of the page.
  • the material of the protruding fin portions 504 in the source or drain locations is removed and replaced with another semiconductor material, e.g., by epitaxial deposition to form epitaxial source or drain structures.
  • the source or drain regions may extend below the height of dielectric layer of trench isolation region 506, i.e., into the sub-fin region 505.
  • the more heavily doped sub-fin regions i.e., the doped portions of the fins below interface 580, inhibits source to drain leakage through this portion of the bulk semiconductor fins.
  • the source and drain regions have associated asymmetric source and drain contact structures, as described above in association with Figure 4J .
  • fins 504/505 are composed of a crystalline silicon germanium layer which may be doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof.
  • a charge carrier such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof.
  • trench isolation region 506 and trench isolation regions (trench isolations structures or trench isolation layers) described throughout may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions.
  • trench isolation region 506 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.
  • Gate line 508 may be composed of a gate electrode stack which includes a gate dielectric layer 552 and a gate electrode layer 550.
  • the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material.
  • the gate dielectric layer 552 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.
  • a portion of gate dielectric layer 552 may include a layer of native oxide formed from the top few layers of the substrate fin 504.
  • the gate dielectric layer 552 is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • the gate electrode layer 550 is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides.
  • the gate electrode layer 550 is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer.
  • the gate electrode layer 550 may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer 550 may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten and conductive metal oxides, e.g., ruthenium oxide.
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • At least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts.
  • the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.
  • Gate contact 514 and overlying gate contact via 516 may be composed of a conductive material.
  • one or more of the contacts or vias are composed of a metal species.
  • the metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).
  • a contact pattern which is essentially perfectly aligned to an existing gate pattern 508 is formed while eliminating the use of a lithographic step with exceedingly tight registration budget.
  • the contact pattern is a vertically symmetric contact pattern, or an asymmetric contact pattern such as described in association with Figure 4J .
  • all contacts are front-side connected and are not asymmetric.
  • the self-aligned approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings.
  • a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation.
  • a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines.
  • a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.
  • providing structure 500 involves fabrication of the gate stack structure 508 by a replacement gate process.
  • dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material.
  • a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing.
  • dummy gates are removed by a dry etch or wet etch process.
  • dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF 6 .
  • dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH 4 OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.
  • a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region, e.g., over a fin 505, and in a same layer as a trench contact via.
  • the structure of Figure 5 is formed using a gate aligned fin cut isolation approach, such as described in association with Figures 1A-1D and 2 .
  • the processes described herein may be used to fabricate one or a plurality of semiconductor devices.
  • the semiconductor devices may be transistors or like devices.
  • the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors.
  • MOS metal-oxide semiconductor
  • the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessed double gate device, or a FIN-FET.
  • One or more embodiments may be particularly useful for fabricating semiconductor devices at a sub-10 nanometer (10 nm) technology node.
  • interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material.
  • suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO 2 )), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof.
  • the interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.
  • metal lines or interconnect line material is composed of one or more metal or other conductive structures.
  • a common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material.
  • the term metal includes alloys, stacks, and other combinations of multiple metals.
  • the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc.
  • the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers.
  • interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.
  • the interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.
  • hardmask materials, capping layers, or plugs are composed of dielectric materials different from the interlayer dielectric material.
  • different hardmask, capping or plug materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers.
  • a hardmask layer, capping or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof.
  • Other suitable materials may include carbon-based materials.
  • Other hardmask, capping or plug layers known in the arts may be used depending upon the particular implementation.
  • the hardmask, capping or plug layers may be formed by CVD, PVD, or by other deposition methods.
  • lithographic operations are performed using 193nm immersion lithography (i193), EUV and/or EBDW lithography, or the like.
  • a positive tone or a negative tone resist may be used.
  • a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer.
  • the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.
  • one or more embodiments are directed to neighboring semiconductor structures or devices separated by self-aligned gate endcap (SAGE) structures.
  • Particular embodiments may be directed to integration of multiple width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by a SAGE wall.
  • nanowires/nanoribbons are integrated with multiple Wsi in a SAGE architecture portion of a front-end process flow.
  • Such a process flow may involve integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance.
  • Associated epitaxial source or drain regions may be embedded (e.g., portions of nanowires removed and then source or drain (S/D) growth is performed).
  • advantages of a self-aligned gate endcap (SAGE) architecture may include the enabling of higher layout density and, in particular, scaling of diffusion to diffusion spacing.
  • Figure 6 illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure.
  • an integrated circuit structure 600 includes a substrate 602 having fins 604 protruding there from by an amount 606 above an isolation structure 608 laterally surrounding lower portions of the fins 604. Upper portions of the fins may include a relaxed buffer layer 622 and a defect modification layer 620, as is depicted. Corresponding nanowires 605 are over the fins 604. A gate structure may be formed over the integrated circuit structure 600 to fabricate a device. However, breaks in such a gate structure may be accommodated for by increasing the spacing between fin 604/nanowire 605 pairs.
  • an integrated circuit structure 650 includes a substrate 652 having fins 654 protruding therefrom by an amount 656 above an isolation structure 658 laterally surrounding lower portions of the fins 654. Upper portions of the fins may include a relaxed buffer layer 672 and a defect modification layer 670, as is depicted. Corresponding nanowires 655 are over the fins 654. Isolating SAGE walls 660 (which may include a hardmask thereon, as depicted) are included within the isolation structure 652 and between adjacent fin 654/nanowire 655 pairs.
  • a gate structure may be formed over the integrated circuit structure 600, between insolating SAGE walls to fabricate a device. Breaks in such a gate structure are imposed by the isolating SAGE walls. Since the isolating SAGE walls 660 are self-aligned, restrictions from conventional approaches can be minimized to enable more aggressive diffusion to diffusion spacing. Furthermore, since gate structures include breaks at all locations, individual gate structure portions may be layer connected by local interconnects formed over the isolating SAGE walls 660.
  • the SAGE walls 660 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion.
  • a fabrication process for structures associated with Figure 6 involves use of a process scheme that provides a gate-all-around integrated circuit structure having epitaxial source or drain structures.
  • the structure of part (b) of Figure 6 is formed using a gate aligned fin cut isolation approach, such as described in association with Figures 1A-1D and 2 .
  • a self-aligned gate endcap (SAGE) processing scheme involves the formation of gate/trench contact endcaps self-aligned to fins without requiring an extra length to account for mask mis-registration.
  • embodiments may be implemented to enable shrinking of transistor layout area.
  • Embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls or self-aligned gate endcap (SAGE) walls.
  • Figure 7 illustrate cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure.
  • SAGE self-aligned gate endcap
  • a starting structure includes a nanowire patterning stack 704 above a substrate 702.
  • a lithographic patterning stack 706 is formed above the nanowire patterning stack 704.
  • the nanowire patterning stack 704 includes alternating sacrificial layers 710 and nanowire layers 712, which may be above a relaxed buffer layer 782 and a defect modification layer 780, as is depicted.
  • a protective mask 714 is between the nanowire patterning stack 704 and the lithographic patterning stack 706.
  • the lithographic patterning stack 706 is trilayer mask composed of a topographic masking portion 720, an anti-reflective coating (ARC) layer 722, and a photoresist layer 724.
  • the topographic masking portion 720 is a carbon hardmask (CHM) layer and the anti-reflective coating layer 722 is a silicon ARC layer.
  • CHM carbon hardmask
  • the stack of part (a) is lithographically patterned and then etched to provide an etched structure including a patterned substrate 702 and trenches 730.
  • the structure of part (b) has an isolation layer 740 and a SAGE material 742 formed in trenches 730.
  • the structure is then planarized to leave patterned topographic masking layer 720' as an exposed upper layer.
  • the isolation layer 740 is recessed below an upper surface of the patterned substrate 702, e.g., to define a protruding fin portion and to provide a trench isolation structure 741 beneath SAGE walls 742.
  • the sacrificial layers 710 are removed at least in the channel region to release nanowires 712A and 712B.
  • a gate stacks may be formed around nanowires 712B or 712A, over protruding fins of substrate 702, and between SAGE walls 742.
  • the remaining portion of protective mask 714 is removed prior to formation of the gate stacks.
  • the remaining portion of protective mask 714 is retained as an insulating fin hat as an artifact of the processing scheme.
  • an integrated circuit structure includes multiple width (multi-Wsi) nanowires.
  • structures of 712B and 712A may be differentiated as nanowires and nanoribbons, respectively, both such structures are typically referred to herein as nanowires.
  • a fabrication process for structures associated with Figure 7 involves use of a process scheme that provides a gate-all-around integrated circuit structure having epitaxial source or drain structures.
  • the structure of part (e) Figure 7 is formed using a gate aligned fin cut isolation approach, such as described in association with Figures 1A-1D and 2 .
  • self-aligned gate endcap (SAGE) isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another.
  • Exemplary materials or material combinations include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.
  • Other exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide.
  • Figure 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure.
  • Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 8A , as taken along the a-a' axis.
  • Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of Figure 8A , as taken along the b-b' axis.
  • an integrated circuit structure 800 includes one or more vertically stacked nanowires (804 set) above a substrate 802.
  • a relaxed buffer layer 802C, a defect modification layer 802B, and a lower substrate portion 802A are included in substrate 802, as is depicted.
  • An optional fin below the bottommost nanowire and formed from the substrate 802 is not depicted for the sake of emphasizing the nanowire portion for illustrative purposes.
  • Embodiments herein are targeted at both single wire devices and multiple wire devices. As an example, a three nanowire-based devices having nanowires 804A, 804B and 804C is shown for illustrative purposes.
  • nanowire 804A is used as an example where description is focused on one of the nanowires. It is to be appreciated that where attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or essentially the same attributes for each of the nanowires.
  • Each of the nanowires 804 includes a channel region 806 in the nanowire.
  • the channel region 806 has a length (L).
  • the channel region also has a perimeter (Pc) orthogonal to the length (L).
  • a gate electrode stack 808 surrounds the entire perimeter (Pc) of each of the channel regions 806.
  • the gate electrode stack 808 includes a gate electrode along with a gate dielectric layer between the channel region 806 and the gate electrode (not shown).
  • the channel region is discrete in that it is completely surrounded by the gate electrode stack 808 without any intervening material such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments having a plurality of nanowires 804, the channel regions 806 of the nanowires are also discrete relative to one another.
  • integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810/812.
  • the pair of non-discrete source or drain regions 810/812 is on either side of the channel regions 806 of the plurality of vertically stacked nanowires 804. Furthermore, the pair of non-discrete source or drain regions 810/812 is adjoining for the channel regions 806 of the plurality of vertically stacked nanowires 804.
  • the pair of non-discrete source or drain regions 810/812 is directly vertically adjoining for the channel regions 806 in that epitaxial growth is on and between nanowire portions extending beyond the channel regions 806, where nanowire ends are shown within the source or drain structures.
  • the pair of non-discrete source or drain regions 810/812 is indirectly vertically adjoining for the channel regions 806 in that they are formed at the ends of the nanowires and not between the nanowires.
  • the source or drain regions 810/812 are non-discrete in that there are not individual and discrete source or drain regions for each channel region 806 of a nanowire 804. Accordingly, in embodiments having a plurality of nanowires 804, the source or drain regions 810/812 of the nanowires are global or unified source or drain regions as opposed to discrete for each nanowire. That is, the non-discrete source or drain regions 810/812 are global in the sense that a single unified feature is used as a source or drain region for a plurality (in this case, 3) of nanowires 804 and, more particularly, for more than one discrete channel region 806.
  • each of the pair of non-discrete source or drain regions 810/812 is approximately rectangular in shape with a bottom tapered portion and a top vertex portion, as depicted in Figure 8B .
  • the source or drain regions 810/812 of the nanowires are relatively larger yet discrete non-vertically merged epitaxial structures such as nubs described in association with Figures 4A-4J .
  • integrated circuit structure 800 further includes a pair of contacts 814, each contact 814 on one of the pair of non-discrete source or drain regions 810/812.
  • each contact 814 completely surrounds the respective non-discrete source or drain region 810/812.
  • the entire perimeter of the non-discrete source or drain regions 810/812 may not be accessible for contact with contacts 814, and the contact 814 thus only partially surrounds the non-discrete source or drain regions 810/812, as depicted in Figure 8B .
  • the entire perimeter of the non-discrete source or drain regions 810/812 is surrounded by the contacts 814.
  • integrated circuit structure 800 further includes a pair of spacers 816.
  • outer portions of the pair of spacers 816 may overlap portions of the non-discrete source or drain regions 810/812, providing for "embedded" portions of the non-discrete source or drain regions 810/812 beneath the pair of spacers 816.
  • the embedded portions of the non-discrete source or drain regions 810/812 may not extend beneath the entirety of the pair of spacers 816.
  • Substrate 802 may be composed of a material suitable for integrated circuit structure fabrication.
  • substrate 802 includes a lower bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or a group III-V compound semiconductor material.
  • An upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride is on the lower bulk substrate.
  • the structure 800 may be fabricated from a starting semiconductor-on-insulator substrate.
  • the structure 800 is formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer.
  • the structure 800 is formed directly from a bulk substrate and doping is used to form electrically isolated active regions, such as nanowires, thereon.
  • the first nanowire i.e., proximate the substrate
  • the nanowires 804 may be sized as wires or ribbons, as described below, and may have squared-off or rounder corners.
  • the nanowires 804 are composed of a material such as, but not limited to, silicon, germanium, or a combination thereof.
  • the nanowires are single-crystalline.
  • a single-crystalline nanowire may be based from a (100) global orientation, e.g., with a ⁇ 100> plane in the z-direction. As described below, other orientations may also be considered.
  • the dimensions of the nanowires 804, from a cross-sectional perspective are on the nano-scale.
  • the smallest dimension of the nanowires 804 is less than approximately 20 nanometers.
  • the nanowires 804 are composed of a strained material, particularly in the channel regions 806.
  • each of the channel regions 806 has a width (Wc) and a height (Hc), the width (Wc) approximately the same as the height (Hc). That is, in both cases, the channel regions 806 are square-like or, if corner-rounded, circle-like in cross-section profile. In another aspect, the width and height of the channel region need not be the same, such as the case for nanoribbons as described throughout.
  • an integrated circuit structure includes non-planar devices such as, but not limited to, a finFET or a tri-gate device with corresponding one or more overlying nanowire structures.
  • a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body.
  • the gate structures surround at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.
  • Figures 8A-8C is formed using a gate aligned fin cut isolation approach, such as described in association with Figures 1A-1D and 2 .
  • an underlying substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate.
  • the substrate is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof, to form an active region.
  • a charge carrier such as but not limited to phosphorus, arsenic, boron, gallium or a combination thereof.
  • the concentration of silicon atoms in a bulk substrate is greater than 97%.
  • a bulk substrate is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate.
  • a bulk substrate may alternatively be composed of a group III-V material.
  • a bulk substrate is composed of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof.
  • a bulk substrate is composed of a group III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.
  • Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
  • FIG. 9 illustrates a computing device 900 in accordance with one implementation of an embodiment of the present disclosure.
  • the computing device 900 houses a board 902.
  • the board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906.
  • the processor 904 is physically and electrically coupled to the board 902.
  • the at least one communication chip 906 is also physically and electrically coupled to the board 902.
  • the communication chip 906 is part of the processor 904.
  • computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna,
  • the communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 900 may include a plurality of communication chips 906.
  • a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904.
  • the integrated circuit die of the processor 904 may include one or more structures, such as integrated circuit structures having a gate aligned fin cut, built in accordance with implementations of embodiments of the present disclosure.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 906 also includes an integrated circuit die packaged within the communication chip 906.
  • the integrated circuit die of the communication chip 906 may include one or more structures, such as integrated circuit structures having a gate aligned fin cut, built in accordance with implementations of embodiments of the present disclosure.
  • another component housed within the computing device 900 may contain an integrated circuit die that includes one or structures, such as integrated circuit structures having a gate aligned fin cut, built in accordance with implementations of embodiments of the present disclosure.
  • the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 900 may be any other electronic device that processes data.
  • FIG. 10 illustrates an interposer 1000 that includes one or more embodiments of the present disclosure.
  • the interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004.
  • the first substrate 1002 may be, for instance, an integrated circuit die.
  • the second substrate 1004 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004.
  • BGA ball grid array
  • the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000.
  • the first and second substrates 1002/1004 are attached to the same side of the interposer 1000.
  • three or more substrates are interconnected by way of the interposer 1000.
  • the interposer 1000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1000 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012.
  • the interposer 1000 may further include embedded devices 1014, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000.
  • apparatuses or processes disclosed herein may be used in the fabrication of interposer 1000 or in the fabrication of components included in the interposer 1000.
  • embodiments of the present disclosure include gate aligned fin cut for advanced integrated circuit structure fabrication.
  • Example embodiment 1 An integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment.
  • a first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment.
  • a second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment.
  • An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.
  • Example embodiment 2 The integrated circuit structure of example embodiment 1, wherein the second fin segment is a dummy fin segment.
  • Example embodiment 3 The integrated circuit structure of example embodiment 1 or 2, wherein the first fin segment includes an epitaxial source or drain structure at a second fin end of the first fin segment, and the second fin segment does not include an epitaxial source or drain structure at a second fin end of the second fin segment.
  • Example embodiment 4 The integrated circuit structure of example embodiment 1, 2 or 3, wherein the fin includes a plurality of horizontally stacked nanowires.
  • Example embodiment 5 The integrated circuit structure of example embodiment 1, 2 or 3, wherein the fin is a unitary body.
  • Example embodiment 6 A method of fabricating an integrated circuit structure includes forming a fin along a first direction, forming a plurality of gate structures over the fins, individual ones of the plurality of gate structures along a second direction orthogonal to the first direction, etching portions of the fin between the individual ones of the plurality of gate structures to form a plurality of fin segments, and forming an isolation structure between a first fin segment and a second fin segment of the plurality of fin segments.
  • Example embodiment 7 The method of example embodiment 6, further including forming an epitaxial source or drain structure between and coupling the second fin segment and a third fin segment of the plurality of fin segments.
  • Example embodiment 8 The method of example embodiment 6 or 7, wherein the first fin segment is a dummy fin segment.
  • Example embodiment 9 The method of example embodiment 6, 7 or 8, wherein the fin includes a plurality of horizontally stacked nanowires.
  • Example embodiment 10 The method of example embodiment 6, 7 or 8, wherein the fin is a unitary body.
  • a computing device includes a board, and a component coupled to the board.
  • the component includes an integrated circuit structure including a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment.
  • a first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment.
  • a second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment.
  • An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.
  • Example embodiment 12 The computing device of example embodiment 11, further including a memory coupled to the board.
  • Example embodiment 13 The computing device of example embodiment 11 or 12, further including a communication chip coupled to the board.
  • Example embodiment 14 The computing device of example embodiment 11, 12 or 13, wherein the component is a packaged integrated circuit die.
  • Example embodiment 15 The computing device of example embodiment 11, 12, 13 or 14, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
  • Example embodiment 16 A computing device includes a board, and a component coupled to the board.
  • the component includes an integrated circuit structure fabricated according to a method including forming a fin along a first direction, forming a plurality of gate structures over the fins, individual ones of the plurality of gate structures along a second direction orthogonal to the first direction, etching portions of the fin between the individual ones of the plurality of gate structures to form a plurality of fin segments, and forming an isolation structure between a first fin segment and a second fin segment of the plurality of fin segments.
  • Example embodiment 17 The computing device of example embodiment 16, further including a memory coupled to the board.
  • Example embodiment 18 The computing device of example embodiment 16 or 17, further including a communication chip coupled to the board.
  • Example embodiment 19 The computing device of example embodiment 16, 17 or 18, wherein the component is a packaged integrated circuit die.
  • Example embodiment 20 The computing device of example embodiment 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
EP22169877.2A 2021-06-04 2022-04-26 Gate-ausgerichteter rippenschnitt zur herstellung fortschrittlicher integrierter schaltkreisstrukturen Pending EP4099373A1 (de)

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US17/339,160 US20220392808A1 (en) 2021-06-04 2021-06-04 Gate aligned fin cut for advanced integrated circuit structure fabrication

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180211955A1 (en) * 2017-01-25 2018-07-26 International Business Machines Corporation Fin Cut to Prevent Replacement Gate Collapse on STI
US20200126867A1 (en) * 2018-10-17 2020-04-23 International Business Machines Corporation Stress modulation of nfet and pfet fin structures
US20200373402A1 (en) * 2019-05-22 2020-11-26 Samsung Electronics Co., Ltd. Semiconductor device
US10916534B2 (en) * 2018-07-19 2021-02-09 Samsung Electronics Co., Ltd. Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180211955A1 (en) * 2017-01-25 2018-07-26 International Business Machines Corporation Fin Cut to Prevent Replacement Gate Collapse on STI
US10916534B2 (en) * 2018-07-19 2021-02-09 Samsung Electronics Co., Ltd. Semiconductor device
US20200126867A1 (en) * 2018-10-17 2020-04-23 International Business Machines Corporation Stress modulation of nfet and pfet fin structures
US20200373402A1 (en) * 2019-05-22 2020-11-26 Samsung Electronics Co., Ltd. Semiconductor device

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