EP4062461A1 - Fan out structure for light-emitting diode (led) device and lighting system - Google Patents

Fan out structure for light-emitting diode (led) device and lighting system

Info

Publication number
EP4062461A1
EP4062461A1 EP20821568.1A EP20821568A EP4062461A1 EP 4062461 A1 EP4062461 A1 EP 4062461A1 EP 20821568 A EP20821568 A EP 20821568A EP 4062461 A1 EP4062461 A1 EP 4062461A1
Authority
EP
European Patent Office
Prior art keywords
silicon backplane
substrate
array
top surface
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20821568.1A
Other languages
German (de)
French (fr)
Inventor
Tze Yang Hin
Anantharaman Vaidyanathan
Srini Banna
Ronald Johannes BONNE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lumileds LLC
Original Assignee
Lumileds LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/750,839 external-priority patent/US11621173B2/en
Application filed by Lumileds LLC filed Critical Lumileds LLC
Publication of EP4062461A1 publication Critical patent/EP4062461A1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]

Definitions

  • An LED lighting system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces.
  • First redistribution layers are provided on the top surface of the silicon backplane and the top surface of the substrate.
  • Second redistribution layers are provided on the bottom surface of the silicon backplane and the bottom surface of the substrate.
  • At least one via extends through the substrate between the first redistribution layers and the second redistribution layers and is filled with a metal material.
  • FIG. 1 A is a top view of an example LED array
  • Fig. 1 B is a cross-sectional view of an example LED lighting system
  • FIG. 1 C is a top view of the example LED lighting system of FIG. 1 B;
  • FIG. 1 D is a bottom view of the example LED lighting system of FIG. 1 B;
  • FIG. 2 is a cross-sectional view of an example application system that incorporates the
  • FIG. 3 is a diagram of an example vehicle headlamp system that incorporates the LED lighting system of FIG. 1B;
  • FIG. 4 is a diagram of another example vehicle headlamp system;
  • FIG. 5 is a flow diagram of an example method of manufacturing an LED lighting system, such as the LED lighting system of FIG. 1 B;
  • FIGs. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I and 6J are cross-sectional views of the LED lighting system at various stages in the manufacturing method.
  • FIG. 7 is a bottom view representing the bottom surface of the LED lighting system of
  • FIG. 6E is a diagrammatic representation of FIG. 6E.
  • LEDs, LED arrays, electrical components and/or electronic components are housed on one, two or more electronics boards may also depend on design constraints and/or application.
  • LEDs Semiconductor light emitting devices
  • UV ultraviolet
  • IR infrared
  • LEDs optical power emitting devices
  • UV ultraviolet
  • IR infrared
  • LEDs may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, or the like. Due to their compact size and lower power requirements, for example, LEDs may be attractive candidates for many different applications. For example, they may be used as light sources (e.g., flash lights and camera flashes) for hand-held battery-powered devices, such as cameras and cell phones.
  • FIG. 1A is a top view of an example LED array 102.
  • HUD heads up display
  • horticultural lighting street lighting
  • torch for video general illumination (e.g., home, shop, office and studio lighting, theater/stage lighting and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as back lights for displays, and IR spectroscopy.
  • a single LED may provide light that is less bright than an incandescent light source, and, therefore, multi-junction devices or arrays of LEDs (such as monolithic LED arrays, micro LED arrays, etc.) may be used for applications where more brightness is desired or required.
  • FIG. 1A is a top view of an example LED array 102. In the example illustrated in FIG.
  • the LED array 102 is an array of emitters 120.
  • LED arrays may be used for any application, such as those requiring precision control of LED array emitters.
  • Emitters 120 in the LED array 102 may be individually addressable or may be addressable in groups/subsets.
  • the LED array 102 may include emitters 120 that each have a width wi.
  • the width wi may be approximately 100pm or less (e.g., 40 pm).
  • Lanes 122 between the emitters 120 may be a width, W2, wide. In embodiments, the width may be approximately 20pm or less (e.g., 5pm).
  • the lanes 122 may provide an air gap between adjacent emitters or may contain other material.
  • a distance di from the center of one emitter 120 to the center of an adjacent emitter 120 may be approximately 120pm or less (e.g., 45pm). It will be understood that the widths and distances provided herein are examples only and that actual widths and/or dimensions may vary.
  • the LED array 102 of FIG. 1A may include over 20,000 emitters in any applicable arrangement, such as a 200x100 matrix, a symmetric matrix, a non-symmetric matrix, or the like. It will also be understood that multiple sets of emitters, matrixes, and/or boards may be arranged in any applicable format to implement the embodiments described herein.
  • LED arrays such as the LED array 102, may include up to 20,000 or more emitters. Such arrays may have a surface area of 90 mm 2 or greater and may require significant power to power them, such as 60 watts or more.
  • An LED array such as this may be referred to as a micro LED array or simply a micro LED.
  • a micro LED may include an array of individual emitters provided on a substrate or may be a single silicon wafer or die divided into segments that form the emitters. The latter type of micro LED may be referred to as a monolithic LED.
  • a silicon backplane may be provided in close proximity to the LED array and may become extremely hot during operation. Accordingly, heat dissipation can be challenging for such devices. While some solutions are known for heat dissipation for semiconductor devices, such solutions often include structures that dissipate heat through the top of the device. Due to light-emission, however, LED arrays, such as the LED array 102 of FIG. 1A, may not be able to dissipate heat through the top of the device.
  • LED arrays such as the LED array 102
  • Embodiments described herein may provide for a low profile LED array package that may accommodate one or more passive elements and enable dissipation of heat generated by the silicon backplane and the LED array.
  • FIG. 1 B is a diagram of a cross-sectional view of an example LED lighting system 100.
  • the LED lighting system 100 includes a silicon backplane 104.
  • the silicon backplane 104 has a top surface 101 , a bottom surface 103 and side surfaces 105.
  • the side surfaces 105 of the silicon backplane 104 are surrounded by a substrate 106 formed from a molding material.
  • the substrate 106 has a top surface 107, a bottom surface 109 and side surfaces 190.
  • One or more metal layers 110 or redistribution layers (RDL) (shown in the alternative embodiment in FIG. 6E) are provided on the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106.
  • RDL redistribution layers
  • RDL 117 may be formed on at least a portion of the top surface 101 of the silicon backplane 104 and a top surface 107 of the substrate 106.
  • the RDL 117 includes two layers 116a and 116b of a dielectric material 116 and a single metal layer 112.
  • One or more vias 108 may extend through the substrate 106 and may be filled with a metal material. The vias may thus form a continuous electrical connection between the silicon backplane 104, the RDL 117 and the metallization/RDL 110.
  • An LED array such as the LED array 102 of FIG. 1A, may be provided on the top surface 101 of the silicon backplane 104 and electrically coupled thereto via an array of metal connectors (not shown in FIG. 1B).
  • electronic components 114 may be provided on the RDL 117 and electrically coupled to the LED lighting system 100 via the metal layer 112.
  • the LED array 102 may be a micro LED, such as described above with respect to FIG.
  • the LED array 102 may have a depth d1.
  • the depth d1 may be, for example, between 5 and 250 pm.
  • the silicon backplane 104 may include the circuitry and connectors that make individually addressable connections to the emitters in the LED array 102.
  • the silicon backplane may be a complementary metal-oxide semiconductor (CMOS) integrated circuit, which, in embodiments, may be an application specific integrated circuit (ASIC).
  • CMOS complementary metal-oxide semiconductor
  • ASIC application specific integrated circuit
  • the silicon backplane 104 may have a depth d3. In embodiments, the depth d3 may be, for example, between 100 pm and 1 mm.
  • a structure made up of the silicon backplane 104, the substrate 106, the metallization/RDL 110, the RDL 117 and the vias 108 may have a depth d2. In embodiments, the depth d2 may be, for example, between 100 pm and 1 mm. Since the silicon backplane 104 is integrated into the substrate, and the LED array 102 is provided on top of the silicon backplane 104, the LED lighting system 100 may have a lower profile relative to systems that vertically stack
  • the RDL 117 includes two layers 116a and 116b of the dielectric material 116 and a single metal layer 112.
  • the first layer 116a of the two layers of the dielectric material 116 may be on the top surface 107 of the substrate 106 and at least a portion of the top surface 101 of the silicon backplane 104.
  • the metal layer 112 may be patterned on the first layer 116a of the dielectric material 116, such as by copper plating and copper etching.
  • the second layer 116b of the dielectric material 116 may be on top of the patterned metal layer 112 and exposed portions of the first layer 116a of the dielectric material 116.
  • RDL consisting of two layers of dielectric material and a single layer of metal are shown in FIG. 1 B, one of ordinary skill in the art will recognize that the RDL 117 may include more or less layers of the dielectric material and/or more metal layers, depending on design constraints.
  • the dielectric material 116 may be any suitable dielectric material.
  • the dielectric material may be a polymer dielectric material, such as polyimide.
  • the RDL 117 may extend from a perimeter region of the silicon backplane 104 towards the side surfaces 190 of the substrate 106. This may both accommodate the LED array 102 attached to the top surface 101 of the silicon backplane 104 in a central region and help with heat dissipation by containing the dielectric materials that may further insulate the LED lighting system 100 to areas away from the highest heat areas in the center of the LED lighting system 100.
  • the metal layer 112 may have portions that are exposed from the dielectric material 116 to form bond pads.
  • the metal layer 112 may include portions that extend between the perimeter region of the silicon backplane 104 and the bond pads to create a continuous electrical connection therebetween.
  • the bond pads may be electrically coupled to the vias 108 to create a continuous electrical connection between top and bottom surfaces of the LED lighting system 100.
  • the bond pads may be placed in the perimeter region of the substrate or spaced apart from but closer to the array (as shown in FIG. 1 C, for example).
  • the metallization/RDL 110 may be formed in a number of different ways.
  • the metallization/RDL 110 is a metal layer including a first portion that is electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region and second portions that fan out from a perimeter region of the silicon backplane 104 toward the side surfaces 190 of the substrate 106.
  • the first portion and the second portions may be electrically insulated from one another in embodiments.
  • the second portions may extend from the silicon backplane 104 and join with individual vias 108 at bond pads, electrically coupling the silicon backplane 104 to the metal layer 112 on the top surface.
  • Both the first and second portions of the metal layer 110 may be coupled to an external circuit board (not shown), such as by soldering. This may enable a direct connection between the LED lighting system 100 and the external circuit board, which provides improved heat sinking through the bottom of the LED lighting system. Additionally, this structure may enable communication between the silicon backplane 104, the LED array 102, the passive components 114 on the substrate 106 and any electronic components on the external circuit board.
  • the metallization/RDL 110 may be a combination of a metal layer and RDL.
  • a metal layer may be electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region.
  • the fanout may be accomplished using RDL instead of the metal layer.
  • the LED lighting device 100 may have RDL on both the top and bottom surfaces.
  • the metallization/RDL 110 may be a thin structure compared to conventional silicon device packages and may include considerably less dielectric material than conventional silicon device packages.
  • the metal layer 100 in the embodiment shown in FIG. 1 B may be a single metal layer, and the RDL may include as few dielectric layers as possible. This may increase the efficiency of the heat dissipation in such packages and enable packaging for micro-LEDs and CMOS backplanes that may emit substantial heat.
  • the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106 are co-planar.
  • the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106 are co-planar.
  • This arrangement may allow for the slimmest possible packaging and ease of manufacture.
  • the substrate 106 is molded, the substrate 106 may take any shape, such as, for example, where the substrate has a top surface 107 that is higher than the top surface 101 of the silicon backplane 104 to further distance the electronic components 114 from the high heat regions of the LED lighting system 100.
  • these surfaces may not be co- planar.
  • FIG. 1 C is a top view showing a top surface 130 of the example LED lighting system 100 of FIG. 1 B.
  • the top surface 130 of the LED lighting system includes the top-most layer 116b of the dielectric material 116 in the RDL 117.
  • Electronic components 114 are electrically coupled to the metal 112 in the RDL and exposed from the dielectric material 116. In embodiments, an electronic component 114 may not be electrically coupled to all regions of the metal 112 and, thus, the top surface 130 may, in embodiments, also include some regions of the metal 112 exposed from the dielectric material 116.
  • a top surface of at least a portion of the silicon backplane 104 is shown in FIG. 1 C and includes the portion of the top surface of the silicon backplane 104 that is not covered by the LED array 102 or the dielectric material 116.
  • a top surface of the LED array 102 is also shown mounted on the top surface of the silicon backplane 104.
  • the LED lighting system 100 has a length £i and a width
  • the length £i may be approximately 20 mm and the width m ⁇ may be approximately 15 mm.
  • the silicon backplane 104 may have a length fe and a width 2.
  • the length £ may be approximately 15.5 mm and the width m2 may be approximately 6.5 mm.
  • the LED array 102 may have a length £ and a width 3
  • the length £ may be approximately 11 mm and the width ms may be approximately 4.4 mm.
  • an LED array package may be provided that has a relatively large surface area (300 mm 2 in the above example) with a relatively large amount of the surface area not taken up by the LED array (which has a surface area of approximately 100 mm 2 in the above example). Accordingly, this design provides ample space for attachment of electronic components on the LED array package.
  • FIG. 1 D is a bottom view showing a bottom surface 140 of the example LED lighting system 100 of FIG. 1 B.
  • the bottom surface 140 includes regions of the substrate 106 and regions of the metal 110 or solder pads coupled thereto that are exposed from the molding material 106.
  • some regions of the substrate may be covered by metallization and/or portions of the RDL that interconnect the silicon backplane and the bond pads, although these are not shown in FIG. 1 D.
  • the interconnecting metal regions and/or RDL may be covered by a dielectric material or other encapsulating or protective material (not shown in FIG. 1 D).
  • the application system 200 may include a circuit board 150 that has a number of bond pads 152.
  • exposed metal regions/bond pads of the RDL/metallization 110 of the LED lighting system 100 are bonded directly to the bond pads 152 of the circuit board 150.
  • the direct bond between the metal layer 110 on the bottom surface of the silicon backplane 104 and the circuit board 150 enables efficient heat transfer from the LED lighting system 100 to the circuit board 150 for heat sinking purposes without need for additional heat dissipating structures over the top of the LED lighting system 100 (or elsewhere) that may, for example, otherwise block light emission from the LED array 102.
  • the circuit board 150 may be part of a larger system used in specific applications, such as vehicle lighting or flash applications (example vehicle lighting systems are described below with respect to FIGs. 3 and 4). In such systems, some of the passive components used in the application may be the components 114 and may be provided directly on the LED lighting system 100 before attachment to the circuit board 150.
  • the circuit board 150 may include other circuit elements required for the larger system in addition to a heat sink.
  • the RDL 117, the RDL/metallization 110 and the vias 108 may provide a continuous electrical connection between the components 114, the silicon backplane 104 and the circuit board 150.
  • FIG. 3 is a diagram of an example vehicle headlamp system 300 that may incorporate the LED lighting system 100 of FIG. 1 B.
  • the example vehicle headlamp system 300 illustrated in FIG. 3 includes power lines 302, a data bus 304, an input filter and protection module 306, a bus transceiver 308, a sensor module 310, an LED direct current to direct current (DC/DC) module 312, a logic low- dropout (LDO) module 314, a micro-controller 316 and an active head lamp 318.
  • the active head lamp 318 may include an LED lighting system, such as the LED lighting system 100 of FIG. 1 B.
  • the LED lighting system 100 provides ample space and bond pads on the top surface of the substrate such that one, more, or all of the modules illustrated in FIG. 3 may be accommodated on the top surface of the LED lighting system 100. Modules not provided on the top surface of the LED lighting system 100 may be provided on the circuit board 150 (as shown in FIG. 2). In some embodiments, some electronic components of some or all of the modules in the vehicle lighting system 300 may be accommodated on the top surface of the LED lighting system 100 and some may be provided on the circuit board 150 (shown in FIG. 2).
  • the power lines 302 may have inputs that receive power from a vehicle, and the data bus 304 may have inputs/outputs over which data may be exchanged between the vehicle and the vehicle headlamp system 300.
  • the vehicle headlamp system 300 may receive instructions from other locations in the vehicle, such as instructions to turn on turn signaling or turn on headlamps, and may send feedback to other locations in the vehicle if desired.
  • the sensor module 310 may be communicatively coupled to the data bus 304 and may provide additional data to the vehicle headlamp system 300 or other locations in the vehicle related to, for example, environmental conditions (e.g., time of day, rain, fog, or ambient light levels), vehicle state (e.g., parked, in-motion, speed of motion, or direction of motion), and presence/position of other objects (e.g., vehicles or pedestrians).
  • a headlamp controller that is separate from any vehicle controller communicatively coupled to the vehicle data bus may also be included in the vehicle headlamp system 300.
  • the headlamp controller may be a micro-controller, such as micro-controller (mo) 316.
  • the micro-controller 316 may be communicatively coupled to the data bus 304.
  • the input filter and protection module 306 may be electrically coupled to the power lines
  • the input filter and protection module 306 may provide electrostatic discharge (ESD) protection, load-dump protection, alternator field decay protection, and/or reverse polarity protection.
  • ESD electrostatic discharge
  • the LED DC/DC module 312 may be coupled between the filter and protection module
  • the LED DC/DC module 312 may have an input voltage between 7 and 18 volts with a nominal voltage of approximately 13.2 volts and an output voltage that may be slightly higher (e.g., 0.3 volts) than a maximum voltage for the LED array (e.g., as determined by factor or local calibration and operating condition adjustments due to load, temperature or other factors).
  • the logic LDO module 314 may be coupled to the input filter and protection module 306 to receive the filtered power.
  • the logic LDO module 314 may also be coupled to the micro-controller 314 and the active headlamp 318 to provide power to the micro-controller 314 and/or the silicon backplane (e.g., CMOS logic) in the active headlamp 318.
  • the silicon backplane e.g., CMOS logic
  • the bus transceiver 308 may have, for example, a universal asynchronous receiver transmitter (UART) or serial peripheral interface (SPI) interface and may be coupled to the microcontroller 316.
  • the micro-controller 316 may translate vehicle input based on, or including, data from the sensor module 310.
  • the translated vehicle input may include a video signal that is transferrable to an image buffer in the active headlamp module 318.
  • the micro-controller 316 may load default image frames and test for open/short pixels during startup.
  • an SPI interface may load an image buffer in CMOS. Image frames may be full frame, differential or partial frames.
  • micro-controller 316 may include control interface monitoring of CMOS status, including die temperature, as well as logic LDO output.
  • LED DC/DC output may be dynamically controlled to minimize headroom.
  • other headlamp functions such as complementary use in conjunction with side marker or turn signal lights, and/or activation of daytime running lights, may also be controlled.
  • FIG. 4 is a diagram of another example vehicle headlamp system 400.
  • the example vehicle headlamp system 400 illustrated in FIG. 4 includes an application platform 402, two LED lighting systems 406 and 408, and optics 410 and 412.
  • the two LED lighting systems 406 and 408 may be LED lighting systems, such as the LED lighting system 100 of FIG. 1 B, or may include the LED lighting system 100 plus some of all of the other modules in the vehicle headlamp system 300 of FIG. 3. In the latter embodiment, the LED lighting systems 406 and 408 may be vehicle headlamp sub-systems.
  • the LED lighting system 408 may emit light beams 414 (shown between arrows 414a and 414b in FIG. 4).
  • the LED lighting system 406 may emit light beams 416 (shown between arrows 416a and 416b in FIG. 4).
  • a secondary optic 410 is adjacent the LED lighting system 408, and the light emitted from the LED lighting system 408 passes through the secondary optic 410.
  • a secondary optic 412 is adjacent the LED lighting system 412, and the light emitted from the LED lighting system 412 passes through the secondary optic 412.
  • no secondary optics 410/412 are provided in the vehicle headlamp system.
  • the secondary optics 410/412 may be or include one or more light guides.
  • the one or more light guides may be edge lit or may have an interior opening that defines an interior edge of the light guide.
  • LED lighting systems 408 and 406 (or the active headlamp of a vehicle headlamp sub-system) may be inserted in the interior openings of the one or more light guides such that they inject light into the interior edge (interior opening light guide) or exterior edge (edge lit light guide) of the one or more light guides.
  • the one or more light guides may shape the light emitted by the LED lighting systems 408 and 406 in a desired manner, such as, for example, with a gradient, a chamfered distribution, a narrow distribution, a wide distribution, or an angular distribution.
  • the application platform 402 may provide power and/or data to the LED lighting systems
  • each LED lighting system 408 and 406 may include its own sensor module, connectivity and control module, power module, and/or LED array.
  • the vehicle headlamp system 400 may represent an automobile with steerable light beams where LEDs may be selectively activated to provide steerable light.
  • an array of LEDs e.g., the LED array 102
  • infrared cameras or detector pixels within LED systems 406 and 408 may be sensors (e.g., similar to sensors in the sensor module 310 of FIG. 3) that identify portions of a scene (e.g., roadway or pedestrian crossing) that require illumination.
  • FIG. 5 is a flow diagram of an example method 500 of manufacturing an LED lighting system, such as the LED lighting system 100 of FIG. 1 B.
  • FIGs. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I and 6J are cross-sectional views of the LED lighting system at various stages in the manufacturing method.
  • the method 500 may produce a panel level packaged high-density LED lighting system.
  • the silicon backplane may be attached to a first carrier (502) to form a first structure.
  • the silicon backplane may be attached to a temporary (e.g., plastic) carrier via an adhesive material, such as a tape or temporary adhesive.
  • An example 600A of the first structure is illustrated in FIG. 6A and includes the silicon backplane 104, the first carrier 602 and the optional adhesive material 604.
  • the silicon backplane, attached to the first carrier, may be molded (504) to form a second structure.
  • An example 600B of the second structure is illustrated in FIG. 6B and includes the first structure 600A of FIG. 6A with the molding material surrounding sides of the silicon backplane 104.
  • the molding material forms a substrate 106 with an embedded silicon backplane 104.
  • a mold may be placed over the structure 600A, filled with the molding material and cured. Any excess molding material may be removed from the top surface of the silicon backplane if needed.
  • the molding may be panel level molding, the molding material may be a polymer material, and the second structure 600B may be a plastic substrate with an embedded silicon backplane on a temporary substrate.
  • One or more vias may be formed through the substrate (506) to form a third structure.
  • the one or more vias may be formed using lasers or drills.
  • An example 600C of the third structure is illustrated in FIG. 6C and includes the silicon backplane 104 embedded in the substrate 106 with two vias 108 formed therethrough. At this stage, the silicon backplane 104 and substrate 106 with vias 108 may remain attached to the first temporary carrier 602. The vias 108 may be filled with a metal material.
  • At least one metal layer may be formed on one surface of the silicon backplane and the substrate (508). This may be done in a number of different ways.
  • a metal layer may be patterned or plated on the one surface of the silicon backplane and substrate to form a fourth structure.
  • FIG. 6D illustrates an example 600D of the fourth structure, which includes the third structure with the metal layer 110.
  • the metal layer 110 forms bond pads over the vias and regions that extend from a perimeter region of the silicon backplane 104.
  • a metal layer is also provided on a central region of the one surface of the silicon backplane 104.
  • the bottom view of the LED lighting system 100 illustrated in FIG. 1 D shows an example of this.
  • a metal layer may be formed on the one surface of the silicon backplane in a central region, and redistribution layers may be formed on the one surface of the silicon backplane and substrate adjacent the single metal layer to form a fifth structure.
  • FIG. 6E illustrates an example 600E of the fifth structure, which includes the third structure with the single metal layer 618 and the redistribution layers 616.
  • the redistribution layers 616 include layers of a dielectric material 614 and metal layers 612. While three metal layers are shown in FIG. 6E, one, two, or more than three metal layers may be used if needed due to design constraints.
  • the redistribution layers may be formed, for example, by alternating deposition of layers of the dielectric material, selective removal of portions of the dielectric material (if needed), and patterning a layer of metal on top.
  • the metal layers 612 begin in a perimeter region of the one surface of the silicon backplane and extend toward the side surfaces of the substrate.
  • the metal layers 612 are electrically coupled between the silicon backplane 104 and the vias.
  • a portion of the metal layers 612 is exposed from the dielectric material 614 to form a solder pad or separate solder pads may be formed on the outer-most surface of the outer-most dielectric layer.
  • FIG. 7 is a bottom view representing a bottom surface 700 of the LED lighting system of
  • the line 702 represents the outer-most perimeter of the substrate.
  • the line 104 represents the outer-most perimeter of a region occupied by the silicon backplane 104 relative to the outer-most perimeter of the substrate.
  • the dashed line 704 denotes a border of a region between the line 704 and the outer-most perimeter of the silicon backplane 104, which may be referred to herein as the perimeter region of the silicon backplane 104.
  • the metal layers 612 of the redistribution layers 616 may begin in the perimeter region and extend toward the side surfaces of the substrate (delineated by the line 702). There is a gap between the border 704 of the perimeter region of the silicon backplane and the single metal layer 618 formed on the one surface of the silicon backplane. This gap may be filled with the dielectric material, for example, as reflected in FIG. 6E.
  • the structure formed as a result of 508 may be flipped and attached to a second carrier (510) to form a sixth structure.
  • the structure e.g., fourth or fifth structure
  • the structure may be placed with the at least one metal layer adjacent the second carrier.
  • An example 600G of the sixth structure is illustrated in FIG. 6G and includes the second carrier 608 and the optional adhesive material 606.
  • the first carrier may be removed (512) to form a seventh structure.
  • An example 600G of the seventh structure is shown in FIG 6G.
  • Redistribution layers and an array of metal connectors may be formed on the surface exposed by removal of the second carrier (514) to form an eighth structure.
  • the array of metal connectors may be formed by plating or otherwise patterning or forming an array of copper pillar bumps on the surface.
  • An example 600H of the eighth structure is illustrated in FIG. 6H and includes the metal connectors 640 and the redistribution layers 117, including the at least one metal layer 112 and the dielectric material 116.
  • the redistribution layers may be formed by alternating deposition of layers of the dielectric material, selective removal of portions of the dielectric material (if needed), and patterning a layer of metal on top. In embodiments, over 20,000 (e.g., approximately 28,000) metal connectors may be formed on the surface.
  • An LED array may be attached to the silicon backplane via the electrical connectors
  • a ninth structure In embodiments, this may be performed by aligning the silicon backplane with the electrical connectors and heating to reflow the solder copper material in the copper pillar bumps. The reflow may create an underfill under the LED array.
  • the LED array may be a monolithic LED array.
  • An example 600I of the ninth structure is illustrated in FIG. 6I and includes the LED array 102 and the underfill.
  • the LED array may undergo a laser liftoff (LLO) process and phosphor integration (518).
  • LLO laser liftoff
  • Any passive components may be mounted on the exposed metal regions in the redistribution layers 117 to form a tenth structure.
  • An example 600J of the tenth structure is illustrated in FIG. 600J and includes the LED array 102 with the phosphor material 610 and passive components 114.
  • the tenth structure which may be an LED lighting system such as the LED lighting system 100 of FIG. 1 B, may be mounted on an external circuit board (520) so as to, for example, incorporate the LED lighting system 100 into a vehicle headlamp or other application system.
  • an LED lighting system such as the LED lighting system 100 of FIG. 1 B
  • an external circuit board 520

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Abstract

Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Description

FAN OUT STRUCTURE FOR LIGHT-EMITTING DIODE (LED) DEVICE AND LIGHTING SYSTEM
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Non-Provisional Application No. 16/750,839, filed January 23, 2020, European Patent Application No. 20158481.0, filed February 20, 2020, U.S. Provisional Application No. 62/951 ,601, filed December 20, 2019, U.S. Provisional Application No. 62/937,629, filed November 19, 2019, the contents of which are hereby incorporated by reference herein.
BACKGROUND
[0002] Precision control lighting applications may require production and manufacturing of small addressable light-emitting diode (LED) lighting systems. The smaller size of such systems may require unconventional components and manufacturing processes.
SUMMARY
[0003] LED lighting systems, vehicle headlamp systems and methods of manufacture are described. An LED lighting system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces. First redistribution layers are provided on the top surface of the silicon backplane and the top surface of the substrate. Second redistribution layers are provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layers and the second redistribution layers and is filled with a metal material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] A more detailed understanding can be had from the following description, given by way of example in conjunction with the accompanying drawings wherein:
[0005] FIG. 1 A is a top view of an example LED array;
[0006] Fig. 1 B is a cross-sectional view of an example LED lighting system;
[0007] FIG. 1 C is a top view of the example LED lighting system of FIG. 1 B;
[0008] FIG. 1 D is a bottom view of the example LED lighting system of FIG. 1 B;
[0009] FIG. 2 is a cross-sectional view of an example application system that incorporates the
LED lighting system of FIG. 1 B;
[0010] FIG. 3 is a diagram of an example vehicle headlamp system that incorporates the LED lighting system of FIG. 1B; [0011] FIG. 4 is a diagram of another example vehicle headlamp system;
[0012] FIG. 5 is a flow diagram of an example method of manufacturing an LED lighting system, such as the LED lighting system of FIG. 1 B;
[0013] FIGs. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I and 6J are cross-sectional views of the LED lighting system at various stages in the manufacturing method; and
[0014] FIG. 7 is a bottom view representing the bottom surface of the LED lighting system of
FIG. 6E.
DETAILED DESCRIPTION
[0015] Examples of different light illumination systems and/or light emitting diode (“LED”) implementations will be described more fully hereinafter with reference to the accompanying drawings. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve additional implementations. Accordingly, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and they are not intended to limit the disclosure in any way. Like numbers refer to like elements throughout.
[0016] It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. For example, a first element may be termed a second element and a second element may be termed a first element without departing from the scope of the present invention. As used herein, the term "and/or" may include any and all combinations of one or more of the associated listed items.
[0017] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it may be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there may be no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element and/or connected or coupled to the other element via one or more intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present between the element and the other element. It will be understood that these terms are intended to encompass different orientations of the element in addition to any orientation depicted in the figures. [0018] Relative terms such as "below," "above," "upper,", "lower," "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
[0019] Further, whether the LEDs, LED arrays, electrical components and/or electronic components are housed on one, two or more electronics boards may also depend on design constraints and/or application.
[0020] Semiconductor light emitting devices (LEDs) or optical power emitting devices, such as devices that emit ultraviolet (UV) or infrared (IR) optical power, are among the most efficient light sources currently available. These devices (hereinafter ‘‘LEDs’’), may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, or the like. Due to their compact size and lower power requirements, for example, LEDs may be attractive candidates for many different applications. For example, they may be used as light sources (e.g., flash lights and camera flashes) for hand-held battery-powered devices, such as cameras and cell phones. They may also be used, for example, for automotive lighting, heads up display (HUD) lighting, horticultural lighting, street lighting, torch for video, general illumination (e.g., home, shop, office and studio lighting, theater/stage lighting and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as back lights for displays, and IR spectroscopy. A single LED may provide light that is less bright than an incandescent light source, and, therefore, multi-junction devices or arrays of LEDs (such as monolithic LED arrays, micro LED arrays, etc.) may be used for applications where more brightness is desired or required. [0021] FIG. 1A is a top view of an example LED array 102. In the example illustrated in FIG.
1A, the LED array 102 is an array of emitters 120. LED arrays may be used for any application, such as those requiring precision control of LED array emitters. Emitters 120 in the LED array 102 may be individually addressable or may be addressable in groups/subsets.
[0022] An exploded view of a 3x3 portion of the LED array 102 is also shown in FIG. 1 A. As shown in the 3x3 portion exploded view, the LED array 102 may include emitters 120 that each have a width wi. In embodiments, the width wi may be approximately 100pm or less (e.g., 40 pm). Lanes 122 between the emitters 120 may be a width, W2, wide. In embodiments, the width may be approximately 20pm or less (e.g., 5pm). The lanes 122 may provide an air gap between adjacent emitters or may contain other material. A distance di from the center of one emitter 120 to the center of an adjacent emitter 120 may be approximately 120pm or less (e.g., 45pm). It will be understood that the widths and distances provided herein are examples only and that actual widths and/or dimensions may vary.
[0023] It will be understood that, although rectangular emitters arranged in a symmetric matrix are shown in FIG. 1A, emitters of any shape and arrangement may be applied to the embodiments described herein. For example, the LED array 102 of FIG. 1A may include over 20,000 emitters in any applicable arrangement, such as a 200x100 matrix, a symmetric matrix, a non-symmetric matrix, or the like. It will also be understood that multiple sets of emitters, matrixes, and/or boards may be arranged in any applicable format to implement the embodiments described herein.
[0024] As mentioned above, LED arrays, such as the LED array 102, may include up to 20,000 or more emitters. Such arrays may have a surface area of 90 mm2 or greater and may require significant power to power them, such as 60 watts or more. An LED array such as this may be referred to as a micro LED array or simply a micro LED. A micro LED may include an array of individual emitters provided on a substrate or may be a single silicon wafer or die divided into segments that form the emitters. The latter type of micro LED may be referred to as a monolithic LED.
[0025] To individually drive or control the individual LEDs in the array, a silicon backplane may be provided in close proximity to the LED array and may become extremely hot during operation. Accordingly, heat dissipation can be challenging for such devices. While some solutions are known for heat dissipation for semiconductor devices, such solutions often include structures that dissipate heat through the top of the device. Due to light-emission, however, LED arrays, such as the LED array 102 of FIG. 1A, may not be able to dissipate heat through the top of the device.
[0026] Additionally, LED arrays, such as the LED array 102, may be used in applications, such as for vehicle headlamp systems, which may include passive elements, such as resistors and capacitors, which may form drivers, controllers and other circuits. It may be desirable to package at least some passive elements with the LED array.
[0027] Embodiments described herein may provide for a low profile LED array package that may accommodate one or more passive elements and enable dissipation of heat generated by the silicon backplane and the LED array.
[0028] FIG. 1 B is a diagram of a cross-sectional view of an example LED lighting system 100.
In the example illustrated in FIG. 1 B, the LED lighting system 100 includes a silicon backplane 104. The silicon backplane 104 has a top surface 101 , a bottom surface 103 and side surfaces 105. The side surfaces 105 of the silicon backplane 104 are surrounded by a substrate 106 formed from a molding material. The substrate 106 has a top surface 107, a bottom surface 109 and side surfaces 190. One or more metal layers 110 or redistribution layers (RDL) (shown in the alternative embodiment in FIG. 6E) are provided on the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106. RDL 117 may be formed on at least a portion of the top surface 101 of the silicon backplane 104 and a top surface 107 of the substrate 106. In the example illustrated in FIG. 1 B, the RDL 117 includes two layers 116a and 116b of a dielectric material 116 and a single metal layer 112. One or more vias 108 may extend through the substrate 106 and may be filled with a metal material. The vias may thus form a continuous electrical connection between the silicon backplane 104, the RDL 117 and the metallization/RDL 110. An LED array, such as the LED array 102 of FIG. 1A, may be provided on the top surface 101 of the silicon backplane 104 and electrically coupled thereto via an array of metal connectors (not shown in FIG. 1B). In embodiments, electronic components 114 may be provided on the RDL 117 and electrically coupled to the LED lighting system 100 via the metal layer 112.
[0029] The LED array 102 may be a micro LED, such as described above with respect to FIG.
1A. The LED array 102 may have a depth d1. In embodiments, the depth d1 may be, for example, between 5 and 250 pm.
[0030] The silicon backplane 104 may include the circuitry and connectors that make individually addressable connections to the emitters in the LED array 102. In embodiments, the silicon backplane may be a complementary metal-oxide semiconductor (CMOS) integrated circuit, which, in embodiments, may be an application specific integrated circuit (ASIC). The silicon backplane 104 may have a depth d3. In embodiments, the depth d3 may be, for example, between 100 pm and 1 mm. [0031] A structure made up of the silicon backplane 104, the substrate 106, the metallization/RDL 110, the RDL 117 and the vias 108 may have a depth d2. In embodiments, the depth d2 may be, for example, between 100 pm and 1 mm. Since the silicon backplane 104 is integrated into the substrate, and the LED array 102 is provided on top of the silicon backplane 104, the LED lighting system 100 may have a lower profile relative to systems that vertically stack one or more of these elements.
[0032] In the example illustrated in FIG. 1 B, the RDL 117 includes two layers 116a and 116b of the dielectric material 116 and a single metal layer 112. The first layer 116a of the two layers of the dielectric material 116 may be on the top surface 107 of the substrate 106 and at least a portion of the top surface 101 of the silicon backplane 104. The metal layer 112 may be patterned on the first layer 116a of the dielectric material 116, such as by copper plating and copper etching. The second layer 116b of the dielectric material 116 may be on top of the patterned metal layer 112 and exposed portions of the first layer 116a of the dielectric material 116. Although RDL consisting of two layers of dielectric material and a single layer of metal are shown in FIG. 1 B, one of ordinary skill in the art will recognize that the RDL 117 may include more or less layers of the dielectric material and/or more metal layers, depending on design constraints. The dielectric material 116 may be any suitable dielectric material. In embodiments, the dielectric material may be a polymer dielectric material, such as polyimide.
[0033] The RDL 117 may extend from a perimeter region of the silicon backplane 104 towards the side surfaces 190 of the substrate 106. This may both accommodate the LED array 102 attached to the top surface 101 of the silicon backplane 104 in a central region and help with heat dissipation by containing the dielectric materials that may further insulate the LED lighting system 100 to areas away from the highest heat areas in the center of the LED lighting system 100. The metal layer 112 may have portions that are exposed from the dielectric material 116 to form bond pads. The metal layer 112 may include portions that extend between the perimeter region of the silicon backplane 104 and the bond pads to create a continuous electrical connection therebetween. The bond pads may be electrically coupled to the vias 108 to create a continuous electrical connection between top and bottom surfaces of the LED lighting system 100. The bond pads may be placed in the perimeter region of the substrate or spaced apart from but closer to the array (as shown in FIG. 1 C, for example).
[0034] The metallization/RDL 110 may be formed in a number of different ways. In the example illustrated in FIG. 1 B, the metallization/RDL 110 is a metal layer including a first portion that is electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region and second portions that fan out from a perimeter region of the silicon backplane 104 toward the side surfaces 190 of the substrate 106. The first portion and the second portions may be electrically insulated from one another in embodiments. Although not visible in FIG. 1 B, the second portions may extend from the silicon backplane 104 and join with individual vias 108 at bond pads, electrically coupling the silicon backplane 104 to the metal layer 112 on the top surface. Both the first and second portions of the metal layer 110 may be coupled to an external circuit board (not shown), such as by soldering. This may enable a direct connection between the LED lighting system 100 and the external circuit board, which provides improved heat sinking through the bottom of the LED lighting system. Additionally, this structure may enable communication between the silicon backplane 104, the LED array 102, the passive components 114 on the substrate 106 and any electronic components on the external circuit board.
[0035] In another example, which will be described in more detail later with respect to FIGs. 6E and 7, the metallization/RDL 110 may be a combination of a metal layer and RDL. As with the embodiment illustrated in FIG. 1 B, a metal layer may be electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region. The fanout, however, may be accomplished using RDL instead of the metal layer. In such embodiments, the LED lighting device 100 may have RDL on both the top and bottom surfaces.
[0036] In both cases, the metallization/RDL 110 may be a thin structure compared to conventional silicon device packages and may include considerably less dielectric material than conventional silicon device packages. For example, the metal layer 100 in the embodiment shown in FIG. 1 B may be a single metal layer, and the RDL may include as few dielectric layers as possible. This may increase the efficiency of the heat dissipation in such packages and enable packaging for micro-LEDs and CMOS backplanes that may emit substantial heat.
[0037] In the LED lighting system 100 illustrated in FIG. 1 B, the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106 are co-planar. Similarly, the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106 are co-planar. This arrangement may allow for the slimmest possible packaging and ease of manufacture. However, one of ordinary skill in the art will recognize that because the substrate 106 is molded, the substrate 106 may take any shape, such as, for example, where the substrate has a top surface 107 that is higher than the top surface 101 of the silicon backplane 104 to further distance the electronic components 114 from the high heat regions of the LED lighting system 100. Thus, in embodiments, these surfaces may not be co- planar.
[0038] FIG. 1 C is a top view showing a top surface 130 of the example LED lighting system 100 of FIG. 1 B. In the example illustrated in FIG. 1 C, the top surface 130 of the LED lighting system includes the top-most layer 116b of the dielectric material 116 in the RDL 117. Electronic components 114 are electrically coupled to the metal 112 in the RDL and exposed from the dielectric material 116. In embodiments, an electronic component 114 may not be electrically coupled to all regions of the metal 112 and, thus, the top surface 130 may, in embodiments, also include some regions of the metal 112 exposed from the dielectric material 116. A top surface of at least a portion of the silicon backplane 104 is shown in FIG. 1 C and includes the portion of the top surface of the silicon backplane 104 that is not covered by the LED array 102 or the dielectric material 116. A top surface of the LED array 102 is also shown mounted on the top surface of the silicon backplane 104.
[0039] As shown in FIG. 1C, the LED lighting system 100 has a length £i and a width In embodiments, the length £i may be approximately 20 mm and the width m\ may be approximately 15 mm. The silicon backplane 104 may have a length fe and a width 2. In embodiments, the length £2 may be approximately 15.5 mm and the width m2 may be approximately 6.5 mm. The LED array 102 may have a length £3 and a width 3 In embodiments, the length £3 may be approximately 11 mm and the width ms may be approximately 4.4 mm.
[0040] Given these example dimensions, an LED array package may be provided that has a relatively large surface area (300 mm2 in the above example) with a relatively large amount of the surface area not taken up by the LED array (which has a surface area of approximately 100 mm2 in the above example). Accordingly, this design provides ample space for attachment of electronic components on the LED array package.
[0041] FIG. 1 D is a bottom view showing a bottom surface 140 of the example LED lighting system 100 of FIG. 1 B. In the example illustrated in FIG. 1 D, the bottom surface 140 includes regions of the substrate 106 and regions of the metal 110 or solder pads coupled thereto that are exposed from the molding material 106. In embodiments, some regions of the substrate may be covered by metallization and/or portions of the RDL that interconnect the silicon backplane and the bond pads, although these are not shown in FIG. 1 D. In some embodiments, the interconnecting metal regions and/or RDL may be covered by a dielectric material or other encapsulating or protective material (not shown in FIG. 1 D). [0042] FIG. 2 is a cross-sectional view of an application system 200 that incorporates the LED lighting system 100 of FIG. 1 B. The application system 200 may include a circuit board 150 that has a number of bond pads 152. In the example illustrated in FIG. 2, exposed metal regions/bond pads of the RDL/metallization 110 of the LED lighting system 100 are bonded directly to the bond pads 152 of the circuit board 150. As mentioned above, the direct bond between the metal layer 110 on the bottom surface of the silicon backplane 104 and the circuit board 150 enables efficient heat transfer from the LED lighting system 100 to the circuit board 150 for heat sinking purposes without need for additional heat dissipating structures over the top of the LED lighting system 100 (or elsewhere) that may, for example, otherwise block light emission from the LED array 102. The circuit board 150 may be part of a larger system used in specific applications, such as vehicle lighting or flash applications (example vehicle lighting systems are described below with respect to FIGs. 3 and 4). In such systems, some of the passive components used in the application may be the components 114 and may be provided directly on the LED lighting system 100 before attachment to the circuit board 150. The circuit board 150 may include other circuit elements required for the larger system in addition to a heat sink. The RDL 117, the RDL/metallization 110 and the vias 108 may provide a continuous electrical connection between the components 114, the silicon backplane 104 and the circuit board 150.
[0043] FIG. 3 is a diagram of an example vehicle headlamp system 300 that may incorporate the LED lighting system 100 of FIG. 1 B. The example vehicle headlamp system 300 illustrated in FIG. 3 includes power lines 302, a data bus 304, an input filter and protection module 306, a bus transceiver 308, a sensor module 310, an LED direct current to direct current (DC/DC) module 312, a logic low- dropout (LDO) module 314, a micro-controller 316 and an active head lamp 318. In embodiments, the active head lamp 318 may include an LED lighting system, such as the LED lighting system 100 of FIG. 1 B. As mentioned above, the LED lighting system 100 provides ample space and bond pads on the top surface of the substrate such that one, more, or all of the modules illustrated in FIG. 3 may be accommodated on the top surface of the LED lighting system 100. Modules not provided on the top surface of the LED lighting system 100 may be provided on the circuit board 150 (as shown in FIG. 2). In some embodiments, some electronic components of some or all of the modules in the vehicle lighting system 300 may be accommodated on the top surface of the LED lighting system 100 and some may be provided on the circuit board 150 (shown in FIG. 2).
[0044] The power lines 302 may have inputs that receive power from a vehicle, and the data bus 304 may have inputs/outputs over which data may be exchanged between the vehicle and the vehicle headlamp system 300. For example, the vehicle headlamp system 300 may receive instructions from other locations in the vehicle, such as instructions to turn on turn signaling or turn on headlamps, and may send feedback to other locations in the vehicle if desired. The sensor module 310 may be communicatively coupled to the data bus 304 and may provide additional data to the vehicle headlamp system 300 or other locations in the vehicle related to, for example, environmental conditions (e.g., time of day, rain, fog, or ambient light levels), vehicle state (e.g., parked, in-motion, speed of motion, or direction of motion), and presence/position of other objects (e.g., vehicles or pedestrians). A headlamp controller that is separate from any vehicle controller communicatively coupled to the vehicle data bus may also be included in the vehicle headlamp system 300. In FIG. 3, the headlamp controller may be a micro-controller, such as micro-controller (mo) 316. The micro-controller 316 may be communicatively coupled to the data bus 304.
[0045] The input filter and protection module 306 may be electrically coupled to the power lines
302 and may, for example, support various filters to reduce conducted emissions and provide power immunity. Additionally, the input filter and protection module 306 may provide electrostatic discharge (ESD) protection, load-dump protection, alternator field decay protection, and/or reverse polarity protection.
[0046] The LED DC/DC module 312 may be coupled between the filter and protection module
306 and the active headlamp 318 to receive filtered power and provide a drive current to power LEDs in the LED array in the active headlamp 318. The LED DC/DC module 312 may have an input voltage between 7 and 18 volts with a nominal voltage of approximately 13.2 volts and an output voltage that may be slightly higher (e.g., 0.3 volts) than a maximum voltage for the LED array (e.g., as determined by factor or local calibration and operating condition adjustments due to load, temperature or other factors). [0047] The logic LDO module 314 may be coupled to the input filter and protection module 306 to receive the filtered power. The logic LDO module 314 may also be coupled to the micro-controller 314 and the active headlamp 318 to provide power to the micro-controller 314 and/or the silicon backplane (e.g., CMOS logic) in the active headlamp 318.
[0048] The bus transceiver 308 may have, for example, a universal asynchronous receiver transmitter (UART) or serial peripheral interface (SPI) interface and may be coupled to the microcontroller 316. The micro-controller 316 may translate vehicle input based on, or including, data from the sensor module 310. The translated vehicle input may include a video signal that is transferrable to an image buffer in the active headlamp module 318. In addition, the micro-controller 316 may load default image frames and test for open/short pixels during startup. In embodiments, an SPI interface may load an image buffer in CMOS. Image frames may be full frame, differential or partial frames. Other features of micro-controller 316 may include control interface monitoring of CMOS status, including die temperature, as well as logic LDO output. In embodiments, LED DC/DC output may be dynamically controlled to minimize headroom. In addition to providing image frame data, other headlamp functions, such as complementary use in conjunction with side marker or turn signal lights, and/or activation of daytime running lights, may also be controlled.
[0049] FIG. 4 is a diagram of another example vehicle headlamp system 400. The example vehicle headlamp system 400 illustrated in FIG. 4 includes an application platform 402, two LED lighting systems 406 and 408, and optics 410 and 412. The two LED lighting systems 406 and 408 may be LED lighting systems, such as the LED lighting system 100 of FIG. 1 B, or may include the LED lighting system 100 plus some of all of the other modules in the vehicle headlamp system 300 of FIG. 3. In the latter embodiment, the LED lighting systems 406 and 408 may be vehicle headlamp sub-systems.
[0050] The LED lighting system 408 may emit light beams 414 (shown between arrows 414a and 414b in FIG. 4). The LED lighting system 406 may emit light beams 416 (shown between arrows 416a and 416b in FIG. 4). In the embodiment shown in FIG. 4, a secondary optic 410 is adjacent the LED lighting system 408, and the light emitted from the LED lighting system 408 passes through the secondary optic 410. Similarly, a secondary optic 412 is adjacent the LED lighting system 412, and the light emitted from the LED lighting system 412 passes through the secondary optic 412. In alternative embodiments, no secondary optics 410/412 are provided in the vehicle headlamp system.
[0051] Where included, the secondary optics 410/412 may be or include one or more light guides. The one or more light guides may be edge lit or may have an interior opening that defines an interior edge of the light guide. LED lighting systems 408 and 406 (or the active headlamp of a vehicle headlamp sub-system) may be inserted in the interior openings of the one or more light guides such that they inject light into the interior edge (interior opening light guide) or exterior edge (edge lit light guide) of the one or more light guides. In embodiments, the one or more light guides may shape the light emitted by the LED lighting systems 408 and 406 in a desired manner, such as, for example, with a gradient, a chamfered distribution, a narrow distribution, a wide distribution, or an angular distribution.
[0052] The application platform 402 may provide power and/or data to the LED lighting systems
406 and/or 408 via lines 404, which may include one or more or a portion of the power lines 302 and the data bus 304 of FIG. 3. One or more sensors (which may be the sensors in the system 300 or other additional sensors) may be internal or external to the housing of the application platform 402. Alternatively or in addition, as shown in the example LED lighting system 300 of FIG. 3, each LED lighting system 408 and 406 may include its own sensor module, connectivity and control module, power module, and/or LED array.
[0053] In embodiments, the vehicle headlamp system 400 may represent an automobile with steerable light beams where LEDs may be selectively activated to provide steerable light. For example, an array of LEDs (e.g., the LED array 102) may be used to define or project a shape or pattern or illuminate only selected sections of a roadway. In an example embodiment, infrared cameras or detector pixels within LED systems 406 and 408 may be sensors (e.g., similar to sensors in the sensor module 310 of FIG. 3) that identify portions of a scene (e.g., roadway or pedestrian crossing) that require illumination.
[0054] FIG. 5 is a flow diagram of an example method 500 of manufacturing an LED lighting system, such as the LED lighting system 100 of FIG. 1 B. FIGs. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I and 6J are cross-sectional views of the LED lighting system at various stages in the manufacturing method. In embodiments, the method 500 may produce a panel level packaged high-density LED lighting system. [0055] In the example method 500 of FIG. 5, the silicon backplane may be attached to a first carrier (502) to form a first structure. In embodiments, the silicon backplane may be attached to a temporary (e.g., plastic) carrier via an adhesive material, such as a tape or temporary adhesive. An example 600A of the first structure is illustrated in FIG. 6A and includes the silicon backplane 104, the first carrier 602 and the optional adhesive material 604.
[0056] The silicon backplane, attached to the first carrier, may be molded (504) to form a second structure. An example 600B of the second structure is illustrated in FIG. 6B and includes the first structure 600A of FIG. 6A with the molding material surrounding sides of the silicon backplane 104. The molding material forms a substrate 106 with an embedded silicon backplane 104. In embodiments, a mold may be placed over the structure 600A, filled with the molding material and cured. Any excess molding material may be removed from the top surface of the silicon backplane if needed. In embodiments, the molding may be panel level molding, the molding material may be a polymer material, and the second structure 600B may be a plastic substrate with an embedded silicon backplane on a temporary substrate. [0057] One or more vias may be formed through the substrate (506) to form a third structure.
In embodiments, the one or more vias may be formed using lasers or drills. An example 600C of the third structure is illustrated in FIG. 6C and includes the silicon backplane 104 embedded in the substrate 106 with two vias 108 formed therethrough. At this stage, the silicon backplane 104 and substrate 106 with vias 108 may remain attached to the first temporary carrier 602. The vias 108 may be filled with a metal material.
[0058] At least one metal layer may be formed on one surface of the silicon backplane and the substrate (508). This may be done in a number of different ways.
[0059] In some embodiments, a metal layer may be patterned or plated on the one surface of the silicon backplane and substrate to form a fourth structure. FIG. 6D illustrates an example 600D of the fourth structure, which includes the third structure with the metal layer 110. As can be seen in FIG. 6D, the metal layer 110 forms bond pads over the vias and regions that extend from a perimeter region of the silicon backplane 104. A metal layer is also provided on a central region of the one surface of the silicon backplane 104. The bottom view of the LED lighting system 100 illustrated in FIG. 1 D shows an example of this.
[0060] In other embodiments, a metal layer may be formed on the one surface of the silicon backplane in a central region, and redistribution layers may be formed on the one surface of the silicon backplane and substrate adjacent the single metal layer to form a fifth structure. FIG. 6E illustrates an example 600E of the fifth structure, which includes the third structure with the single metal layer 618 and the redistribution layers 616. In the example illustrated in FIG. 6E, the redistribution layers 616 include layers of a dielectric material 614 and metal layers 612. While three metal layers are shown in FIG. 6E, one, two, or more than three metal layers may be used if needed due to design constraints. The redistribution layers may be formed, for example, by alternating deposition of layers of the dielectric material, selective removal of portions of the dielectric material (if needed), and patterning a layer of metal on top. As can be seen in FIG. 6E, the metal layers 612 begin in a perimeter region of the one surface of the silicon backplane and extend toward the side surfaces of the substrate. The metal layers 612 are electrically coupled between the silicon backplane 104 and the vias. A portion of the metal layers 612 is exposed from the dielectric material 614 to form a solder pad or separate solder pads may be formed on the outer-most surface of the outer-most dielectric layer.
[0061 ] FIG. 7 is a bottom view representing a bottom surface 700 of the LED lighting system of
FIG. 6E. The line 702 represents the outer-most perimeter of the substrate. The line 104 represents the outer-most perimeter of a region occupied by the silicon backplane 104 relative to the outer-most perimeter of the substrate. The dashed line 704 denotes a border of a region between the line 704 and the outer-most perimeter of the silicon backplane 104, which may be referred to herein as the perimeter region of the silicon backplane 104. The metal layers 612 of the redistribution layers 616 may begin in the perimeter region and extend toward the side surfaces of the substrate (delineated by the line 702). There is a gap between the border 704 of the perimeter region of the silicon backplane and the single metal layer 618 formed on the one surface of the silicon backplane. This gap may be filled with the dielectric material, for example, as reflected in FIG. 6E.
[0062] The structure formed as a result of 508 (e.g., the fourth or fifth structure) may be flipped and attached to a second carrier (510) to form a sixth structure. In embodiments, the structure (e.g., fourth or fifth structure) may be attached to a temporary (e.g., plastic) carrier via an adhesive material, such as a tape or temporary adhesive. The structure may be placed with the at least one metal layer adjacent the second carrier. An example 600G of the sixth structure is illustrated in FIG. 6G and includes the second carrier 608 and the optional adhesive material 606. Once the structure is attached to the second carrier, the first carrier may be removed (512) to form a seventh structure. An example 600G of the seventh structure is shown in FIG 6G. [0063] Redistribution layers and an array of metal connectors may be formed on the surface exposed by removal of the second carrier (514) to form an eighth structure. In embodiments, the array of metal connectors may be formed by plating or otherwise patterning or forming an array of copper pillar bumps on the surface. An example 600H of the eighth structure is illustrated in FIG. 6H and includes the metal connectors 640 and the redistribution layers 117, including the at least one metal layer 112 and the dielectric material 116. As described above with respect to FIG. 6E, the redistribution layers may be formed by alternating deposition of layers of the dielectric material, selective removal of portions of the dielectric material (if needed), and patterning a layer of metal on top. In embodiments, over 20,000 (e.g., approximately 28,000) metal connectors may be formed on the surface.
[0064] An LED array may be attached to the silicon backplane via the electrical connectors
(516) to form a ninth structure. In embodiments, this may be performed by aligning the silicon backplane with the electrical connectors and heating to reflow the solder copper material in the copper pillar bumps. The reflow may create an underfill under the LED array. In embodiments, the LED array may be a monolithic LED array. An example 600I of the ninth structure is illustrated in FIG. 6I and includes the LED array 102 and the underfill.
[0065] The LED array may undergo a laser liftoff (LLO) process and phosphor integration (518).
Any passive components may be mounted on the exposed metal regions in the redistribution layers 117 to form a tenth structure. An example 600J of the tenth structure is illustrated in FIG. 600J and includes the LED array 102 with the phosphor material 610 and passive components 114.
[0066] Optionally, the tenth structure, which may be an LED lighting system such as the LED lighting system 100 of FIG. 1 B, may be mounted on an external circuit board (520) so as to, for example, incorporate the LED lighting system 100 into a vehicle headlamp or other application system.
[0067] Having described the embodiments in detail, those skilled in the art will appreciate that, given the present description, modifications may be made to the embodiments described herein without departing from the spirit of the inventive concept. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.

Claims

CLAIMS What is claimed is:
1. A system comprising: a silicon backplane having a top surface, a bottom surface, and side surfaces; a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces; at least one bond pad on the bottom surface of the substrate; a metal layer on the bottom surface of the substrate and the bottom surface of the silicon backplane, the metal layer having a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad; and an array of metal connectors on the top surface of the silicon backplane.
2. The system of claim 1 , further comprising at least one via through the substrate, the at least one via filled with a metal material and electrically coupled to the at least one bond pad.
3. The system of claim 2, further comprising redistribution layers on the top surface of the silicon backplane and the top surface of the substrate, the redistribution layers comprising: at least one first dielectric layer, and at least one first metal layer, the at least one first metal layer extending from a perimeter region of the silicon backplane toward the side surfaces of the substrate and having a least a portion exposed from the at least one dielectric layer to form at least one other bond pad.
4. The system of claim 3, wherein the at least one other bond pad is electrically coupled to the at least one via.
5. The system of claim 4, further comprising at least one passive component electrically coupled to the at least one bond pad.
6. The system of claim 1 , further comprising a light-emitting diode (LED) array electrically coupled to the array of metal connectors on the top surface of the silicon backplane.
7. The system of claim 6, wherein the LED array is a monolithic LED array comprising a plurality of rows and columns of emitters, each of the emitters having a width of 100 pm or less, and lanes between adjacent rows and columns having a width of 20 pm or less.
8. The system of claim 1 , wherein the array of metal connectors is an array of copper pillar bumps.
9. The system of claim 1 , wherein the substrate comprises a molding material.
10. The system of claim 1 , wherein the silicon backplane is a complementary metal-oxide semiconductor (CMOS) integrated circuit.
11. A system comprising: a silicon backplane having a top surface, a bottom surface, and side surfaces; a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces; a first metal layer electrically and thermally coupled to the bottom surface of the silicon backplane in a central region; redistribution layers on the bottom surface of the silicon backplane and the bottom surface of the substrate, the redistribution layers comprising at least one dielectric layer and at least one second metal layer, the at least one second metal layer extending from a perimeter region of the silicon backplane toward the side surfaces of the substrate and having at least a portion exposed from the at least one dielectric layer to form at least one bond pad; and an array of metal connectors on the top surface of the silicon backplane.
12. The system of claim 11 , further comprising at least one via through the substrate, the at least one via filled with a metal material and electrically coupled to the at least one bond pad.
13. The system of claim 12, further comprising other redistribution layers on the top surface of the silicon backplane and the top surface of the substrate, the other redistribution layers comprising: at least one other dielectric layer, and at least one third metal layer, the at least one third metal layer extending from a perimeter region of the silicon backplane toward the side surfaces of the substrate and having a least a portion exposed from the at least one other dielectric layer to form at least one other bond pad.
14. The system of claim 13, wherein the at least one third metal layer is electrically coupled to the at least one via.
15. The system of claim 14, further comprising at least one passive component electrically coupled to the at least one other bond pad.
16. The system of claim 11 , further comprising a light-emitting diode (LED) array electrically coupled to the array of metal connectors on the top surface of the silicon backplane.
17. The system of claim 16, wherein the LED array is a monolithic LED array comprising a plurality of rows and columns of emitters, each of the emitters having a width of 100 pm or less, and lanes between adjacent rows and columns having a width of 20 pm or less.
18. The system of claim 11 , wherein the array of metal connectors is an array of copper pillar bumps.
19. The system of claim 11 , wherein the substrate comprises a molding material.
20. The system of claim 11 , wherein the silicon backplane is a complementary metal-oxide semiconductor (CMOS) integrated circuit.
EP20821568.1A 2019-11-19 2020-11-19 Fan out structure for light-emitting diode (led) device and lighting system Pending EP4062461A1 (en)

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