EP4047642A1 - Hybrid substrate with improved insulation - Google Patents

Hybrid substrate with improved insulation Download PDF

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Publication number
EP4047642A1
EP4047642A1 EP22167250.4A EP22167250A EP4047642A1 EP 4047642 A1 EP4047642 A1 EP 4047642A1 EP 22167250 A EP22167250 A EP 22167250A EP 4047642 A1 EP4047642 A1 EP 4047642A1
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EP
European Patent Office
Prior art keywords
zone
insulation
active
semiconductor material
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22167250.4A
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German (de)
French (fr)
Inventor
Claire Fenouillet-Beranger
Stéphane Denorme
Philippe Coronel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Publication of EP4047642A1 publication Critical patent/EP4047642A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands

Definitions

  • field-effect transistors formed on substrates of the silicon-on-insulator type has numerous advantages, in particular, a simplification of the design of the integrated circuits and an improvement in the performance of the devices.
  • the substrates used have increasingly thin silicon and buried oxide thicknesses.
  • hybrid substrates are used. As shown in figure 1 , these hybrid substrates comprise a first active zone 1 in first semiconductor material 2, typically a semiconductor-on-insulator zone and a second active zone 3 in second semiconductor material 4 which is of the solid substrate type. The first 1 and second 3 active zones are laterally separated by an isolation zone 5.
  • these hybrid substrates are made from a stem substrate of the semiconductor-on-insulator type which is transformed in order to present the two types of active zones 1, 3.
  • the stem substrate comprises an insulation layer 6 which is arranged between the first and second semiconductor materials.
  • These two types of active areas are then used to form different devices.
  • a conventional way of producing such a hybrid substrate is to etch the second semiconductor material 4 and the insulation layer 6 to reach the first semiconductor material 2, once the insulation zones have been produced.
  • the silicon substrate is exposed and forms the first active area 1.
  • the insulation area 5 sinks into the silicon substrate 2 and is higher than the layer of silicon on insulator of the second active area 3
  • the first active zone 1 is therefore enclosed between the different isolation zones 5.
  • the process for producing a hybrid substrate is complicated to implement. It requires the alignment of a photolithography and etching step with respect to the various active zones present. A misalignment of the second active 3 protection step results in the obtaining of spurious patterns in the first 1 and/or the second 3 active zones and an at least partial elimination of a insulation patterns 5 bordering the first 1 and/or second 3 active zones. It therefore appears that the production method greatly limits the possibilities of integrating the structure from an industrial point of view.
  • the substrate obtained is also not optimal because it is less practical to use than conventional substrates and the circuits obtained do not have a lifetime and a manufacturing yield as good as the circuits produced on conventional substrates.
  • the subject of the invention is a substrate which is particularly advantageous for the production of integrated circuits with a high manufacturing yield.
  • the insulation zone comprises a first portion bordering at least one lateral edge of the first active zone, the first portion and the first active area having a free main face forming the same plane with the interface between the first semiconductor material layer and the insulation layer, the insulation area and the first active area having complementary shapes along an interface between the isolation zone and the first active zone.
  • the starting substrate is a stub substrate which comprises at least one layer of first semiconductor material 2, a layer of second semiconductor material 4 and an insulation layer 6.
  • the stub substrate also comprises a support layer 7 .
  • the layer of first semiconductor material 2 can be formed on the surface of the support layer 7 or be formed by a surface area of the support layer 7, that is to say in the support layer 7 ( picture 2 ).
  • the first semiconductor material layer 2 can also be of the semiconductor-on-insulator type, for example of the partially depleted type. It is then separated from support layer 7 by a dielectric material called buried dielectric (not shown). Therefore, the first semiconductor material 2 can be in the same material as the support layer 7 or else in a different material. It is also possible that the layer support 7 and the first semiconductor material 2 have the same crystallographic orientation or different orientations.
  • the second semiconductor material layer 4 is separated from the first semiconductor material layer 2 by at least one insulation layer 6.
  • the second semiconductor material 4 is therefore of the semiconductor-on-insulator type.
  • the second semiconductor material 4 is separated from the support layer 7 at least by the insulation layer 6 if the first semiconductor material 2 is made directly on the surface of the support layer 7.
  • the first 2 and second 4 semiconductor materials can be in the same or different materials and have the same or different orientations.
  • the stem substrate comprises at least successively the support layer 7, the layer of first semiconductor material 2, the insulation layer 6 and the second layer. semiconductor material 4.
  • the stem substrate may also comprise additional layers of semiconductor materials and additional insulation layers.
  • the layer of first semiconductor material 2 is placed between the support layer 7 and the insulation layer 6.
  • the insulation layer 6 is placed between the first 2 and second 4 semiconductor materials.
  • the source substrate can therefore be of the semiconductor-on-insulator type.
  • the hybrid substrate having to be used to produce integrated circuits, it is advantageous to limit as much as possible the difference in height between the main surface of the first active zone 1 in first semiconductor material 2 and the main surface of the second active zone 3 in second semiconductor material 4.
  • the main surface of the active zones is the surface on which a transistor or an electronic device in general is formed. More this difference in height is significant and the more difficult it is to carry out good quality photolithography steps because of the depth of field limitations of the equipment used.
  • an etching mask 8 is formed on the stem substrate, that is to say on the layer farthest from the support layer 7, here the second semiconductor material 4.
  • the mask etching is formed in a hard mask in first protective material 9.
  • the etching mask 8 comprises at least a first protective material 9 which covers an additional protective material 10.
  • the first protective material 9 and additional protective material 10 may have different structures and therefore different designs.
  • the hard mask is structured in order to form the etching mask 8.
  • the etching mask 8 delimits at least a first active area 1 of the substrate, a second active area 3 of the substrate and an insulation area 5 of the substrate.
  • the etching mask can delimit a plurality of first active zones 1, second active zones 3 and isolation zones 5.
  • the first 1 and second 3 active zones and the isolation zone 5 being formed in the etching mask, they are necessarily offset laterally relative to each other.
  • An isolation zone 5 separates the first 1 and second 3 active zones. In other words, in an integrated circuit, the first active zone 1 and the second active zone 3 are surrounded by an insulation zone 5 as illustrated in top view at figure 4 .
  • the delimitation of the isolation zone 5 is defined by an empty zone whereas the delimitation of the first 1 and second 3 active zones is carried out by a solid zone.
  • the etching mask 8 therefore comprises distinct drawings delimiting the first active zones 1, drawings delimiting the second active zones 3 and drawings delimiting the isolation zones 5. These three types of drawings represent the entire surface of the mask of engraving 5 ( figure 4 ).
  • the layer of first semiconductor material 2, the layer of second semiconductor material 4 and the insulation layer 6 are structured to delimit the insulation zone 5 in the first material semiconductor 2 and release the main surface of the first active zone 1 in first semiconductor material 2.
  • the main surface of the first active zone 1 having to be released, it is necessary to eliminate above the first semiconductor material conductor 2, the insulation layer 6, the second semiconductor material 4 and the etching mask 8 in the area indicated.
  • the structuring of the first semiconductor material 2 simultaneously delimits the first active zone 1 and the insulation zone 5.
  • the main surface of the first active zone corresponds to the surface of the support substrate which formed the interface with the layer of insulation. In this way, the main surface of the first active zone is below the level of the insulation layer 6.
  • the main surface of the first active zone is here in the same plane as the interface between the first semiconductor material and insulation layer 6.
  • the first active zone 1, the isolation zone 5 and the second active zone 3 are delimited.
  • this structuring of the etching mask 8 can occur at different times depending on the embodiments used.
  • the layer of second semiconductor material 4 and the insulation layer 6 are structured.
  • This structuring can be carried out conventionally by means of plasma etching and it can sink after the first semiconductor material 2, for example right down to the support layer 7.
  • the free area of the etching mask 8 delimits the insulation area 5.
  • the second semiconductor material 4, the insulation layer 6 then the first semiconductor material 2 are successively structured from the drawing represented by the area free of the etching mask 8.
  • the design of the insulation zone 5 is therefore etched in the different layers located between the etching mask 8 and the layer of first semiconductor material 2. This structuring forms an empty zone in the second semiconductor material 4, the insulation layer 6 and the first semiconductor material 2. This structuring also delimits the second active zone 3 in second semiconductor material 4 at the time of the etching of this second semiconductor material 4.
  • the etching mask 8 is then structured to be eliminated at the level of the first active zone 1.
  • the elimination of the portion of the etching mask 8 which delimits the first active zone 1 can be carried out by any suitable technique, for example at means of a step of photolithography and etching.
  • the main surface of the first active area is then freed by removing the second semiconductor material 4 and the insulation layer 6 located just above the first active area.
  • the etching mask 8 can advantageously be used to protect the rest of the substrate during etching.
  • the drawing delimiting the first active zone 1 in the etching mask 8 is produced by means of a plurality of patterns spaced from each other.
  • the delimitation of the first active zone 1 is carried out by alternating patterns and empty areas.
  • the distance between two side edges facing two adjacent patterns is less than the smallest distance that exists between a side edge of a design delimiting the first active area 1 and a side edge of a design delimiting the second active area 3.
  • the greatest distance between two adjacent patterns is less than the smallest distance which separates the side wall of the design delimiting the first active area from the side wall of the design of the second active area 3.
  • the lateral and/or longitudinal dimension of the patterns is less than the thickness of the etching mask.
  • the patterns are spaced apart by approximately one third of the distance that normally separates two transistors. In an integration for the 45nm technological node, the minimum distance which separates two transistors is of the order of 100nm and therefore the distance which separates two patterns is of the order of 30nm. For integration in lower technological nodes, it suffices to reduce the distances specified above.
  • the patterns can be of any shape, for example, they can be square or rectangular or both.
  • the side wall of the design delimiting the first active area is obtained by connecting all the patterns located on the edges.
  • Their size can be any as long as the distance between the patterns is respected.
  • a first plug 11 is formed in the spaces between the patterns of the drawing delimiting the first active zone in order to form a solid drawing, that is to say without any empty zone.
  • the first plug 11 is formed by means of a covering material deposited in a conformal manner, that is to say which matches the shape of the material which it covers.
  • the space between the patterns being smaller than the space between the first active zone 1 and the second active zone 3, the covering material fills in the empty zones of the design of the first active zone 1 without completely filling in the drawing delimiting the zone insulation, also an empty area.
  • the thickness of the covering material is chosen accordingly and the covering material is then removed isotropically. In this way, the covering material is present only in the drawing delimiting the first active zone 1.
  • the empty zone of the etching mask 8 now only delimits the isolation zone 5.
  • the structuring of the second semiconductor material 4, of the insulation layer 6 and of the first semiconductor material 2 can then be carried out.
  • the covering material is selectively eliminated by any suitable method and the patterns delimiting the first active zone 1 are eliminated.
  • This elimination is advantageously carried out by means of an isotropic etching of the material or materials constituting the etching mask 8. There is then a slight shrinkage of the etching mask 8 at the level of the side walls of the drawings of the first 1 and second 3 active zones .
  • the etching mask 8 above the first active zone 1 comprises an additional protective material 10
  • the elimination of the patterns of the drawing delimiting the first active zone 1 is carried out by means of the selective etching of the protective material.
  • additional protection 10 This selective etching causes the patterns to detach. It is conceivable that the covering material and the additional protective material 10 are the same or that they exhibit a reactivity to the same etching process.
  • the first protective material 9 is replaced by a second protective material 12 only in the drawing delimiting the first active zone 1.
  • This second protective material 12 has an etching selectivity with respect to the first protective material 9.
  • the second material protection 12 can be formed by any suitable technique, for example, by implanting a dopant or another material in the first protection material 9 at the level of the zone to be transformed.
  • a second plug 13 is formed in the etching mask 8 at the level of the drawing delimiting the isolation zone 5.
  • the second plug 13 then delimits the isolation zone in the etching mask 8.
  • the second protective material 12 is formed in the empty zone of the etching mask 8.
  • the etching mask comprises the first protective material 9 formed on the additional protective material 10.
  • the second protective material 12 is then formed by the additional protective material 10 after removal of the first material from protection 9.
  • the second cap is used in order to avoid the lateral engraving of the drawings delimiting the first 1 and second 3 active zones.
  • the etching mask 8 then delimits the first active zone 1, the second active zone 3 and the isolation zone 5 at the means of three different materials which may have differences in thickness between them.
  • the design of the etching mask 8 delimiting the first active zone 1 can be constituted by a plurality of patterns spaced from each other and which have the same dimensional constraints as before.
  • the first plug 11 is then formed before the formation of the second protective material 12.
  • the etching mask 8 comprises a first protective material 9 deposited above an additional protective material 10.
  • the first plug 11 is formed before the second plug 13.
  • the additional protective layer 10 is structured once the first plug is formed.
  • the first cap 11 is eliminated and the first protective material is eliminated at the level of the design of the first active zone by means of an anisotropic etching.
  • the thickness of the first protective material 9 is slightly reduced in the etching mask 8 and the design of the first active zone in first protective material 9 is eliminated ( figure 15 ).
  • the second plug 13 is then removed and the substrate is substantially identical to that of the figure 12 , the thickness of the etching mask 8 above the active area being lower.
  • the second cap 13 is eliminated and the insulation zone 5 is structured in the first semiconductor material.
  • the layers located above the first active zone in first semiconductor material are removed.
  • the second protective material 12 is in the same material as the insulating layer 6 or in a material which is etched with the same etching process.
  • the etching mask 8 in first 9 and second 12 materials protection is used to structure the second semiconductor material 4 and delimit the isolation zone 5 and the second active zone 3 in the second semiconductor material 4.
  • the insulation layer 6 is then structured to delimit the zone of insulation 5.
  • the insulation layer 6 and the second protective material 12 being reactive to the same etching process, the second protective material 12 is eliminated at the level of the first active zone 1.
  • the first semiconductor material 2 is then structured to delimit the insulation zone 5 and therefore the first active zone 1 by means of the pattern in the insulation layer 6 delimiting the first active zone 1.
  • the pattern in the insulation layer 6 is then eliminated.
  • the structurings are produced by means of anisotropic etchings which reproduce in the lower layer the design of the first active zone 1 originating from the etching mask 8.
  • the structuring of the insulation layer 6 and of the layers of first semiconductor material 2, of second semiconductor material 4 and the release of the main surface of the first active zone 1 form zones voids in the stem substrate. These empty areas are located in the second semiconductor material 4, in the insulation layer 6 and in the first semiconductor material 2. The empty areas are also present in the etching mask 8.
  • the empty areas correspond to the surface of the first active area 1 and of the insulation area 5.
  • the empty zone corresponds only to the insulation zone 5.
  • a first insulation material 14 is deposited to fill the void areas of the substrate strain and the etching mask 8.
  • This first insulating material 14 is an electrically insulating material, for example silicon oxide or silicon nitride.
  • the first insulation material 14 may be different from the second insulation material constituting the insulation layer 6.
  • the first and second insulation materials may also be identical.
  • the first insulation material 14 fills in the insulation zone formed in the first semiconductor material 2, but also the empty zone representative of the insulation zone 5 and of the first active zone 1 in the insulation layer 6 and in the second semiconductor material 4.
  • the first insulation material 14 is also deposited on the etching mask 8.
  • the first insulation material 14 preferably undergoes a flattening step, this step can stop above or at the level of the etching mask 8. During this operation, the etching mask can also be etched, but it must avoid damaging the main surface of the second semiconductor material 4.
  • the first insulation material 14 has been flattened, it undergoes an isotropic or anisotropic etching step in order to locate it at the level of the insulation zone 5 in the first semiconductor material 2. In this etching step, the flatness of the first insulation material is maintained throughout the etching. If the insulation layer 6 or another of the layers present and accessible is reactive to the etching process of the first insulation material 14, the etching is carried out by means of an anisotropic process.
  • the first insulation material 14 having a flat surface, this flat surface is passed on while throughout the etching, even above the main surface of the first active zone 1, that is to say after the release of the main surface of the first active zone 1.
  • Additional insulating material is conformally deposited on the substrate.
  • the additional insulating material covers the etching mask 8, the first active area 1, the first insulation material 14 and the side walls of the etching mask 8, of the second semiconductor material 4 and of the insulation layer 6.
  • the additional insulating material is then etched by plasma in an anisotropic manner so as to locate only on the side walls and thus form the side spacer 15.
  • the deposited thickness of the additional insulating material as well as the etched thickness depend on the thickness chosen for the lateral spacer.
  • the lateral spacer 15 is formed before the release of the main surface of the first active zone 1 and if the thickness of the lateral spacer 15 is greater than the distance separating the first 1 and the second 3 active zones (the width of the isolation zone 5), the lateral spacer 15 is arranged above the first active zone 1. It is then possible to use the lateral spacer 15 as an etching mask and to release only part of the first active zone 1. This embodiment is particularly advantageous if it is desired to achieve an elevation of the height of the main face of the first active zone 1, for example, by selective epitaxy.
  • Etching mask 8 is then eliminated, by any suitable technique, for example by means of anisotropic etching such as wet etching, and the main surface of the second active zone is freed.
  • a hybrid substrate which comprises a first active zone 1 of first semiconductor material 2, a second active zone 3 of second semiconductor material 4, the first 1 and second 2 active zones being arranged, laterally , on either side of an insulation zone 5 of first insulation material 14.
  • the first 2 and second 4 semiconductor materials are separated by an insulation layer 6 of second insulation material in a direction perpendicular to a main surface of a support layer 7.
  • the isolation zone 5 comprises a main surface which forms a single plane with the main surface of the first active zone 1.
  • the isolation zone 5 and the first active area 1 have complementary shapes along the interface between the insulation area 5 and the first active area 1.
  • the second active areas 3 are electrically separated from the first active areas 1 by the insulation layer 6, from a point t of vertical view.
  • This hybrid substrate is particularly advantageous because it allows the formation of specific devices on active areas having predefined electronic and/or crystallographic characteristics. Active areas have excellent surface quality as they have always been protected from aggressive steps. The main surfaces of the active areas are, in general, released by means of wet etching. The substrate does not have surface topographies in the immediate vicinity of the active zones, especially at the level of the first active zone. This has the effect of limiting the risks of contamination linked to a cleaning problem and of limiting parasitic transistors. The existing topographies are offset above the isolation zones, which limits the effect of parasitic materials on the operation of the device.

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Abstract

Un substrat hybride comporte des première (1) et seconde (3) zones actives en matériaux semi-conducteur décalées latéralement et séparées par une zone d'isolation (5). Les surfaces principales de la zone d'isolation (5) et de la première zone active (1) forment un plan. Le substrat hybride est obtenu à partir d'un substrat souche comportant successivement des couches en premier (2) et second (4) matériaux semi-conducteurs séparées par une couche d'isolation (6). Un unique masque de gravure est utilisé pour structurer la zone d'isolation (5), la première zone active (1) et la seconde zone active (3). La surface principale de la première zone active (1) est libérée formant ainsi des zones vides dans le substrat souche. Le masque de gravure est éliminé au-dessus de la première zone active (1). Un premier matériau d'isolation est déposé, aplani et gravé jusqu'à libérer la surface principale de la première zone active (1).A hybrid substrate comprises first (1) and second (3) active areas made of semiconductor materials offset laterally and separated by an insulation area (5). The main surfaces of the isolation zone (5) and the first active zone (1) form a plane. The hybrid substrate is obtained from a stem substrate comprising successively layers of first (2) and second (4) semiconductor materials separated by an insulation layer (6). A single etching mask is used to structure the isolation zone (5), the first active zone (1) and the second active zone (3). The main surface of the first active zone (1) is released thus forming empty zones in the stem substrate. The etching mask is eliminated above the first active area (1). A first insulation material is deposited, flattened and etched until the main surface of the first active area (1) is freed.

Description

Domaine technique de l'inventionTechnical field of the invention

L'invention est relative à un substrat hybride comportant :

  • une première zone active en premier matériau semi-conducteur,
  • une seconde zone active en second matériau semi-conducteur,
  • les première et seconde zones actives étant disposées, latéralement, de part et d'autre d'une zone d'isolation en premier matériau d'isolation,
  • les premier et second matériaux semi-conducteurs étant séparés par une couche d'isolation en second matériau d'isolation dans une direction perpendiculaire à une surface principale d'une couche de support.
The invention relates to a hybrid substrate comprising:
  • a first active area made of first semiconductor material,
  • a second active area made of second semiconductor material,
  • the first and second active zones being arranged, laterally, on either side of an insulation zone made of first insulation material,
  • the first and second semiconductor materials being separated by an insulation layer of second insulation material in a direction perpendicular to a major surface of a support layer.

État de la techniqueState of the art

L'utilisation de transistors à effet de champ formés sur des substrats de type silicium sur isolant présente de nombreux avantages, notamment, une simplification du dessin des circuits intégrés et une amélioration des performances des dispositifs. De plus, afin de satisfaire à des contraintes toujours plus importantes, les substrats utilisés présentent des épaisseurs de silicium et d'oxyde enterré de plus en plus fines.The use of field-effect transistors formed on substrates of the silicon-on-insulator type has numerous advantages, in particular, a simplification of the design of the integrated circuits and an improvement in the performance of the devices. In addition, in order to satisfy ever greater constraints, the substrates used have increasingly thin silicon and buried oxide thicknesses.

Cependant, l'utilisation d'un transistor intégré sur un film mince présente également de nombreux inconvénients. Les dispositifs à effet de champ sont, par exemple, inadaptés à l'utilisation de courants importants que l'on retrouve typiquement dans les modules d'entrée/sortie. Il est également difficile d'intégrer un transistor bipolaire sur un substrat de type semi-conducteur sur isolant mince ce qui limite les possibilités offertes quant aux dispositifs utilisables dans les circuits intégrés.However, the use of an integrated transistor on a thin film also has many disadvantages. Field effect devices are, for example, unsuitable for the use of high currents that are typically found in input/output modules. It is also difficult to integrate a bipolar transistor on a semiconductor type substrate on thin insulator which limits the possibilities offered as to the devices that can be used in integrated circuits.

Afin de s'autoriser une plus grande largesse dans la conception des circuits intégrés, des substrats hybrides sont utilisés. Comme illustré à la figure 1, ces substrats hybrides comportent une première zone active 1 en premier matériau semi-conducteur 2, typiquement une zone de semi-conducteur sur isolant et une seconde zone active 3 en second matériau semi-conducteur 4 qui est de type substrat massif. Les première 1 et seconde 3 zones actives sont séparées latéralement par une zone d'isolation 5.In order to allow greater generosity in the design of integrated circuits, hybrid substrates are used. As shown in figure 1 , these hybrid substrates comprise a first active zone 1 in first semiconductor material 2, typically a semiconductor-on-insulator zone and a second active zone 3 in second semiconductor material 4 which is of the solid substrate type. The first 1 and second 3 active zones are laterally separated by an isolation zone 5.

Comme illustré à la figure 2, ces substrats hybrides sont réalisés à partir d'un substrat souche de type semi-conducteur sur isolant qui est transformé afin de présenter les deux types de zones actives 1, 3. Le substrat souche comporte une couche d'isolation 6 qui est disposée entre les premier et second matériaux semi-conducteur. Ces deux types de zones actives sont alors utilisées pour former des dispositifs différents. Une manière conventionnelle de réaliser un tel substrat hybride est de graver le second matériau semi-conducteur 4 et la couche d'isolation 6 pour atteindre le premier matériau semi-conducteur 2, une fois que les zones d'isolation sont réalisées. Ainsi, le substrat de silicium est mis à nu et forme la première zone active 1. La zone d'isolation 5 s'enfonce dans le substrat en silicium 2 et est plus haute que la couche de silicium sur isolant de la seconde zone active 3. La première zone active 1 est donc encaissée entre les différentes zones d'isolation 5.As shown in picture 2 , these hybrid substrates are made from a stem substrate of the semiconductor-on-insulator type which is transformed in order to present the two types of active zones 1, 3. The stem substrate comprises an insulation layer 6 which is arranged between the first and second semiconductor materials. These two types of active areas are then used to form different devices. A conventional way of producing such a hybrid substrate is to etch the second semiconductor material 4 and the insulation layer 6 to reach the first semiconductor material 2, once the insulation zones have been produced. Thus, the silicon substrate is exposed and forms the first active area 1. The insulation area 5 sinks into the silicon substrate 2 and is higher than the layer of silicon on insulator of the second active area 3 The first active zone 1 is therefore enclosed between the different isolation zones 5.

Afin de ne libérer que les zones actives choisies, le procédé de réalisation d'un substrat hybride est compliqué à mettre en oeuvre. Il nécessite l'alignement d'une étape de photolithographie et de gravure par rapport aux différentes zones actives présente. Un désalignement de l'étape de protection des secondes actives 3 entraîne l'obtention de motifs parasites dans la première 1 et/ou la seconde 3 zones actives et une élimination au moins partielle d'un des motifs d'isolation 5 bordant les première 1 et/ou seconde 3 zones actives. Il apparaît donc que le procédé de réalisation limite fortement les possibilités d'intégration de la structure d'un point de vue industriel.In order to release only the chosen active areas, the process for producing a hybrid substrate is complicated to implement. It requires the alignment of a photolithography and etching step with respect to the various active zones present. A misalignment of the second active 3 protection step results in the obtaining of spurious patterns in the first 1 and/or the second 3 active zones and an at least partial elimination of a insulation patterns 5 bordering the first 1 and/or second 3 active zones. It therefore appears that the production method greatly limits the possibilities of integrating the structure from an industrial point of view.

Le substrat obtenu n'est pas non plus optimal car il est moins pratique à utiliser que les substrats conventionnels et les circuits obtenus n'ont pas une durée de vie et un rendement de fabrication aussi bon que les circuits réalisés sur les substrats conventionnels.The substrate obtained is also not optimal because it is less practical to use than conventional substrates and the circuits obtained do not have a lifetime and a manufacturing yield as good as the circuits produced on conventional substrates.

Objet de l'inventionObject of the invention

L'invention a pour objet un substrat qui est particulièrement intéressant pour la réalisation de circuits intégrés à fort rendement de fabrication.The subject of the invention is a substrate which is particularly advantageous for the production of integrated circuits with a high manufacturing yield.

On tend à obtenir un tel résultat au moyen d'un substrat selon la revendication 1 et plus particulièrement un substrat dans lequel la zone d'isolation comporte une première portion bordant au moins un bord latéral de la première zone active, la première portion et la première zone active ayant une face principale libre formant un même plan avec l'interface entre la couche en premier matériau semi-conducteur et la couche d'isolation, la zone d'isolation et la première zone active ayant des formes complémentaires le long d'une interface entre la zone d'isolation et la première zone active.One tends to obtain such a result by means of a substrate according to claim 1 and more particularly a substrate in which the insulation zone comprises a first portion bordering at least one lateral edge of the first active zone, the first portion and the first active area having a free main face forming the same plane with the interface between the first semiconductor material layer and the insulation layer, the insulation area and the first active area having complementary shapes along an interface between the isolation zone and the first active zone.

Description sommaire des dessinsBrief description of the drawings

D'autres avantages et caractéristiques ressortiront plus clairement de la description qui va suivre de modes particuliers de réalisation de l'invention donnés à titre d'exemples non limitatifs et représentés aux dessins annexés, dans lesquels :

  • la figure 1 représente, de manière schématique, en coupe, un substrat hybride selon l'art antérieur,
  • la figure 2 représente, de manière schématique, en coupe, un substrat selon l'art antérieur,
  • les figures 3, 4, 5, 19 et 20 représentent, de manière schématique, en coupe et en vue de dessus, les étapes d'un procédé de réalisation d'un substrat hybride, selon l'invention,
  • les figures 6 à 10 représentent de manière schématique, en coupe, différentes variantes d'un premier mode de réalisation du procédé selon l'invention,
  • les figures 11 à 18 représentent de manière schématique, en coupe, différentes variantes d'un second mode de réalisation du procédé selon l'invention.
Other advantages and characteristics will emerge more clearly from the following description of particular embodiments of the invention given by way of non-limiting examples and shown in the appended drawings, in which:
  • the figure 1 schematically represents, in section, a hybrid substrate according to the prior art,
  • the figure 2 schematically represents, in section, a substrate according to the prior art,
  • them figure 3 , 4 , 5 , 19 and 20 represent, schematically, in section and in top view, the steps of a method for producing a hybrid substrate, according to the invention,
  • them figures 6 to 10 schematically represent, in section, different variants of a first embodiment of the method according to the invention,
  • them figures 11 to 18 schematically represent, in section, different variants of a second embodiment of the method according to the invention.

Description d'un mode de réalisation préférentiel de l'inventionDescription of a preferred embodiment of the invention

Comme illustré à la figure 2, le substrat de départ est un substrat souche qui comporte au moins une couche en premier matériau semi-conducteur 2, une couche en second matériau semi-conducteur 4 et une couche d'isolation 6. Le substrat souche comporte également une couche de support 7.As shown in figure 2 , the starting substrate is a stub substrate which comprises at least one layer of first semiconductor material 2, a layer of second semiconductor material 4 and an insulation layer 6. The stub substrate also comprises a support layer 7 .

La couche en premier matériau semi-conducteur 2 peut être formée à la surface de la couche de support 7 ou être formée par une zone surfacique de la couche de support 7, c'est-à-dire dans la couche de support 7 (figure 2). La couche en premier matériau semi-conducteur 2 peut également être de type semi-conducteur sur isolant, par exemple de type partiellement déplété. Elle est alors séparée de la couche de support 7 par un matériau diélectrique dit diélectrique enterré (non représenté). De ce fait, le premier matériau semi-conducteur 2 peut être dans le même matériau que la couche de support 7 ou alors dans un matériau différent. Il est également envisageable que la couche de support 7 et le premier matériau semi-conducteur 2 présentent la même orientation cristallographique ou des orientations différentes.The layer of first semiconductor material 2 can be formed on the surface of the support layer 7 or be formed by a surface area of the support layer 7, that is to say in the support layer 7 ( picture 2 ). The first semiconductor material layer 2 can also be of the semiconductor-on-insulator type, for example of the partially depleted type. It is then separated from support layer 7 by a dielectric material called buried dielectric (not shown). Therefore, the first semiconductor material 2 can be in the same material as the support layer 7 or else in a different material. It is also possible that the layer support 7 and the first semiconductor material 2 have the same crystallographic orientation or different orientations.

La couche en second matériau semi-conducteur 4 est séparée de la couche en premier matériau semi-conducteur 2 par au moins une couche d'isolation 6. Le second matériau semi-conducteur 4 est donc de type semi-conducteur sur isolant. Le second matériau semi-conducteur 4 est séparé de la couche de support 7 au moins par la couche d'isolation 6 si le premier matériau semi-conducteur 2 est réalisé directement à la surface de la couche de support 7. Les premier 2 et second 4 matériaux semi-conducteurs peuvent être dans des matériaux identiques ou différents et présenter des orientations identiques ou différentes.The second semiconductor material layer 4 is separated from the first semiconductor material layer 2 by at least one insulation layer 6. The second semiconductor material 4 is therefore of the semiconductor-on-insulator type. The second semiconductor material 4 is separated from the support layer 7 at least by the insulation layer 6 if the first semiconductor material 2 is made directly on the surface of the support layer 7. The first 2 and second 4 semiconductor materials can be in the same or different materials and have the same or different orientations.

Ainsi, dans une vue en coupe et quel que soit l'empilement utilisé, le substrat souche comporte au moins successivement la couche de support 7, la couche en premier matériau semi-conducteur 2, la couche d'isolation 6 et la couche en second matériau semi-conducteur 4. Le substrat souche peut également comporter des couches additionnelles en matériaux semi-conducteurs et des couches d'isolation additionnelles. Cependant, quel que soit le mode de réalisation, la couche en premier matériau semi-conducteur 2 est disposée entre la couche de support 7 et la couche d'isolation 6. De même, la couche d'isolation 6 est disposée entre les premier 2 et second 4 matériaux semi-conducteurs. Le substrat source peut donc être de type semi-conducteur sur isolant.Thus, in a sectional view and regardless of the stack used, the stem substrate comprises at least successively the support layer 7, the layer of first semiconductor material 2, the insulation layer 6 and the second layer. semiconductor material 4. The stem substrate may also comprise additional layers of semiconductor materials and additional insulation layers. However, whatever the embodiment, the layer of first semiconductor material 2 is placed between the support layer 7 and the insulation layer 6. Similarly, the insulation layer 6 is placed between the first 2 and second 4 semiconductor materials. The source substrate can therefore be of the semiconductor-on-insulator type.

Le substrat hybride devant être utilisé pour réaliser des circuits intégrés, il est avantageux de limiter au maximum la différence de hauteur entre la surface principale de la première zone active 1 en premier matériau semi-conducteur 2 et la surface principale de la seconde zone active 3 en second matériau semi-conducteur 4. La surface principale des zones actives est la surface sur laquelle est formée un transistor ou un dispositif électronique en général. Plus cette différence de hauteur est importante et plus il est difficile de réaliser des étapes de photolithographies de bonne qualité à cause des limitations de profondeur de champ des équipements utilisés.The hybrid substrate having to be used to produce integrated circuits, it is advantageous to limit as much as possible the difference in height between the main surface of the first active zone 1 in first semiconductor material 2 and the main surface of the second active zone 3 in second semiconductor material 4. The main surface of the active zones is the surface on which a transistor or an electronic device in general is formed. More this difference in height is significant and the more difficult it is to carry out good quality photolithography steps because of the depth of field limitations of the equipment used.

Comme illustré à la figure 3, un masque de gravure 8 est formé sur le substrat souche, c'est-à-dire sur la couche la plus éloignée de la couche de support 7, ici le second matériau semi-conducteur 4. A titre d'exemple, le masque de gravure est formé dans un masque dur en premier matériau de protection 9. Dans une variante de réalisation, le masque de gravure 8 comporte au moins un premier matériau de protection 9 qui recouvre un matériau de protection additionnel 10. Selon les modes de réalisation le premier matériau de protection 9 et le matériau de protection additionnel 10 peuvent présenter des structurations différentes et donc des dessins différents.As shown in picture 3 , an etching mask 8 is formed on the stem substrate, that is to say on the layer farthest from the support layer 7, here the second semiconductor material 4. By way of example, the mask etching is formed in a hard mask in first protective material 9. In a variant embodiment, the etching mask 8 comprises at least a first protective material 9 which covers an additional protective material 10. According to the embodiments the first protective material 9 and additional protective material 10 may have different structures and therefore different designs.

Le masque dur est structuré afin de former le masque de gravure 8. Le masque de gravure 8 délimite au moins une première zone active 1 du substrat, une seconde zone active 3 du substrat et une zone d'isolation 5 du substrat. Le masque de gravure peut délimiter une pluralité de premières zones actives 1, de secondes zones actives 3 et de zones d'isolation 5. Les première 1 et seconde 3 zones actives et la zone d'isolation 5 étant formées dans le masque de gravure, elles sont obligatoirement décalées latéralement les unes par rapport aux autres. Une zone d'isolation 5 sépare les première 1 et seconde 3 zones actives. En d'autres termes, dans un circuit intégré, la première zone active 1 et la seconde zone active 3 sont entourées par une zone d'isolation 5 comme illustré en vue de dessus à la figure 4. Dans le masque de gravure 8, la délimitation de la zone d'isolation 5 est définie par une zone vide alors que la délimitation des première 1 et seconde 3 zones actives est réalisée par une zone pleine. Cependant, il est envisageable de réalisée un masque de gravure de polarité inverse et de modifier cette polarité au fur et à mesure des étapes du procédé.The hard mask is structured in order to form the etching mask 8. The etching mask 8 delimits at least a first active area 1 of the substrate, a second active area 3 of the substrate and an insulation area 5 of the substrate. The etching mask can delimit a plurality of first active zones 1, second active zones 3 and isolation zones 5. The first 1 and second 3 active zones and the isolation zone 5 being formed in the etching mask, they are necessarily offset laterally relative to each other. An isolation zone 5 separates the first 1 and second 3 active zones. In other words, in an integrated circuit, the first active zone 1 and the second active zone 3 are surrounded by an insulation zone 5 as illustrated in top view at figure 4 . In the etching mask 8, the delimitation of the isolation zone 5 is defined by an empty zone whereas the delimitation of the first 1 and second 3 active zones is carried out by a solid zone. However, it is conceivable to produce an etching mask of reverse polarity and to modify this polarity as the steps of the method progress.

Le masque de gravure 8 comporte donc des dessins distincts délimitant les premières zones actives 1, des dessins délimitant les secondes zones actives 3 et des dessins délimitant les zones d'isolation 5. Ces trois types de dessins représentent l'intégralité de la surface du masque de gravure 5 (figure 4).The etching mask 8 therefore comprises distinct drawings delimiting the first active zones 1, drawings delimiting the second active zones 3 and drawings delimiting the isolation zones 5. These three types of drawings represent the entire surface of the mask of engraving 5 ( figure 4 ).

Comme illustré à la figure 5, une fois le masque de gravure 8 réalisé, la couche en premier matériau semi-conducteur 2, la couche en second matériau semi-conducteur 4 et la couche d'isolation 6 sont structurées pour délimiter la zone d'isolation 5 dans le premier matériau semi-conducteur 2 et libérer la surface principale de la première zone active 1 en premier matériau semi-conducteur 2. La surface principale de la première zone active 1 devant être libérée, il est nécessaire d'éliminer au-dessus du premier matériau semi-conducteur 2, la couche d'isolation 6, le second matériau semi-conducteur 4 et le masque de gravure 8 dans la zone indiquée. La structuration du premier matériau semi-conducteur 2 délimite simultanément la première zone active 1 et la zone d'isolation 5. La surface principale de la première zone active correspond à la surface du substrat de support qui réalisait l'interface avec la couche d'isolation. De cette manière, la surface principale de la première zone active est sous le niveau de la couche d'isolation 6. La surface principale de la première zone active est ici dans le même plan que l'interface entre le premier matériau semi-conducteur et la couche d'isolation 6.As shown in figure 5 , once the etching mask 8 has been produced, the layer of first semiconductor material 2, the layer of second semiconductor material 4 and the insulation layer 6 are structured to delimit the insulation zone 5 in the first material semiconductor 2 and release the main surface of the first active zone 1 in first semiconductor material 2. The main surface of the first active zone 1 having to be released, it is necessary to eliminate above the first semiconductor material conductor 2, the insulation layer 6, the second semiconductor material 4 and the etching mask 8 in the area indicated. The structuring of the first semiconductor material 2 simultaneously delimits the first active zone 1 and the insulation zone 5. The main surface of the first active zone corresponds to the surface of the support substrate which formed the interface with the layer of insulation. In this way, the main surface of the first active zone is below the level of the insulation layer 6. The main surface of the first active zone is here in the same plane as the interface between the first semiconductor material and insulation layer 6.

Lors de cette structuration, la première zone active 1, la zone d'isolation 5 et la seconde zone active 3 sont délimitées. Il y a également structuration du masque de gravure 8 pour éliminer la portion du masque de gravure 8 qui délimite la première zone active 1. Cependant, cette structuration du masque de gravure 8 peut intervenir à différents moments selon les modes de réalisation utilisés.During this structuring, the first active zone 1, the isolation zone 5 and the second active zone 3 are delimited. There is also structuring of the etching mask 8 to eliminate the portion of the etching mask 8 which delimits the first active zone 1. However, this structuring of the etching mask 8 can occur at different times depending on the embodiments used.

De manière classique, pour atteindre le premier matériau semi-conducteur 2, la couche en second matériau semi-conducteur 4 et la couche d'isolation 6 sont structurées. Cette structuration peut être réalisée classiquement au moyen d'une gravure par plasma et elle peut s'enfoncer après le premier matériau semi-conducteur 2, par exemple jusque dans la couche de support 7.Conventionally, to reach the first semiconductor material 2, the layer of second semiconductor material 4 and the insulation layer 6 are structured. This structuring can be carried out conventionally by means of plasma etching and it can sink after the first semiconductor material 2, for example right down to the support layer 7.

Dans un premier mode de réalisation, illustré à la figure 6, la zone libre du masque de gravure 8 délimite la zone d'isolation 5. Le second matériau semi-conducteur 4, la couche d'isolation 6 puis le premier matériau semi-conducteur 2 sont structurés successivement à partir du dessin représenté par la zone libre du masque de gravure 8. Le dessin de la zone d'isolation 5 est donc gravé dans les différentes couches se situant entre le masque de gravure 8 et la couche en premier matériau semi-conducteur 2. Cette structuration forme une zone vide dans le second matériau semi-conducteur 4, la couche d'isolation 6 et le premier matériau semi-conducteur 2. Cette structuration délimite également la seconde zone active 3 en second matériau semi-conducteur 4 au moment de la gravure de ce second matériau semi-conducteur 4.In a first embodiment, illustrated in figure 6 , the free area of the etching mask 8 delimits the insulation area 5. The second semiconductor material 4, the insulation layer 6 then the first semiconductor material 2 are successively structured from the drawing represented by the area free of the etching mask 8. The design of the insulation zone 5 is therefore etched in the different layers located between the etching mask 8 and the layer of first semiconductor material 2. This structuring forms an empty zone in the second semiconductor material 4, the insulation layer 6 and the first semiconductor material 2. This structuring also delimits the second active zone 3 in second semiconductor material 4 at the time of the etching of this second semiconductor material 4.

Comme illustré à la figure 7, le masque de gravure 8 est ensuite structuré pour être éliminé au niveau de la première zone active 1. L'élimination de la portion du masque de gravure 8 qui délimite la première zone active 1 peut être réalisée par toute technique adaptée, par exemple au moyen d'une étape de photolithographie et de gravure. La surface principale de la première zone active est ensuite libérée en éliminant le second matériau semi-conducteur 4 et la couche d'isolation 6 se trouvant juste au-dessus de la première zone active. Le masque de gravure 8 peut être avantageusement utilisé pour protéger le reste du substrat lors de la gravure.As shown in figure 7 , the etching mask 8 is then structured to be eliminated at the level of the first active zone 1. The elimination of the portion of the etching mask 8 which delimits the first active zone 1 can be carried out by any suitable technique, for example at means of a step of photolithography and etching. The main surface of the first active area is then freed by removing the second semiconductor material 4 and the insulation layer 6 located just above the first active area. The etching mask 8 can advantageously be used to protect the rest of the substrate during etching.

Dans une variante de réalisation avantageuse, illustrée à la figure 8, le dessin délimitant la première zone active 1 dans le masque de gravure 8 est réalisé au moyen d'une pluralité de motifs espacés les uns des autres. Ainsi, dans le masque de gravure 8, la délimitation de la première zone active 1 est réalisée par une alternance de motifs et de zones vides. La distance entre deux bords latéraux en regard de deux motifs adjacents est inférieure à la plus petite distance qui existe entre un bord latéral d'un dessin délimitant la première zone active 1 et un bord latéral d'un dessin délimitant la seconde zone active 3. En d'autres termes, la plus grande distance entre deux motifs adjacents est inférieure à la plus petite distance qui sépare la paroi latérale du dessin délimitant la première zone active de la paroi latérale du dessin de la seconde zone active 3. De plus, la dimension latérale et/ou longitudinale des motifs est inférieure à l'épaisseur du masque de gravure. A titre d'exemple, les motifs sont espacés d'environ le tiers de la distance qui sépare normalement deux transistors. Dans une intégration pour le noeud technologique 45nm, la distance minimale qui sépare deux transistors est de l'ordre de 100nm et de ce fait, la distance qui sépare deux motifs est de l'ordre de 30nm. Pour une intégration dans des noeuds technologiques inférieurs, il suffit de diminuer les distances précisées plus haut.In an advantageous embodiment variant, illustrated in figure 8 , the drawing delimiting the first active zone 1 in the etching mask 8 is produced by means of a plurality of patterns spaced from each other. Thus, in the etching mask 8, the delimitation of the first active zone 1 is carried out by alternating patterns and empty areas. The distance between two side edges facing two adjacent patterns is less than the smallest distance that exists between a side edge of a design delimiting the first active area 1 and a side edge of a design delimiting the second active area 3. In other words, the greatest distance between two adjacent patterns is less than the smallest distance which separates the side wall of the design delimiting the first active area from the side wall of the design of the second active area 3. In addition, the lateral and/or longitudinal dimension of the patterns is less than the thickness of the etching mask. By way of example, the patterns are spaced apart by approximately one third of the distance that normally separates two transistors. In an integration for the 45nm technological node, the minimum distance which separates two transistors is of the order of 100nm and therefore the distance which separates two patterns is of the order of 30nm. For integration in lower technological nodes, it suffices to reduce the distances specified above.

De ce fait, les motifs peuvent être de forme quelconque, par exemple, ils peuvent être carrés ou rectangulaires ou les deux. La paroi latérale du dessin délimitant la première zone active est obtenue en reliant tous les motifs se situant sur les bords. Leur taille peut être quelconque tant que la distance entre les motifs est respectée.Therefore, the patterns can be of any shape, for example, they can be square or rectangular or both. The side wall of the design delimiting the first active area is obtained by connecting all the patterns located on the edges. Their size can be any as long as the distance between the patterns is respected.

Comme illustré à la figure 9, un premier bouchon 11 est formé dans les espaces entre les motifs du dessin délimitant la première zone active afin de former un dessin plein, c'est-à-dire sans zone vide. Avantageusement, le premier bouchon 11 est formé au moyen d'un matériau de recouvrement déposé de manière conforme, c'est-à-dire qui épouse la forme du matériau qu'il recouvre. L'espace entre les motifs étant plus petit que l'espace entre la première zone active 1 et la seconde zone active 3, le matériau de recouvrement rebouche les zones vides du dessin de la première zone active 1 sans complètement reboucher le dessin délimitant la zone d'isolation, également une zone vide. L'épaisseur du matériau de recouvrement est choisie en conséquence et le matériau de recouvrement est ensuite éliminé de manière isotrope. De cette manière, le matériau de recouvrement n'est présent que dans le dessin délimitant la première zone active 1. La zone vide du masque de gravure 8 ne délimite plus que la zone d'isolation 5.As shown in figure 9 , a first plug 11 is formed in the spaces between the patterns of the drawing delimiting the first active zone in order to form a solid drawing, that is to say without any empty zone. Advantageously, the first plug 11 is formed by means of a covering material deposited in a conformal manner, that is to say which matches the shape of the material which it covers. The space between the patterns being smaller than the space between the first active zone 1 and the second active zone 3, the covering material fills in the empty zones of the design of the first active zone 1 without completely filling in the drawing delimiting the zone insulation, also an empty area. The thickness of the covering material is chosen accordingly and the covering material is then removed isotropically. In this way, the covering material is present only in the drawing delimiting the first active zone 1. The empty zone of the etching mask 8 now only delimits the isolation zone 5.

La structuration du second matériau semi-conducteur 4, de la couche d'isolation 6 et du premier matériau semi-conducteur 2 peut ensuite être réalisée. Une fois la structuration effectuée, le matériau de recouvrement est éliminé sélectivement par tout procédé adapté et les motifs délimitant la première zone active 1 sont éliminés. Cette élimination est avantageusement réalisée au moyen d'une gravure isotrope du ou des matériaux constituant le masque de gravure 8. Il y a alors un léger retrait du masque de gravure 8 au niveau des parois latérales des dessins des première 1 et seconde 3 zones actives.The structuring of the second semiconductor material 4, of the insulation layer 6 and of the first semiconductor material 2 can then be carried out. Once the structuring has been carried out, the covering material is selectively eliminated by any suitable method and the patterns delimiting the first active zone 1 are eliminated. This elimination is advantageously carried out by means of an isotropic etching of the material or materials constituting the etching mask 8. There is then a slight shrinkage of the etching mask 8 at the level of the side walls of the drawings of the first 1 and second 3 active zones .

Dans le cas où le masque de gravure 8 au-dessus de la première zone active 1 comporte un matériau de protection additionnel 10, l'élimination des motifs du dessin délimitant la première zone active 1 est réalisée au moyen de la gravure sélective du matériau de protection additionnel 10. Cette gravure sélective entraîne un décollement des motifs. Il est envisageable que le matériau de recouvrement et le matériau de protection additionnel 10 soit les mêmes ou qu'ils présentent une réactivité au même procédé de gravure.In the case where the etching mask 8 above the first active zone 1 comprises an additional protective material 10, the elimination of the patterns of the drawing delimiting the first active zone 1 is carried out by means of the selective etching of the protective material. additional protection 10. This selective etching causes the patterns to detach. It is conceivable that the covering material and the additional protective material 10 are the same or that they exhibit a reactivity to the same etching process.

Comme illustré à la figure 10, une fois le dessin du masque de gravure 8 délimitant la première zone active 1 éliminé, les parties du second matériau semi-conducteur 2 et de la couche d'isolation 6 délimitant la première zone active 1 sont également éliminées. Ainsi, une fois la zone d'isolation 5 définie dans le premier matériau semi-conducteur 2, tous les matériaux qui se trouvent au-dessus de la première zone active 1 en premier matériau semi-conducteur 2 sont enlevés, y compris le masque de gravure 8 pour libérer la surface principale de la première zone active 1.As shown in figure 10 , once the design of the etching mask 8 delimiting the first active zone 1 has been eliminated, the parts of the second semiconductor material 2 and of the insulation layer 6 delimiting the first active zone 1 are also eliminated. Thus, once the insulation zone 5 has been defined in the first semiconductor material 2, all the materials which are above the first active zone 1 in the first semiconductor material 2 are removed, including the etching mask 8 to free the main surface of the first active zone 1.

Dans une variante de réalisation illustrée aux figures 11 et 12, le premier matériau de protection 9 est remplacé par un second matériau de protection 12 uniquement dans le dessin délimitant la première zone active 1. Ce second matériau de protection 12 présente une sélectivité de gravure par rapport au premier matériau de protection 9. Le second matériau de protection 12 peut être formé par toute technique adaptée, par exemple, par l'implantation d'un dopant ou d'un autre matériau dans le premier matériau de protection 9 au niveau de la zone à transformer.In a variant embodiment illustrated in figure 11 and 12 , the first protective material 9 is replaced by a second protective material 12 only in the drawing delimiting the first active zone 1. This second protective material 12 has an etching selectivity with respect to the first protective material 9. The second material protection 12 can be formed by any suitable technique, for example, by implanting a dopant or another material in the first protection material 9 at the level of the zone to be transformed.

Dans une autre variante de réalisation illustrée à la figure 13, un second bouchon 13 est formé dans le masque de gravure 8 au niveau du dessin délimitant la zone d'isolation 5. Le second bouchon 13 délimite alors la zone d'isolation dans le masque de gravure 8. Après élimination du premier matériau de protection au niveau du dessin délimitant la première zone active, le second matériau de protection 12 est formé dans la zone vide du masque de gravure 8.In another alternative embodiment illustrated in figure 13 , a second plug 13 is formed in the etching mask 8 at the level of the drawing delimiting the isolation zone 5. The second plug 13 then delimits the isolation zone in the etching mask 8. After removal of the first protective material at the level of the drawing delimiting the first active zone, the second protective material 12 is formed in the empty zone of the etching mask 8.

Dans encore une autre variante de réalisation, le masque de gravure comporte le premier matériau de protection 9 formé sur le matériau de protection additionnel 10. Le second matériau de protection 12 est alors formé par le matériau de protection additionnel 10 après élimination du premier matériau de protection 9. Avantageusement, le second bouchon est utilisé afin d'éviter la gravure latérale des dessins délimitant les première 1 et seconde 3 zones actives.In yet another alternative embodiment, the etching mask comprises the first protective material 9 formed on the additional protective material 10. The second protective material 12 is then formed by the additional protective material 10 after removal of the first material from protection 9. Advantageously, the second cap is used in order to avoid the lateral engraving of the drawings delimiting the first 1 and second 3 active zones.

Dans tous ces modes de réalisation, le masque de gravure 8 délimite alors la première zone active 1, la seconde zone active 3 et la zone d'isolation 5 au moyen de trois matériaux différents qui peuvent présenter entre eux des différences d'épaisseur.In all these embodiments, the etching mask 8 then delimits the first active zone 1, the second active zone 3 and the isolation zone 5 at the means of three different materials which may have differences in thickness between them.

Comme dans un mode de réalisation précédent, le dessin du masque de gravure 8 délimitant la première zone active 1 peut être constitué par une pluralité de motifs espacés les uns des autres et qui présentent les mêmes contraintes dimensionnelles que précédemment. Le premier bouchon 11 est alors formé avant la formation du second matériau de protection 12. Dans une variante de réalisation avantageuse illustrée aux figures 14 et 15, le masque de gravure 8 comporte un premier matériau de protection 9 déposé au-dessus d'un matériau de protection additionnel 10. Le premier bouchon 11 est formé avant le second bouchon 13. La couche de protection additionnelle 10 est structurée une fois que le premier bouchon est formé. Le premier bouchon 11 est éliminé et le premier matériau de protection est éliminé au niveau du dessin de la première zone active au moyen d'une gravure anisotrope. De cette manière, l'épaisseur du premier matériau de protection 9 est légèrement diminuée dans le masque de gravure 8 et le dessin de la première zone active en premier matériau de protection 9 est éliminé (figure 15). Le second bouchon 13 est alors éliminé et le substrat est sensiblement identique à celui de la figure 12, l'épaisseur du masque de gravure 8 au-dessus de la zone active étant plus faible.As in a previous embodiment, the design of the etching mask 8 delimiting the first active zone 1 can be constituted by a plurality of patterns spaced from each other and which have the same dimensional constraints as before. The first plug 11 is then formed before the formation of the second protective material 12. In an advantageous embodiment variant illustrated in figure 14 and 15 , the etching mask 8 comprises a first protective material 9 deposited above an additional protective material 10. The first plug 11 is formed before the second plug 13. The additional protective layer 10 is structured once the first plug is formed. The first cap 11 is eliminated and the first protective material is eliminated at the level of the design of the first active zone by means of an anisotropic etching. In this way, the thickness of the first protective material 9 is slightly reduced in the etching mask 8 and the design of the first active zone in first protective material 9 is eliminated ( figure 15 ). The second plug 13 is then removed and the substrate is substantially identical to that of the figure 12 , the thickness of the etching mask 8 above the active area being lower.

Comme illustré à la figure 13, une fois le second matériau de protection formé, le second bouchon 13 est éliminé et la zone d'isolation 5 est structurée dans le premier matériau semi-conducteur. Les couches situées au-dessus de la première zone active en premier matériau semi-conducteur sont enlevés.As shown in figure 13 , once the second protective material has been formed, the second cap 13 is eliminated and the insulation zone 5 is structured in the first semiconductor material. The layers located above the first active zone in first semiconductor material are removed.

Dans un mode de réalisation avantageux illustré aux figures 16 à 18, le second matériau de protection 12 est dans le même matériau que la couche d'isolation 6 ou dans un matériau qui se grave avec le même procédé de gravure. De cette manière, le masque de gravure 8 en premier 9 et second 12 matériaux de protection est utilisé pour structurer le second matériau semi-conducteur 4 et délimiter la zone d'isolation 5 et la seconde zone active 3 dans le second matériau semi-conducteur 4. La couche d'isolation 6 est ensuite structurée pour délimiter la zone d'isolation 5. La couche d'isolation 6 et le second matériau de protection 12 étant réactifs au même procédé de gravure, le second matériau de protection 12 est éliminé au niveau de la première zone active 1. Le premier matériau semi-conducteur 2 est ensuite structuré pour délimiter la zone d'isolation 5 et donc la première zone active 1 au moyen du motif en couche d'isolation 6 délimitant la première zone active 1. Le motif en couche d'isolation 6 est ensuite éliminé.In an advantageous embodiment illustrated in figures 16 to 18 , the second protective material 12 is in the same material as the insulating layer 6 or in a material which is etched with the same etching process. In this way, the etching mask 8 in first 9 and second 12 materials protection is used to structure the second semiconductor material 4 and delimit the isolation zone 5 and the second active zone 3 in the second semiconductor material 4. The insulation layer 6 is then structured to delimit the zone of insulation 5. The insulation layer 6 and the second protective material 12 being reactive to the same etching process, the second protective material 12 is eliminated at the level of the first active zone 1. The first semiconductor material 2 is then structured to delimit the insulation zone 5 and therefore the first active zone 1 by means of the pattern in the insulation layer 6 delimiting the first active zone 1. The pattern in the insulation layer 6 is then eliminated.

Dans ce mode de réalisation, les structurations sont réalisées au moyen de gravures anisotropes qui reproduisent dans la couche inférieure le dessin de la première zone active 1 provenant du masque de gravure 8.In this embodiment, the structurings are produced by means of anisotropic etchings which reproduce in the lower layer the design of the first active zone 1 originating from the etching mask 8.

Dans tous ces modes de réalisation, la structuration de la couche d'isolation 6 et des couches en premier matériau semi-conducteur 2, en second matériau semi-conducteur 4 et la libération de la surface principale de la première zone active 1 forme des zones vides dans le substrat souche. Ces zones vides sont localisées dans le second matériau semi-conducteur 4, dans la couche d'isolation 6 et dans le premier matériau semi-conducteur 2. Les zones vides sont également présentes dans le masque de gravure 8.In all these embodiments, the structuring of the insulation layer 6 and of the layers of first semiconductor material 2, of second semiconductor material 4 and the release of the main surface of the first active zone 1 form zones voids in the stem substrate. These empty areas are located in the second semiconductor material 4, in the insulation layer 6 and in the first semiconductor material 2. The empty areas are also present in the etching mask 8.

Dans le masque de gravure 8, dans le second matériau semi-conducteur 4 et dans la couche d'isolation 6, les zones vides correspondent à la surface de la première zone active 1 et de la zone d'isolation 5. Dans le premier matériau semi-conducteur 1, la zone vide correspond uniquement à la zone d'isolation 5.In the etching mask 8, in the second semiconductor material 4 and in the insulation layer 6, the empty areas correspond to the surface of the first active area 1 and of the insulation area 5. In the first material semiconductor 1, the empty zone corresponds only to the insulation zone 5.

Comme illustré à la figure 19, dans tous les modes de réalisation, un premier matériau d'isolation 14 est déposé afin de remplir les zones vides du substrat souche et le masque de gravure 8. Ce premier matériau d'isolation 14 est un matériau isolant électriquement, par exemple de l'oxyde de silicium ou du nitrure de silicium. Le premier matériau d'isolation 14 peut être différent du second matériau d'isolation constituant la couche d'isolation 6. Les premier et second matériaux d'isolation peuvent également être identiques.As shown in figure 19 , in all embodiments, a first insulation material 14 is deposited to fill the void areas of the substrate strain and the etching mask 8. This first insulating material 14 is an electrically insulating material, for example silicon oxide or silicon nitride. The first insulation material 14 may be different from the second insulation material constituting the insulation layer 6. The first and second insulation materials may also be identical.

Le premier matériau d'isolation 14 rebouche la zone d'isolation formée dans le premier matériau semi-conducteur 2, mais également la zone vide représentative de la zone d'isolation 5 et de la première zone active 1 dans la couche d'isolation 6 et dans le second matériau semi-conducteur 4. Le premier matériau d'isolation 14 se dépose également sur le masque de gravure 8.The first insulation material 14 fills in the insulation zone formed in the first semiconductor material 2, but also the empty zone representative of the insulation zone 5 and of the first active zone 1 in the insulation layer 6 and in the second semiconductor material 4. The first insulation material 14 is also deposited on the etching mask 8.

Le premier matériau d'isolation 14 subit de préférence une étape d'aplanissement, cette étape peut s'arrêter au-dessus ou au niveau du masque de gravure 8. Lors de cette opération, le masque de gravure peut être également gravé, mais il faut éviter de détériorer la surface principale du second matériau semi-conducteur 4. Une fois le premier matériau d'isolation 14 aplani, il subit une étape de gravure isotrope ou anisotrope afin de le localiser au niveau de la zone d'isolation 5 dans le premier matériau semi-conducteur 2. Dans cette étape de gravure, la planéité du premier matériau d'isolation est conservée tout au long de la gravure. Si la couche d'isolation 6 ou une autre des couches présentes et accessibles est réactive au procédé de gravure du premier matériau d'isolation 14, la gravure est réalisée au moyen d'un procédé anisotrope.The first insulation material 14 preferably undergoes a flattening step, this step can stop above or at the level of the etching mask 8. During this operation, the etching mask can also be etched, but it must avoid damaging the main surface of the second semiconductor material 4. Once the first insulation material 14 has been flattened, it undergoes an isotropic or anisotropic etching step in order to locate it at the level of the insulation zone 5 in the first semiconductor material 2. In this etching step, the flatness of the first insulation material is maintained throughout the etching. If the insulation layer 6 or another of the layers present and accessible is reactive to the etching process of the first insulation material 14, the etching is carried out by means of an anisotropic process.

De cette manière, il est possible de positionner la surface supérieure du premier matériau d'isolation 14 où l'on veut par rapport à la surface principale de la première zone active 1 et/ou de la seconde zone active 2.In this way, it is possible to position the upper surface of the first insulating material 14 where desired with respect to the main surface of the first active zone 1 and/or of the second active zone 2.

Dans un mode de réalisation avantageux illustré à la figure 20, la gravure du premier matériau d'isolation 14 est réalisée jusqu'à libérer la surface principale de la première zone active 1. Dans ce cas de figure, la surface principale de la première zone active 1 est exactement au même niveau que la surface principale de la zone d'isolation 5 en premier matériau d'isolation 14. La première zone active 1 et la zone d'isolation 5 ayant des formes complémentaires, aucune impureté ne peut se déposer à l'interface entre ces deux zones et les impuretés ne sont pas coincés sur la première zone active 1, par exemple à cause de zones d'isolation 5 qui sont plus hautes que la surface principale de la première zone active 1. De plus, le transistor formé sur la première zone active 1 ne présente pas de transistor parasite car la surface principale de la première zone active 1 n'est pas au-dessus de la surface de la zone d'isolation 5.In an advantageous embodiment illustrated in figure 20 , the etching of the first insulation material 14 is carried out until the main surface is freed of the first active area 1. In this case, the main surface of the first active area 1 is exactly at the same level as the main surface of the insulation area 5 made of first insulation material 14. The first active area 1 and the isolation zone 5 having complementary shapes, no impurity can be deposited at the interface between these two zones and the impurities are not stuck on the first active zone 1, for example because of isolation zones 5 which are higher than the main surface of the first active zone 1. In addition, the transistor formed on the first active zone 1 does not present any parasitic transistor because the main surface of the first active zone 1 is not above above the surface of the insulation zone 5.

Il est également possible, de volontairement rabaisser la surface principale de la zone d'isolation par rapport à celle de la première zone active 1. Dans ce cas, le premier matériau d'isolation 14 présentant une surface plane, cette surface plane est répercutée tout au long de la gravure, même en dessus de la surface principale de la première zone active 1, c'est-à-dire après la libération de la surface principale de la première zone active 1.It is also possible to voluntarily lower the main surface of the insulation zone relative to that of the first active zone 1. In this case, the first insulation material 14 having a flat surface, this flat surface is passed on while throughout the etching, even above the main surface of the first active zone 1, that is to say after the release of the main surface of the first active zone 1.

Dans une variante de réalisation illustrée à la figure 20, un espaceur latéral 15 est formé sur le bord latéral de la seconde zone active 3 en second matériau semi-conducteur 4, au-dessus de la zone d'isolation 5 en premier matériau d'isolation 14. L'espaceur latéral 15 peut être formé après la localisation du premier matériau d'isolation 14 dans la zone d'isolation 5 du premier matériau semi-conducteur 2.In a variant embodiment illustrated in figure 20 , a lateral spacer 15 is formed on the lateral edge of the second active zone 3 in second semiconductor material 4, above the insulation zone 5 in first insulation material 14. The lateral spacer 15 can be formed after the location of the first insulation material 14 in the insulation area 5 of the first semiconductor material 2.

Un matériau isolant additionnel est déposé de manière conforme sur le substrat. Le matériau isolant additionnel recouvre le masque de gravure 8, la première zone active 1, le premier matériau d'isolation 14 et les parois latérales du masque de gravure 8, du second matériau semi-conducteur 4 et de la couche d'isolation 6. Le matériau isolant additionnel est ensuite gravé par plasma de manière anisotrope afin de ne localiser uniquement sur les parois latérales et ainsi former l'espaceur latéral 15.Additional insulating material is conformally deposited on the substrate. The additional insulating material covers the etching mask 8, the first active area 1, the first insulation material 14 and the side walls of the etching mask 8, of the second semiconductor material 4 and of the insulation layer 6. The additional insulating material is then etched by plasma in an anisotropic manner so as to locate only on the side walls and thus form the side spacer 15.

L'espaceur latéral peut également être formé au cours de la gravure du premier matériau d'isolation 14. Le matériau isolant additionnel est déposé de manière conforme sur le substrat. Le matériau isolant additionnel recouvre le masque de gravure 8, le premier matériau d'isolation 14 et les parois latérales découvertes. Le matériau isolant additionnel est ensuite gravé par plasma de manière anisotrope afin de ne le localiser uniquement que sur les parois latérales. La gravure du premier matériau d'isolation 14 est alors reprise avec un procédé de gravure anisotrope et l'espaceur latéral est formé par le matériau isolant additionnel dans une partie supérieure et par le premier matériau d'isolation dans une partie inférieure.The lateral spacer can also be formed during the etching of the first insulating material 14. The additional insulating material is conformally deposited on the substrate. The additional insulating material covers the etching mask 8, the first insulating material 14 and the exposed side walls. The additional insulating material is then etched by plasma in an anisotropic manner so that it is only located on the side walls. The etching of the first insulating material 14 is then resumed with an anisotropic etching process and the lateral spacer is formed by the additional insulating material in an upper part and by the first insulating material in a lower part.

L'épaisseur déposée du matériau isolant additionnel ainsi que l'épaisseur gravée dépendent de l'épaisseur choisie pour l'espaceur latéral.The deposited thickness of the additional insulating material as well as the etched thickness depend on the thickness chosen for the lateral spacer.

Dans encore une autre variante de réalisation (non représentée), il est envisageable de ne libérer qu'une portion de la première zone active 1. Si l'espaceur latéral 15 est formé avant la libération de la surface principale de la première zone active 1 et si l'épaisseur de l'espaceur latéral 15 est supérieure à la distance séparant la première 1 et la seconde 3 zones actives (la largeur de la zone d'isolation 5), l'espaceur latéral 15 est disposé au-dessus de la première zone active 1. Il est alors possible d'utiliser l'espaceur latéral 15 comme masque de gravure et de ne libérer qu'une partie de la première zone active 1. Ce mode de réalisation est particulièrement avantageux si on souhaite réaliser une élévation de la hauteur de la face principale de la première zone active 1, par exemple, par épitaxie sélective. Il est à noter que ce mode de réalisation est difficile à mettre en oeuvre car il nécessite un certain nombre de contraintes géométriques pour obtenir un espaceur latéral 15 qui empiète sur la première zone active 1 (typiquement un masque de gravure très épais). L'ouverture dans le premier matériau d'isolation peut également être réalisée au moyen d'une étape de photolithographie additionnelle mais il y a alors perte de l'autoalignement de la première zone active 1 par rapport à la seconde zone active 3 et à la zone d'isolation 5.In yet another alternative embodiment (not shown), it is possible to release only a portion of the first active zone 1. If the lateral spacer 15 is formed before the release of the main surface of the first active zone 1 and if the thickness of the lateral spacer 15 is greater than the distance separating the first 1 and the second 3 active zones (the width of the isolation zone 5), the lateral spacer 15 is arranged above the first active zone 1. It is then possible to use the lateral spacer 15 as an etching mask and to release only part of the first active zone 1. This embodiment is particularly advantageous if it is desired to achieve an elevation of the height of the main face of the first active zone 1, for example, by selective epitaxy. It should be noted that this embodiment is difficult to implement because it requires a certain number of geometric constraints to obtain a lateral spacer 15 which encroaches on the first active zone 1 (typically an etching mask very thick). The opening in the first insulation material can also be produced by means of an additional photolithography step, but there is then a loss of the self-alignment of the first active zone 1 with respect to the second active zone 3 and to the isolation zone 5.

Le masque de gravure 8 est ensuite éliminé, par toute technique adaptée, par exemple au moyen d'une gravure anisotrope telle qu'une gravure par voie humide et la surface principale de la seconde zone active est libérée.Etching mask 8 is then eliminated, by any suitable technique, for example by means of anisotropic etching such as wet etching, and the main surface of the second active zone is freed.

Ce procédé de réalisation est particulièrement intéressant car il permet de manière autoalignée de former des première 1 et seconde 3 zones actives et une zone d'isolation 5. La position, la forme et les dimensions des différentes zones sont définies dès le masque de gravure 8.This production method is particularly interesting because it allows self-aligned manner to form first 1 and second 3 active zones and an isolation zone 5. The position, shape and dimensions of the different zones are defined from the etching mask 8 .

Il est ainsi possible d'obtenir un substrat hybride qui comporte une première zone active 1 en premier matériau semi-conducteur 2, une seconde zone active 3 en second matériau semi-conducteur 4, les première 1 et seconde 2 zones actives étant disposées, latéralement, de part et d'autre d'une zone d'isolation 5 en premier matériau d'isolation 14. Les premier 2 et second 4 matériaux semi-conducteurs sont séparés par une couche d'isolation 6 en second matériau d'isolation dans une direction perpendiculaire à une surface principale d'une couche de support 7. Par ailleurs, la zone d'isolation 5 comporte une surface principale qui forme un plan unique avec la surface principale de la première zone active 1. La zone d'isolation 5 et la première zone active 1 ont des formes complémentaires le long de l'interface entre la zone d'isolation 5 et la première zone active 1. Les secondes zones actives 3 sont séparées électriquement des premières zones actives 1 par la couche d'isolation 6, d'un point de vue vertical.It is thus possible to obtain a hybrid substrate which comprises a first active zone 1 of first semiconductor material 2, a second active zone 3 of second semiconductor material 4, the first 1 and second 2 active zones being arranged, laterally , on either side of an insulation zone 5 of first insulation material 14. The first 2 and second 4 semiconductor materials are separated by an insulation layer 6 of second insulation material in a direction perpendicular to a main surface of a support layer 7. Furthermore, the isolation zone 5 comprises a main surface which forms a single plane with the main surface of the first active zone 1. The isolation zone 5 and the first active area 1 have complementary shapes along the interface between the insulation area 5 and the first active area 1. The second active areas 3 are electrically separated from the first active areas 1 by the insulation layer 6, from a point t of vertical view.

Ce substrat hybride est particulièrement avantageux car il autorise la formation de dispositifs spécifiques sur des zones actives présentant des caractéristiques électroniques et/ou cristallograhiques prédéfinies. Les zones actives présentent une excellente qualité de surface car elles ont toujours été protégées des étapes agressives. Les surfaces principales des zones actives sont, en générale, libérées au moyen d'une gravure humide. Le substrat ne présente pas des topographies de surface à proximité immédiate des zones actives surtout au niveau de la première zone active. Ceci a pour effet de limiter les risques de contamination lié à un problème de nettoyage et de limiter les transistors parasites. Les topographies existantes sont déportées au-dessus des zones d'isolation ce qui limite l'effet de matériaux parasites sur le fonctionnement du dispositif.This hybrid substrate is particularly advantageous because it allows the formation of specific devices on active areas having predefined electronic and/or crystallographic characteristics. Active areas have excellent surface quality as they have always been protected from aggressive steps. The main surfaces of the active areas are, in general, released by means of wet etching. The substrate does not have surface topographies in the immediate vicinity of the active zones, especially at the level of the first active zone. This has the effect of limiting the risks of contamination linked to a cleaning problem and of limiting parasitic transistors. The existing topographies are offset above the isolation zones, which limits the effect of parasitic materials on the operation of the device.

Claims (8)

Substrat hybride comportant : - un empilement comportant successivement, selon une première direction, une couche de support (7), une couche en premier matériau semi-conducteur (2), une couche d'isolation (6) en second matériau d'isolation et une couche en second matériau semi-conducteur (4), - une première zone active (1) définie dans la couche en premier matériau semi-conducteur (2), - une seconde zone active (3) définie dans la couche en second matériau semi-conducteur (4), - une zone d'isolation (5) en premier matériau d'isolation (14) formée dans la couche en premier matériau semi-conducteur (2), la zone d'isolation (5) entourant la première zone active (1) et séparant la première zone active (1) et la deuxième zone active (3) dans une direction d'observation selon la première direction, substrat hybride caractérisé en ce que la zone d'isolation (5) comporte une première portion bordant au moins un bord latéral de la première zone active (1), la première portion et la première zone active (1) ayant une face principale libérée en éliminant le second matériau semi-conducteur (4) et la couche d'isolation (6) se trouvant juste au-dessus de la première zone active (1), la face principale libérée formant un même plan avec l'interface entre la couche en premier matériau semi-conducteur (2) et la couche d'isolation (6), la zone d'isolation (5) et la première zone active (1) ayant des formes complémentaires le long d'une interface entre la zone d'isolation (5) et la première zone active (1).Hybrid substrate comprising: - a stack comprising successively, in a first direction, a support layer (7), a layer of first semiconductor material (2), an insulation layer (6) of second insulation material and a layer of second semiconductor material (4), - a first active zone (1) defined in the layer of first semiconductor material (2), - a second active zone (3) defined in the layer of second semiconductor material (4), - an insulation zone (5) of first insulation material (14) formed in the layer of first semiconductor material (2), the insulation zone (5) surrounding the first active zone (1) and separating the first active zone (1) and the second active zone (3) in a viewing direction along the first direction, hybrid substrate characterized in that the insulation zone (5) comprises a first portion bordering at least one lateral edge of the first active zone (1), the first portion and the first active zone (1) having a main face released in eliminating the second semiconductor material (4) and the insulation layer (6) located just above the first active zone (1), the released main face forming the same plane with the interface between the layer in first semiconductor material (2) and the isolation layer (6), the isolation region (5) and the first active region (1) having complementary shapes along an interface between the isolation region (5) and the first active area (1). Substrat hybride selon la revendication 1 dans lequel la couche en premier matériau semi-conducteur (2) présente une orientation identique à l'orientation du second matériau semi-conducteur (4).Hybrid substrate according to Claim 1, in which the layer of first semiconductor material (2) has an orientation identical to the orientation of the second semiconductor material (4). Substrat hybride selon la revendication 1 dans lequel la couche en premier matériau semi-conducteur (2) présente une orientation différente de l'orientation du second matériau semi-conducteur (4).Hybrid substrate according to Claim 1, in which the layer of first semiconductor material (2) has an orientation different from the orientation of the second semiconductor material (4). Substrat hybride selon l'une des revendications 1 à 3 dans lequel le premier matériau semi-conducteur (2) est identique au second matériau semi-conducteur (4).Hybrid substrate according to one of Claims 1 to 3, in which the first semiconductor material (2) is identical to the second semiconductor material (4). Substrat hybride selon l'une des revendications 1 à 3 dans lequel le premier matériau semi-conducteur (2) est différent du second matériau semi-conducteur (4).Hybrid substrate according to one of Claims 1 to 3, in which the first semiconductor material (2) is different from the second semiconductor material (4). Substrat hybride selon l'une des revendications 1 à 5 dans lequel le premier matériau d'isolation (14) est différent du second matériau d'isolation.Hybrid substrate according to one of Claims 1 to 5, in which the first insulation material (14) is different from the second insulation material. Substrat hybride selon l'une des revendications 1 à 5 dans lequel le premier matériau d'isolation (14) est identique au second matériau d'isolation la couche d'isolation 6.Hybrid substrate according to one of Claims 1 to 5, in which the first insulation material (14) is identical to the second insulation material, the insulation layer 6. Substrat hybride selon l'une des revendications 1 à 7 comportant un espaceur latéral (15) sur un bord latéral de la seconde zones active (3) en second matériau semiconducteur (4), au-dessus de la zone d'isolation (5) en premier matériau d'isolation (14).Hybrid substrate according to one of Claims 1 to 7 comprising a lateral spacer (15) on a lateral edge of the second active zone (3) made of second semiconductor material (4), above the insulation zone (5) into a first insulation material (14).
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