EP4020244A1 - Speichersystemarchitektur für heterogene speichertechnologien - Google Patents

Speichersystemarchitektur für heterogene speichertechnologien Download PDF

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Publication number
EP4020244A1
EP4020244A1 EP21215712.7A EP21215712A EP4020244A1 EP 4020244 A1 EP4020244 A1 EP 4020244A1 EP 21215712 A EP21215712 A EP 21215712A EP 4020244 A1 EP4020244 A1 EP 4020244A1
Authority
EP
European Patent Office
Prior art keywords
command
response
sub
memory
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP21215712.7A
Other languages
English (en)
French (fr)
Inventor
Simone Corbetta
Antonino Caprí
Alessandro Lucio Iannuzzi
Filippo Leonini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP4020244A1 publication Critical patent/EP4020244A1/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
EP21215712.7A 2020-12-17 2021-12-17 Speichersystemarchitektur für heterogene speichertechnologien Withdrawn EP4020244A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17/125,888 US11614892B2 (en) 2020-12-17 2020-12-17 Memory system architecture for heterogeneous memory technologies

Publications (1)

Publication Number Publication Date
EP4020244A1 true EP4020244A1 (de) 2022-06-29

Family

ID=79270321

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21215712.7A Withdrawn EP4020244A1 (de) 2020-12-17 2021-12-17 Speichersystemarchitektur für heterogene speichertechnologien

Country Status (3)

Country Link
US (1) US11614892B2 (de)
EP (1) EP4020244A1 (de)
CN (1) CN114649033A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11614892B2 (en) 2020-12-17 2023-03-28 Micron Technology, Inc. Memory system architecture for heterogeneous memory technologies
CN114817968B (zh) * 2022-06-29 2022-10-14 深圳红途科技有限公司 无特征数据的路径追溯方法、装置、设备及存储介质
CN116502291B (zh) * 2023-06-28 2023-10-03 之江实验室 基于三维异质集成的数据安全存储设备及数据存储方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7584335B2 (en) * 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
US8370558B2 (en) * 2004-12-30 2013-02-05 Intel Corporation Apparatus and method to merge and align data from distributed memory controllers

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7103684B2 (en) * 2003-12-02 2006-09-05 Super Talent Electronics, Inc. Single-chip USB controller reading power-on boot code from integrated flash memory for user storage
CN105027211B (zh) * 2013-01-31 2018-09-21 慧与发展有限责任合伙企业 自适应粒度行缓冲器高速缓存
US9335936B2 (en) * 2014-05-30 2016-05-10 Netapp, Inc. Event based tagging of storage system commands
US10645164B1 (en) * 2015-10-27 2020-05-05 Pavilion Data Systems, Inc. Consistent latency for solid state drives
US10740003B2 (en) * 2018-03-23 2020-08-11 International Business Machines Corporation Latency-agnostic memory controller
US10901862B2 (en) * 2018-11-13 2021-01-26 Micron Technology, Inc. High-reliability non-volatile memory using a voting mechanism
US11614892B2 (en) 2020-12-17 2023-03-28 Micron Technology, Inc. Memory system architecture for heterogeneous memory technologies

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8370558B2 (en) * 2004-12-30 2013-02-05 Intel Corporation Apparatus and method to merge and align data from distributed memory controllers
US7584335B2 (en) * 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage

Also Published As

Publication number Publication date
US20220197552A1 (en) 2022-06-23
CN114649033A (zh) 2022-06-21
US11614892B2 (en) 2023-03-28

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