EP4020228B1 - Vorrichtung, system und verfahren zum selektiven löschen von prefetch-befehlen für software - Google Patents

Vorrichtung, system und verfahren zum selektiven löschen von prefetch-befehlen für software Download PDF

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Publication number
EP4020228B1
EP4020228B1 EP21197392.0A EP21197392A EP4020228B1 EP 4020228 B1 EP4020228 B1 EP 4020228B1 EP 21197392 A EP21197392 A EP 21197392A EP 4020228 B1 EP4020228 B1 EP 4020228B1
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Prior art keywords
prefetch
instruction
entry
processor
registry
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English (en)
French (fr)
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EP4020228A1 (de
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Wim Heiman
Ibrahim Hur
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
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    • G06F12/10—Address translation
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    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This disclosure generally relates to processing devices and more particularly, but not exclusively, to prefetch operations performed based on information in a translation lookaside buffer.
  • Data prefetching is a feature implemented in a processor to augment a probability of having requested data in a timely manner, and thereby maintain a high processing efficiency.
  • a number of cycles where the processor stalls may be reduced. For example, a processor may stall when waiting for data to come back from more distant (with respect to the processor) cache levels or memory.
  • Data prefetches typically rely on the searching of a translation lookaside buffer (TLB) for address translation information which identifies a location from which data is to be prefetched.
  • TLB translation lookaside buffer
  • some processors selectively drop (that is, forego executing) a software prefetch instruction which has address information that results in a TLB miss. Such dropping of a prefetch instruction also foregoes the creation of a TLB entry for the address information.
  • processor cache management is sometimes at odds with the efficient management of a TLB, in one or more respects.
  • US 2014/052955 A1 discloses a system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.
  • the invention is defined by a processor and a method according to the independent claims. Preferred embodiments are defined by the dependent claims.
  • Embodiments discussed herein variously provide techniques and mechanisms for tracking software instructions which result in the prefetching of data.
  • the technologies described herein may be implemented in one or more electronic devices.
  • electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired telephones, combinations thereof, and the like. More generally, the technologies described herein may be employed in any of a variety of electronic devices including processors which provide data prefetch functionality.
  • signals are represented with lines. Some lines may be thicker, to indicate a greater number of constituent signal paths, and/or have arrows at one or more ends, to indicate a direction of information flow. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • a device may generally refer to an apparatus according to the context of the usage of that term.
  • a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc.
  • a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system.
  • the plane of the device may also be the plane of an apparatus which comprises the device.
  • scaling generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area.
  • scaling generally also refers to downsizing layout and devices within the same technology node.
  • scaling may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.
  • the terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/- 10% of a target value.
  • the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between among things so described. In the art, such variation is typically no more than +/-10% of a predetermined target value.
  • a first material "over" a second material in the context of a figure provided herein may also be "under” the second material if the device is oriented upside-down relative to the context of the figure provided.
  • one material disposed over or under another may be directly in contact or may have one or more intervening materials.
  • one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers.
  • a first material "on" a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.
  • between may be employed in the context of the z-axis, x-axis or y-axis of a device.
  • a material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials.
  • a material "between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material.
  • a device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.
  • a list of items joined by the term "at least one of” or “one or more of” can mean any combination of the listed terms.
  • the phrase "at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C. It is pointed out that those elements of a figure having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • combinatorial logic and sequential logic discussed in the present disclosure may pertain both to physical structures (such as AND gates, OR gates, or XOR gates), or to synthesized or otherwise optimized collections of devices implementing the logical structures that are Boolean equivalents of the logic under discussion.
  • TLB translation lookaside buffer
  • the registry of prefetch instructions is made available to facilitate a determination as to whether the execution of a given prefetch instruction is to be prevented.
  • utilization information refers to information which specifies or otherwise indicates whether some data (for example, data which has been prefetched to a cache of a processor in anticipation of a later instruction to use said data) is - according to some predefined criteria - sufficiently utilized or, alternatively, insufficiently utilized.
  • prefetched data is insufficiently utilized where such data, after prefetching thereof, has yet to be loaded once (or some other minimum threshold number of times) for use in an execution pipeline of the processor.
  • utilization information comprises a parameter (referred to herein as a "utilization indicator") which, if set to one value - e.g., zero ("0") - indicates that corresponding prefetched data is sufficiently utilized.
  • a utilization indicator a parameter which, if set to one value - e.g., zero ("0") - indicates that corresponding prefetched data is sufficiently utilized.
  • the setting of such a parameter to some alternative value - e.g., an identifier for a corresponding software instruction - indicates that corresponding prefetched data is insufficiently utilized.
  • such an identifier for a software instruction - or "instruction identifier" herein - includes, or is otherwise based on, a value of an instruction pointer (program counter) which points to the corresponding software instruction.
  • an instruction identifier comprises a hash which is calculated based on the value of a pointer to a corresponding software instruction.
  • an instruction identifier serves to identify either/both of one instance of a software instruction being provided for possible execution, and another instance of the software instruction being provided (e.g., with one or more of the same operands and/or with one or more different operands) at a different time for possible execution.
  • FIG. 1 illustrates features of a system 100 which selectively prevents execution of a prefetch instruction according to an embodiment.
  • System 100 illustrates one example of an embodiment which maintains an address translation with a translation lookaside buffer (TLB) to facilitate address translation for memory accesses.
  • TLB translation lookaside buffer
  • some embodiments Based on the eviction of entries from such a TLB, some embodiments variously register identifiers of prefetch instructions for which corresponding prefetched data was deemed underutilized. Based on a registry of such prefetch instructions, said embodiments determine whether one or more subsequent prefetch instructions are to be dropped.
  • system 100 comprises a processor 101 and a memory 140 coupled thereto.
  • Processor 101 comprises a core region 120 and an uncore 122.
  • Core region 120 includes multiple processor cores 102 (for example), but functionality disclosed herein is additionally or alternatively supported by a single core processor, in other embodiments.
  • processor 101 includes a first processor core 102-1 and a second processor core 102-2, but other embodiments include more or fewer processor cores.
  • cores 102-1, 102-2 (and/or one or more other cores of processor 101) communicate via a shared bus, a point-to-point interconnection, or in some other manner.
  • core 102 includes a front-end 104, an execution pipeline 106, and a cache memory (such as the illustrative shown).
  • L1 data cache 111 is an architecturally closest cache to execution pipeline 106 - e.g., wherein L1 data cache 111 is dedicated for caching data rather than instructions.
  • front-end 104 is operable to fetch instructions from an instruction cache (not shown) and to schedule the fetched instructions for execution.
  • execution pipeline 106 includes logic and microcode to decode and execute various mathematical, logical, memory access, and flow control instructions.
  • front-end 104 is responsible for ensuring that a steady stream of instructions is fed to execution pipeline 106 while execution pipeline 106 is responsible for executing instructions and processing the results.
  • execution pipeline 106 includes two or more arithmetic pipelines in parallel, two or more memory access or load/store pipelines in parallel, and two or more flow control or branch pipelines. Additionally or alternatively, execution pipeline 106 includes one or more floating point pipelines. In some embodiments, execution pipeline 106 includes register and logical resources for executing instructions out of order, executing instructions speculatively, or both.
  • execution pipeline 106 attempts to execute the instruction by accessing a copy of data stored in the applicable memory address residing, for example, in memory 140, or in a lower level cache memory of a cache memory subsystem that includes two or more cache memories arranged in a hierarchical configuration.
  • Depicted elements of such a cache memory subsystem include, for example, the L1 data cache 111 and a last level cache (LLC) 132 in the uncore 122.
  • Other elements of the cache memory subsystem include a per-core instruction cache (not depicted) that operates in conjunction with front end 104 and one or more per-core intermediate caches (not depicted).
  • uncore 122 further comprises a cache controller 130 to implement a cache coherency policy and, in conjunction with a memory controller 134, to maintain coherency between a system memory 140 and the various cache memories.
  • the cache memory subsystem for processor 101 includes L1 data and instruction caches per-core, an intermediate or L2 cache memory per-core that includes both instructions and data, and the LLC 132, which includes instructions and data and is shared among multiple cores 102. If a memory access instruction misses in the L1 data cache, execution of the applicable program or thread stalls or slows while the cache memory subsystem accesses the various cache memories until a copy of the applicable memory address is found.
  • processor 101 further comprises a translation lookaside buffer TLB 110 which is to store address translation information that facilitates (for example) a translation of a virtual address to a corresponding physical address for a given memory location.
  • a TLB manager 115 of processor 101 comprises circuitry to manage TLB 110 - e.g., wherein such management includes variously creating TLB entries, updating TLB entries, evicting TLB entries, and/or the like.
  • TLB manager 115 manages the provisioning of utilization information which corresponds to (for example, is included in) a given TLB entry.
  • TLB manager 115 variously provides utilization values - corresponding to different respective TLB entries - which each indicate, for some corresponding prefetched data, a respective classification of said prefetched data.
  • a utilization value indicates that prefetched data is (according to some predetermined criteria) insufficiently utilized, or sufficiently utilized.
  • processor 101 further comprises a registry 116, and a registry manager 117 comprising circuitry to manage a registration of prefetch instructions with registry 116.
  • registry manager 117 provides functionality to keep track of values, for each of one or more registered prefetch instructions, which each indicate a respective count of future prefetch instructions to be dropped.
  • an eviction of an entry from TLB 110 results in a registration of a corresponding prefetch instruction in registry 116.
  • FIG. 2 illustrates features of a method 200 for determining, according to an embodiment, whether a prefetch instruction is to be dropped by circuitry of a processor.
  • Method 200 is one example of an embodiment which manages utilization information for one or more entries of a TLB and/or manages a registry of prefetch instructions. Some or all operations of method 200 are performed with circuitry of processor 101, for example.
  • processor 300 provide some or all features of processor 101 - e.g., wherein processor 300 comprises a TLB 310, a TLB manager 315, a registry of prefetch instructions 316, a registry manager 317, and prefetch control circuitry 318 that, for example, correspond functionally to TLB 110, TLB manager 115, registry 116, registry manager 117, and prefetch control circuitry 118 (respectively).
  • method 200 comprises operations 201 performed by first manager circuitry which provides functionality such as that of TLB manager 115.
  • operations 201 comprise (at 210) detecting a prefetch instruction, wherein an entry in a translation lookaside buffer (TLB) is generated based on the first prefetch instruction.
  • TLB translation lookaside buffer
  • an execution of the prefetch instruction results in data being prefetched to a cache of a processor which performs some or all of method 200.
  • TLB manager 315 receives any of a variety of one or more signals - e.g., including the illustrative signal 323 shown - which indicate, in various embodiments, that TLB 310 is to include an entry for an address which is indicated by a software instruction that has executed (or that will execute).
  • signal 323 indicates that the software instruction is a prefetch instruction - e.g., wherein signal 323 specifies or otherwise indicates an instruction pointer (or program counter) value for the software instruction.
  • signal 323 indicates that a TLB entry - previously created based on an older instruction - is to be evicted so that TLB 310 can provide an entry based on a more recent instruction.
  • Operations 201 further comprise (at 212) providing utilization information, based on the detecting at 210, which corresponds to - e.g., which is included in - the TLB entry.
  • the utilization information comprises a value which indicates that data - which has been (or is to be) prefetched by the execution of the prefetch instruction - is classified as insufficiently utilized.
  • setting such a utilization indicator to some particular value - e.g., zero ("0") - serves to indicate to circuitry of the processor that the corresponding prefetched data has been classified, according to one or more predetermined criteria, as sufficiently utilized.
  • setting the utilization indicator to any of one or more alternative values - e.g., including a value of an instruction identifier - serves to indicate that, according to the one or more predetermined criteria, the prefetched data is insufficiently utilized.
  • TLB manager 315 participates with TLB 310 in communications 320 which facilitate one or more operations including, but not limited to, creating an entry of TLB 310, evicting an entry of TLB 310, and/or updating or otherwise accessing utilization information which is included in (or otherwise corresponds to) a given entry of TLB 310.
  • TLB manager 315 participates in communications to update utilization information based on an indication - by signal 323, for example - that some previously prefetched data has been loaded for use in an execution pipeline of processor 300.
  • an entry of TLB 310 comprises translation information 312 which specifies or otherwise indicates a correspondence of a first address to one or more other addresses (e.g., including a correspondence of a virtual address to another virtual address and/or to a physical address).
  • This TLB entry is created (for example) based on the execution of a software instruction to prefetch data from an address which is indicated by translation information 312.
  • the TLB entry further includes (or otherwise corresponds to) utilization information 314 which indicates a current classification of the prefetched data as being, according to some predetermined criteria, sufficiently utilized (or, alternatively, insufficiently utilized).
  • Method 200 further comprises operations 202 performed by second manager circuitry which provides functionality such as that of registry manager 117.
  • operations 202 comprise (at 214) detecting an eviction of the TLB entry at a time when the utilization information, provided at 212, still indicates that the prefetched data is classified as insufficiently utilized.
  • Operations 202 further comprise (at 216) generating a second entry in a registry of prefetch instructions, where said generating is based on the eviction detected at 214 (and, for example, on the instruction identifier). For example, generating the second entry at 216 is based on the prefetched data being classified as insufficiently utilized (e.g., wherein such generating would be prevented in an alternative scenario wherein the prefetched data is classified as sufficiently utilized).
  • the second entry comprises the instruction identifier (or a value which is based on the instruction identifier), and a count value which represents a number of subsequent prefetch instruction to be dropped.
  • TLB manager 315 communicates a signal 322 which indicates to registry manager 317 that the TLB entry which comprises translation information 312 has been (or is to be) evicted from TLB 310 when, for example, utilization information 314 indicates that the corresponding prefetched data is insufficiently utilized.
  • utilization information 314 indicates such insufficient utilization with an instruction identifier for the prefetch instruction which originally targeted the prefetched data.
  • registry manager 317 sends a signal 325 to create, update or otherwise access an entry of registry 316.
  • registry 316 comprises one or more instruction identifiers 326 which each correspond to a different respective prefetch instruction that previously resulted in both a prefetching of data and a creation of a corresponding TLB entry. For example, each such corresponding TLB entry was evicted from TLB 310 prior to the corresponding prefetched data being classified as sufficiently utilized.
  • registry 316 further comprises one or more count values 327 which each correspond to a different respective identifier of the one or more instruction identifiers 326. The one or more count values 327 each indicate a respective number of one or more future prefetch instructions (if any) are to be dropped - e.g., wherein said one or more future prefetch instructions each correspond to the same instruction identifier.
  • Method 200 further comprises (at 218) preventing an execution of a second prefetch instruction based on the second entry - e.g., where such preventing is by prefetch control circuitry 118 or other suitable prefetch controller.
  • the count value is initially set at 216 to represent a threshold minimum number of one or more prefetch instructions - which each correspond to the instruction identifier in the registry entry - for which execution is to be prevented (assuming such execution is ever under consideration).
  • method 200 decrements or otherwise updates the count value one or more times as prefetch instructions are successively detected (and dropped).
  • such one or more prefetch instructions include the second prefetch instruction (for which execution is prevented at 218) - e.g., wherein based on a detection of the second prefetch instruction, method 200 further decrements or otherwise updates the count value to indicate that one less prefetch instruction has yet to be dropped.
  • prefetch control circuitry 318 is coupled to receive an indication (e.g., via a signal 328 from an execution pipeline or other suitable resource) which specifies or otherwise indicates that the execution of a prefetch instruction is under consideration.
  • signal 328 includes or otherwise indicates a program counter value, or other such instruction identifier, for the prefetch instruction in question.
  • prefetch control circuitry 318 searches registry 316 for a match with any of the one or more instruction identifiers 326.
  • prefetch control circuitry 318 further determines whether one of the one or more count values 327 (corresponding to the matching one of the one or more instruction identifiers 326) indicates that the prefetch instruction in question is to be dropped or, alternatively, executed. Prefetch control circuitry 318 then generates one or more signals to selectively prevent, or enable, the execution of the prefetch instruction based on the corresponding count value.
  • method 200 additionally or alternatively performs operations (not shown) to selectively prevent a generation of another entry of the registry of prefetch instructions.
  • signal 323 alternatively or in additionally indicates that a software instruction has loaded (or will load) some already prefetched data, in a cache of processor 300 (not shown), for use by an execution pipeline (not shown) of processor 300.
  • TLB manager 315 determines, based on such loading, that utilization information, for some other TLB entry (if any) which corresponds to such prefetched data, is to be updated to indicate that the prefetched data is sufficiently utilized.
  • TLB manager 315 detects (e.g., based on signal 323) that this other TLB entry is to be evicted while the utilization information for said TLB entry indicates that the corresponding prefetched data is sufficiently utilized. Based on this indication, registry manager 317 and/or registry manager 317 prevent the generation of an entry in registry 316 which would otherwise be based on this other evicted TLB entry.
  • FIGs. 4A, 4B show (respectively) features of a translation lookaside buffer (TLB) 400 and a registry 450 of prefetch instructions according to an embodiment.
  • TLB 400 provides functionality such as that of TLB 110 or TLB 310 - e.g., wherein registry 450 provides functionality of registry 116 or registry 316.
  • entries of TLB 400 each comprise a respective logical address field 410 and a respective physical address field 412 which corresponds to logical address field 410.
  • address translation using an entry of TLB 400 comprises identifying a targeted physical address based on an instruction which targets a corresponding logical address.
  • entries of TLB 400 each further comprise (or otherwise correspond to) a respective utilization value field 416 which is available to store utilization information as variously described herein.
  • entries of TLB 400 each further comprise a respective one or more other fields - e.g., including the illustrative permission field 414 shown.
  • entry 401 is provided at TLB 400 based on an execution of a first software prefetch instruction.
  • the utilization value field 416 of entry 401 stores a utilization value which specifies or otherwise indicates whether utilization (if any) of first data - prefetched by execution of the first software prefetch instruction - has satisfied some predefined criteria.
  • the first prefetched data (which, in an embodiment, is in a processor cache) is deemed insufficiently utilized until it has been loaded for use by an execution pipeline of a processor.
  • an instruction identifier in this example, 0x1234) for the first software prefetch instruction indicates that the corresponding first prefetched data is currently classified as insufficiently utilized.
  • a subsequent eviction of entry 401 from TLB 400 results in a creation of an entry 451 in table 450 (due to the utilization value field 416 of entry 401 indicating that the first prefetched data is insufficiently utilized).
  • entries of table 450 each comprise a respective instruction identifier field 460 and a respective count value field 462 to indicate a number of prefetch instructions (each corresponding to the same instruction identifier) which are to be dropped.
  • entry 402 is provided at TLB 400 based on an execution of a second software prefetch instruction - where a subsequent loading of the second prefetched data results in the utilization value field 416 of entry 402 being set to a zero ("0") to indicate that the second prefetched data is sufficiently utilized.
  • classifying of the second prefetched data as sufficiently utilized prevents the creation of an entry in registry 450 that might otherwise take place based on a subsequent eviction of entry 402 from TLB 400.
  • the utilization value field 416 for a given entry of TLB 400 is set to a zero value (to prevent the creation of a corresponding entry in a registry 450) if the TLB entry in question is created based on an instruction other than a software prefetch instruction.
  • the respective count value fields 462 of entries 451, 452 are variously updated over time as prefetch instructions are selectively dropped based on table 450.
  • FIG. 5A illustrates features of a method 500 to process a software prefetch according to an embodiment.
  • Method 500 is one example of an embodiment wherein the execution (if any) of a software prefetch is selectively performed based on whether a TLB includes an entry for a corresponding virtual address, and - in some embodiments - whether the prefetch instruction in question is of a type which is currently registered as one for which prefetches are to be prevented.
  • method 500 is performed with one or more of TLB 110, TLB manager 115, registry 116, registry manager 117, or prefetch control circuitry 118 - e.g., wherein method 200 includes operations of method 500.
  • method 500 comprises (at 510) detecting a software instruction, the execution of which - if any - is to prefetch data from a relatively more distant memory to a cache memory of a processor.
  • the prefetch instruction includes, or otherwise corresponds to, a virtual address which indicates a memory location from which the data in question is to be prefetched.
  • the prefetch instruction further corresponds to an instruction identifier which (for example) is equal to, includes, or is otherwise based on a value of a pointer to the prefetch instruction.
  • Method 500 further comprises (at 512) searching a TLB, based on the virtual address which corresponds to the prefetch instruction, for another address (e.g., a physical address) for the targeted memory location.
  • the searching at 512 comprises TLB manager 115 searching TLB 110 (or, for example, TLB manager 315 searching TLB 310).
  • Method 500 further comprises (at 514) determining whether the search at 512 has hit any entry in the TLB.
  • method 500 performs the data prefetch which is indicated by the prefetch instruction.
  • method 500 (at 518) performs a search of a registry of prefetch instructions - e.g., where the registry search is based on the instruction identifier which corresponds to the prefetch instruction.
  • the search at 518 comprises registry manager 117 searching registry 116 (or, for example, registry manager 317 searching registry 316).
  • Method 500 subsequently evaluates (at 520) whether the search at 518 has hit an entry in the registry of prefetch instructions.
  • method 500 (at 526) allocates an entry of the TLB and (at 522) populates the allocated TLB entry with address translation information for the virtual address provided by the prefetch instruction. Furthermore, method 500 performs the data prefetch (at 516) which is indicated by the prefetch instruction.
  • method 500 determines whether the count value of the identified registry entry is greater than zero (or otherwise indicates that prefetches corresponding to the instruction identifier are still to be prevented). Where it is determined at 524 that the count value of the identified registry entry equal to (or, for example, less than) zero, method 500 performs the allocation of a TLB entry (at 526), the populating of said TLB entry (at 522), and the prefetching of the data (at 516). Where it is instead determined at 524 that the count value of the identified registry entry is greater than zero, method 500 decrements the count value (at 528), and drops the prefetch instruction (at 530).
  • FIG. 5B shows features of a method 550 to maintain utilization information for one or more entries of a TLB according to an embodiment.
  • Method 500 illustrates one embodiment wherein a utilization indicator - which corresponds to (e.g., which is included in) an entry of a TLB - is updated to indicate a use of prefetched data which, for example, corresponds to an address indicated by the TLB entry.
  • method 550 is performed (for example, in combination with method 500) with one or more of TLB 110, or TLB manager 115 - e.g., wherein method 200 includes operations of method 550.
  • method 550 comprises (at 560) detecting that prefetched data, in a cache of a processor, has been loaded for use by an execution pipeline of the processor.
  • the data was prefetched to the cache (that is, prior to the loading detected at 560) by the execution of a software prefetch instruction - e.g., wherein said software prefetch instruction resulted in the creation of an entry in a TLB such as one of TLBs 110, 310.
  • method 500 performs a search to detect whether any such TLB entry has been evicted, and/or whether a corresponding utilization indicator is to be updated.
  • method 550 further comprises (at 562) identifying an address - e.g., a virtual address - which corresponds to the prefetched data, and (at 564) searching the TLB based on said address.
  • Method 550 further comprises (at 566) determining whether the search at 564 has hit any entry in the TLB. Where a TLB hit is indicated at 566 (that is, where the search at 564 finds a TLB entry for the address identified at 562), method 550 (at 568) confirms that the corresponding utilization indicator indicates a sufficiently utilized prefetched data.
  • the confirming at 568 comprises setting the utilization indicator to zero - e.g., to erase an instruction identifier from the utilization indicator. Otherwise, method 550 foregoes any such confirming (e.g., updating) of a utilization indicator.
  • FIG. 6 illustrates features of a method 600 to manage a registry of prefetch instructions according to an embodiment.
  • Method 600 is one example of an embodiment wherein, for each of one or more prefetch instructions, an instruction identifier for the prefetch instruction is kept in a registry based on the eviction of a TLB entry which includes (or is otherwise identified as corresponding to) the instruction identifier.
  • the registry facilitates the determining of whether - e.g., for at least some predetermined number of times - any subsequent prefetch instruction which corresponds to that same instruction identifier is to be dropped (wherein the desired data prefetch is prevented).
  • method 200 is performed (for example, in combination with one or both of methods 500, 550) with one or more of TLB 110, TLB manager 115, registry 116, registry manager 117, or prefetch control circuitry 118 - e.g., wherein method 200 includes operations of method 600.
  • method 600 comprises (at 610) detecting the eviction - from a TLB such as one of TLBs 110, 310 - of an entry which corresponds to an underutilized prefetched data.
  • the detecting at 610 comprises determining that the evicted TLB entry includes, or is otherwise identified as corresponding to, a tracker value which is not equal to zero (e.g., wherein the tracker value is equal to an identifier of an instruction which resulted in the underutilized prefetched data).
  • Method 600 further comprises (at 612) performing a search of a registry of prefetch instructions - such as one of registries 116, 316 - based on the TLB eviction which is detected at 610.
  • the registry search at 612 comprises searching for an entry of the registry which includes the instruction identifier that corresponds to (for example, which is included in) the evicted TLB entry.
  • Method 600 further comprises (at 614) determining whether the search at 612 has hit an entry in the registry of prefetch instructions. Where a registry hit is indicated at 614, method 600 (at 620) performs an update to a counter value of the registry entry which has been identified as including the instruction identifier. In an embodiment, the updating at 620 sets the counter value to specify or otherwise indicate a threshold number of one or more subsequent prefetch instructions (if any) that are to be dropped, where said one or more subsequent prefetch instructions each correspond to the instruction identifier in question.
  • method 600 performs operations to find a location in the registry where the prefetch instruction which corresponds to the evicted TLB entry is to be registered.
  • operations include determining (at 616) whether there is an entry of the registry which currently has a count value which is equal to zero (or which otherwise indicates that a sufficient number of corresponding prefetch instructions have been dropped).
  • method 600 sets an identifier field of that registry entry to include the instruction identifier which corresponds to the evicted TLB entry.
  • method 600 sets the counter value of the registry entry to specify or otherwise indicate a threshold number of one or more subsequent prefetch instructions (if any) that are to be dropped.
  • method 600 selects a registry entry according to a predefined criteria (other than that of the registry entry having a count value which is equal to zero).
  • a registry entry is selected at 622 based on the registry entry having a count value which is equal to a lowest count value of all registry entries. In other embodiments, the selecting at 622 is based on a least recently used (LRU) replacement scheme, a random replacement scheme, a round-robin replacement scheme, or the like.
  • LRU least recently used
  • method 600 sets the identifier field of that picked registry entry to include the instruction identifier which corresponds to the evicted TLB entry.
  • method 600 sets the counter value of the picked registry entry to specify or otherwise indicate a threshold number of one or more subsequent prefetch instructions (if any) that are to be dropped.
  • Processor cores may be implemented in different ways, for different purposes, and in different processors.
  • implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing.
  • Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput).
  • Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality.
  • Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.
  • FIG. 7A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention.
  • FIG. 7B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention.
  • the solid lined boxes in FIGs. 7A-B illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.
  • a processor pipeline 700 includes a fetch stage 702, a length decode stage 704, a decode stage 706, an allocation stage 708, a renaming stage 710, a scheduling (also known as a dispatch or issue) stage 712, a register read/memory read stage 714, an execute stage 716, a write back/memory write stage 718, an exception handling stage 722, and a commit stage 724.
  • FIG. 7B shows processor core 790 including a front end unit 730 coupled to an execution engine unit 750, and both are coupled to a memory unit 770.
  • the core 790 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type.
  • the core 790 may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.
  • GPGPU general purpose computing graphics processing unit
  • the front end unit 730 includes a branch prediction unit 732 coupled to an instruction cache unit 734, which is coupled to an instruction translation lookaside buffer (TLB) 736, which is coupled to an instruction fetch unit 738, which is coupled to a decode unit 740.
  • the decode unit 740 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions.
  • the decode unit 740 may be implemented using various different mechanisms.
  • the core 790 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit 740 or otherwise within the front end unit 730).
  • the decode unit 740 is coupled to a rename/allocator unit 752 in the execution engine unit 750.
  • the execution engine unit 750 includes the rename/allocator unit 752 coupled to a retirement unit 754 and a set of one or more scheduler unit(s) 756.
  • the scheduler unit(s) 756 represents any number of different schedulers, including reservations stations, central instruction window, etc.
  • the scheduler unit(s) 756 is coupled to the physical register file(s) unit(s) 758.
  • Each of the physical register file(s) units 758 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc.
  • the physical register file(s) unit 758 comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers.
  • the physical register file(s) unit(s) 758 is overlapped by the retirement unit 754 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).
  • the retirement unit 754 and the physical register file(s) unit(s) 758 are coupled to the execution cluster(s) 760.
  • the execution cluster(s) 760 includes a set of one or more execution units 762 and a set of one or more memory access units 764.
  • the execution units 762 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions.
  • the scheduler unit(s) 756, physical register file(s) unit(s) 758, and execution cluster(s) 760 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 764). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
  • the set of memory access units 764 is coupled to the memory unit 770, which includes a data TLB unit 772 coupled to a data cache unit 774 coupled to a level 2 (L2) cache unit 776.
  • the memory access units 764 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 772 in the memory unit 770.
  • the instruction cache unit 734 is further coupled to a level 2 (L2) cache unit 776 in the memory unit 770.
  • the L2 cache unit 776 is coupled to one or more other levels of cache and eventually to a main memory.
  • the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 700 as follows: 1) the instruction fetch 738 performs the fetch and length decoding stages 702 and 704; 2) the decode unit 740 performs the decode stage 706; 3) the rename/allocator unit 752 performs the allocation stage 708 and renaming stage 710; 4) the scheduler unit(s) 756 performs the schedule stage 712; 5) the physical register file(s) unit(s) 758 and the memory unit 770 perform the register read/memory read stage 714; the execution cluster 760 perform the execute stage 716; 6) the memory unit 770 and the physical register file(s) unit(s) 758 perform the write back/memory write stage 718; 7) various units may be involved in the exception handling stage 722; and 8) the retirement unit 754 and the physical register file(s) unit(s) 758 perform the commit stage 724.
  • the core 790 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA), including the instruction(s) described herein.
  • the core 790 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.
  • a packed data instruction set extension e.g., AVX1, AVX2
  • the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel ® Hyperthreading technology).
  • register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture.
  • the illustrated embodiment of the processor also includes separate instruction and data cache units 734/QAE74 and a shared L2 cache unit 776, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache.
  • the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.
  • FIGs. 8A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip.
  • the logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.
  • a high-bandwidth interconnect network e.g., a ring network
  • FIG. 8A is a block diagram of a single processor core, along with its connection to the on-die interconnect network 802 and with its local subset of the Level 2 (L2) cache 804, according to embodiments of the invention.
  • an instruction decoder 800 supports the x86 instruction set with a packed data instruction set extension.
  • An L1 cache 806 allows low-latency accesses to cache memory into the scalar and vector units.
  • a scalar unit 808 and a vector unit 810 use separate register sets (respectively, scalar registers 812 and vector registers 814) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache 806, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).
  • the local subset of the L2 cache 804 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 804. Data read by a processor core is stored in its L2 cache subset 804 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 804 and is flushed from other subsets, if necessary.
  • the ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1012-bits wide per direction.
  • FIG. 8B is an expanded view of part of the processor core in FIG. 8A according to embodiments of the invention.
  • FIG. 8B includes an L1 data cache 806A part of the L1 cache 806, as well as more detail regarding the vector unit 810 and the vector registers 814.
  • the vector unit 810 is a 16-wide vector processing unit (VPU) (see the 16-wide ALU 828), which executes one or more of integer, single-precision float, and double-precision float instructions.
  • the VPU supports swizzling the register inputs with swizzle unit 820, numeric conversion with numeric convert units 822A-B, and replication with replication unit 824 on the memory input.
  • Write mask registers 826 allow predicating resulting vector writes.
  • FIG. 9 is a block diagram of a processor 900 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention.
  • the solid lined boxes in FIG. 9 illustrate a processor 900 with a single core 902A, a system agent 910, a set of one or more bus controller units 916, while the optional addition of the dashed lined boxes illustrates an alternative processor 900 with multiple cores 902A-N, a set of one or more integrated memory controller unit(s) 914 in the system agent unit 910, and special purpose logic 908.
  • different implementations of the processor 900 may include: 1) a CPU with the special purpose logic 908 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 902A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 902A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 902A-N being a large number of general purpose in-order cores.
  • the special purpose logic 908 being integrated graphics and/or scientific (throughput) logic
  • the cores 902A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two)
  • a coprocessor with the cores 902A-N being a large number of special purpose
  • the processor 900 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like.
  • the processor may be implemented on one or more chips.
  • the processor 900 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
  • the memory hierarchy includes respective one or more levels of caches 904A-N within cores 902A-N, a set or one or more shared cache units 906, and external memory (not shown) coupled to the set of integrated memory controller units 914.
  • the set of shared cache units 906 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit 912 interconnects the special purpose logic 908, the set of shared cache units 906, and the system agent unit 910/integrated memory controller unit(s) 914, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 906 and cores 902-A-N.
  • the system agent 910 includes those components coordinating and operating cores 902A-N.
  • the system agent unit 910 may include for example a power control unit (PCU) and a display unit.
  • the PCU may be or include logic and components needed for regulating the power state of the cores 902A-N and the integrated graphics logic 908.
  • the display unit is for driving one or more externally connected displays.
  • the cores 902A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 902A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.
  • FIGs. 10 through 13 are block diagrams of exemplary computer architectures.
  • Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable.
  • DSPs digital signal processors
  • graphics devices video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable.
  • DSPs digital signal processors
  • FIGs. 10 through 13 are block diagrams of exemplary computer architectures.
  • the system 1000 may include one or more processors 1010, 1015, which are coupled to a controller hub 1020.
  • the controller hub 1020 includes a graphics memory controller hub (GMCH) 1090 and an Input/Output Hub (IOH) 1050 (which may be on separate chips);
  • the GMCH 1090 includes memory and graphics controllers to which are coupled memory 1040 and a coprocessor 1045;
  • the IOH 1050 couples input/output (I/O) devices 1060 to the GMCH 1090.
  • the memory and graphics controllers are integrated within the processor (as described herein), the memory 1040 and the coprocessor 1045 are coupled directly to the processor 1010, and the controller hub 1020 in a single chip with the IOH 1050.
  • processors 1015 may include one or more of the processing cores described herein and may be some version of the processor 900.
  • the memory 1040 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two.
  • the controller hub 1020 communicates with the processor(s) 1010, 1015 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 1095.
  • a multi-drop bus such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 1095.
  • the coprocessor 1045 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
  • controller hub 1020 may include an integrated graphics accelerator.
  • processors 1010, 1015 there can be a variety of differences between the processors 1010, 1015 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.
  • the processor 1010 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 1010 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 1045. Accordingly, the processor 1010 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 1045. Coprocessor(s) 1045 accept and execute the received coprocessor instructions.
  • multiprocessor system 1100 is a point-to-point interconnect system, and includes a first processor 1170 and a second processor 1180 coupled via a point-to-point interconnect 1150.
  • processors 1170 and 1180 may be some version of the processor 900.
  • processors 1170 and 1180 are respectively processors 1010 and 1015, while coprocessor 1138 is coprocessor 1045.
  • processors 1170 and 1180 are respectively processor 1010 coprocessor 1045.
  • Processors 1170 and 1180 are shown including integrated memory controller (IMC) units 1172 and 1182, respectively.
  • Processor 1170 also includes as part of its bus controller unit's point-to-point (P-P) interfaces 1176 and 1178; similarly, second processor 1180 includes P-P interfaces 1186 and 1188.
  • Processors 1170, 1180 may exchange information via a point-to-point (P-P) interconnect 1150 using P-P interface circuits 1178, 1188.
  • IMCs 1172 and 1182 couple the processors to respective memories, namely a memory 1132 and a memory 1134, which may be portions of main memory locally attached to the respective processors.
  • Processors 1170, 1180 may each exchange information with a chipset 1190 via individual P-P interfaces 1152, 1154 using point to point interface circuits 1176, 1194, 1186, 1198.
  • Chipset 1190 may optionally exchange information with the coprocessor 1138 via a high-performance interface 1192 and an interconnect 1139.
  • the coprocessor 1138 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
  • a shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
  • first bus 1116 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.
  • PCI Peripheral Component Interconnect
  • various I/O devices 1114 may be coupled to first bus 1116, along with a bus bridge 1118 which couples first bus 1116 to a second bus 1120.
  • one or more additional processor(s) 1115 such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus 1116.
  • second bus 1120 may be a low pin count (LPC) bus.
  • Various devices may be coupled to a second bus 1120 including, for example, a keyboard and/or mouse 1122, communication devices 1127 and a storage unit 1128 such as a disk drive or other mass storage device which may include instructions/code and data 1130, in one embodiment.
  • a storage unit 1128 such as a disk drive or other mass storage device which may include instructions/code and data 1130, in one embodiment.
  • an audio I/O 1124 may be coupled to the second bus 1120.
  • a system may implement a multi-drop bus or other such architecture.
  • FIG. 12 shown is a block diagram of a second more specific exemplary system 1200 in accordance with an embodiment of the present invention.
  • Like elements in FIGs. 11 and 12 bear like reference numerals, and certain aspects of FIG. 11 have been omitted from FIG. 12 in order to avoid obscuring other aspects of FIG. 12 .
  • FIG. 12 illustrates that the processors 1170, 1180 may include integrated memory and I/O control logic ("CL") 1272 and 1282, respectively.
  • CL 1272, 1282 include integrated memory controller units and include I/O control logic.
  • FIG. 12 illustrates that not only are the memories 1132, 1134 coupled to the CL 1272, 1282, but also that I/O devices 1214 are also coupled to the control logic 1272, 1282. Legacy I/O devices 1215 are coupled to the chipset 1190.
  • FIG. 13 shown is a block diagram of a SoC 1300 in accordance with an embodiment of the present invention. Similar elements in FIG. 9 bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In FIG. 13 , shown is a block diagram of a SoC 1300 in accordance with an embodiment of the present invention. Similar elements in FIG. 9 bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In FIG.
  • an interconnect unit(s) 1302 is coupled to: an application processor 1310 which includes a set of one or more cores 902A-N and shared cache unit(s) 906; a system agent unit 910; a bus controller unit(s) 916; an integrated memory controller unit(s) 914; a set or one or more coprocessors 1320 which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit 1330; a direct memory access (DMA) unit 1332; and a display unit 1340 for coupling to one or more external displays.
  • the coprocessor(s) 1320 include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.
  • Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches.
  • Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
  • Program code such as code 1130 illustrated in FIG. 11
  • Program code may be applied to input instructions to perform the functions described herein and generate output information.
  • the output information may be applied to one or more output devices, in known fashion.
  • a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • the program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system.
  • the program code may also be implemented in assembly or machine language, if desired.
  • the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
  • IP cores may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
  • Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
  • storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto
  • embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein.
  • HDL Hardware Description Language
  • Such embodiments may also be referred to as program products.
  • Emulation including binary translation, code morphing, etc.
  • an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set.
  • the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core.
  • the instruction converter may be implemented in software, hardware, firmware, or a combination thereof.
  • the instruction converter may be on processor, off processor, or part on and part off processor.
  • FIG. 14 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.
  • the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof.
  • FIG. 14 shows a program in a high level language 1402 may be compiled using an x86 compiler 1404 to generate x86 binary code 1406 that may be natively executed by a processor with at least one x86 instruction set core 1416.
  • the processor with at least one x86 instruction set core 1416 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core.
  • the x86 compiler 1404 represents a compiler that is operable to generate x86 binary code 1406 (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core 1416.
  • FIG. 14 shows the program in the high level language 1402 may be compiled using an alternative instruction set compiler 1408 to generate alternative instruction set binary code 1410 that may be natively executed by a processor without at least one x86 instruction set core 1414 (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, CA and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, CA).
  • the instruction converter 1412 is used to convert the x86 binary code 1406 into code that may be natively executed by the processor without an x86 instruction set core 1414.
  • This converted code is not likely to be the same as the alternative instruction set binary code 1410 because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set.
  • the instruction converter 1412 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1406.
  • This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

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Claims (11)

  1. Prozessor (101, 300), der Folgendes umfasst:
    einen Translation-Lookaside-Buffer- bzw. TEB-Manager (115, 315), umfassend eine Schaltungsanordnung zum:
    Detektieren einer ersten Vorabrufanweisung, wobei ein erster Eintrag eines TLB (110, 310) basierend auf der ersten Vorabrufanweisung erzeugt wird; und
    Bereitstellen, basierend auf der ersten Vorabrufanweisung, von ersten Nutzungsinformationen, die dem ersten Eintrag entsprechen, wobei die ersten Nutzungsinformationen angeben, dass erste Daten, die durch eine Ausführung der ersten Vorabrufanweisung vorabgerufen werden, als nicht ausreichend genutzt klassifiziert sind, wobei die ersten Nutzungsinformationen eine Anweisungskennung umfassen, die der ersten Vorabrufanweisung entspricht; wobei der Prozessor dadurch gekennzeichnet ist, dass er Folgendes umfasst:
    einen Registermanager (117, 317), der mit dem TLB-Manager (115, 315) gekoppelt ist zum:
    Detektieren einer Ausräumung des ersten Eintrags, während die ersten Nutzungsinformationen angeben, dass erste Daten als nicht ausreichend genutzt klassifiziert sind, wobei die ersten Daten als nicht ausreichend genutzt klassifiziert werden, wenn die ersten Daten noch mindestens eine vorbestimmte Anzahl von Malen zur Verwendung in einer Ausführungs-Pipeline (106) des Prozessors (101, 300) zu laden sind;
    Erzeugen, basierend auf der Ausräumung und der Anweisungskennung, eines zweiten Eintrags eines Registers (116, 316) von Vorabrufanweisungen, wobei der zweite Eintrag die Anweisungskennung und einen Wert, der einen Zählwert von zu verwerfenden Vorabrufanweisungen repräsentiert, umfasst; und
    eine Vorabrufsteuerung (118, 318), die mit dem Register (116, 316) gekoppelt ist, umfassend eine Schaltungsanordnung zum Verhindern einer Ausführung einer zweiten Vorabrufanweisung basierend auf dem zweiten Eintrag, wobei der Registermanager (117, 317) basierend auf einer Detektion der zweiten Vorabrufanweisung ferner ausgelegt ist zum Aktualisieren des Werts zum Dekrementieren des Zählwerts von zu verwerfenden Vorabrufanweisungen, und
    wobei die Vorabrufsteuerung (118, 318) ausgelegt ist zum:
    Durchführen einer ersten Durchsuchung des TLB (110, 310) basierend auf einer Adresse, die der zweiten Vorabrufanweisung entspricht;
    Detektieren eines Miss basierend auf der ersten Durchsuchung;
    als Reaktion auf den Miss, Durchführen einer zweiten Durchsuchung des Registers (116, 316) von Vorabrufanweisungen basierend auf einer Anweisungskennung, die der zweiten Vorabrufanweisung entspricht; und
    Detektieren eines Hit des zweiten Eintrags basierend auf der zweiten Durchsuchung;
    wobei die Vorabrufsteuerung (118, 318) zum Verhindern der Ausführung der zweiten Vorabrufanweisung basierend auf dem zweiten Eintrag die Vorabrufanweisung (118, 318) zum Verhindern der Ausführung basierend auf dem Hit umfasst.
  2. Prozessor (101, 300) nach Anspruch 1, wobei der erste Eintrag die ersten Nutzungsinformationen umfasst.
  3. Prozessor (101, 300) nach Anspruch 1, wobei die Vorabrufsteuerung (118, 318) ferner ausgelegt ist zum Detektieren, basierend auf dem Hit des zweiten Eintrags, dass der Zählwert von zu verwerfenden Vorabrufanweisungen größer als null ist; und
    wobei die Vorabrufsteuerung (118, 318) zum Verhindern der Ausführung basierend auf dem Hit die Vorabrufanweisung (118, 318) zum Verhindern der Ausführung basierend auf dem Zählwert umfasst.
  4. Prozessor (101, 300) nach Anspruch 1 oder Anspruch 2, wobei die Anweisungskennung auf einem Wert eines Anweisungszeigers basiert.
  5. Prozessor (101, 300) nach Anspruch 1 oder Anspruch 2, wobei der TLB-Manager (115, 315) ferner ausgelegt ist zum:
    Detektieren einer dritten Vorabrufanweisung, wobei der dritte Eintrag des TLB (110, 310) basierend auf der dritten Vorabrufanweisung erzeugt wird;
    Bereitstellen von zweiten Nutzungsinformationen, die dem dritten Eintrag entsprechen, wobei die zweiten Nutzungsinformationen angeben, dass zweite Daten, die durch eine Ausführung der dritten Vorabrufanweisung vorabgerufen werden, als nicht ausreichend genutzt klassifiziert sind, wobei die zweiten Nutzungsinformationen eine zweite Anweisungskennung umfassen, die der dritten Vorabrufanweisung entspricht;
    Detektieren einer Verwendung der zweiten Daten durch die Ausführungs-Pipeline (106); und
    Aktualisieren der zweiten Nutzungsdaten basierend auf der Nutzung, um anzugeben, dass die zweiten Daten als ausreichend genutzt klassifiziert sind.
  6. Prozessor (101, 300) nach Anspruch 5, wobei der Registermanager (117, 317) ferner ausgelegt ist zum:
    Detektieren einer zweiten Ausräumung des dritten Eintrags nach dem Aktualisieren;
    Durchführen einer Auswertung der zweiten Nutzungsinformation basierend auf der zweiten Ausräumung; und
    basierend auf der Auswertung, Verhindern einer Erzeugung eines vierten Eintrags des Registers (116, 316).
  7. Prozessor (101, 300) nach Anspruch 1 oder Anspruch 2, wobei:
    der Registermanager (117, 317) ferner ausgelegt ist zum Auswählen eines durch den zweiten Eintrag zu ersetzenden dritten Eintrags des Registers (116, 316);
    der dritte Eintrag einen Wert umfasst, der einen Zählwert von zu verwerfenden Vorabrufanweisungen umfasst; und
    der Registermanager (117, 317) ausgelegt ist zum Auswählen der dritten Schaltungsanordnung basierend auf einem der Folgenden:
    einer Angabe durch den Wert, dass der Zählwert gleich null ist; oder
    einer Angabe durch den Wert, dass der Zählwert gleich einem niedrigsten Zählwert von mehreren Zählwerten ist, die jeweils durch einen anderen jeweiligen Eintrag des Registers (116, 316) repräsentiert werden.
  8. Verfahren an einem Prozessor (101, 300), wobei das Verfahren Folgendes umfasst:,
    mit einem Translation-Lookaside-Buffer- bzw. TEB-Manager (115, 315):
    Detektieren (210) einer ersten Vorabrufanweisung, wobei ein erster Eintrag eines Translation Lookaside Buffer, TLB, (110, 310) basierend auf der ersten Vorabrufanweisung erzeugt wird; und
    basierend auf dem Detektieren, Bereitstellen (212) von ersten Nutzungsinformationen, die dem ersten Eintrag entsprechen, wobei die ersten Nutzungsinformationen angeben, dass erste Daten, die durch eine Ausführung der ersten Vorabrufanweisung vorabgerufen werden, als nicht ausreichend genutzt klassifiziert sind, wobei die ersten Nutzungsinformationen eine Anweisungskennung umfassen, die der ersten Vorabrufanweisung entspricht;
    mit einem Registermanager (117, 317):
    Detektieren (214) einer Ausräumung des ersten Eintrags, während die ersten Nutzungsinformationen angeben, dass erste Daten als nicht ausreichend genutzt klassifiziert sind, wobei die ersten Daten als nicht ausreichend genutzt klassifiziert werden, wenn die ersten Daten noch mindestens eine vorbestimmte Anzahl von Malen zur Verwendung in einer Ausführungs-Pipeline (106) des Prozessors (101, 300) zu laden sind;
    basierend auf der Ausräumung und der Anweisungskennung, Erzeugen (216) eines zweiten Eintrags eines Registers (116, 316) von Vorabrufanweisungen, wobei der zweite Eintrag die Anweisungskennung und einen Wert, der einen Zählwert von zu verwerfenden Vorabrufanweisungen repräsentiert, umfasst;
    mit einer Vorabrufsteuerung (118, 318), Verhindern (218) einer Ausführung einer zweiten Vorabrufanweisung basierend auf dem zweiten Eintrag; und
    mit dem Registermanager (117, 317) basierend auf einer Detektion der zweiten Vorabrufanweisung, Aktualisieren des Werts zum Dekrementieren des Zählwerts von zu verwerfenden Vorabrufanweisungen,
    wobei das Verfahren ferner Folgendes umfasst:
    durch die Vorabrufsteuerung (118, 318):
    Durchführen (512) einer ersten Durchsuchung des TLB (110, 310) basierend auf einer Adresse, die der zweiten Vorabrufanweisung entspricht;
    Detektieren (514) eines Miss basierend auf der ersten Durchsuchung;
    als Reaktion auf den Miss, Durchführen (518) einer zweiten Durchsuchung des Registers (116, 316) von Vorabrufanweisungen basierend auf einer Anweisungskennung, die der zweiten Vorabrufanweisung entspricht; und
    Detektieren (520) eines Hit des zweiten Eintrags basierend auf der zweiten Durchsuchung;
    wobei das Verhindern der Ausführung der zweiten Vorabrufanweisung basierend auf dem zweiten Eintrag Verhindern der Ausführung basierend auf dem Hit umfasst.
  9. Verfahren nach Anspruch 8, wobei der erste Eintrag die ersten Nutzungsinformationen umfasst.
  10. Verfahren nach Anspruch 8, wobei das Verfahren ferner Folgendes umfasst: mit der Vorabrufsteuerung (118, 318), Detektieren, basierend auf dem Hit des zweiten Eintrags, dass der Zählwert von zu verwerfenden Vorabrufanweisungen größer als null ist; und
    wobei das Verhindern der Ausführung basierend auf dem Hit Verhindern der Ausführung basierend auf dem Zählwert umfasst.
  11. Verfahren nach Anspruch 8 oder Anspruch 9, wobei die Anweisungskennung auf einem Wert eines Anweisungszeigers basiert.
EP21197392.0A 2020-12-23 2021-09-17 Vorrichtung, system und verfahren zum selektiven löschen von prefetch-befehlen für software Active EP4020228B1 (de)

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