EP3980996A4 - Bit string accumulation in memory array periphery - Google Patents

Bit string accumulation in memory array periphery Download PDF

Info

Publication number
EP3980996A4
EP3980996A4 EP20818144.6A EP20818144A EP3980996A4 EP 3980996 A4 EP3980996 A4 EP 3980996A4 EP 20818144 A EP20818144 A EP 20818144A EP 3980996 A4 EP3980996 A4 EP 3980996A4
Authority
EP
European Patent Office
Prior art keywords
memory array
bit string
array periphery
string accumulation
accumulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20818144.6A
Other languages
German (de)
French (fr)
Other versions
EP3980996A1 (en
Inventor
Vijay S. Ramesh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16/430,789 external-priority patent/US11487699B2/en
Priority claimed from US16/430,737 external-priority patent/US10942890B2/en
Priority claimed from US16/430,689 external-priority patent/US10942889B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP3980996A1 publication Critical patent/EP3980996A1/en
Publication of EP3980996A4 publication Critical patent/EP3980996A4/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
EP20818144.6A 2019-06-04 2020-04-17 Bit string accumulation in memory array periphery Pending EP3980996A4 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US16/430,789 US11487699B2 (en) 2019-06-04 2019-06-04 Processing of universal number bit strings accumulated in memory array periphery
US16/430,737 US10942890B2 (en) 2019-06-04 2019-06-04 Bit string accumulation in memory array periphery
US16/430,689 US10942889B2 (en) 2019-06-04 2019-06-04 Bit string accumulation in memory array periphery
PCT/US2020/028658 WO2020247077A1 (en) 2019-06-04 2020-04-17 Bit string accumulation in memory array periphery

Publications (2)

Publication Number Publication Date
EP3980996A1 EP3980996A1 (en) 2022-04-13
EP3980996A4 true EP3980996A4 (en) 2023-06-28

Family

ID=73653021

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20818144.6A Pending EP3980996A4 (en) 2019-06-04 2020-04-17 Bit string accumulation in memory array periphery

Country Status (4)

Country Link
EP (1) EP3980996A4 (en)
KR (1) KR102440692B1 (en)
CN (1) CN113924622B (en)
WO (1) WO2020247077A1 (en)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3845009B2 (en) * 2001-12-28 2006-11-15 富士通株式会社 Product-sum operation apparatus and product-sum operation method
JP3845636B2 (en) * 2004-01-21 2006-11-15 株式会社東芝 Function approximation calculator
GB2464292A (en) * 2008-10-08 2010-04-14 Advanced Risc Mach Ltd SIMD processor circuit for performing iterative SIMD multiply-accumulate operations
US8386895B2 (en) * 2010-05-19 2013-02-26 Micron Technology, Inc. Enhanced multilevel memory
US9430735B1 (en) 2012-02-23 2016-08-30 Micron Technology, Inc. Neural network in a memory device
US8869436B2 (en) 2013-02-27 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive switching random access memory structure and method to recreate filament and recover resistance window
US9158667B2 (en) 2013-03-04 2015-10-13 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US8971124B1 (en) * 2013-08-08 2015-03-03 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9583163B2 (en) * 2015-02-03 2017-02-28 Micron Technology, Inc. Loop structure for operations in memory
US10474628B2 (en) * 2015-10-08 2019-11-12 Via Alliance Semiconductor Co., Ltd. Processor with variable rate execution unit
US10216479B2 (en) * 2016-12-06 2019-02-26 Arm Limited Apparatus and method for performing arithmetic operations to accumulate floating-point numbers
US10748603B2 (en) * 2018-09-28 2020-08-18 Intel Corporation In-memory multiply and accumulate with global charge-sharing
US10884957B2 (en) 2018-10-15 2021-01-05 Intel Corporation Pipeline circuit architecture to provide in-memory computation functionality

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
ANDREA BOCCO ET AL: "SMURF", 20190313; 20190313 - 20190314, 13 March 2019 (2019-03-13), pages 1 - 8, XP058435001, ISBN: 978-1-4503-7139-1, DOI: 10.1145/3316279.3316280 *
SCHULTE M J ET AL: "A FAMILY OF VARIABLE-PRECISION INTERVAL ARITHMETIC PROCESSORS", IEEE TRANSACTIONS ON COMPUTERS, IEEE, USA, vol. 49, no. 5, 31 May 2000 (2000-05-31), pages 387 - 397, XP000970026, ISSN: 0018-9340, DOI: 10.1109/12.859535 *
See also references of WO2020247077A1 *
VAN DAM LAURENS: "Enabling High Performance Posit Arithmetic Applications Using Hardware Acceleration", MASTER THESIS, DELFT UNIVERSITY OF TECHNOLOGY, 17 September 2018 (2018-09-17), pages 1 - 8, XP055832833, Retrieved from the Internet <URL:https://repository.tudelft.nl/islandora/object/uuid%3A943f302f-7667-4d88-b225-3cd0cd7cf37c> [retrieved on 20210818] *

Also Published As

Publication number Publication date
CN113924622B (en) 2022-09-09
KR102440692B1 (en) 2022-09-07
WO2020247077A1 (en) 2020-12-10
KR20220003674A (en) 2022-01-10
CN113924622A (en) 2022-01-11
EP3980996A1 (en) 2022-04-13

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