EP3945607A1 - Diode de carbure de silicium à faible chute de tension, et son procédé de fabrication - Google Patents

Diode de carbure de silicium à faible chute de tension, et son procédé de fabrication Download PDF

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Publication number
EP3945607A1
EP3945607A1 EP21187915.0A EP21187915A EP3945607A1 EP 3945607 A1 EP3945607 A1 EP 3945607A1 EP 21187915 A EP21187915 A EP 21187915A EP 3945607 A1 EP3945607 A1 EP 3945607A1
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sub
region
regions
forming
implanted
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EP21187915.0A
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German (de)
English (en)
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Simone RASCUNA'
Claudio CHIBBARO
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STMicroelectronics SRL
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STMicroelectronics SRL
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • the present invention relates to an electronic device of silicon carbide (SiC) and to a manufacturing method thereof.
  • JBS Joint Barrier Schottky
  • MPS Merged PiN Schottky diodes
  • These devices are generally of a SiC substrate and comprise implanted areas having a conductivity opposite to that of the substrate (e.g., of a P type for a substrate of an N type).
  • two distinct types of contacts are present: an ohmic one in the implanted areas, and a Schottky one in the areas comprised between the implanted areas.
  • JBS diodes particularly suited to working in high-voltage power devices.
  • Figure 1 shows, in lateral sectional view in a (triaxial) cartesian reference system of axes X, Y, Z, an MPS device 1 of a known type.
  • the MPS device 1 includes: a substrate 3, of SiC of an N type, having a first dopant concentration, provided with a surface 3a opposite to a surface 3b, and having a thickness equal to approximately 350 pm; a drift layer (grown epitaxially) 2, of SiC of an N type, having a second dopant concentration lower than the first dopant concentration, which extends over the surface 3a of the substrate 3 and has a thickness comprised between 5 and 15 ⁇ m; an ohmic-contact region 6 (for example, of nickel silicide), which extends over the surface 3b of the substrate 3; a cathode metallization 16, which extends over the ohmic-contact region 6; an anode metallization 8, which extends over a top surface 2a of the drift layer 2; multiple junction-barrier (JB) elements 9 in the drift layer 2, which face the top surface 2a of the drift layer 2 and each include a respective implanted region 9' of a P type and an ohmic contact 9" of metal
  • Schottky diodes 12 are formed at the interface between the drift layer 2 and the anode metallization 8.
  • Schottky junctions i.e., semiconductor-metal junctions
  • portions of the drift layer 2 in direct electrical contact with respective portions of the anode metallization 8.
  • the region of the MPS device 1 that includes the JB elements 9 and the Schottky diodes 12 is an active area 4 of the MPS device 1.
  • the current flows in the non-depleted Schottky regions comprised between the P implants 9', preserving the unipolar operating mode.
  • reverse biasing conduction between the Schottky regions is suppressed by the pinch-off effect of the adjacent PN junctions.
  • the reverse-biasing characteristic of the JBS device substantially corresponds to that of a PN junction. It is evident that the distance d (in the direction X of Figure 1 ) between the P implants 9' must be chosen in an appropriate way to optimize the trade-off between the potential drop in the ON state (which increases with the reduction of said distance d) and the current losses (which decrease with the reduction of said distance d).
  • the possibility of controlling the SBH (Schottky-Barrier Height) value is particularly important for controlling the potential drop of Schottky diodes.
  • the reduction of the SBH value produces a significant reduction of the potential drop.
  • the reduction of the SBH value presents the disadvantage of causing a substantial increase in the leakage current in reverse biasing. The distance between the P+ implants 9' must consequently be carefully designed.
  • a prior-art solution is provided by US2015/0372093 , where a switching device is described, such as a JBS (Junction Schottky Barrier) diode, which has a solid body of silicon carbide of an N type, housing implanted regions of a P type (similar to the regions 9' of Figure 1 ).
  • the P implanted regions extend in the solid body starting from a surface thereof and delimit, between them, N+ doped surface portions, i.e., ones having a doping density higher than that of the bulk of the solid body.
  • N+ doped surface portions i.e., ones having a doping density higher than that of the bulk of the solid body.
  • Patent document US2002/125541 describes a metal-semiconductor rectifier and a manufacturing method thereof.
  • Patent document EP3067935 describes a power rectifier with controllable on-state voltage.
  • the aim of the present invention is to provide a SiC electronic device and a manufacturing method thereof that will overcome the drawbacks of the prior art, in particular one having a low voltage drop and a high efficiency.
  • Figure 2 shows, in lateral sectional view in a (triaxial) cartesian reference system of axes X, Y, Z, a base cell of a JBS device (or diode) 50, according to an embodiment of the present invention.
  • the JBS device 50 includes: a substrate 53, of SiC of an N type, having a first dopant concentration, provided with a surface 53a opposite to a surface 53b, and having a thickness comprised between 50 ⁇ m and 350 ⁇ m, more in particular between 160 ⁇ m and 200 ⁇ m, for example equal to 180 pm; a drift layer (grown epitaxially) 52, of SiC of an N type, having a second dopant concentration lower than the first dopant concentration, which extends over the surface 53a of the substrate 53 and has a thickness comprised, for example, between 5 and 15 pm; an ohmic-contact region, or layer, 56 (for example, of nickel silicide), which extends over the surface 53b of the substrate 53; a cathode metallization 57, for example of Ti/NiV/Ag or Ti/NiV/Au, which extends over the ohmic-contact region 56; an anode metallization 58, for example of Ti/AlSiCu or
  • An edge-termination region, or protection ring (in particular, an implanted region of a P type, similar to the region 10 of Figure 1 ) is optionally present and is not illustrated in Figure 2 .
  • One or more Schottky diodes 62 are formed at the interface between the drift layer 52 and the anode metallization 58, alongside the implanted regions 59'.
  • (semiconductor-metal) Schottky junctions are formed by portions of the drift layer 52 in direct electrical contact with respective portions of the anode metallization 58.
  • the region of the JBS device 50 that includes the JB elements 59 and the Schottky diodes 62 is an active area 54 of the JBS device 50.
  • the top portion of the drift layer 52 is enriched, with respect to the rest of the drift layer 52, by a doped region 64 of an N+ type.
  • the doped region 64 may have a doping level higher than 1.5 ⁇ 10 16 at/cm 3 .
  • the depth of the doped region 64 is equal to or less than that of the implanted regions 59'; for example, the maximum depth d 1 of the implanted regions 59', measured along the axis Z starting from the surface 52a, is comprised between 0.4 ⁇ m and 1 ⁇ m, and the maximum depth d 2 of the doped region 64, measured along the axis Z starting from the surface 52a, is comprised between 0.4 ⁇ m and 1 ⁇ m.
  • the depth of the doped region 64 is equal to or less than that of the implanted regions 59'.
  • the purpose of the implant that forms the region 64 is to reduce the resistance linked to pinch-off of the current path of the charge carriers in the area comprised between the implanted regions 59'.
  • the present applicant notes that extending said N+ implant underneath the implanted regions 59', albeit possible, would not lead to an important advantage in so far as the path of the charge carriers in this area extends over the entire dimension of the layer 52.
  • a further N+ implant underneath the implanted regions 59' could reduce breakdown of the device by altering the PN junction.
  • the doped region 64 comprises, according to one aspect of the present invention, three doped sub-regions 64a, 64b, 64c, having respective doping levels.
  • three doped sub-regions 64a, 64b, 64c having respective doping levels.
  • the value of doping level of the region 64a is important because this region 64a is the one that, in a preponderant way, determines lowering of the barrier height (energy gap) of the Schottky contact, thanks to the increase of the surface electrical field.
  • the doping level of the region 64a is consequently higher than the doping level of the epitaxial layer.
  • the doping value of the intermediate sub-region 64b is instead higher, such that the electrical resistance of the layer is lowered.
  • the region 64c instead, represents the "tail" of the implant and has a value that, in the limit, coincides with the doping level of the epitaxial layer.
  • FIG. 3A-3C illustrate a portion of a wafer 100 including a plurality of base cells of the type illustrated in Figure 2 .
  • a hard mask 102 having windows 102', is provided on the top surface 52a of the drift layer 52.
  • a P type represented schematically by arrows 103, for example of aluminium atoms at a dose of between 1.0 ⁇ 10 14 at/cm 2 and 1.0 ⁇ 10 15 at/cm 2 with energies of between 30 and 300 keV.
  • Implanted regions of a P type 104 are thus formed.
  • the implanted regions of a P type 104 will form the regions 59' of Figure 2 .
  • a plurality of implantations is carried out at different energies and different doses, for positioning the dopants at the desired depth and with the desired concentrations (in particular, to obtain regions evenly doped in all directions). This is due to the fact that, unlike in silicon, in silicon carbide the dopant species do not diffuse following upon thermal annealing. It is therefore important to position the dopants as defined in the design stage, differentiating the different implantations according to energy and dose.
  • a guard ring 105 may be optionally formed, simultaneously with formation of the implanted regions of a P type 104.
  • a further hard mask 108 is formed on the top surface 52a of the drift layer 52.
  • the hard mask 108 is provided with windows 108', which expose regions of the drift layer 52 comprised between the implanted regions of a P type 104.
  • a step of masked implantation is then carried out to modify the conductivity of the surface region exposed through the windows 108'.
  • doping agents of an N type are implanted in the drift layer 52 on its top surface 52a (as represented schematically by the arrows 112), to form one or more implanted regions 114 comprised between respective implanted regions 104.
  • the implanted regions 114 extend between implanted regions 104 and are adjacent to the implanted regions 104.
  • the implantation step of Figure 3B comprises, in particular, one or more successive implantations, in particular two implantations, performed at different energies so as to localize the implanted dopant species at respective depths in the drift layer 52 in order to form the sub-regions 64a-64c described previously.
  • a single implantation is carried out, with which it is possible to obtain a lowering of the Schottky barrier raising the surface electrical field, and a reduction of the resistance in the pinch-off area between the regions 59', concentrating therein the majority of the charge (in this case, the dose and the energy of the implantation are appropriately chosen in such a way that the residual dose of the implant at the surface is equal to the dose that is normally used for lowering the barrier, i.e., low dose and low energy).
  • the implantation has, by way of example, a dose ranging between 1.0 ⁇ 10 13 and 1.0 ⁇ 10 15 (e.g., 1.0 ⁇ 10 14 ) at/cm 2 , with energies of between 150 keV and 250 keV (e.g., 200 keV).
  • two distinct implantations are carried out: one at a low energy and low dose dedicated to lowering the Schottky barrier; and one at a higher energy and higher concentration to localize an additional charge in the pinch-off area between the regions 59'.
  • the regions 64a and 64b are thus formed; the region 64c is formed as direct consequence of these two implantations, in particular as "tail" of the second implant at a high dose and high energy.
  • the first implantation has a dose of between 1.0 ⁇ 10 11 and 1.0 ⁇ 10 13 (e.g., 1.0 ⁇ 10 12 ), with an energy level of between 10 keV and 20 keV (e.g., 15 keV), and the second implantation has a dose of between 1.0 ⁇ 10 13 and 1.0 ⁇ 10 15 (e.g., 1.0 ⁇ 10 14 ) and an energy of between 150 keV and 250 keV (e.g., 200 keV).
  • Manufacture of the JBS device 50 is then completed with steps, which are in themselves known, do not form the subject of the present invention, and are therefore not illustrated in the figures, of formation of the anode metallization 58 and the cathode metallization 57, to obtain the JBS device 50 of Figure 2 .
  • the JBS device 50 described presents numerous advantages.
  • the voltage drop of the diode Schottky is reduced by reducing the SBH value and the resistance between the P+ implanted regions, as is evident from what has been described previously.
  • the material of the substrate 53 and/or of the epitaxial layer 52 may be one of the following: 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC.
  • the implanted region 64 may comprise only two sub-regions 64a and 64b, or else a number of implanted sub-regions greater than three.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thermistors And Varistors (AREA)
  • Inorganic Insulating Materials (AREA)
EP21187915.0A 2020-07-27 2021-07-27 Diode de carbure de silicium à faible chute de tension, et son procédé de fabrication Pending EP3945607A1 (fr)

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IT102020000018130A IT202000018130A1 (it) 2020-07-27 2020-07-27 Diodo in carburo di silicio con ridotta caduta di tensione, e relativo procedimento di fabbricazione

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4340034A1 (fr) * 2022-09-15 2024-03-20 Nexperia B.V. Diode mps ayant une région dopée de façon non uniforme et son procédé de fabrication
EP4340033A1 (fr) * 2022-09-15 2024-03-20 Nexperia B.V. Diode mps ayant une région dopée et son procédé de fabrication

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990955A (zh) * 2020-07-27 2022-01-28 意法半导体股份有限公司 具有减小的电压降的碳化硅二极管以及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020125541A1 (en) 1999-12-30 2002-09-12 Jacek Korec Method of fabricating trench junction barrier rectifier
US20150372093A1 (en) 2014-06-20 2015-12-24 Stmicroelectronics S.R.L. Wide bandgap high-density semiconductor switching device and manufacturing process thereof
EP3067935A1 (fr) 2015-03-10 2016-09-14 ABB Technology AG Redresseur à semi-conducteurs de puissance à commande de tension à l'état passant

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1696490A1 (fr) * 2005-02-25 2006-08-30 STMicroelectronics S.r.l. Dispositif semi-conducteur à compensation de charge et procédé de fabrication associé
FR3003685B1 (fr) 2013-03-21 2015-04-17 St Microelectronics Crolles 2 Procede de modification localisee des contraintes dans un substrat du type soi, en particulier fd soi, et dispositif correspondant
US10483389B2 (en) * 2014-07-02 2019-11-19 Hestia Power Inc. Silicon carbide semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020125541A1 (en) 1999-12-30 2002-09-12 Jacek Korec Method of fabricating trench junction barrier rectifier
US20150372093A1 (en) 2014-06-20 2015-12-24 Stmicroelectronics S.R.L. Wide bandgap high-density semiconductor switching device and manufacturing process thereof
EP3067935A1 (fr) 2015-03-10 2016-09-14 ABB Technology AG Redresseur à semi-conducteurs de puissance à commande de tension à l'état passant

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4340034A1 (fr) * 2022-09-15 2024-03-20 Nexperia B.V. Diode mps ayant une région dopée de façon non uniforme et son procédé de fabrication
EP4340033A1 (fr) * 2022-09-15 2024-03-20 Nexperia B.V. Diode mps ayant une région dopée et son procédé de fabrication

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US11715769B2 (en) 2023-08-01
IT202000018130A1 (it) 2022-01-27

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