EP3891802B1 - Finfet-based split gate non-volatile flash memory with extended source line finfet, and method of fabrication - Google Patents

Finfet-based split gate non-volatile flash memory with extended source line finfet, and method of fabrication Download PDF

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Publication number
EP3891802B1
EP3891802B1 EP19759479.9A EP19759479A EP3891802B1 EP 3891802 B1 EP3891802 B1 EP 3891802B1 EP 19759479 A EP19759479 A EP 19759479A EP 3891802 B1 EP3891802 B1 EP 3891802B1
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Prior art keywords
fin
insulated
fins
gate
source
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German (de)
French (fr)
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EP3891802A1 (en
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Serguei Jourba
Catherine Decobert
Feng Zhou
Jinho Kim
Xian Liu
Nhan Do
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Definitions

  • the present invention relates to non-volatile flash memory cell arrays.
  • Non-volatile memory devices are well known in the art.
  • a split-gate memory cell is disclosed in U.S. Patent 5,029,130 .
  • This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions.
  • Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region under the floating gate to determine the programming state of the floating gate).
  • U.S. Patent 7,315,056 discloses a memory cell that additionally includes a program/erase gate over the source region.
  • U.S. Patent 7,868,375 discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate. See also U.S. Patents 6,747,310 , 7,868,375 , 9,276,005 and 9,276,006 .
  • US 2016/064398 A1 considered to be the closest prior art of the present invention, relates to a finFET flash memory cell with floating gates covering the sides of a first fin at either side of a second, orthogonal fin (the source line). Select gates are provided adjacent to the floating gate wrapping around the sides and top surface of the fin at opposite side of the floating gate with respect to the source fin; control gates are provided wrapping around the fin, covering the floating gates; and a central erase gate is provided wrapping around the first fin and the orthogonal source line fin. Because the problem of shrinking the lithography size thereby reducing the channel width affects all semiconductor devices, a Fin-FET type of structure has been proposed.
  • a fin shaped member of the semiconductor substrate material connects the source region to the drain region.
  • the fin shaped member has a top surface and two opposing side surfaces. Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces. Thus, the surface width of the channel region is increased, thereby increasing the current flow, without sacrificing more semiconductor real estate, by "folding" the channel region into two side surfaces, thereby reducing the "footprint" of the channel region.
  • Non-volatile memory cells using such Fin-FETs have been disclosed.
  • Ultra-thin polysilicon or amorphous silicon film deposition and doping techniques are complex and often suffer from insufficient and non-uniform doping combined with structural non-uniformities.
  • Ballistic electron transport in ultra-thin polysilicon floating gates leads to programming issues (difficulties to capture the hot electrons in ultra-thin floating gates).
  • Integration of the control gate on top of the floating gate results in a thick poly stack posing serious process integration challenges for advanced CMOS technologies (CMP planarization steps and following advanced lithography steps used in high K metal gate process flows). Capacitive coupling between neighboring floating gates is drastically increased with horizontal scaling. This results in strong cross-talk effects (i.e.
  • Planar floating gate architecture doesn't allow for efficient control of the sub-threshold leakage of the floating gate and select transistors at advanced technology nodes, resulting in high background leakage from the unselected cells sharing the same bit line with selected cell.
  • the present invention is a memory cell design (and method of making) that can be scaled down in size, so that the number of memory cells that can be formed in any given unit area of a substrate can be increased without sacrificing performance.
  • the formation of the memory cell is shown in Figs. 1A to 1X .
  • the process continues with growth of a silicon dioxide (oxide) layer 12 on the surface of substrate 10.
  • a silicon nitride (nitride) layer 14 is formed on oxide layer 12.
  • Another oxide layer 16 is formed on the nitride layer 14, and another nitride layer 18 is formed on the oxide layer 16.
  • a hard mask material 20 is formed on the nitride layer 18.
  • Photoresist 22 is formed on the hard mask material 20.
  • the photoresist 22 is then patterned with a masking step, which includes a photolithography process that selectively exposes portions of the photoresist, and selectively removes portions of the photoresist to expose selective portions of the underlying material (i.e., strips of the underlying hard mask material 20 in this case).
  • a masking step which includes a photolithography process that selectively exposes portions of the photoresist, and selectively removes portions of the photoresist to expose selective portions of the underlying material (i.e., strips of the underlying hard mask material 20 in this case).
  • the resulting structure is shown in Fig. 1B .
  • oxide spacers 24 are formed along the sides of the hard mask material strips 20 by performing an oxide deposition followed by anisotropic oxide etch, which leaves spacers 24 on vertical sidewalls of hard mask strips 20. Photoresist is formed over the structure and patterned to leave strips of photoresist covering alternating spacers 24 (e.g., the right hand spacer along each strip 20). An oxide etch is then used to remove those oxide spacers 24 left exposed by the photoresist. After photoresist removal, an etch is performed to remove hard mask strips 20. The resulting structure is shown in Fig. 1C .
  • Photoresist 26 is formed on the structure and patterned leaving strips of the photoresist 26 each having a length extending orthogonally to the length direction of oxide spacers 24, as shown in Fig. 1D .
  • a nitride etch is then performed to remove exposed portions of nitride layer 18 (leaving behind those portions thereof protected by oxide spacers 24 and photoresist strips 26, as shown in Fig. 1E (after photoresist 26 is removed).
  • a series of etches are then performed. Specifically, an oxide etch is used to remove spacers 24 and exposed portions of oxide 16, exposing portions of nitride layer 14.
  • a nitride etch is used to remove the remaining portions of nitride 18, and remove exposed portions of nitride layer 14, exposing portions of oxide layer 12.
  • An oxide etch is used to remove the exposed portions of oxide layer 12, exposing portions of substrate 10.
  • a silicon etch is then used to etch pairs of trenches 28/29 into the exposed portions of substrate 10, with a thin fin 30 of substrate 10 between adjacent pairs of trenches 28/29. Fins 30 extend lengthwise in the vertical/column direction and are parallel to each other.
  • the trenches 28/29 are periodically interrupted by thin fin structures 32 of substrate 10 that extend lengthwise in the horizontal/row direction, such that vertically extending fins 30 periodically intersect the horizontally extending fins 32. The resulting structure is shown in 1F.
  • each fin 30/32 includes two sidewalls that oppose each other and terminate in a top surface (on which oxide 12 is disposed).
  • Implantation can be performed at this time to the exposed substrate (e.g., CMOS baseline and bottom fin isolation).
  • Insulation material 34 e.g., oxide
  • oxide planarization to remove the oxide above the tops of nitride 14, as shown in Fig. 1G .
  • a hard mask insulation layer (e.g., nitride) 36 is formed on the structure, followed by a masking step to form photoresist 38 extending over just one side of the fin 30 (i.e., over filled trench 28 but not over filled trench 29), as shown in Fig. 1H .
  • a nitride etch is used to remove the exposed portions of nitride 36, followed by an oxide etch that removes the upper portion of oxide 34 on one side of fin 32 (i.e., in trench 29), as shown in Fig. 1I (after photoresist 38 is removed).
  • a cell implant can be performed at this time.
  • An oxide layer 40 is formed over the structure, including along the exposed sidewalls of fins 30 and 32 in trench 29.
  • a polysilicon deposition, doping, anneal, and etch back are performed to form a block of polysilicon (poly) 42 in trench 29 (on one side of fin 30 and one side of fin 32, where the two fins intersect), as shown in Fig. 11.
  • Poly block 42 is laterally adjacent to both fin 30 and fin 32 and insulated therefrom by oxide layer 40.
  • Photoresist is formed over a portion of the poly block 42 that is closest to where fins 30 and 32 intersect, and a poly etch is used to remove the other portion of poly block 42 (i.e., so that poly block 42 extends only partially along the length of trench 29 that is immediately adjacent intersection of fins 30/32), as shown in Fig. 1K (after photoresist removal).
  • Oxide 44 is deposited on the structure, which is followed by CMP (chemical mechanical polish) planarization, as shown in Fig. 1L .
  • a nitride etch is used to remove nitride 14.
  • An oxide deposition (to fill the void left by removed nitride 14) and CMP planarization (using poly block 42 as the polish stop) is used to laterally surround poly block 42 with oxide, as shown in Fig. 1M .
  • An insulation layer 46 (preferably ONO, which includes oxide-nitride-oxide sublayers) is formed over the structure.
  • a polysilicon layer 48 is formed on ONO layer 46.
  • a masking step is used to cover the poly layer 48 with photoresist except for a strip extending over the fin 32.
  • a poly etch is then used to remove the portion of poly layer 48 over fin 32, as shown in Fig. 1N (after photoresist removal).
  • An oxide spacer 50 is formed along the side of poly layer 48 and extending along fin 32 by oxide deposition and etch, using the nitride of layer 46 as etch stop. Spacer 50 protects fin 30, but does not cover fin 32.
  • An implantation and anneal are then performed to form a source region 52 in fin 32, as shown in Fig. 1O .
  • An oxide etch is used to remove spacer 50 (which served as protection for exposed portions of fin 30 during implantation of fin 32 to form source region 52).
  • the exposed portion of insulation layer 46 is removed by isotropic etch steps (i.e., exposed areas on top of the floating gate 42 and source line 52).
  • a masking process is used to form photoresist 54 over fin 32, over the portion of poly block 42 not underneath poly layer 48, and over a portion of poly layer 48 that is over poly block 42, as shown in Fig. 1P .
  • Etches are then used to remove exposed portions of poly layer 48 (leaving a poly block 48a), to remove exposed portions of ONO layer 46 and to remove upper portions of oxide 44 in trenches 28/29.
  • Photoresist 54 is then removed. The resulting structure is shown in Fig. 1Q .
  • An oxide layer 56 is formed over the structure. Nitride spacers are formed along the sidewalls of poly block 48a by nitride deposition and etch. An oxide layer (tunnel oxide) 60 is formed over the structure, followed by a masking step to form photoresist 62 over fin 32 and poly block 48a, as shown in Fig. 1R . An oxide etch is used to remove the exposed oxide on the sides of the structure and fin 30. Photoresist 62 is removed. An oxide layer 64 is formed over the structure, followed by the formation of a thick layer of polysilicon.
  • the structure is then planarized removing the upper portions of the thick layer of polysilicon and upper portion of poly block 48a, resulting in poly block 66 disposed on one side of poly block 48a (over fin 32 and source region 52) and poly block 68 disposed on the other side of poly block 48 (and wrapping around fin 30), as shown in Fig. 1S .
  • An implantation and anneal can be performed at this time to dope poly blocks 48a, 66 and 68.
  • a hardmask layer 70 (e.g., amorphous carbon) is formed over the structure, and an oxide layer 72 is formed on layer 70.
  • a masking process is then performed to cover the structure with photoresist except for a portion (but not all) of poly block 68. Etches are then used to remove the exposed portions of oxide layer 72, amorphous carbon layer 70, and poly block 68 (leaving intact the portion of poly block 68 closest to poly blocks 42 and 48a).
  • An n-type drain extension implant and anneal is performed into the portion of fin 30 exposed by the etches. The resulting structure is shown in Fig. 1T (after photoresist removal).
  • Nitride or low-K material spacer 74 is formed along the exposed sidewall of poly block 68 by deposition and etch steps. An oxide etch is used to remove oxide on, and expose, the portion of fin 30 adjacent the nitride spacer 74. The exposed portion of fin 30 is subjected to epitaxial formation of silicon carbon (SiC), anneal, and implantation, for forming an enlarged drain region 76 of fin 30. Etches are then used to remove oxide layer 72 and amorphous carbon layer 70, as shown in Fig. 1U .
  • a nitride layer 78 is formed over the structure, and a layer of oxide 80 is formed on nitride layer 78.
  • a CMP is performed to remove the portion of oxide 80 on top the flat portion of nitride layer 78 (i.e., use nitride 78 as the CMP stop, where oxide 80 remains over drain region 76).
  • a masking step is used to form photoresist 82 on portions of nitride layer 78 over poly blocks 48a and 66, but not over poly block 68.
  • a nitride etch is used to remove the exposed portion of nitride layer 78, exposing poly block 68, as shown in Fig. 1V . Photoresist 82 is removed.
  • a poly etch is used to remove poly block 68.
  • An insulation layer 84 of a high K dielectric material i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials
  • a metal layer which can include an appropriate metal gate stack.
  • Etches are used to remove portions of the metal layer and insulation layer 84 except for a metal block 86 laterally adjacent to poly block 42 (i.e., where poly block 68 used to be before its removal).
  • Metal block 86 is insulated on its sides and bottom by insulation layer 84, as shown in Fig. 1W .
  • Nitride 88 is deposited on the structure (including over metal block 86), which is followed by a CMP to planarize the top surface.
  • Oxide 90 is then deposited over the structure.
  • a masking step is performed to form photoresist over the structure except for over the drain region 76 of fin 30.
  • One or more etches are then performed to form a contact hole that extends down to and exposes drain region 76.
  • the contact hole is then filled with a conductive material (material deposition followed by CMP) to form a conductive contact 92 that is electrically connected to the drain region 76.
  • Contact 92 can be formed of Ti, TiN, salicide and/or tungsten (e.g.
  • CMOS baseline process flow to form multi-layer metal inter-connections for routing.
  • Fig. 2 is a partial perspective view of the structure of a memory cell 2 formed at the intersection of one of the fins 30 and one of the fins 32.
  • This portion of the memory cell 2 includes spaced apart source region 52 and drain region 76 (defining a channel region 93 of the substrate extending there between along the opposing side surfaces and top surface of fin 30).
  • the memory cell 2 further includes a word line gate 86, a floating gate 42, a control gate 48a and an erase gate 66.
  • the word line gate 86 extends along and is insulated from both opposing side surfaces and the top surface of fin 30, and is disposed adjacent the drain region 76.
  • the floating gate 42 is disposed only on only one side of the fin 30 and only one side of fin 32 (adjacent where fins 30 and 32 intersect).
  • the control gate 48a is disposed over the fin 30, and over the floating gate 42.
  • the erase gate 66 is disposed over the source region 52 (i.e., over the intersection of fins 30 and 32) and over a portion of the floating gate 42, and includes a notch 66a that faces an upper corner of the floating gate 42 for enhanced erase tunneling efficiency.
  • the conductivity of one portion of the channel region 93 is controlled by the word line gate 86 wrapping around it, and the conductivity of another portion of the channel region is controlled by the floating gate 42 disposed laterally adjacent to it.
  • FIG. 1X and 2 show only a portion of the memory cell.
  • Each memory cell 2 includes portions of two fins 30 that share a common floating gate 42 disposed there between. This is best shown in Fig. 3 , which is a top plan view showing the memory cell 2 is formed over portions of two adjacent fins 30.
  • the drain regions 76 of the two fins 30 are electrically connected together by contact 92.
  • the source regions 52 for both fins 30 are electrically connected together by fin 32.
  • the word line gate 86 extends along both side surfaces and top surface of both fins 30.
  • Control gate 48a extends over both fins 30 and the floating gate 42.
  • Each memory cell 2 includes two channel regions 93, one in each fin 30, that operate in parallel. Therefore, for example, during a read operation, the total channel region current would be the current in the channel region 93 on the left hand fin 30 of Fig. 3 added to the current in the channel region 93 on the right hand fin 30 of Fig. 3 .
  • Fig. 4 illustrates an array of memory cells 2. Fins 30 extend in the column direction, and fins 32 extend in the row direction.
  • Word line gates 86 are formed as a continuous line (word line) extending in the row direction and forming the word line gate 86 for a row of the memory cells 2.
  • control gates 48a are formed as a continuous line (control gate line) extending in the row direction and forming the control gates 48a for a row of the memory cells 2.
  • the control gate line can include one or more control gate line contacts 94 electrically connected thereto.
  • Fin 32 is a continuous line that constitutes at least a portion of the source region 52 for a row of the memory cells 2.
  • Erase gates 66 are formed as discontinuous lines (erase gate lines electrically connected to some but not all of the erase gates in each row) extending in the row direction.
  • Source line contacts 96 are formed on top of the source line regions 52 in the areas not covered by erase gates 66 (see strap cell in Fig. 5 ).
  • Erase gates 66 are connected by contacts 97 formed in a similar way as control gate contacts 94.
  • Discontinuous erase gate lines allow less than one row erase granularity (i.e., less than a full row of memory cells can be separately erased).
  • Word line contacts 98 are formed on top of the word lines 86.
  • the drain contacts 92 of the memory cells sharing the same column are electrically connected by a bit line 92a formed in first metal interconnect layer.
  • Figure 5 shows a perspective view of strap cell 3 implementing control gate contact 94 and source line contact 96.
  • Each of the channel regions 93 for each memory cell 2 extends along the opposing side surfaces and top surface of one of the fins 30.
  • the word line gate 86 wraps around both fins 30, and extends along both side surfaces and top surface of each of the two fins 30 for better channel region control.
  • the source regions 52 for a row of memory cells 2 are formed as a continuous source line in fin 32 that intersects fins 30. This allows for scaling the cells down to a smaller size, because this configuration avoids the need to form source line contacts for each pair of memory cells.
  • the continuous source line extending along the fin 32 can be electrically connected to a strap through periodic contacts 96 (e.g., every 32 or 64 columns). By having a contact every 32 or 64 columns instead of one for every column, the size of the memory cells 2 and thus a memory array of the memory cells 2 can be significantly reduced.
  • the erase gate 66 is disposed over the source line (i.e., over the source region 52), for further memory cell scaling.
  • the floating gate 42 has a box like shape positioned at the corners formed by two vertical extending fins 30 intersecting a horizontal extending fin 32, for better voltage coupling (during hot electron injection programming) to the source line in fin 32, and for better control of the channel regions 93 in fins 30 (during reading).
  • the inventors have discovered that this configuration of the floating gate 42 relative to the intersections of fins 30 with fin 32 reduces unwanted corner rounding of the floating gate 42 during its manufacture, thus reducing unwanted variability in memory cell read and program characteristics and performance.
  • the same oxide layer 40 can be used insulate the floating gate 42 from both fins 30 and fin 32 (i.e., this insulation has a uniform thickness between the floating gate and all three fins).
  • the height of the memory cell is reduced by embedding at least some of the floating gate 42 inside the isolation insulation material (oxide) that insulates adjacent fins 30 from each other.
  • Using metal and a high K dielectric to form the word line gate 86 provides better conduction and performance, and thus allows the word line gate 86 to be scaled down in size resulting in shorter channel regions 93.
  • This configuration of the word line gate 86 improves the control of the sub-threshold leakage current from unselected cells sharing the same column, and improves high temperature read performance.
  • Manufacturing is simplified by forming the erase gate 66 and the dummy poly block 68 (which is replaced with metal block 86) from the same layer of deposited polysilicon.
  • the density of memory cells per square unit area of the substrate 10 can be significantly increased due to the extension of the channel width in the vertical direction in fins 30, and the extension of the source region 52 width in the vertical direction in fin 32.
  • Tables 1 and 2 Two separate, non-limiting sets of exemplary operating voltages for the memory cells 2 are provided in Tables 1 and 2 below.
  • Table 1 Program Erase Read Drain 76 1-2 ⁇ A 0V 0.5-1.1V Word Line Gate 86 0.5-1.2V 0V 0.5-2.5V Control Gate 48a 5.5-13.5V 0V 0.5-2.5V Erase Gate 66 3.5-5.5V 8.5-15.5V 0V Source 52 3.5-5.5V 0V 0V Table 2 Program Erase Read Drain 76 1-2 ⁇ A 0V 0.5-1.1V Word Line Gate 86 0.5-1.2V 0V 0.5-2.5V Control Gate 48a 5.5-13.5V -10V to -15V 0.5-2.5V Erase Gate 66 3.5-5.5V 8.5-12V 0V Source 52 3.5-5.5V 0V 0V During the program operation, electrons travelling along the channel regions 93 from the drain regions 76 toward the source regions 52, become heated, and some of which will be injected onto the
  • the electrons on the floating gate 42 will tunnel through the intervening insulation to the erase gate 66 by Fowler-Nordheim tunneling.
  • the floating gate if the floating gate is erased of electrons, current will flow along the channel regions 93 from the source regions 52 to the drain regions 76, which is sensed as an erased state. If the floating gate is programed with electrons, little or no current will flow along the channel regions from the source regions 52 to the drain regions 76, which will be sensed as a programmed state.
  • the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element "over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

Description

    PRIORITY CLAIM FIELD OF THE INVENTION
  • The present invention relates to non-volatile flash memory cell arrays.
    • BACKGROUND OF THE INVENTION
  • Non-volatile memory devices are well known in the art. For example, a split-gate memory cell is disclosed in U.S. Patent 5,029,130 . This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions. Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region under the floating gate to determine the programming state of the floating gate).
  • The configuration and number of gates in non-volatile memory cells can vary. For example, U.S. Patent 7,315,056 discloses a memory cell that additionally includes a program/erase gate over the source region. U.S. Patent 7,868,375 discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate. See also U.S. Patents 6,747,310 , 7,868,375 , 9,276,005 and 9,276,006 .
  • US 2016/064398 A1 , considered to be the closest prior art of the present invention, relates to a finFET flash memory cell with floating gates covering the sides of a first fin at either side of a second, orthogonal fin (the source line). Select gates are provided adjacent to the floating gate wrapping around the sides and top surface of the fin at opposite side of the floating gate with respect to the source fin; control gates are provided wrapping around the fin, covering the floating gates; and a central erase gate is provided wrapping around the first fin and the orthogonal source line fin. Because the problem of shrinking the lithography size thereby reducing the channel width affects all semiconductor devices, a Fin-FET type of structure has been proposed. In a Fin-FET type of structure, a fin shaped member of the semiconductor substrate material connects the source region to the drain region. The fin shaped member has a top surface and two opposing side surfaces. Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces. Thus, the surface width of the channel region is increased, thereby increasing the current flow, without sacrificing more semiconductor real estate, by "folding" the channel region into two side surfaces, thereby reducing the "footprint" of the channel region. Non-volatile memory cells using such Fin-FETs have been disclosed. Some examples of prior art Fin-FET non-volatile memory structures include U.S. Pat. Nos. 7,423,310 , 7,410,913 , 8,461,640 , and 9,634,018 . However, these prior art Fin-FET structures have disclosed using the floating gate as a stack gate device, or using trapping material, or using SRO (silicon rich oxide) or using nanocrystal silicon to store charges, or other memory cell configurations that are either too simplistic for memory cells having more than 2 gates or too complex for the number of gates at issue.
  • A number of problems have been discovered by the inventors when scaling memory cells down in size. Ultra-thin polysilicon or amorphous silicon film deposition and doping techniques are complex and often suffer from insufficient and non-uniform doping combined with structural non-uniformities. Ballistic electron transport in ultra-thin polysilicon floating gates leads to programming issues (difficulties to capture the hot electrons in ultra-thin floating gates). Integration of the control gate on top of the floating gate results in a thick poly stack posing serious process integration challenges for advanced CMOS technologies (CMP planarization steps and following advanced lithography steps used in high K metal gate process flows). Capacitive coupling between neighboring floating gates is drastically increased with horizontal scaling. This results in strong cross-talk effects (i.e. the read current of the cell becomes dependent on the charge state of the neighbor cells) and requires complex management by design. The scaling of the planar floating gate memory cells is limited by reduction of the read currents related to transistors width scaling. Lower read currents penalize the access times and require complex design techniques to meet high speed access time specifications. Planar floating gate architecture doesn't allow for efficient control of the sub-threshold leakage of the floating gate and select transistors at advanced technology nodes, resulting in high background leakage from the unselected cells sharing the same bit line with selected cell.
    • BRIEF SUMMARY OF THE INVENTION
  • The aforementioned issues are addressed by a memory device according to claims 1 and 5; and by the method of making a memory device according to claim 10.
  • Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
    • Figs. 1A-1C are side cross sectional views showing the steps in forming the split-gate non-volatile memory cell of the present invention.
    • Figs. 1D-1X are perspective cross sectional views showing the steps in forming the split-gate non-volatile memory cell of the present invention.
    • Fig. 2 is a partial perspective view of the split-gate non-volatile memory cell of the present invention.
    • Fig. 3 is a top plan view of the split-gate non-volatile memory cell of the present invention.
    • Fig. 4 is a top plan view of an array of the memory cell of the present invention.
    • Fig. 5 is a partial perspective view of the strap cell implementing contacts to the control gate and the source line.
    DETAILED DESCRIPTION OF THE INVENTION
  • The present invention is a memory cell design (and method of making) that can be scaled down in size, so that the number of memory cells that can be formed in any given unit area of a substrate can be increased without sacrificing performance. The formation of the memory cell is shown in Figs. 1A to 1X. After forming an appropriate p-type doping profile 10a in semiconductor substrate10, the process continues with growth of a silicon dioxide (oxide) layer 12 on the surface of substrate 10. A silicon nitride (nitride) layer 14 is formed on oxide layer 12. Another oxide layer 16 is formed on the nitride layer 14, and another nitride layer 18 is formed on the oxide layer 16. A hard mask material 20 is formed on the nitride layer 18. These layers are shown in Fig. 1A.
  • Photoresist 22 is formed on the hard mask material 20. The photoresist 22 is then patterned with a masking step, which includes a photolithography process that selectively exposes portions of the photoresist, and selectively removes portions of the photoresist to expose selective portions of the underlying material (i.e., strips of the underlying hard mask material 20 in this case). The resulting structure is shown in Fig. 1B.
  • An etch is performed to remove the exposed portions of hard mask material 20, leaving strips of hard mask material. After photoresist removal, oxide spacers 24 are formed along the sides of the hard mask material strips 20 by performing an oxide deposition followed by anisotropic oxide etch, which leaves spacers 24 on vertical sidewalls of hard mask strips 20. Photoresist is formed over the structure and patterned to leave strips of photoresist covering alternating spacers 24 (e.g., the right hand spacer along each strip 20). An oxide etch is then used to remove those oxide spacers 24 left exposed by the photoresist. After photoresist removal, an etch is performed to remove hard mask strips 20. The resulting structure is shown in Fig. 1C.
  • Photoresist 26 is formed on the structure and patterned leaving strips of the photoresist 26 each having a length extending orthogonally to the length direction of oxide spacers 24, as shown in Fig. 1D. A nitride etch is then performed to remove exposed portions of nitride layer 18 (leaving behind those portions thereof protected by oxide spacers 24 and photoresist strips 26, as shown in Fig. 1E (after photoresist 26 is removed). A series of etches are then performed. Specifically, an oxide etch is used to remove spacers 24 and exposed portions of oxide 16, exposing portions of nitride layer 14. A nitride etch is used to remove the remaining portions of nitride 18, and remove exposed portions of nitride layer 14, exposing portions of oxide layer 12. An oxide etch is used to remove the exposed portions of oxide layer 12, exposing portions of substrate 10. A silicon etch is then used to etch pairs of trenches 28/29 into the exposed portions of substrate 10, with a thin fin 30 of substrate 10 between adjacent pairs of trenches 28/29. Fins 30 extend lengthwise in the vertical/column direction and are parallel to each other. The trenches 28/29 are periodically interrupted by thin fin structures 32 of substrate 10 that extend lengthwise in the horizontal/row direction, such that vertically extending fins 30 periodically intersect the horizontally extending fins 32. The resulting structure is shown in 1F. While only one fin 30 and one fin 32 are shown in the figures, it should be appreciated that there is a grid of intersecting fins 30 and 32, with fins 30 extending lengthwise in the column direction and fins 32 extending lengthwise in the row direction. Each fin 30/32 includes two sidewalls that oppose each other and terminate in a top surface (on which oxide 12 is disposed).
  • Implantation can be performed at this time to the exposed substrate (e.g., CMOS baseline and bottom fin isolation). Insulation material 34 (e.g., oxide) is formed over the structure (including filling trenches 28/29 with oxide 34), followed by oxide planarization to remove the oxide above the tops of nitride 14, as shown in Fig. 1G. A hard mask insulation layer (e.g., nitride) 36 is formed on the structure, followed by a masking step to form photoresist 38 extending over just one side of the fin 30 (i.e., over filled trench 28 but not over filled trench 29), as shown in Fig. 1H. A nitride etch is used to remove the exposed portions of nitride 36, followed by an oxide etch that removes the upper portion of oxide 34 on one side of fin 32 (i.e., in trench 29), as shown in Fig. 1I (after photoresist 38 is removed). A cell implant can be performed at this time.
  • An oxide layer 40 is formed over the structure, including along the exposed sidewalls of fins 30 and 32 in trench 29. A polysilicon deposition, doping, anneal, and etch back are performed to form a block of polysilicon (poly) 42 in trench 29 (on one side of fin 30 and one side of fin 32, where the two fins intersect), as shown in Fig. 11. Poly block 42 is laterally adjacent to both fin 30 and fin 32 and insulated therefrom by oxide layer 40. Photoresist is formed over a portion of the poly block 42 that is closest to where fins 30 and 32 intersect, and a poly etch is used to remove the other portion of poly block 42 (i.e., so that poly block 42 extends only partially along the length of trench 29 that is immediately adjacent intersection of fins 30/32), as shown in Fig. 1K (after photoresist removal). Oxide 44 is deposited on the structure, which is followed by CMP (chemical mechanical polish) planarization, as shown in Fig. 1L. A nitride etch is used to remove nitride 14. An oxide deposition (to fill the void left by removed nitride 14) and CMP planarization (using poly block 42 as the polish stop) is used to laterally surround poly block 42 with oxide, as shown in Fig. 1M.
  • An insulation layer 46 (preferably ONO, which includes oxide-nitride-oxide sublayers) is formed over the structure. A polysilicon layer 48 is formed on ONO layer 46. A masking step is used to cover the poly layer 48 with photoresist except for a strip extending over the fin 32. A poly etch is then used to remove the portion of poly layer 48 over fin 32, as shown in Fig. 1N (after photoresist removal). An oxide spacer 50 is formed along the side of poly layer 48 and extending along fin 32 by oxide deposition and etch, using the nitride of layer 46 as etch stop. Spacer 50 protects fin 30, but does not cover fin 32. An implantation and anneal are then performed to form a source region 52 in fin 32, as shown in Fig. 1O.
  • An oxide etch is used to remove spacer 50 (which served as protection for exposed portions of fin 30 during implantation of fin 32 to form source region 52). the exposed portion of insulation layer 46 is removed by isotropic etch steps (i.e., exposed areas on top of the floating gate 42 and source line 52). A masking process is used to form photoresist 54 over fin 32, over the portion of poly block 42 not underneath poly layer 48, and over a portion of poly layer 48 that is over poly block 42, as shown in Fig. 1P. Etches are then used to remove exposed portions of poly layer 48 (leaving a poly block 48a), to remove exposed portions of ONO layer 46 and to remove upper portions of oxide 44 in trenches 28/29. Photoresist 54 is then removed. The resulting structure is shown in Fig. 1Q.
  • An oxide layer 56 is formed over the structure. Nitride spacers are formed along the sidewalls of poly block 48a by nitride deposition and etch. An oxide layer (tunnel oxide) 60 is formed over the structure, followed by a masking step to form photoresist 62 over fin 32 and poly block 48a, as shown in Fig. 1R. An oxide etch is used to remove the exposed oxide on the sides of the structure and fin 30. Photoresist 62 is removed. An oxide layer 64 is formed over the structure, followed by the formation of a thick layer of polysilicon. The structure is then planarized removing the upper portions of the thick layer of polysilicon and upper portion of poly block 48a, resulting in poly block 66 disposed on one side of poly block 48a (over fin 32 and source region 52) and poly block 68 disposed on the other side of poly block 48 (and wrapping around fin 30), as shown in Fig. 1S. An implantation and anneal can be performed at this time to dope poly blocks 48a, 66 and 68.
  • A hardmask layer 70 (e.g., amorphous carbon) is formed over the structure, and an oxide layer 72 is formed on layer 70. A masking process is then performed to cover the structure with photoresist except for a portion (but not all) of poly block 68. Etches are then used to remove the exposed portions of oxide layer 72, amorphous carbon layer 70, and poly block 68 (leaving intact the portion of poly block 68 closest to poly blocks 42 and 48a). An n-type drain extension implant and anneal is performed into the portion of fin 30 exposed by the etches. The resulting structure is shown in Fig. 1T (after photoresist removal). Nitride or low-K material spacer 74 is formed along the exposed sidewall of poly block 68 by deposition and etch steps. An oxide etch is used to remove oxide on, and expose, the portion of fin 30 adjacent the nitride spacer 74. The exposed portion of fin 30 is subjected to epitaxial formation of silicon carbon (SiC), anneal, and implantation, for forming an enlarged drain region 76 of fin 30. Etches are then used to remove oxide layer 72 and amorphous carbon layer 70, as shown in Fig. 1U.
  • A nitride layer 78 is formed over the structure, and a layer of oxide 80 is formed on nitride layer 78. A CMP is performed to remove the portion of oxide 80 on top the flat portion of nitride layer 78 (i.e., use nitride 78 as the CMP stop, where oxide 80 remains over drain region 76). A masking step is used to form photoresist 82 on portions of nitride layer 78 over poly blocks 48a and 66, but not over poly block 68. A nitride etch is used to remove the exposed portion of nitride layer 78, exposing poly block 68, as shown in Fig. 1V. Photoresist 82 is removed. Then, a poly etch is used to remove poly block 68. An insulation layer 84 of a high K dielectric material (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials) is formed over the structure, followed by the deposition of a metal layer (which can include an appropriate metal gate stack). Etches are used to remove portions of the metal layer and insulation layer 84 except for a metal block 86 laterally adjacent to poly block 42 (i.e., where poly block 68 used to be before its removal). Metal block 86 is insulated on its sides and bottom by insulation layer 84, as shown in Fig. 1W.
  • Nitride 88 is deposited on the structure (including over metal block 86), which is followed by a CMP to planarize the top surface. Oxide 90 is then deposited over the structure. A masking step is performed to form photoresist over the structure except for over the drain region 76 of fin 30. One or more etches are then performed to form a contact hole that extends down to and exposes drain region 76. The contact hole is then filled with a conductive material (material deposition followed by CMP) to form a conductive contact 92 that is electrically connected to the drain region 76. Contact 92 can be formed of Ti, TiN, salicide and/or tungsten (e.g. by Ti deposition, TiN deposition, salicidation and anneal, W deposition, and CMP). The structure after contact formation is shown in Fig. 1X. From this point, further processing can follow CMOS baseline process flow to form multi-layer metal inter-connections for routing.
  • Fig. 2 is a partial perspective view of the structure of a memory cell 2 formed at the intersection of one of the fins 30 and one of the fins 32. This portion of the memory cell 2 includes spaced apart source region 52 and drain region 76 (defining a channel region 93 of the substrate extending there between along the opposing side surfaces and top surface of fin 30). The memory cell 2 further includes a word line gate 86, a floating gate 42, a control gate 48a and an erase gate 66. The word line gate 86 extends along and is insulated from both opposing side surfaces and the top surface of fin 30, and is disposed adjacent the drain region 76. The floating gate 42 is disposed only on only one side of the fin 30 and only one side of fin 32 (adjacent where fins 30 and 32 intersect). The control gate 48a is disposed over the fin 30, and over the floating gate 42. The erase gate 66 is disposed over the source region 52 (i.e., over the intersection of fins 30 and 32) and over a portion of the floating gate 42, and includes a notch 66a that faces an upper corner of the floating gate 42 for enhanced erase tunneling efficiency. The conductivity of one portion of the channel region 93 is controlled by the word line gate 86 wrapping around it, and the conductivity of another portion of the channel region is controlled by the floating gate 42 disposed laterally adjacent to it.
  • Figures 1X and 2 show only a portion of the memory cell. Each memory cell 2 includes portions of two fins 30 that share a common floating gate 42 disposed there between. This is best shown in Fig. 3, which is a top plan view showing the memory cell 2 is formed over portions of two adjacent fins 30. The drain regions 76 of the two fins 30 are electrically connected together by contact 92. The source regions 52 for both fins 30 are electrically connected together by fin 32. The word line gate 86 extends along both side surfaces and top surface of both fins 30. Control gate 48a extends over both fins 30 and the floating gate 42. Each memory cell 2 includes two channel regions 93, one in each fin 30, that operate in parallel. Therefore, for example, during a read operation, the total channel region current would be the current in the channel region 93 on the left hand fin 30 of Fig. 3 added to the current in the channel region 93 on the right hand fin 30 of Fig. 3.
  • Fig. 4 illustrates an array of memory cells 2. Fins 30 extend in the column direction, and fins 32 extend in the row direction. Word line gates 86 are formed as a continuous line (word line) extending in the row direction and forming the word line gate 86 for a row of the memory cells 2. Similarly, control gates 48a are formed as a continuous line (control gate line) extending in the row direction and forming the control gates 48a for a row of the memory cells 2. The control gate line can include one or more control gate line contacts 94 electrically connected thereto. Fin 32 is a continuous line that constitutes at least a portion of the source region 52 for a row of the memory cells 2. Erase gates 66 are formed as discontinuous lines (erase gate lines electrically connected to some but not all of the erase gates in each row) extending in the row direction. Source line contacts 96 are formed on top of the source line regions 52 in the areas not covered by erase gates 66 (see strap cell in Fig. 5). Erase gates 66 are connected by contacts 97 formed in a similar way as control gate contacts 94. Discontinuous erase gate lines allow less than one row erase granularity (i.e., less than a full row of memory cells can be separately erased). Word line contacts 98 are formed on top of the word lines 86. The drain contacts 92 of the memory cells sharing the same column are electrically connected by a bit line 92a formed in first metal interconnect layer. Figure 5 shows a perspective view of strap cell 3 implementing control gate contact 94 and source line contact 96.
  • The above described method of forming the memory cells, and the resulting memory array, provide many advantages including compact size, better manufacturability and better performance. These advantages are achieved from one or more of the following features. Each of the channel regions 93 for each memory cell 2 extends along the opposing side surfaces and top surface of one of the fins 30. The word line gate 86 wraps around both fins 30, and extends along both side surfaces and top surface of each of the two fins 30 for better channel region control. The source regions 52 for a row of memory cells 2 are formed as a continuous source line in fin 32 that intersects fins 30. This allows for scaling the cells down to a smaller size, because this configuration avoids the need to form source line contacts for each pair of memory cells. Instead, the continuous source line extending along the fin 32 can be electrically connected to a strap through periodic contacts 96 (e.g., every 32 or 64 columns). By having a contact every 32 or 64 columns instead of one for every column, the size of the memory cells 2 and thus a memory array of the memory cells 2 can be significantly reduced. The erase gate 66 is disposed over the source line (i.e., over the source region 52), for further memory cell scaling.
  • The floating gate 42 has a box like shape positioned at the corners formed by two vertical extending fins 30 intersecting a horizontal extending fin 32, for better voltage coupling (during hot electron injection programming) to the source line in fin 32, and for better control of the channel regions 93 in fins 30 (during reading). The inventors have discovered that this configuration of the floating gate 42 relative to the intersections of fins 30 with fin 32 reduces unwanted corner rounding of the floating gate 42 during its manufacture, thus reducing unwanted variability in memory cell read and program characteristics and performance. The same oxide layer 40 can be used insulate the floating gate 42 from both fins 30 and fin 32 (i.e., this insulation has a uniform thickness between the floating gate and all three fins). The height of the memory cell is reduced by embedding at least some of the floating gate 42 inside the isolation insulation material (oxide) that insulates adjacent fins 30 from each other. Using metal and a high K dielectric to form the word line gate 86 provides better conduction and performance, and thus allows the word line gate 86 to be scaled down in size resulting in shorter channel regions 93. The inventors have further discovered that this configuration of the word line gate 86 improves the control of the sub-threshold leakage current from unselected cells sharing the same column, and improves high temperature read performance. Manufacturing is simplified by forming the erase gate 66 and the dummy poly block 68 (which is replaced with metal block 86) from the same layer of deposited polysilicon. Finally, the density of memory cells per square unit area of the substrate 10 can be significantly increased due to the extension of the channel width in the vertical direction in fins 30, and the extension of the source region 52 width in the vertical direction in fin 32.
  • Two separate, non-limiting sets of exemplary operating voltages for the memory cells 2 are provided in Tables 1 and 2 below. Table 1
    Program Erase Read
    Drain
    76 1-2 µA 0V 0.5-1.1V
    Word Line Gate 86 0.5-1.2V 0V 0.5-2.5V
    Control Gate
    48a 5.5-13.5V 0V 0.5-2.5V
    Erase Gate 66 3.5-5.5V 8.5-15.5V 0V
    Source
    52 3.5-5.5V 0V 0V
    Table 2
    Program Erase Read
    Drain
    76 1-2 µA 0V 0.5-1.1V
    Word Line Gate 86 0.5-1.2V 0V 0.5-2.5V
    Control Gate
    48a 5.5-13.5V -10V to -15V 0.5-2.5V
    Erase Gate 66 3.5-5.5V 8.5-12V 0V
    Source
    52 3.5-5.5V 0V 0V
    During the program operation, electrons travelling along the channel regions 93 from the drain regions 76 toward the source regions 52, become heated, and some of which will be injected onto the floating gate 42 by hot-electron injection. During the erase operation, the electrons on the floating gate 42 will tunnel through the intervening insulation to the erase gate 66 by Fowler-Nordheim tunneling. During the read operation, if the floating gate is erased of electrons, current will flow along the channel regions 93 from the source regions 52 to the drain regions 76, which is sensed as an erased state. If the floating gate is programed with electrons, little or no current will flow along the channel regions from the source regions 52 to the drain regions 76, which will be sensed as a programmed state.
  • It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of any claims supported thereby. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit any claims. For example, the floating gate, control gate and/or erase gate could be formed of amorphous silicon instead of polysilicon. Further, not all method steps need be performed in the exact order illustrated. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
  • It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed there between) and "indirectly on" (intermediate materials, elements or space disposed there between). Likewise, the term "adjacent" includes "directly adjacent" (no intermediate materials, elements or space disposed there between) and "indirectly adjacent" (intermediate materials, elements or space disposed there between), "mounted to" includes "directly mounted to" (no intermediate materials, elements or space disposed there between) and "indirectly mounted to" (intermediate materials, elements or spaced disposed there between), and "electrically coupled" includes "directly electrically coupled to" (no intermediate materials or elements there between that electrically connect the elements together) and "indirectly electrically coupled to" (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

Claims (15)

  1. A memory device, comprising:
    a semiconductor substrate (10) having an upper surface with a plurality of upwardly extending fins (30, 32), wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface;
    a first fin (30) of the plurality of fins has a length that extends in a first direction;
    a second fin (30) of the plurality of fins has a length that extends in the first direction;
    a third fin (32) of the plurality of fins has a length that extends in a second direction that is perpendicular to the first direction;
    a memory cell (2), comprising:
    spaced apart first source (52) and first drain (76) regions in the first fin, with a first channel region (93) of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions, wherein the first source region is disposed at an intersection of the first and third fins,
    spaced apart second source (52) and second drain (76) regions in the second fin, with a second channel region (93) of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, wherein the second source region is disposed at an intersection of the second and third fins,
    a floating gate (42) disposed laterally between and insulated from the first and second fins, and disposed laterally adjacent to and insulated from the third fin, wherein the floating gate extends along and is insulated from a first portion of the first channel region and a first portion of the second channel region, wherein the floating gate is insulated from the second side surface of the first fin only by first insulation (40) having a first thickness, is insulated from the first side surface of the second fin only by second insulation (40) having a second thickness, and is insulated from the first side surface of the third fin only by third insulation (40) having a third thickness, wherein the first, second and third thicknesses are equal to each other,
    a word line gate (86) that extends along and is insulated from a second portion of the first channel region and a second portion of the second channel region,
    a control gate (48a) that is disposed over and insulated from the floating gate, and
    an erase gate (66) that includes a first portion disposed over and insulated from the first and second source regions and a second portion that is disposed over and insulated from the floating gate.
  2. The memory device of claim 1, wherein the word line gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin and extends along and is insulated from the first and second side surfaces and the top surface of the second fin.
  3. The memory device of claim 1, wherein the erase gate includes a notch (66a) facing an upper edge of the floating gate.
  4. The memory device of claim 1, wherein the word line gate is formed of a metal material and is insulated from the first and second channel regions by a high K dielectric material.
  5. A memory device, comprising:
    a semiconductor substrate (10) having an upper surface with a plurality of upwardly extending fins (30, 32), wherein each of the fins including first and second side surfaces that oppose each other and that terminate in a top surface;
    first fins (30) of the plurality of fins each having a length that extends in a column direction;
    second fins (32) of the plurality of fins each having a length that extends in a row direction that is perpendicular to the column direction;
    a plurality of memory cells (2) arranged in rows and columns on the substrate, each of the memory cells comprising:
    spaced apart first source (52) and first drain (76) regions in one of the first fins, with a first channel region (93) of the one first fin extending along the top surface and the opposing side surfaces of the one first fin between the first source and first drain regions, wherein the first source region is disposed at an intersection of the one first fin and one of the second fins,
    spaced apart second source (52) and second drain (76) regions in another one of the first fins, with a second channel region (93) of the another one first fin extending along the top surface and the opposing side surfaces of the another one first fin between the second source and second drain regions, wherein the second source region is disposed at an intersection of the another one first fin and the one second fin,
    a floating gate (42) disposed laterally between and insulated from the one first fin and the another one first fin, and is disposed laterally adjacent to and insulated from the one second fin, wherein the floating gate extends along and is insulated from a first portion of the first channel region and a first portion of the second channel region,
    a word line gate (86) that extends along and is insulated from a second portion of the first channel region and a second portion of the second channel region,
    a control gate (48a) that is disposed over and insulated from the floating gate, and
    an erase gate (66) that includes a first portion disposed over and insulated from the first and second source regions and a second portion that is disposed over and insulated from the floating gate;
    wherein for each of the memory cells, the floating gate is insulated from the second side surface of the one first fin only by first insulation (40) having a first thickness, is insulated from the first side surface of the another one fin only by second insulation (40) having a second thickness, and is insulated from the first side surface of the one second fin only by third insulation (40) having a third thickness, wherein the first, second and third thicknesses are equal to each other.
  6. The memory device of claim 5, wherein for each of the memory cells, the word line gate extends along and is insulated from the first and second side surfaces and the top surface of the one first fin and extends along and is insulated from the first and second side surfaces and the top surface of the another one first fin.
  7. The memory device of claim 5, wherein for each of the memory cells, the erase gate includes a notch (66a) facing an upper edge of the floating gate.
  8. The memory device of claim 5, wherein for each of the memory cells, the word line gate is formed of a metal material and is insulated from the first and second channel regions by a high K dielectric material.
  9. The memory device of claim 5, further comprising:
    a plurality of word lines (86) each electrically connected to the word line gates of a row of the memory cells;
    a plurality of control gate lines (48a) each electrically connected to the control gates of a row of the memory cells; and
    a plurality of erase gate lines (66) each electrically connected to some but not all of the erase gates of a row of the memory cells.
  10. A method of forming a memory device, comprising:
    forming a plurality of upwardly extending fins (30, 32) in an upper surface of a semiconductor substrate (10), wherein:
    each of the fins include first and second side surfaces that oppose each other and that terminate in a top surface,
    first fins of the plurality of fins each has a length that extends in a column direction,
    second fins of the plurality of fins each has a length that extends in a row direction that is perpendicular to the column direction;
    forming a plurality of memory cells (2) arranged in rows and columns on the substrate, each of the memory cells being formed by:
    forming spaced apart first source (52) and first drain (76) regions in one of the first fins, with a first channel region (93) of the one first fin extending along the top surface and the opposing side surfaces of the one first fin between the first source and first drain regions, wherein the first source region is disposed at an intersection of the one first fin and one of the second fins,
    forming spaced apart second source (52) and second drain (76) regions in another one of the first fins, with a second channel region (93) of the another one first fin extending along the top surface and the opposing side surfaces of the another one first fin between the second source and second drain regions, wherein the second source region is disposed at an intersection of the another one first fin and the one second fin,
    forming a floating gate (42) laterally between and insulated from the one first fin and the another one first fin, and laterally adjacent to and insulated from the one second fin, wherein the floating gate extends along and is insulated from a first portion of the first channel region and a first portion of the second channel region,
    forming a word line gate (86) that extends along and is insulated from a second portion of the first channel region and a second portion of the second channel region,
    forming a control gate (48a) over and insulated from the floating gate, and
    forming an erase gate (66) that includes a first portion disposed over and insulated from the first and second source regions and a second portion that is disposed over and insulated from the floating gate;
    wherein for each of the memory cells, the floating gate is insulated from the second side surface of the one first fin only by first insulation (40) having a first thickness, is insulated from the first side surface of the another one fin only by second insulation (40) having a second thickness, and is insulated from the first side surface of the one second fin only by third insulation (40) having a third thickness, wherein the first, second and third thicknesses are equal to each other.
  11. The method of claim 10, wherein for each of the memory cells, the word line gate extends along and is insulated from the first and second side surfaces and the top surface of the one first fin and extends along and is insulated from the first and second side surfaces and the top surface of the another one first fin.
  12. The method of claim 10, wherein for each of the memory cells, the method further comprising:
    forming a conductive contact (92) electrically connected to the first and second drain regions.
  13. The method of claim 10, wherein for each of the memory cells, the forming of the erase gate includes forming a notch (66a) in the erase gate facing an upper edge of the floating gate.
  14. The method of claim 10, wherein for each of the memory cells, the word line gate is formed of a metal material and is insulated from the first and second channel regions by a high K dielectric material.
  15. The method of claim 10, further comprising:
    forming a plurality of word lines (86) each electrically connected to the word line gates of a row of the memory cells;
    forming a plurality of control gate lines (48a) each electrically connected to the control gates of a row of the memory cells; and
    forming a plurality of erase gate lines (66) each electrically connected to some but not all of the erase gates of a row of the memory cells.
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI723371B (en) * 2019-04-03 2021-04-01 國立清華大學 Micro detector and defect measurement method
US11362100B2 (en) 2020-03-24 2022-06-14 Silicon Storage Technology, Inc. FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling
KR102567123B1 (en) * 2020-09-21 2023-08-14 실리콘 스토리지 테크놀로지 인크 Method of Forming Devices with Isolated Plane Gate Non-Volatile Memory Cells, High Voltage Devices and FinFET Logic Devices
CN114335186A (en) * 2020-09-30 2022-04-12 硅存储技术股份有限公司 Split-gate non-volatile memory cell with erase gate disposed over word line gate and method of making the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150035040A1 (en) * 2013-08-02 2015-02-05 Silicon Storage Technology, Inc. Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
US6747310B2 (en) 2002-10-07 2004-06-08 Actrans System Inc. Flash memory cells with separated self-aligned select and erase gates, and process of fabrication
US20050012137A1 (en) 2003-07-18 2005-01-20 Amitay Levi Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing
KR100621628B1 (en) 2004-05-31 2006-09-19 삼성전자주식회사 Non-volatile memory cells and methods of the same
US7315056B2 (en) 2004-06-07 2008-01-01 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with program/erase and select gates
JP4927321B2 (en) 2004-06-22 2012-05-09 ルネサスエレクトロニクス株式会社 Semiconductor memory device
US7423310B2 (en) 2004-09-29 2008-09-09 Infineon Technologies Ag Charge-trapping memory cell and charge-trapping memory device
KR100652384B1 (en) 2004-11-08 2006-12-06 삼성전자주식회사 2 bit type non-volatile memory device and method of fabricating the same
TWI259585B (en) 2005-03-21 2006-08-01 Powerchip Semiconductor Corp Split gate flash memory and manufacturing method thereof
KR101100428B1 (en) 2005-09-23 2011-12-30 삼성전자주식회사 Manufacturing method of Silicon Rich Oxide and Semiconductor adopting the same
CN100590799C (en) 2005-09-28 2010-02-17 Nxp股份有限公司 FinFET-based non-volatile memory device
KR100663366B1 (en) * 2005-10-26 2007-01-02 삼성전자주식회사 Method of fabricating flash memory devices having self-aligned floating gate and related device
US7754560B2 (en) 2006-01-10 2010-07-13 Freescale Semiconductor, Inc. Integrated circuit using FinFETs and having a static random access memory (SRAM)
US7544980B2 (en) 2006-01-27 2009-06-09 Freescale Semiconductor, Inc. Split gate memory cell in a FinFET
US7838922B2 (en) 2007-01-24 2010-11-23 Freescale Semiconductor, Inc. Electronic device including trenches and discontinuous storage elements
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
US8068370B2 (en) 2008-04-18 2011-11-29 Macronix International Co., Ltd. Floating gate memory device with interpoly charge trapping structure
US8148768B2 (en) 2008-11-26 2012-04-03 Silicon Storage Technology, Inc. Non-volatile memory cell with self aligned floating and erase gates, and method of making same
JP2011003742A (en) 2009-06-18 2011-01-06 Toshiba Corp Nonvolatile semiconductor memory device and method of manufacturing the same
US8461640B2 (en) * 2009-09-08 2013-06-11 Silicon Storage Technology, Inc. FIN-FET non-volatile memory cell, and an array and method of manufacturing
US8941153B2 (en) 2009-11-20 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with different fin heights
US8420476B2 (en) 2010-05-27 2013-04-16 International Business Machines Corporation Integrated circuit with finFETs and MIM fin capacitor
JP2012234885A (en) 2011-04-28 2012-11-29 Toshiba Corp Semiconductor device and manufacturing method of the same
US8785273B2 (en) 2012-04-11 2014-07-22 International Business Machines Corporation FinFET non-volatile memory and method of fabrication
US9406689B2 (en) * 2013-07-31 2016-08-02 Qualcomm Incorporated Logic finFET high-K/conductive gate embedded multiple time programmable flash memory
US9614048B2 (en) 2014-06-17 2017-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Split gate flash memory structure and method of making the split gate flash memory structure
US9312268B2 (en) * 2014-09-02 2016-04-12 Globalfoundries Singapore Pte. Ltd. Integrated circuits with FinFET nonvolatile memory
US9276005B1 (en) 2014-12-04 2016-03-01 Silicon Storage Technology, Inc. Non-volatile memory array with concurrently formed low and high voltage logic devices
US9276006B1 (en) 2015-01-05 2016-03-01 Silicon Storage Technology, Inc. Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same
JP6343721B2 (en) 2015-01-23 2018-06-13 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． Self-aligned split gate memory cell array with metal gate and method of forming logic device
US9634018B2 (en) 2015-03-17 2017-04-25 Silicon Storage Technology, Inc. Split gate non-volatile memory cell with 3D finFET structure, and method of making same
US10134475B2 (en) 2015-03-31 2018-11-20 Silicon Storage Technology, Inc. Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system
US9570454B2 (en) * 2015-06-25 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure with emedded EFS3 and FinFET device
KR102395485B1 (en) 2015-06-26 2022-05-09 인텔 코포레이션 Semi-Volatile Embedded Memory and Method with Pin-to-Pin Floating Gate Device
US9793279B2 (en) 2015-07-10 2017-10-17 Silicon Storage Technology, Inc. Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing
US10141321B2 (en) 2015-10-21 2018-11-27 Silicon Storage Technology, Inc. Method of forming flash memory with separate wordline and erase gates
WO2017078920A1 (en) 2015-11-03 2017-05-11 Silicon Storage Technology, Inc. Split gate non-volatile flash memory cell having metal gates and method of making same
JP6620034B2 (en) 2016-02-24 2019-12-11 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US9666589B1 (en) 2016-03-21 2017-05-30 Globalfoundries Inc. FinFET based flash memory cell
CN107293546B (en) 2016-04-08 2020-09-04 硅存储技术公司 Reduced size split gate non-volatile flash memory cell and method of making same
US9837425B2 (en) 2016-04-19 2017-12-05 United Microelectronics Corp. Semiconductor device with split gate flash memory cell structure and method of manufacturing the same
US9985042B2 (en) 2016-05-24 2018-05-29 Silicon Storage Technology, Inc. Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells
US10276726B2 (en) * 2016-05-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory cell and non-volatile memory
US9947676B2 (en) 2016-07-08 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. NVM memory HKMG integration technology
TWI632558B (en) * 2017-05-01 2018-08-11 卡比科技有限公司 Non-volatile memory device and operation method of the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150035040A1 (en) * 2013-08-02 2015-02-05 Silicon Storage Technology, Inc. Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same

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