EP3888245A1

EP3888245A1 - Pulse-width modulation signal generator

Info

Publication number: EP3888245A1
Application number: EP18811484.7A
Authority: EP
Inventors: Volker Langer
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2018-11-26
Filing date: 2018-11-26
Publication date: 2021-10-06
Also published as: WO2020108731A1

Abstract

A pulse-width modulation signal generator (3) is described. The pulse-width modulation signal generator comprises an analogue delay-locked loop (7) which comprises a delay line (11) arranged to receive a clock signal (CLKSYS), the delay line comprising a chain (12) of delay cells (131, 132, 133, 134, 13n-1, 13n) outputting a plurality of phases, a phase selector (17) for selecting a one of the plurality of phases as a selected phase signal (OUTPHASE) in dependence upon a phase-selection signal (SELPHASE), and a delay controller (18) configured to compare respective phases of the clock signal and the last delay cell and to generate a delay control signal (Δ) for the delay cells in dependence thereon. The pulse-width modulation signal generator comprises a logic circuit (20) configured to receive the selected phase signal (OUTPHASE) and a clock period-selecting signal (SELPERIOD) selecting a one clock period (8) in the clock period for a pulse-width modulation signal period, and to output the pulse-width modulation signal period having a rising edge or a falling edge (10) whose timing corresponds to an edge of the selected phase signal (OUTPHASE) occurring in the one clock period.

Description

Pulse-width m odulation signal generator

Field

The present invention relates to a pulse- width modulation signal generator.

Background

A pulse-width modulation (PWM) signal generator can be used to control voltage or power supplied to a device or load, such as a motor. For example, the PWM signal controller can be used to control a DC-to-DC converter.

JP Ho6 326574 A describes a signal generation circuit employing a delay circuit comprising a series of delay elements. The delay circuit receives a clock signal and outputs a succession of increasingly-delayed clock signals via a series of taps. The original clock signal and a clock signal from a final delay element are compared by a phase difference detection circuit. The phase difference is converted into a voltage which is fed back to the delay circuit. The amount of delay can be controlled so that the original clock signal and the clock signal from a final delay element coincide. The increasingly-delayed clock signals are supplied to an output selection circuit which can select one of them and so generate a higher resolution signal.

Although the signal generation circuit can provide a high-resolution signal, the delay circuit needs a large number of delay elements. For example, if a 20 MHz clock signal is used and a signal resolution of 0.1 ns is required, then 500 delay elements are needed.

A higher frequency clock can be used or a PWM signal can be generated using an averaging method. However, these approaches suffer drawbacks. For example, a high frequency clock can lead to electromagnetic compatibility issues and consume more power, whereas the PWM signal cannot be changed from cycle-to-cycle if the averaging approach is used.

Examples of other PWM signal generation circuits employing delay lines can be found, for example, in US 2016/0118967 Ai, US 2015/0171843 Ai, US 9 438 219 B2, US 2017/0040988 Ai and US 6 819 190 B2. Reference is also made to SPRUG04A

Reference guide to TMS320X2833X, 2823X Enhanced Pulse Width Modulator (ePWM) Module October 2008. Sum m ary

According to a first aspect of the present invention there is provided a pulse-width modulation signal generator. The pulse-width modulation signal generator comprises an analogue delay-locked loop which comprises a delay line arranged to receive a clock signal, the delay line comprising a chain of delay cells outputting a plurality of phases, a phase selector for selecting a one of the plurality of phases as a selected phase signal in dependence upon a phase selection signal, and a delay controller configured to compare respective phases of the clock signal and the last delay cell and to generate a delay control signal for the delay cells in dependence thereon. The pulse-width modulation signal generator further comprises a logic circuit configured to receive the selected phase signal and a clock period-selecting signal selecting a one clock period for a pulse- width modulation signal period, and to output the pulse-width modulation signal period having a rising edge or falling edge whose timing corresponds to an edge (preferably, the rising edge) of the selected phase signal occurring in the one clock period.

Thus, it is possible to obtain a high- resolution signal using a low-frequency clock signal, e.g., obtain a resolution of 200ps with 50 MHz clock. Moreover, the PWM signal can be changed every PWM cycle.

The logic may be configured to receive a first set of bits and to generate the clock-period selection signal in dependence on the first set of bits. The logic may be configured to receive a second set of bits and to generate the phase-period selection signal in dependence on the second set of bits. The logic may be further configured to receive the clock signal and to generate a rising edge of the pulse- width modulation signal period in dependence upon the clock signal.

According to a second aspect of the present invention there is provided a monolithic integrated circuit comprising the apparatus of the first aspect of the invention.

The integrated circuit may be an application-specific integrated circuit.

According to a third aspect of the present invention there is provided a system comprising the apparatus of the first aspect of the invention or the integrated circuit of the second aspect of the invention and a controller, such as a microcontroller or system-on-a-chip, in communication with the apparatus or integrated circuit. According to a fourth aspect of the present invention there is provided a motor vehicle comprising the apparatus of the first aspect of the invention or the integrated circuit of the second aspect of the present invention.

The motor vehicle may further comprise a controller, such as a microcontroller or system-on-a-chip, in communication with the apparatus of the first aspect of the invention or integrated circuit of the second aspect of the present invention The motor vehicle may be a motorcycle, an automobile (sometimes referred to as a “car”), a minibus, a bus, a truck or loriy. The motor vehicle may be powered by an internal combustion engine and/or one or more electric motors.

According to a fifth aspect of the present invention there is provided a method comprising generating a selected phase signal using an analogue delay-locked loop in dependence on a clock signal and a phase-selection signal, and generating a pulse width a pulse-width modulation signal period having a rising edge or falling edge whose timing corresponds to an edge of the selected phase signal occurring in the one clock period.

Brief Description of the Drawings

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure l illustrates vaiying timing of a falling edge of a PWM signal;

Figure 2 is a schematic block diagram of a system for generating a PWM signal;

Figure 3 illustrates a two-stage approach to varying timing of a falling edge;

Figure 4 is a schematic block diagram of a PWM signal generator;

Figure 5 shows timings of signals in the PWM signal generator shown in Figure 4; and Figure 6 illustrates a vehicle which includes a PWM signal generating system.

Detailed Description of Certain Em bodim ents

Introduction

Referring to Figure 1, one period of a PWM signal is shown. The PWM signal has a period T_PWM and includes a rising edge and a falling edge, which define a pulse width (or“pulse duration”) during which the PWM signal is HIGH. The remaining part of the PWM signal period is LOW.

A high resolution may be required for a low-frequency PWM signal, that is, for a PWM signal having a frequency in the range of 1 to 500 kHz. A high-resolution PWM signal may be needed in a variety of different applications, such as DC-to-DC converters and motor control. Typically, such a PWM signal requires a resolution of I/T_PWM. If such a high resolution is required, then a high clock frequency can be used. For example, using i/T_PWM, a clock frequency of 5 GHz can be used to achieve a resolution of 200 ns. Using such a high clock frequency can, however, be undesirable.

System 1 for generating a PWM signal

Referring to Figure 2, a system 1 for generating a PWM signal OUT_PWM is shown. The system 1 comprises a controller 2 and a hardware-implemented PWM signal generator 3. The controller 2 provides, to the PWM signal generator 3, first and second sets of control bits 4, 5 and configuration bits CONFIG to specify the form of the PWM signal, for example, to specify whether to set the rising edge and/or the falling edge of the PWM signal OUT_PWM-

The system 1 may take the form of a single, monolithic integrated circuit, such as a microcontroller or system-on-a-chip. Thus, the controller 2 may take the form of a CPU subsystem and the PWM signal generator 3 may take the form of a peripheral module. However, the system l may comprise two or more integrated circuits, wherein the controller 2 takes the form of a microcontroller or system-on- a-chip and the PWM signal generator 3 takes the form of an application specific integrated circuit or other form of integrated circuit.

A clock 6, which may be an internal controller clock ( ._<?., in the controller 2) or an external clock (for example, a clock chip) provides a system clock signal CLKSYS (herein also referred to simply as the“clock signal”)· The clock signal CLKSYS has a frequency fsYs and a period TSYS.

The PWM signal generator 3 can achieve a high-resolution employing a low clock frequency, herein defined as a clock frequency equal to or less than 100 MHz, and using an analogue delay-locked loop 7 without using large numbers (i.e., 200 or more) of delay elements. Moreover, the PWM signal generator 3 is able to vary the duty cycle and control resolution on a cycle-by-cycle basis and be used to compensate for drift due to process, temperature, aging and other influences.

General approach

Referring also to Figure 3, the PWM signal generator 3 uses a two-part approach to adjust the timing of the falling edge 10 and so control the duty cycle. The PWM signal generator 3 effectively selects one system clock period 8 from N system clock periods 8, 9 running during a PWM signal period T_PWM, where N ~ T_PWM/TSYS, to generate the PWM signal OUT_PWM by enabling output of a PWM signal OUT_PHASE· The other system clock periods 9 are effectively ignored and are masked or hidden. The PWM signal generator 3 divides the selected system clock period into n parts and uses this finer graduation within the selected system clock period 8 to select a timing for the falling edge 10. For example, T_PWM may be 2 ps, TSYS may be 10 ns (corresponding to a system clock frequency of 100 MHz) and n may be 50 to achieve a resolution of (10 ns/50) = 200 ps. Although the two-part approach has been described in relation to the falling edge, this approach can be used to control the rising edge of a PWM signal.

PWM signal generator 2

Referring to Figure 4, the PWM signal generator 3 is shown in more detail. The clock 6 (Figure 2) provides an input system clock signal CLKSYS. The controller 2 provides a first set of bits 4 for selecting a one clock period and a second set of bits 5 for selecting the position of the falling edge 10 (Figure 3) of the PWM signal OUT_PWM· The first set of bits 4 consist of n bits BitoH, BitiH,...,BitnH. The first set of bits 4 may consist of 8 bits (or more) which allows selection of one of, for example, 100 or 200 periods. The second set of bits 5 may consist of m bits BitoL, BitiL,..., BitmL. The second set of bits 5 may consist of 6 (or more) bits. The first and second sets of bits 4, 5 may correspond to a set of high bits and a set of low bits respectively of, for example, 16-bit word.

The analogue delay-locked loop 7 comprises an delay circuit 11 comprising a chain 12 of n delay cells 13₁, 13₂, 13₃, 13₄,···, i3_n-i, i3_n, an output selection circuit 17 (herein also referred to as a“phase selection circuit”), a delay controller 18, a first (or“input”) logic circuit 19 and a second (or“output”) logic circuit. The first and second logic circuits 19, 20 may be combined into a single logic circuit (“hardware logic” or“logic”). Herein, a logic circuit may be referred to as“hardware logic” or simply“logic”. The delay-locked loop 7 operates continually, i.e. , while PWM periods are output, and is controlled in time-continuous way. A delay-locked loop 7 can provide accurate resolution over temperature, process, aging and other factors. Also, no trimming or calibration is needed.

The delay circuit 11 comprises a first delay cell 13₁ and a last delay cell i3_n at first and second ends of the chain 12 respectively. Each delay cell I3i,...,i3_n has a respective input and a respective output and is configured to introduce a delay which is adjustable according to a delay control signal 21. The delay cells I3i,...,i3_n each introduce the same delay, e.g. , 200 ps, which is adjustable. The first delay cell 13₂ is arranged to receive the system clock signal CLKSYS as an input system clock signal and the last delay cell I3_n is arranged to provide an output system clock signal CLKSYS’. The chain 12 may consist of between 20 and 200 delay cells 13. Preferably, there are 50 or 100 delay cells 13.

The output section circuit 17 takes the form of a multiplexer configured to receive outputs (i.e. , phases) from the first delay cell 13₁ through to the last delay cell 13₁ and to select one of the outputs as an output signal in dependence upon a selection signal SELPHASE. The phase-selection signal SELPHASE is determined from the second set of bits 5. Six bits allows selection of any one of 49 delay cells. The output selection circuit 17 has a delay which is small compared to PWM period.

The delay controller 18 is configured to measure a phase difference between the input system clock signal CLKSYS and the output system clock signal CLKSYS’, and to generate a delay control signal D in dependence upon the phase difference. The delay control signal D takes the form of an analogue signal taking a value between a lower limit and an upper limit, for example, between 1 and 2 V. The delay controller 18 may comprise a phase discriminator 22, a charge pump 23 and a low-pass filter 24, for example a first- or second-order low-pass filter.

The first logic circuit 19 receives the system clock signal CLKSYS and passes this as one of the inputs to the phase discriminator 22 in the delay controller 18 and as an input to the analogue delay circuit 11. The clock signal CLKSYS need not pass through the first logic 19 but can be fed directly to the phase discriminator 22 and the analogue delay circuit 11.

The first logic circuit 19 generates a period-selection signal SEL_PERIOD based on the first set of control bits 4. The period-selection signal SEL_PERIOD effectively selects one period of the system clock to be used to generating one period of a PWM signal OUT_PWM by passing the selected phase OUT_PHAS_E from the multiplexer 17 for the period as the output OUT_PWM and masking the rest of the output from the multiplexer 17 for the other periods. The first logic circuit 19 receives the second set of bits 5 and outputs a selection signal phase-selection signal SEL_PHAS_E which causes the output selection circuit 17 to select the output of the corresponding the delay cell 13₁, 13₂,..., i3_n-i.

The phase-selection signal SEL_PHAS_E provides fine adjustment of the period of the output signal.

The second logic circuit 20 receives the period-selection signal SEL_PERIOD, the system clock system CLKs_YS and the selected phase OUT_PHAS_E form the multiplexer 17 and generates a period of a PWM signal OUT_PHAS_E based on the period-selection signal SEL_PERIOD, the system clock system CLKSYS and the selected phase OUT_PHAS_E. For example, the second logic circuit 10 may include or take the form of R-S flip flop, for example, the SEL_PERIOD is used to make the correct period visible (for example, using an AND gate) and SEL_PHASE can be the reset.

Referring also to Figure 5, the rising edge of the PWM signal OUT_PWM is defined by a rising edge of CLK_SYS and the falling edge of the PWM signal OUT_PWM is defined by a rising edge of a selected output phase OUT_PHASE output from the delay-locked loop 7 which falls within the selected period SEL_PERIOD.

As explained earlier, a PWM signal be used in a variety of different applications.

Referring to Figure 5, a motor vehicle 101 is shown.

The motor vehicle may include a battery 102, a DC-to-DC converter 103, a DC-to-AC converter 104 and a motor 105. The motor 105 may be used to drive one or more wheels of the of the motor vehicle 101.

The DC-to-DC converter 103 may be controlled, via a PWM signal OUT_PWM, provided by the PWM signal generator 3 under the control of controller 2. Modifications

It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the design, manufacture and use of pulse-width

modulation generators and component parts thereof and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

A rising edge of a PWM signal may be controlled using the process herein described. The controller 2 need not provide the clock signal CLK_SYS. AS separate clock may provide the clock signal.

Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

Claim s

1. A pulse-width modulation signal generator comprising:

an analogue delay-locked loop which comprises a delay line arranged to receive a clock signal, the delay line comprising a chain of delay cells outputting a plurality of phases, a phase selector for selecting a one of the plurality of phases as a selected phase signal in dependence upon a phase selection signal, and a delay controller configured to compare respective phases of the clock signal and the last delay cell and to generate a delay control signal for the delay cells in dependence thereon ; and

logic configured to receive the selected phase signal and a clock period-selecting signal selecting a one clock period for a pulse-width modulation signal period, and to output the pulse-width modulation signal period having a rising edge or falling edge whose timing corresponds to an edge of the selected phase signal occurring in the one clock period.

2. The pulse-width modulation signal generator of claim 1, wherein n is between 20 and 200 , preferably 50 or 100.

3. The pulse-width modulation signal generator of claim 1 or 2, wherein the logic is configured to receive a first set of bits and to generate the clock-period selection signal in dependence on the first set of bits.

4. The pulse-width modulation signal generator of any one of claims 1 to 3, wherein the logic is configured to receive a second set of bits and to generate the phase-period selection signal in dependence on the second set of bits

5. The pulse-width modulation signal generator of any one of claims 1 to 4, wherein the logic is further configured to receive the clock signal and to generate a rising edge of the pulse-width modulation signal period in dependence upon the clock signal.

6. A system comprising:

a controller; and

the pulse-width modulation signal generator of any one of claims 1 to 5.

7. A monolithic integrated circuit comprising:

the pulse-width modulation signal generator of any one of claims 1 to 5.

8. The monolithic integrated circuit of claim 7, which is a microcontroller or a system on a chip.

9. A motor vehicle comprising:

the pulse-width modulation signal generator of any one of claims 1 to 5, the system of claim 6, or the integrated circuit of claim 7 or 8.

10. A method, comprising:

generating a selected phase signal using an analogue delay-locked loop in dependence on a clock signal and a phase-selection signal; and

generating a pulse width a pulse-width modulation signal period having a rising edge or falling edge whose timing corresponds to an edge of the selected phase signal occurring in the one clock period.