EP3874700A1

EP3874700A1 - Data transmission system

Info

Publication number: EP3874700A1
Application number: EP19816376.8A
Authority: EP
Inventors: Serge Delwasse; Vincent Laporte
Original assignee: Silkan Rt
Current assignee: Silkan Rt
Priority date: 2018-10-31
Filing date: 2019-10-29
Publication date: 2021-09-08
Also published as: FR3087979B1; WO2020089558A1; US11552908B2; US20210352025A1; FR3087979A1

Abstract

The present invention relates to a data transmission system comprising a data exchange unit, wherein, to transmit a data frame, it passes successively at least through an interface module that is configured to receive said data frame from outside the transmission system; an analysis and filtering module responsible for processing said data frame which is received from the interface module before encapsulation; and an encapsulation module responsible for encapsulating said data frame processed by the analysis and filtering module, wherein two successive modules through which said data frame passes are connected to one another by an interconnection device each comprising a temporary memory for storing said frame and the read and write accesses to said memory being frequency-independent.

Description

TITLE OF THE INVENTION

Data transmission system

FIELD OF THE INVENTION

The present invention relates to the field of telecommunications.

More particularly, the present invention relates to the transport of data in a reliable and deterministic manner.

TECHNOLOGICAL BACKGROUND

In a telecommunications network, data transport is carried out in the usual way in the form of data frames established according to a predefined protocol. To transport a frame between a data transmitter (or producer) and a receiver (or consumer), a switch made from processing units controlled by software is usually used. A classic example of a network switch is the Ethernet switch.

This type of switch does not guarantee in a secure manner either the effective delivery of the data frame or a maximum delay for transmission of this frame. The use of such switches in so-called "critical" systems where total reliability of transmissions is required is therefore not possible. In addition, this type of switch is generally limited to use according to a single physical and logical communication protocol.

Thus, there is a need for a data communication system allowing the communication of data in an integrated manner and within a maximum guaranteed time, without limitation of use of a particular protocol.

The present invention falls within this context.

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided a data transmission system comprising a data exchange unit; in which, to transmit a data frame, it passes successively at least through:

- an interface module configured to receive said data frame from outside the transmission system;

- an analysis and filtering module in charge of processing said data frame received from the interface module before encapsulation; and - an encapsulation module in charge of encapsulating said data frame processed by the analysis and filtering module; characterized in that, two successive modules through which said data frame passes are interconnected by an interconnection device each comprising a temporary memory for storing said frame and the write and read accesses to said memory being independent in frequency.

A data transmission system according to the first aspect makes it possible to guarantee the independence of an upstream module and a downstream module through which a data frame passes. Indeed, the presence of an interconnection device according to claim 1 between two modules makes it possible to isolate the data processing chains of each module from each other. The interconnect device is used as a storage barrier in the data flow.

The interconnection device according to the invention allows each module to have its own operating clock. The performances are thus increased because each module can carry out the treatments which are specific to it without having to take into account what can happen in the module which follows or precedes it.

In a system according to the first aspect, each module can thus be designed independently. In addition, updating a system according to the first aspect is simplified because it is possible to modify a module without affecting the rest of the system.

The use of an interconnection device between two modules finally makes it possible not to modify the determinism of the entire transmission system. The level of safety is therefore preserved.

For example, the interconnection device can provide so-called "FIFO" ("First In, First Out" or even "first in, first out" in French) management of the data exchanged through it.

The interconnection device according to the invention also makes it possible to present at the output only valid data thanks to the filtering of the abnormal data.

In one embodiment, the data transmission system further comprises a database unit configured to store the frames of data encapsulated by the encapsulation module; it is connected to the encapsulation module by an interconnection device comprising a temporary memory for storing said frame and the write and read accesses to said memory being independent in frequency. In one embodiment, in order to transmit a data frame, it also passes successively at least by:

- a module for generating the data to be sent, responsible for receiving encapsulated data frames from the database unit and processing them for retransmission; and

a transmission control module in charge of de-encapsulating an encapsulated data frame received from the module for generating the data to be transmitted and then transmitting the de-encapsulated data frame to the interface module for the transmission of the data frame data encapsulated outside the transmission system.

In one embodiment, the database unit is connected to the module for generating the data to be transmitted by an interconnection device comprising a temporary memory for storing said frame and the write and read accesses to said memory being independent in frequency.

In one embodiment, the data exchange unit also includes:

- a management module in charge of managing the transmissions of encapsulated data frames from the database unit; and

- a command generation module in charge of generating commands to the database unit for controlling the extraction of data to be retransmitted and communicating it to the module for generating the data to be sent. In one embodiment, the database unit is connected to the management module by an interconnection device comprising a temporary memory for storing control and signaling data and the write and read accesses to said memory being independent in frequency. In one embodiment, the database unit is connected to the command generation module by an interconnection device comprising a temporary memory for storing command and signaling data and the write and read accesses to said command memory being independent in frequency.

In one embodiment, which the data exchange unit further comprises a status management module, responsible for storing the current operating states of each of the modules of the data transmission system, connected to the module interface by an interconnection device comprising a temporary memory for storing control and signaling data and the write and read accesses to said memory being independent in frequency.

In one embodiment, two successive modules through which said data frame passes operate according to independent clocks. In one embodiment, the memory of each interconnection device can be configured during initialization.

In one embodiment, each interconnection device comprises a write interface for storing data in the temporary memory as they are received and a read interface for reading said data in the order of their reception. In one embodiment, each interconnection device in which a data frame passes is configured to store the data frames as they are received and to read said data frames in the order of their reception.

In one embodiment, the read and write interfaces have an asynchronous clock relationship. In one embodiment, the write interface is configured to perform processing on at least one piece of data stored in said temporary memory to detect errors and stop storing the data if an error is detected. In one embodiment, the read interface is configured to read the entire data, to re-read the data, or to delete the data. In one embodiment, the read interface is configured to perform processing on at least one datum stored in said temporary memory in order to extract information on said at least one datum. In one embodiment, each interconnection device includes an error reporting interface for transmitting operating errors in writing or in reading.

In one embodiment, each module is produced in a programmable circuit or an integrated circuit specific to an application. In one embodiment, each interconnection device is produced in a programmable circuit or an integrated circuit specific to an application. In one embodiment, the analysis and filtering module comprises:

a data frame reception unit to be retransmitted,

- a memory unit for storing said data of said frame as and when they are received by the reception unit,

at least one processing unit for carrying out processing on at least one data item stored in said memory unit, the result of said processing being intended to be used in the management of the retransmission of the data.

In one embodiment, the analysis and filtering module also includes a control unit for triggering the loading of data from at least one of said reception unit and from the memory unit to said at least one unit. processing, said loading and said processing being carried out during the reception of said frame as and when data is stored in said memory.

The analysis and filtering module allows maximum parallelization of the arrival of a frame, its decoding and its filtering which increases performance (processing speed).

The analysis and filtering module allows multi-protocol compatibility.

It can also allow an increase in the intrinsic security of data processing because its fully hardware implementation does not allow modification of its behavior and its ability to operate faster than the arrival of any data ensures its permanent availability.

According to embodiments, the operation of the module is synchronous.

For example, the control unit is a finite state machine.

For example again, the memory unit includes a set of registers.

According to embodiments, the loading of data and triggered as a function of the availability of said data in a given register.

According to embodiments, the module comprises a processing unit enabling the integrity of said frame to be checked during reception.

For example, the integrity check relates to data loaded from said receiving unit.

According to embodiments, the module comprises a processing unit which allows the validity of said frame to be checked during reception. For example, the processing unit enabling the validity of said frame to be checked during reception operates dichotomous processing of said frame.

According to embodiments, the processing unit enabling the validity of said frame to be checked during reception comprises a plurality of stages in series.

According to embodiments, at least one stage of the processing unit comprises a plurality of parallel substages.

For example, the module includes a processing unit (503) allowing specific calculations to be carried out to supply at least one of a stage and a sub-stage of said processing unit allowing the validity of said frame in progress to be checked. reception.

According to embodiments, the control unit also makes it possible to control the reception unit as a function of information received from said at least one processing unit.

For example, the module is configured to generate an output indicating an anomaly in receiving said frame as a function of information received from said at least one processing unit.

For example again, the module is configured to generate an output indicating the content of said memory unit as a function of information received from said at least one processing unit.

According to embodiments, the module is configured to generate an output pointer by at least one processing unit pointing to a memory space of the system containing a data structure to encapsulate said data frame to be retransmitted.

BRIEF DESCRIPTION OF THE FIGURES

Other characteristics and advantages of the invention will appear on reading the present detailed description which follows, by way of nonlimiting example, and of the appended figures among which:

Figure 1 illustrates a system according to embodiments;

Figure 2 illustrates the transmission of data according to embodiments;

Figures 3a-3b illustrate the reception of a data (or message) by a data exchange unit according to embodiments; FIG. 4 illustrates the processing of a frame according to embodiments;

FIG. 5 is a diagram illustrating an analysis and filtering module according to embodiments;

Figure 6 is a diagram illustrating a database unit according to embodiments.

DETAILED DESCRIPTION OF THE INVENTION

A system according to embodiments is described with reference to FIG. 1.

The system shown in this figure is implemented in hardware, that is to say that it is not controlled in software. The system is for example produced in the form of a FPGA type circuit (acronym for "Field-Programmable Gate Array").

The system includes one or more data exchange units 100 (ComSet) and a database unit 101 (Base station).

The database unit allows the storage of data exchanged between the data exchange units. The number of data exchange units is equal to the number of communication ports desired for the system. These communication ports are connected

The exchange units 100 can be connected to a database unit 101 by means of a standardized interface, that is to say that the interface is the same for all the modules. The standard interface has as many data transport buses as there are modules in direct communication with the database unit.

For example, a module 112 is in charge of encapsulating frames of data received and to be processed within the system. This module communicates with the database unit via a dedicated bus 102. A module 113 is for example in charge of the generation of commands intended for the database unit 101 to extract data to be retransmitted. This module communicates with the database unit via a dedicated bus 103. A module 115 is responsible for receiving encapsulated frames from the database unit and processing them for retransmission. This module communicates with the database unit via a dedicated bus 105. A module 114 is responsible for managing the transmissions on the part of the database unit indicating certain events such as the storage of frames encapsulated. This management includes, for example, the coordination of modules 113 and 115. This module communicates with the database unit via a dedicated bus 104. A clock module 116 is responsible for receiving time updates of the system from the base station. In addition, it provides the time to all the modules of the data transmission system which must either mark the data or verify the data transmission times. The clock module can also generate events for the supply of synchronization signals to the process which requested it. It can also warn the data transmission modules when data is sent when they are defined as cyclic by the configuration. The clock module communicates with the database unit via a dedicated bus 106.

The analysis and filtering module 117 is a module for processing the data frames received before their encapsulation by the module 112.

Conversely, the module 118 allows to encapsulate an encapsulated frame received from the module 115.

A status management module 119 is responsible for storing the current operating states of each of the modules of the data transmission system. Preferably, the status management module 119 is responsible for storing the current operating states of each of the modules of the data transmission system if the configuration requires it. Indeed, the behavior of the data transmission system can be modified by the initial supply of configuration data in which we can specify the states and incidents that we want to be able to manage. In addition, all the modules are designed to transmit any operational incident to this status management module, which then updates its information base and generates an error event immediately if the configuration requests it to the data transmission system. intended for this purpose.

The data exchanged by an exchange unit is received and sent through an interface module 107 configured according to the protocol used outside the system. Examples of protocols with which the system can be interfaced are Ethernet, CAN, ARINC 664P7 or others.

Communication between on the one hand the different modules 112, 113, 114, 115 of each exchange unit with on the other hand the respective communication buses 102, 103, 104, 105 is done via interconnection devices 108, 109, 110, 111 described more precisely below.

Communication between the different modules 117, 119, 118 of each exchange unit on the one hand, and on the other hand the interface module 107 is also carried out via interconnection devices 120, 121, 122.

An interconnection device is also present between two successive modules along a data stream. By "along a data stream" is meant the succession of modules through which a data frame passes.

Thus, an interconnection device 123 connects the analysis and filtering module 117 in charge of processing the received data frames with the module 112 in charge of encapsulating received data frames and to be processed within the transmission system Datas.

An interconnection device 125 connects the module 115 in charge of receiving encapsulated frames from the database unit 101 and of processing them for retransmission with the module 118 allowing to encapsulate an encapsulated frame received from the module 115 .

The interconnection devices include a temporary memory independently accessible in time by the module downstream from the interconnection device and by the module upstream from the interconnection device. According to one embodiment, the temporary memory of the interconnection device is a buffer memory. The memory is independently accessible for writing by the upstream module and for reading by the downstream module. This memory independently accessible in time by the upstream and downstream modules allows the upstream module to write to the memory independently of the reading by the downstream module. In other words, the upstream module and the downstream module use the memory of the interconnection device in an unsynchronized manner.

Thanks to the interconnection devices, the modules of the transmission system do not share storage space and exchange data via the memory of an interconnection device. In addition, the modules of the transmission system do not share a clock plane. The upstream and downstream modules are completely independent in the use of the memory of the interconnection device. There is no alteration in the determinism of the entire transmission system. The interconnection devices allow minimum latency and have a bandwidth much higher than the maximum speed of each transmission and can therefore operate in “starvation” mode.

The interconnection devices can for example be memories called DPM (acronym for "Dual Port Memory" in English) or DAM (acronym for "Dual Access memory" in English) produced in the form of a FPGA type circuit (acronym for "Field -Programmable Gâte Array "in English).

The memory of the interconnection devices is accessible to the upstream module via a write interface and to the downstream module via a read interface. According to one embodiment, the read and write interfaces have an asynchronous clock relation.

The write interface makes it possible to store the data in the memory as they are received and the read interface makes it possible to read said data from said frame in the order of their reception.

The read interface is configured to read the data stored in the memory in the write order (thus the interconnection devices provide so-called "FIFO" management of the data exchanged through them). Data stored in the memory can be read, re-read or even canceled by the read interface of the interconnection device.

According to one embodiment, the write interface is configured to perform processing on at least one piece of data stored in said memory in order to detect errors and to interrupt the storage of data in a data frame if an error is detected. The errors detected can for example be the absence of buffer space or a sequence error in the data order. E

According to one embodiment, the read interface is configured to perform processing on at least one data item stored in said temporary memory in order to extract information on said at least one item of data. The information extracted can be for example a sequence number, its production time or its length. This information is transmitted to the downstream module at the same time as the data. They can be useful, for example, for processing in the data exchange units 100 or storage in the database unit 101.

According to one embodiment, each interconnection device also comprises an error reporting interface reporting the operating errors in writing or in reading. This information is transmitted through the error reporting interface to a status reporting mechanism of the data transmission system.

When the interconnect devices are located along a stream of data frames (120, 123, 108, 11 1, 125, 118), the temporary memory of the interconnect devices store the data frames.

When the interconnect devices are not located along a stream of data frames (109, 110, 121), the temporary memory of the interconnect devices stores control and signaling data. This control and signaling data has the same format as the data frames.

With reference to FIG. 2, the transmission of a data (or message) is described by an exchange unit 200 which has the same structure as described previously with reference to FIG. 1.

The message 201 is received at the interface module 202. This interface module is in charge of the dialogue with the components responsible for the physical management of the signals of the protocol linked to the data transmission system. It collects the information of the frames received via these components and transmits them byte by byte to the next module via an interconnection device 207. The message 201 is transmitted from the interface module 202 to the module 203 in charge of the analysis and message filtering via the interconnection device 207.

The module 203 verifies the integrity of the message and also verifies that the message is authorized, by configuration, to be received by the exchange unit 200. In other words, the module 203 extracts the information from the incoming frame in order to to make sure that the source IP address and the source port of the message as well as its size are as defined by the configuration. On the other hand, the calculation of CRC (acronym for "Cyclic redundancy check" or checksums in English) makes it possible to verify that the frame received is indeed integrated.

The message is then transmitted from the module 203 in charge of analysis and filtering to the encapsulation module 204 via an interconnection device 208. The message is encapsulated in the encapsulation module 204. Once encapsulated, the message is processed independently of the protocol used for transport outside the system. The encapsulated message is then transmitted to the database unit 205, via the interconnection device 209 and the bus 206, for storage in memory.

The encapsulated message can be stored taking into account different parameters. This is for example to avoid duplication of information in memory. The recording of a message is unique even if it has several recipients. Each recipient and notified of the arrival of the data and its location. Recipients are then authorized to pick it up for transmission. The arrival time of the data is also part of the encapsulation data so that the receivers of the information can control the temporal validity of the latter. For example, the aging of the message must also be taken into account. For example, it is also a question of managing the access methods to the message which define the addresses of the objects in memory (we can for example cite the methods called "Sampling", "Queuing", "Flip / Flop" which are standard methods.

With reference to FIGS. 3a-3b, the reception of a data (or message) by a exchange unit 300 is described.

Following the storage of the message encapsulated in the database unit 205 described above with reference to FIG. 2, data of the "event" type is sent to the exchange unit 300 to which the message 201 is intended via the bus 304 and the interconnection device 308. An “event” type data is an object in common encapsulation format whose object is to warn the recipient module either of the behavior of another module or of '' an action to be performed for the latter.

The database unit 205 (common to modules 200 and 300) generates and manages events relating to the transmission of an encapsulated message. The database unit also rates the moments of transmission of "event" type data to the exchange modules which must send the encapsulated message concerned by the data. The transmission module is notified by message that the data to be transmitted is available and where to go to get it.

The “event” type data is then received by a module 301 for managing cyclic and event emissions in charge of receiving this data. On receipt of such data the module 301 sends a command request to the command generation module 302.

The command generation module 302 then sends a command to the database unit via an interconnection device 310 and the bus 311 so that the encapsulated object is sent to the exchange unit 300.

In parallel, the module 301 sends a request to put the encapsulated message in standby mode to the module 303 for generating data to be transmitted. The module 302 thus plays a role in managing the cycle (in particular the frequency) of sending messages.

The database unit then sends the encapsulated message via the bus 305 and an interconnection device 313 to the module 303 which decapsulates the message to make it a message conforming to the protocol of the equipment connected to the physical port of the exchange unit 300.

The message thus encapsulated is transmitted via an interconnection device 314 to the module 306 for controlling the transmission and then to the interface module 307 via an interconnection device 315. The control module 306 after a final verification of the integrity of the data using the control code (CRC) also verifies that the information contained corresponds to all the criteria defined by the configuration of the output port.

In the following, the operations performed by the analysis and filtering module of a data exchange unit are described.

Filtering takes place between the reception of a frame and its encapsulation. The purpose of filtering is to verify that the frame received is indeed a known, expected and well-formed frame. If not, the frame is rejected and an error message is generated. Filtering also aims to provide, if the frame is accepted, information on the locations where the data necessary for the encapsulation of the frame can be retrieved.

Generally speaking, filtering in the area of networks is the operation of verifying the integrity and validity of a frame received.

Verification of the integrity of the frame makes it possible to ensure that a frame received respects properties related to its structure.

Among the checks carried out, there are for example the alterations at the elementary logical level (bit or set of bits). The verification is carried out using an error detection code of the cyclic redundancy check or CRC type (acronym for "Cyclic Redundancy Check").

Among the checks carried out, we also find that the arrival of two successive frames must respect a minimum delay (we speak of IFG, acronym for "InterFrame Gap"). If this deadline is not respected, the frame is considered corrupt.

Other verifications are possible such as for example the length intervals of the frame, denoted [LMAX, LMIN] which may depend on the protocols. A frame can have a fixed size (this is the case for example in the Arinc 429 protocol) or a variable size bounded in lower and upper values (for example the Ethernet 802.3 protocol). In addition to the regulatory restrictions, the user can tighten the conditions on sizes. When the frame does not respect the size constraints, it is considered corrupt.

Verification of validity makes it possible to ensure that a frame received at a given reception point is indeed authorized to be received at this location (the term "location" means "communication port" in network terminology). Authorization decision making is based on frame encapsulation data. If we take the example of IP type frames (acronym for "Internet Protocol"), respecting the IEEE 802.3 standard, the encapsulation data is to be retrieved from fields in the protocol stack such as: "IP sources", "EtherType "," MAC source "," MAC destination ", etc.

Each frame which passes through the filtering module causes a binary decision-making, therefore with two stable states and no possible indecision: the frame passes the filtering or the frame does not pass the filtering. Any violation of the integrity and / or validity of the frame causes its rejection (frame therefore does not pass filtering).

Two actions are then triggered. A first action is the removal (purging) of the frame of the filtering module. A second action is to lift an error status by checking the status management module mentioned above. The statutes can be managed in different ways. For example, it is possible to choose the sending of status information cyclically and this, with a configurable periodicity, or to send an event as soon as a particular event occurs to the module and the system. data transmission configured for this purpose. The statutes can be active and therefore taken into account or hidden and therefore ignored.

In the event that no violation of the integrity and validity rules is detected, the frame is accepted in the system, in other words, the frame passes the filtering.

Two actions are then triggered. A first action is the supply of the frame to the next module (that is to say the encapsulation module). A second action is the generation of a pointer to the encapsulation tables which makes it possible to find, in the internal memories, the data of certain object encapsulation fields (over-encapsulation of the frame). The encapsulation of a frame is in fact an over-encapsulation. A frame is already an encapsulation of the useful data by fields specific to the protocol. Here it is a question of adding other fields. It is then possible to speak of over-encapsulation. Some fields are calculated and loaded into memory by a configurator in offline mode (before the start of the operational phase) and other fields are calculated by the component in online mode (during the operational phase).

A special feature of the filter module, apart from the fact that it is designed for an exclusively hardware implementation, is the guarantee of a very high performance compared to existing systems on the market. The "hardware implementation" aspect here is opposed to a software implementation based on a Von Neumann type scheme. The filtering module, like the data exchange unit to which it belongs, can be installed in FPGA type programmable circuits (acronym for "Field-Programmable Gate Array" or ASIC (acronym for "application-specific integrated circuit"). performance combines both high throughput and temporal determinism.

The operation of the filtering module includes a frame reception register base, dichotomy modules, and a control state machine.

The entire mechanism of the filtering module is clocked by a control state machine which pushes the frame into a register structure as it is received, and, at appropriate times, loads particular data and / or make calculations on some of this data.

Even before the end of the reception of the frame, filtering, which uses dichotomy tables to search for the information and actions to be carried out, is already launched because all the necessary information is made available.

If necessary, it is possible to stop the operation, and to purge the module if, for example, data corruption is detected via protection mechanisms (such as CRC (acronym for "Cyclic redundancy check" or sums "checksum" in English).

In this operation, several treatments are parallelized. When the arrival of a frame is detected, it is de-serialized as it arrives. Each time a sufficient number of bits is correctly received, the state machine fills a reception register in the register base provided for this purpose. Each register is clearly identified. So, depending on the protocol of the frame being reception, it is possible to retrieve particular information on the fly for the needs, either of processing, or of passing parameters for a given function.

An example of a frame is described with reference to FIG. 4. The invention is not limited to a particular protocol and can be applied to any protocol such as the Arinc 429 protocol or the 802.3 Ethernet protocol.

In the example of a frame conforming to the IEEE 802.3 standard, the first 6 bytes received are the destination MAC address, the next 6 bytes are the source MAC address, the next 2 bytes are the EtherType field. If for filtering purposes, the module requires the last two bytes of the destination MAC address (“Virtual Link” number in the Arinc standard 664P7), and if the registry is made up of 32-bit registers (4 bytes) then the reception of the second register, noted “Reg2” in FIG. 4, triggers a recovery of bytes 1 and 2 for processing purposes (identification of the “Virtual Link”).

The reception and storage operation, in addition to the task of recovering the parameters during reception, ensures verification of the integrity of the frames: verification of the frame envelope, IFG, size, CRC, etc.

The information recovered from the encapsulation (sometimes after processing above) is used to ensure the validity of the frame. In other words, check if the frame is authorized to pass through the rest of the system. This activity is handled by the “dichotomy tables” also called “filter tables”.

For optimal performance, the dichotomy diagram is divided into several stages, each stage of which can itself be subdivided into several parts. The principle of partitioning into "stages" and "parts" obeys the following two rules. The "stages" are "pipelined", that is to say, the outputs of a "stage" of order n-1 are inputs for the stage of order n. The execution of all "parts" in the same "floor" is parallelized.

In an exemplary implementation, the dichotomy is organized in two stages, the first of which is itself subdivided into two parts. Chronologically, research on the first floor is parallelized. The outputs of the first stage constitute inputs for the second stage which, at the output, provides a pointer to memory structures which allow the encapsulation module to over-encapsulate the received frame.

FIG. 5 is a diagram illustrating a filtering module according to embodiments. The overall operation of this module is synchronous. This module uses a single distributed clock. It is also managed by a finite state machine 501 (FSM acronym for "Final State Machine"). The advantage of this way of doing things is to be able to control the trigger and the duration of each operation, which induces a guarantee of a limited and known processing time, and therefore, a guarantee of temporal determinism.

The frame on reception is de-serialized in the input module 500 "DataJN" which stores it as and when it arrives in a register 507. As soon as relevant information is available in the latter, these are recovered to be used. In the example of FIG. 5, the first byte of the first register can be made available, upon receipt, of the module 502 for the dichotomous search of stage 1 part 2, denoted E1 P2. The launching of block 502 requires a command from the machine 501 as well as additional data (denoted "external data" such as the frame envelope and the clock).

In parallel, the reception of the continuous frame and other information is taken on the fly either to feed the dichotomous searches, or to feed a specific calculation unit 503 which subsequently feeds the dichotomous searches. The unit 503 makes it possible to process certain encapsulation information which is not usable in their raw state and / or must be combined together so that they can be used subsequently. For example, the module 502 can only be launched after direct extraction of byte 2 from register 2 and provision of a processing result of unit 503 based on byte 1 of register 2. Launching of the module

504 comprising stage 2 of the dichotomy, noted E2, can only be done after the treatments of stage 1 have been completed. Indeed, the results of modules 502 (E1 P1) and

505 (part 1 of stage 1 denoted E1 P2) are injected as inputs into module 504. In addition, these inputs are not exclusive. Each floor may need additional entrances (in addition to that of the upstream floor). In the example in FIG. 5, the module 504 requires the last byte of the penultimate register as well as a result supplied by the unit 503.

In parallel with all these processing operations, an integrity control unit 506 verifies that the frame on reception does not contain any anomaly. The checks relate to several parameters such as for example the CRC, the length, the IFG, or other. This unit informs the machine 501 of the status of the reception in progress and raises an anomaly if necessary. Throughout the operation, statuses are generated and exchanged in order to prevent any malfunction and detect any anomaly.

The outputs of the filter modules can be one or three depending on the final state of the control state machine. An output is a status word containing the final state of the state machine with, if necessary, an indication (commonly called a flag) about the anomaly observed. If the processing was carried out correctly, then the filtering module provides in addition the content of the register base which is none other than the frame received and a pointer, coming from the last stage of the dichotomy, on the memory structures allowing create the object from the frame encapsulation.

With reference to FIG. 6, the operation of a database unit 600 will now be described.

An encapsulated data frame is received via the bus 602 from the exchange unit as described above with reference to FIG. 1 (in particular from an encapsulation module such as the module 112 of FIG. 1) by the module RX interface module 610. This data frame is transmitted to a write event module 630 via an interconnection device 620. The write event module 630 is responsible for transmitting the encapsulated data received at a memory management module 650.

For this, as a function of the information in the transmitted encapsulated data frame, in particular as a function of the information located at the header of the frame, the write event module 630 communicates with a data management module 642 in order to obtain the write address in the memory 660 of the data frame. The data management module 642 is responsible for assigning a write address in the memory 660 to each data frame.

Once the write address of the data frame received from the data management module 642, the write event module 630 communicates with the memory management module 650 by transmitting a write request by the via a first interconnection device 641 and by transmitting the data frame via a second interconnection device 640.

As soon as the data frame received, the memory management module 650 stores the data frame in the memory 660.

When the data frame has been stored, the write event module 630 communicates with an event module 631 and informs it of the storage of the data frame in the memory 660. As a function of the information of the stored encapsulated data frame, in particular as a function of the information located at the header of the frame, the event module 631 communicates with the event interface module 611 via the 'through an interconnection device 621 which sends via the bus 604 a message to the exchange unit (in particular, to the emission management module 114) concerning the available data with the references of the available data. The event module 631 is responsible for informing the exchange unit of the available stored data frames.

When the exchange unit wishes to recover a data frame, the command generation module 113 sends a read command via the bus 603 to the command interface 612. The command interface 612 transmits this command to the command module read command 632 via an interconnection device 622. The read control module 632 is in charge of receiving commands for data frames from the exchange unit module and of sending ordered data frames.

The read control module 632 which receives the command makes a request to the data management module 642 in order to obtain the address from which to retrieve the data frame according to the references provided in the command.

The data management module 642 then transmits the address to the read control module 632 which communicates its command to the memory management module 650 via a first interconnection device 643. The management module the memory 650 retrieves the data frame from the memory 660 from the address communicated and transmits the data frame to the read control module 632 via a second interconnection device 644.

Once the data frame has been retrieved by the read control module 632, the latter transmits the data frame to the TX interface module 613 via an interconnection device 623. The TX interface module 613 finally transmits the data frame to the exchange unit (in particular to the module for generating the data to be transmitted 115) via the bus 605.

The database unit also includes a time management module 614 which communicates with the clock module 116 of the exchange unit via the bus 606 in order to transmit the updates of the general time of the system. . The time management module 614 is also in charge of supplying the synchronization signals to the modules which have requested it. The interconnection devices 620, 621, 622, 623, 640, 641, 643, 644 of the database unit have the same properties and capacities as the interconnection devices described above with reference to the unit exchange. The present invention has been described and illustrated in the present detailed description with reference to the attached figures. However, the present invention is not limited to the embodiments presented. Other variants, embodiments and combinations of characteristics can be deduced and implemented by a person skilled in the art on reading the present description and the appended figures.

To meet specific needs, a person competent in the field of the invention may apply modifications or adaptations.

In the claims, the term "include" does not exclude other elements or steps. The indefinite article "one" does not exclude the plural. A single processor or several other units can be used to carry out the invention. The various features presented and / or claimed can be advantageously combined. Their presence in the description or in different dependent claims does not exclude the possibility of combining them. The reference signs should not be understood as limiting the scope of the invention.

Claims

1. Data transmission system comprising a data exchange unit (100, 200, 300); in which, to transmit a data frame, it passes successively at least through:

- an interface module (107, 202, 307) configured to receive said data frame from outside the transmission system;

- an analysis and filtering module (1 17, 203) in charge of processing said data frame received from the interface module before encapsulation; and

- an encapsulation module (1 12, 204) in charge of encapsulating said data frame processed by the analysis and filtering module; characterized in that, two successive modules through which said data frame passes are linked together by an interconnection device (120, 123; 207, 208) each comprising a temporary memory for storing said frame and the write and write accesses reading to said memory being independent in frequency.

The data transmission system according to claim 1 further comprising a database unit (101, 205), wherein the database unit (101, 205) is configured to store the frames of data encapsulated by the encapsulation module (1 12, 204) and in which the database unit is connected to the encapsulation module by an interconnection device (108, 209) comprising a temporary memory for storing said frame and the accesses in writing and reading in said memory being independent in frequency.

3. The data transmission system as claimed in claim 2, in which to transmit a data frame, the latter also passes successively at least through:

- a module for generating the data to be sent (1 15, 303) responsible for receiving encapsulated data frames from the database unit (101, 205) and processing them for retransmission ; and

- a transmission control module (1 18, 306) in charge of de-encapsulating an encapsulated data frame received from the module for generating the data to be transmitted (115, 303) then transmitting the de-encapsulated data frame to the module interface (107, 202, 307) for sending the unencapsulated data frame outside the transmission system.

4. Data transmission system according to claim 3, wherein the database unit (101, 205) is connected to the module for generating the data to be transmitted (1 15, 303) by an interconnection device (1 1 1, 313) comprising a temporary memory for storing said frame and the write and read accesses to said memory being independent in frequency.

5. Data transmission system according to any one of claims 2 to 4, in which the data exchange unit (100, 200, 300) also comprises:

- a management module (1 14, 301) in charge of managing the transmissions of encapsulated data frames on the part of the database unit (101, 205); and

- A command generation module (1 13, 302) in charge of generating commands to the database unit (101, 205) to control the extraction of data to be retransmitted and communicate it to the module for generating the data to be transmitted (115, 303).

6. Data transmission system according to claim 5, wherein the database unit (101, 205) is connected to the management module (1 14, 301) by an interconnection device (1 10, 308) comprising a temporary memory for storing control and signaling data and the write and read accesses to said memory being independent in frequency.

7. A data transmission system according to any one of claims 5 or 6, wherein the database unit (101, 205) is connected to the command generation module (1 13, 302) by a device d interconnection (109, 310) comprising a temporary memory for storing control and signaling data and the write and read accesses to said memory being independent in frequency.

8. Data transmission system according to any one of claims 1 to 7, wherein the data exchange unit (100, 200, 300) further comprises a status management module (1 19), in task of storing the current operating states of each of the modules of the data transmission system, connected to the interface module (107, 202, 307) by an interconnection device (121) comprising a temporary memory for storing data of command and signaling and the write and read accesses to said memory being independent in frequency.

9. Data transmission system according to any one of claims 1 to 8, in which two successive modules through which said data frame passes operate according to independent clocks.

10. Data transmission system according to any one of claims 1 to 9, wherein the memory of each interconnection device is configurable at initialization.

1 1. Data transmission system according to any one of claims 1 to 10, in which each interconnection device comprises a write interface for storing data in the temporary memory as they are received and a read interface for reading said data in the order of their reception.

12. The data transmission system according to claim 11, in which each interconnection device (120, 123, 108, 11 1, 125, 122; 207, 208, 209; 313, 134, 315) in which a frame passes through. is configured to store data frames as they are received and to read said data frames in the order of their reception.

13. The data transmission system according to claim 11 or claim 12, wherein the read and write interfaces have an asynchronous clock relation.

14. Data transmission system according to any one of claims 11 to 13, in which the write interface is configured to carry out processing on at least one data stored in said temporary memory to detect errors and interrupt the storage. data if an error is detected.

15. The data transmission system according to any one of claims 11 to 14, wherein the read interface is configured to read the whole data, to re-read the data or to delete the data.

16. Data transmission system according to any one of claims 11 to 15, in which the read interface is configured to carry out processing on at least one data item stored in said temporary memory in order to extract information on said au minus one data.

17. Data transmission system according to any one of claims 1 to 16, in which each interconnection device comprises an error reporting interface for transmitting operating errors in writing or in reading.

18. Data transmission system according to any one of claims 1 to 17, in which the analysis and filtering module (1 17, 203) comprises:

a reception unit (500) of data frame to be retransmitted,

- a memory unit (507) for storing said data of said frame as and when they are received by the reception unit,

- at least one processing unit (505, 502, 504) for carrying out processing on at least one data item stored in said memory unit, the result of said processing being intended to be used in the management of data retransmission.

19. The data transmission system according to claim 18, in which the analysis and filtering module (1 17, 203) also comprises a control unit (501) for triggering the loading of data from at least one of said receiving unit and the memory unit to said at least one processing unit, said loading and said processing being carried out during the reception of said frame as data is stored in said memory.

20. Data transmission system according to any one of claims 1 to 19, in which each module is produced in a programmable circuit or an integrated circuit specific to an application.

21. Data transmission system according to any one of claims 1 to 20, in which each interconnection device is produced in a programmable circuit or an integrated circuit specific to an application.