EP3864791A1 - Conception de séquence de signal de référence de démodulation (dmrs) de rapport de puissance faible de crête à moyenne (papr) de liaison montante - Google Patents

Conception de séquence de signal de référence de démodulation (dmrs) de rapport de puissance faible de crête à moyenne (papr) de liaison montante

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Publication number
EP3864791A1
EP3864791A1 EP19871391.9A EP19871391A EP3864791A1 EP 3864791 A1 EP3864791 A1 EP 3864791A1 EP 19871391 A EP19871391 A EP 19871391A EP 3864791 A1 EP3864791 A1 EP 3864791A1
Authority
EP
European Patent Office
Prior art keywords
sequences
sequence
papr
binary
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19871391.9A
Other languages
German (de)
English (en)
Other versions
EP3864791A4 (fr
Inventor
Avik SENGUPTA
Alexei Davydov
Gregory V. Morozov
Sameer PAWAR
Guotong Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
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Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP3864791A1 publication Critical patent/EP3864791A1/fr
Publication of EP3864791A4 publication Critical patent/EP3864791A4/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2614—Peak power aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0011—Complementary
    • H04J13/0014—Golay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0055—ZCZ [zero correlation zone]
    • H04J13/0059—CAZAC [constant-amplitude and zero auto-correlation]
    • H04J13/0062—Zadoff-Chu
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/10—Code generation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2035—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers
    • H04L27/2042—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers with more than two phase states
    • H04L27/205—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers with more than two phase states in which the data are represented by the change in phase of the carrier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2602—Signal structure
    • H04L27/261—Details of reference signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2614—Peak power aspects
    • H04L27/262—Reduction thereof by selection of pilot symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
    • H04L27/2636—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0026—Division using four or more dimensions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0003—Two-dimensional division
    • H04L5/0005—Time-frequency
    • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
    • H04L5/001—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT the frequencies being arranged in component carriers

Definitions

  • FIG. 9 illustrates a length 12 CGS sequence with FD-PAPR minimization in accordance with an example
  • FIG. 12 illustrates a frequency domain power profile of Sequence #1
  • FIG. 15 illustrates a table of a length 18 CGS sequence with Max to 2nd Min power ratio minimization in accordance with an example
  • FIG. 23 illustrates a table of a length 18 CGS sequence with a 40 th percentile power maximization in accordance with an example
  • FIG. 31 depicts functionality of a user equipment (UE) operable to generate a demodulation reference signal (DM-RS) having a reduced peak-to-average power ratio (PAPR) in accordance with an example;
  • UE user equipment
  • DM-RS demodulation reference signal
  • PAPR peak-to-average power ratio
  • FIG. 1 provides an example of a 3GPP NR Release 15 frame structure.
  • FIG. 1 illustrates a downlink radio frame structure.
  • a radio frame 100 of a signal used to transmit the data can be configured to have a duration, T/, of 10 milliseconds (ms).
  • T/ duration
  • Each radio frame can be segmented or divided into ten subframes llOi that are each 1 ms long.
  • Each RE l40i can transmit two bits l50a and l50b of information in the case of quadrature phase-shift keying (QPSK) modulation.
  • QPSK quadrature phase-shift keying
  • Other types of modulation may be used, such as 16 quadrature amplitude modulation (QAM) or 64 QAM to transmit a greater number of bits in each RE, or bi-phase shift keying (BPSK) modulation to transmit a lesser number of bits (a single bit) in each RE.
  • QAM quadrature amplitude modulation
  • BPSK bi-phase shift keying
  • the RB can be configured for a downlink transmission from the eNodeB to the UE, or the RB can be configured for an uplink transmission from the UE to the eNodeB.
  • a blockwise repeated sequence can be converted to a frequency domain by using a fast Fourier transform (FFT) operation.
  • FFT fast Fourier transform
  • the FFT operation can applied to a groups of B blocks, i.e., the FFT is taken independently for each k-th group of samples of r(i) satisfying the following condition:
  • the sequence of the above actions can be different depending on implementation.
  • the pi/2 BPSK modulation in the third action the and cyclic extension / puncturing in the second action can be different.
  • the DM-RS signal can be generated using a“generalized modulation” of BPSK and QPSK.
  • One solution to design a low PAPR reference signal is to“follow the data path”, i.e., generate a random binary signal using a Gold code and modulate the random binary signal using pi/2 BPSK before DFT spreading, which can guarantee that the DMRS PAPR is the same as pi/2 BPSK modulation DFT-s-OFDM PUSCH data symbols.
  • the reference signal since the reference signal is designed in the time- domain, the reference signal can have amplitude variations in the frequency domain. This results in potential loss in channel estimation performance depending on the channel statistics (frequency selectivity).
  • the DM-RS signal can be generated using a DFT spread ZC sequence.
  • a DMRS reference signal sequence can be designed using DFT spreading ofZC sequences, such as physical uplink shared channel (PUSCH) data symbols.
  • PUSCH physical uplink shared channel
  • the DM-RS signal can be generated using“block concatenation” of a base sequence(s) design.
  • a base reference signal sequence or sequences can be designed using any of the techniques described herein, as well as computer generated sequences, and generalizing the design to other lengths using block- wise concatenation. Sequences that have low PAPR can be identified while
  • a technique is described for designing a low PAPR DM-RS while simultaneously achieving good channel estimation performance via an almost constant modulus signal in the frequency domain.
  • the DMRS can be generated using Golay sequences.
  • the DRMS can be generated using generalized pi/M modulation of BPSK or QPSK.
  • a value of integer M can be selected to satisfy a good PAPR in the time domain, as well as almost constant modulus envelop in the frequency domain.
  • the DMRS signal can be generated using DFT spreading of ZC sequences.
  • the DMRS signal can be generated using block concatenation of generated base sequences. Further, block wise phase modulations can be applied to achieve low PAPR and almost constant modulation in the frequency domain.
  • new DMRS sequences are specified in Rel.16 NR to reduce the PAPR to the same level as for data symbols, with a consideration of channel estimation performance and cross correlation performance.
  • the corresponding demodulation reference signals can be generated in the frequency domain based on computer generated sequences (CGS) mapped to a QPSK constellation for the case of resource allocation of up to 4 PRBs, or based on extended Zadoff-Chu sequences for larger resource allocations.
  • CCS computer generated sequences
  • the PAPR of the DMRS can be degraded compared to the data.
  • the DMRS base sequence can be generated in the frequency domain according to a first case or a second case.
  • the first case small resource allocation
  • the first case can be for base sequences of length ⁇ 6, 12, 18, 24 ⁇ computer generated sequences mapped to QPSK constellation.
  • the sequence also has a constant modulus and is based on points chosen from the unit circle in an in-phase and quadrature (I/Q) plane.
  • the second case larger resource allocation
  • cyclically extended Zadoff-Chu sequence can be used.
  • the DMRS sequences are generated in the frequency domain i.e., they are not DFT-spread and are constant modulus signals in the frequency domain.
  • the PAPR of the data can become much lower than of the ZC or CGS based DMRS.
  • a sequence design is described herein for the case of PUSCH/PUCCH when pi/2 BPSK modulation and a DFT-s-OFDM waveform are used.
  • the DMRS for pi/2 BPSK modulated PUSCH and PUCCH can be generated in the time domain as a binary sequence, mapped to a pi/2 BPSK constellation and then transmitted after DFT-spreading and OFDM symbol generation, similar to PUSCH/PUCCH.
  • a Type 1 DMRS structure in frequency domain with the following sequence options can be used:
  • mapping of the binary sequence b(i) to pi/2 BPSK sequence d(i) is defined according to the following:
  • frequency domain pulse/spectrum shaping can be applied.
  • time domain spectrum shaping can be applied before DFT-spreading.
  • FIG. 4 illustrates an example of a technique for generating computer generated (CGS) sequences, for the case of resource allocation of less than 5 PRBs.
  • the technique can involve generating all binary sequences of length L, ordering all sequences based on a value of a metric, choosing a first N sequences, initializing a set with a first sequence, and then choosing another sequence.
  • the smallest i.e., length 6 sequence design can be started with. Then based on the sequences designed in this case, the length 12 sequences can be designed such that cross-correlation between chosen length 6 and length 12 sequences are minimized. Similarly, for a length 18 sequence design, cross-correlation between length chosen 6, 12 sequences and length 18 sequences are minimized and for length 24, cross correlation between chosen length 6, 12, 18 sequences and length 24 sequences are minimized.
  • FIGS. 6A and 6B illustrate an example of different cases for f T ( ⁇ ) for sequences with same or different lengths. This can be generalized to sequences of any two lengths. The sequences are then mapped to the subcarriers based on Type 1 DMRS mapping and linear cross-correlation is calculated in the time domain after OFDM symbol generation.
  • the sequence design in this embodiment depends on the values of the metric M l which is chosen.
  • the metric can be chosen to optimize sequence design with respect to improved channel estimation performance and PAPR.
  • FIG. 8 illustrates an exemplary table of a length 6 CGS sequence with FD-PAPR minimization
  • FIG. 9 illustrates an exemplary table of a length 12 CGS sequence with FD-PAPR minimization
  • FIG. 10 illustrates an exemplary table of a length 18 CGS sequence with FD-PAPR minimization
  • FIG. 11 illustrates an exemplary table of a length 24 CGS sequence with FD-PAPR minimization.
  • FIG. 12 illustrates an example of a frequency domain power profile of Sequence #1 and Sequence #5 from a length 12 CGS sequence with maximum-to-second-minimum (Max to 2nd Min) power ratio minimization (shown in FIG. 14).
  • FIG. 13 illustrates an exemplary table of a length 6 CGS sequence with maximum-to-second-0 minimum (Max to 2nd Min) power ratio minimization
  • FIG. 14 illustrates an exemplary table of a length 12 CGS sequence with Max to 2nd Min power ratio minimization
  • FIG. 15 illustrates an exemplary table of a length 18 CGS sequence with Max to 2nd Min power ratio minimization
  • FIG. 16 illustrates an exemplary table of a length 24 CGS sequence with Max to 2nd Min power ratio minimization.
  • FIG. 21 illustrates an exemplary table of a length 6 CGS sequence with a 40 th percentile power maximization
  • FIG. 22 illustrates an exemplary table of a length 12 CGS sequence with a 40 th percentile power maximization
  • FIG. 23 illustrates an exemplary table of a length 18 CGS sequence with a 40 th percentile power maximization
  • FIG. 24 illustrates an exemplary table of a length 24 CGS sequence with a 40 th percentile power maximization.
  • the sequence can be selected to minimize the sum of the elements of signal auto correlation function, as follows: [0097]
  • the cyclic shift which is a multiple of 6 subcarriers can be excluded in the generation procedure to avoid high cross correlation between partially overlapping resource allocation in the frequency domain.
  • the cyclic shift defined by a parameter offset which has value lower the pre-determined threshold f and larger than pre-determined threshold‘n-y’ should not be considered to accommodate propagation delay difference between different UEs in different cells.
  • FIG. 26 illustrates an example of complementary DM-RS sequences d a and db assigned to DM-RS symbols.
  • complementary sequences for the case of two-symbol DMRS i.e., DMRS sequences d a and db occupying two adjacent symbols can be used.
  • complementary sequences a, b, etc. can be used where d a is assigned to front loaded DM-RS and db is assigned to the first additional DM-RS.
  • the pattern can be repeated wherein d a can be assigned to the third DM-RS symbol in the slot and db can be assigned to the fourth DM-RS symbol in the slot.
  • d c and dd can be used in the third and fourth DM-RS symbol respectively.
  • the complimentary DM-RS sequence can be defined to have a sum of auto-correlation function close to the delta function. For example, for two sequence d a and db, the sum of auto-correlation function can be defined as follows:
  • a technique for low PAPR reference signal generation in an uplink is defined, when pi/2 BPSK modulation is used along with DFT-S-OFDM waveform or transform precoding.
  • a binary DMRS sequence can be generated in the time domain, modulated by pi/2 BPSK and transform precoded before an OFDM transmission.
  • Type 1 DMRS can be considered for a PUSCH and a DMRS for PUCCH format 3 and 4 with no comb structure is applicable.
  • a PN sequence can be used for a PUSCH with greater than 4 PRB allocation and a PUCCH with greater than 2 PRB allocation.
  • a technique to generate a CGS sequence is based on a metric design.
  • FD or TD cyclic shifts can be used to generate additional sequences.
  • complementary sequences can be used.
  • non-pi/2 BPSK modulated sequences i.e., sequences differentially modulated with M-PSK can be used.
  • a user equipment operable to generate a demodulation reference signal (DM-RS) having a reduced peak-to- average power ratio (PAPR), as shown in FIG. 30.
  • the UE can comprise one or more processors configured to generate, at the UE, a binary DM-RS sequence in a time domain, as in block 3010.
  • the UE can comprise one or more processors configured to map, at the UE, the binary DM-RS sequence to a pi/2 binary phase shift keying (BPSK) constellation to form a pi/2 BPSK modulated binary DM-RS sequence, as in block 3020.
  • BPSK binary phase shift keying
  • the UE can comprise one or more processors configured to encode, at the UE, the DM-RS having the reduced PAPR for transmission to a Next Generation NodeB (gNB) on a physical uplink shared channel (PUSCH) or a physical uplink control channel (PUCCH), as in block 3130.
  • the UE can comprise a memory interface configured to send to a memory the binary DM-RS sequence.
  • Another example provides at least one machine readable storage medium having instructions 3200 embodied thereon for generating a demodulation reference signal (DM-RS) having a reduced peak-to-average power ratio (PAPR), as shown in FIG. 32.
  • the instructions can be executed on a machine, where the instructions are included on at least one computer readable medium or one non-transitory machine readable storage medium.
  • the instructions when executed by one or more processors of a user equipment (UE) perform: generating, at the UE, a binary DM-RS sequence in a time domain, as in block 3210.
  • the instructions when executed by the one or more processors perform: mapping, at the UE, the binary DM-RS sequence to a pi/2 binary phase shift keying (BPSK) constellation to form a pi/2 BPSK modulated binary DM-RS sequence, as in block 3220.
  • the instructions when executed by the one or more processors perform: performing, at the UE, Discrete Fourier Transform (DFT) spreading and Orthogonal Frequency Division Multiplexing (OFDM) symbol generation on the pi/2 BPSK modulated binary DM-RS sequence to produce the DM-RS having the reduced PAPR, as in block 3230.
  • DFT Discrete Fourier Transform
  • OFDM Orthogonal Frequency Division Multiplexing
  • FIG. 33 illustrates an architecture of a system 3300 of a network in accordance with some embodiments.
  • the system 3300 is shown to include a user equipment (UE) 3301 and a UE 3302.
  • the UEs 3301 and 3302 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but may also comprise any mobile or non-mobile computing device, such as Personal Data Assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets, or any computing device including a wireless communications interface.
  • PDAs Personal Data Assistants
  • pagers pagers
  • laptop computers desktop computers
  • wireless handsets wireless handsets
  • any of the UEs 3301 and 3302 can comprise an Internet of Things (IoT) UE, which can comprise a network access layer designed for low-power IoT applications utilizing short-lived UE connections.
  • IoT UE can utilize
  • the UEs 3301 and 3302 may be configured to connect, e.g., communicatively couple, with a radio access network (RAN) 3310—
  • the RAN 3310 may be, for example, an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN), aNextGen RAN (NG RAN), or some other type of RAN.
  • UMTS Evolved Universal Mobile Telecommunications System
  • E-UTRAN Evolved Universal Mobile Telecommunications System
  • NG RAN NextGen RAN
  • the UE 3302 is shown to be configured to access an access point (AP) 3306 via connection 3307.
  • the connection 3307 can comprise a local wireless connection, such as a connection consistent with any IEEE 3402.15 protocol, wherein the AP 3306 would comprise a wireless fidelity (WiFi®) router.
  • WiFi® wireless fidelity
  • the AP 3306 is shown to be connected to the Internet without connecting to the core network of the wireless system (described in further detail below).
  • the RAN 3310 may include one or more RAN nodes for providing macrocells, e.g., macro RAN node 3311, and one or more RAN nodes for providing femtocells or picocells (e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells), e.g., low power (LP) RAN node 3312.
  • macro RAN node 3311 e.g., macro RAN node 3311
  • femtocells or picocells e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells
  • LP low power
  • any of the RAN nodes 3311 and 3312 can terminate the air interface protocol and can be the first point of contact for the UEs 3301 and 3302.
  • any of the RAN nodes 3311 and 3312 can fulfill various logical functions for the RAN 3310 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.
  • RNC radio network controller
  • the UEs 3301 and 3302 can be configured to communicate using Orthogonal Frequency-Division Multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 3311 and 3312 over a multi carrier communication channel in accordance various communication techniques, such as, but not limited to, an Orthogonal Frequency-Division Multiple Access (OFDMA) communication technique (e.g., for downlink communications) or a Single Carrier Frequency Division Multiple Access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), although the scope of the embodiments is not limited in this respect.
  • OFDM signals can comprise a plurality of orthogonal subcarriers.
  • a downlink resource grid can be used for downlink transmissions from any of the RAN nodes 3311 and 3312 to the UEs 3301 and 3302, while uplink transmissions can utilize similar techniques.
  • the grid can be a time- frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane
  • Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively.
  • the duration of the resource grid in the time domain corresponds to one slot in a radio frame.
  • the smallest time- frequency unit in a resource grid is denoted as a resource element.
  • Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements.
  • Each resource block comprises a collection of resource elements; in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated. There are several different physical downlink channels that are conveyed using such resource blocks.
  • the physical downlink shared channel may carry user data and higher-layer signaling to the UEs 3301 and 3302.
  • the physical downlink control channel (PDCCH) may carry information about the transport format and resource allocations related to the PDSCH channel, among other things. It may also inform the UEs 3301 and 3302 about the transport format, resource allocation, and H-ARQ (Hybrid Automatic Repeat Request) information related to the uplink shared channel.
  • downlink scheduling (assigning control and shared channel resource blocks to the UE 3302 within a cell) may be performed at any of the RAN nodes 3311 and 3312 based on channel quality information fed back from any of the UEs 3301 and 3302.
  • the downlink resource assignment information may be sent on the PDCCH used for (e.g., assigned to) each of the UEs 3301 and 3302.
  • the PDCCH may use control channel elements (CCEs) to convey the control information.
  • CCEs control channel elements
  • the PDCCH complex-valued symbols may first be organized into quadruplets, which may then be permuted using a sub-block interleaver for rate matching.
  • Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as resource element groups (REGs).
  • RAGs resource element groups
  • QPSK Quadrature Phase Shift Keying
  • the PDCCH can be transmitted using one or more CCEs, depending on the size of the downlink control information (DCI) and the channel condition.
  • DCI downlink control information
  • There can be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L l, 2,
  • Some embodiments may use concepts for resource allocation for control channel information that are an extension of the above-described concepts. For example, some embodiments may utilize an enhanced physical downlink control channel
  • EPDCCH that uses PDSCH resources for control information transmission.
  • the EPDCCH may be transmitted using one or more enhanced the control channel elements (ECCEs). Similar to above, each ECCE may correspond to nine sets of four physical resource elements known as an enhanced resource element groups (EREGs). An ECCE may have other numbers of EREGs in some situations.
  • ECCE enhanced the control channel elements
  • the RAN 3310 is shown to be communicatively coupled to a core network (CN) 3320— via an Sl interface 3313.
  • the CN 3320 may be an evolved packet core (EPC) network, a NextGen Packet Core (NPC) network, or some other type of CN.
  • EPC evolved packet core
  • NPC NextGen Packet Core
  • the Sl interface 3313 is split into two parts: the Sl-U interface 3314, which carries traffic data between the RAN nodes 3311 and 3312 and the serving gateway (S-GW) 3322, and the Sl-mobility management entity (MME) interface 3315, which is a signaling interface between the RAN nodes 3311 and 3312 and MMEs 3321.
  • S-GW serving gateway
  • MME Sl-mobility management entity
  • the CN 3320 comprises the MMEs 3321, the S-GW 3322, the Packet Data Network (PDN) Gateway (P-GW) 3323, and a home subscriber server (HSS) 3324.
  • the MMEs 3321 may be similar in function to the control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN).
  • GPRS General Packet Radio Service
  • the MMEs 3321 may manage mobility aspects in access such as gateway selection and tracking area list management.
  • the HSS 3324 may comprise a database for network users, including subscription-related information to support the network entities’ handling of
  • the CN 3320 may comprise one or several HSSs 3324, depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc.
  • the HSS 3324 can provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, etc.
  • the S-GW 3322 may terminate the Sl interface 3313 towards the RAN 3310, and routes data packets between the RAN 3310 and the CN 3320.
  • the S-GW may terminate the Sl interface 3313 towards the RAN 3310, and routes data packets between the RAN 3310 and the CN 3320.
  • the S-GW may terminate the Sl interface 3313 towards the RAN 3310, and routes data packets between the RAN 3310 and the CN 3320.
  • the S-GW 3322 may terminate the Sl interface 3313 towards the RAN 3310, and routes data packets between the RAN 3310 and the CN 3320.
  • the S-GW may terminate the Sl interface 3313 towards the RAN 3310, and routes data packets between the RAN 3310 and the CN 3320.
  • 3322 may be a local mobility anchor point for inter-RAN node handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement.
  • the P-GW 3323 may terminate an SGi interface toward a PDN.
  • the P-GW may terminate an SGi interface toward a PDN.
  • the 3323 may route data packets between the EPC network 3323 and external networks such as a network including the application server 3330 (alternatively referred to as application function (AF)) via an Internet Protocol (IP) interface 3325.
  • the application server 3330 may be an element offering applications that use IP bearer resources with the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.).
  • PS Packet Services
  • LTE PS data services etc.
  • the P-GW 3323 is shown to be communicatively coupled to an application server 3330 via an IP communications interface 3325.
  • the application server 3330 can also be configured to support one or more communication services (e.g., Voice over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 3301 and 3302 via the CN 3320.
  • VoIP Voice over-Internet Protocol
  • PTT sessions PTT sessions
  • group communication sessions social networking services, etc.
  • the P-GW 3323 may further be a node for policy enforcement and charging data collection.
  • Policy and Charging Enforcement Function (PCRF) 3326 is the policy and charging control element of the CN 3320.
  • PCRF Policy and Charging Enforcement Function
  • HPLMN Home Public Land Mobile Network
  • IP-CAN Internet Protocol Connectivity Access Network
  • HPLMN Home Public Land Mobile Network
  • V-PCRF Visited PCRF
  • VPLMN Visited Public Land Mobile Network
  • the PCRF 3326 may be communicatively coupled to the application server 3330 via the P-GW 3323.
  • the application server 3330 may signal the PCRF 3326 to indicate a new service flow and select the appropriate Quality of Service (QoS) and charging parameters.
  • the PCRF 3326 may provision this rule into a Policy and Charging Enforcement Function (PCEF) (not shown) with the appropriate traffic flow template (TFT) and QoS class of identifier (QCI), which commences the QoS and charging as specified by the application server 3330.
  • PCEF Policy and Charging Enforcement Function
  • TFT traffic flow template
  • QCI QoS class of identifier
  • FIG. 34 illustrates example components of a device 1100 in accordance with some embodiments.
  • the device 1100 may include application circuitry 3402, baseband circuitry 3404, Radio Frequency (RF) circuitry 3406, front-end module (FEM) circuitry 3408, one or more antennas 3410, and power management circuitry (PMC) 3412 coupled together at least as shown.
  • the components of the illustrated device 1100 may be included in a UE or a RAN node.
  • the device 1100 may include less elements (e.g., a RAN node may not utilize application circuitry 3402, and instead include a processor/controller to process IP data received from an EPC).
  • the device 1100 may include additional elements such as, for example, memory /storage, display, camera, sensor, or input/output (I/O) interface.
  • additional elements such as, for example, memory /storage, display, camera, sensor, or input/output (I/O) interface.
  • the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).
  • C-RAN Cloud-RAN
  • the application circuitry 3402 may include one or more application processors.
  • the application circuitry 3402 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
  • the processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.).
  • the processors may be coupled with or may include memory /storage and may be configured to execute instructions stored in the memory /storage to enable various applications or operating systems to run on the device 1100.
  • processors of application circuitry 3402 may process IP data packets received from an EPC.
  • the baseband circuitry 3404 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
  • the baseband circuitry 3404 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 3406 and to generate baseband signals for a transmit signal path of the RF circuitry 3406.
  • Baseband processing circuity 3404 may interface with the application circuitry 3402 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 3406.
  • the baseband circuitry 3404 may include a third generation (3G) baseband processor 3404a, a fourth generation (4G) baseband processor 3404b, a fifth generation (5G) baseband processor 3404c, or other baseband processor(s) 3404d for other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), sixth generation (6G), etc.).
  • the baseband circuitry 3404 e.g., one or more of baseband processors 3404a-d
  • some or all of the functionality of baseband processors 3404a-d may be included in modules stored in the memory 3404g and executed via a Central Processing Unit (CPU) 3404e.
  • CPU Central Processing Unit
  • modulation/demodulation circuitry of the baseband circuitry 3404 may include Fast- Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality.
  • FFT Fast- Fourier Transform
  • encoding/decoding circuitry of the baseband circuitry 3404 may include convolution, tail-biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality.
  • LDPC Low Density Parity Check
  • the baseband circuitry 3404 may include one or more audio digital signal processor(s) (DSP) 3404f.
  • the audio DSP(s) 3404f may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments.
  • Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments.
  • some or all of the constituent components of the baseband circuitry 3404 and the application circuitry 3402 may be implemented together such as, for example, on a system on a chip (SOC).
  • SOC system on a chip
  • the baseband circuitry 3404 may provide for communication compatible with one or more radio technologies.
  • the baseband circuitry 3404 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN).
  • EUTRAN evolved universal terrestrial radio access network
  • WMAN wireless metropolitan area networks
  • WLAN wireless local area network
  • WPAN wireless personal area network
  • multi-mode baseband circuitry Embodiments in which the baseband circuitry 3404 is configured to support radio communications of more than one wireless protocol.
  • RF circuitry 3406 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium.
  • the RF circuitry 3406 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network.
  • RF circuitry 3406 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 3408 and provide baseband signals to the baseband circuitry 3404.
  • RF circuitry 3406 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 3404 and provide RF output signals to the FEM circuitry 3408 for transmission.
  • the receive signal path of the RF circuitry 3406 may include mixer circuitry 3406a, amplifier circuitry 3406b and filter circuitry 3406c.
  • the transmit signal path of the RF circuitry 3406 may include filter circuitry 3406c and mixer circuitry 3406a.
  • RF circuitry 3406 may also include synthesizer circuitry 3406d for synthesizing a frequency for use by the mixer circuitry 3406a of the receive signal path and the transmit signal path.
  • the mixer circuitry 3406a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 3408 based on the synthesized frequency provided by synthesizer circuitry 3406d.
  • the amplifier circuitry 3406b may be configured to amplify the down-converted signals and the filter circuitry 3406c may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals.
  • Output baseband signals may be provided to the baseband circuitry 3404 for further processing.
  • the output baseband signals may be zero-frequency baseband signals, although this is not a requirement.
  • mixer circuitry 3406a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.
  • the mixer circuitry 3406a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 3406d to generate RF output signals for the FEM circuitry 3408.
  • the baseband signals may be provided by the baseband circuitry 3404 and may be filtered by filter circuitry 3406c.
  • the mixer circuitry 3406a of the receive signal path and the mixer circuitry 3406a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively.
  • the mixer circuitry 3406a of the receive signal path and the mixer circuitry 3406a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection).
  • the mixer circuitry 3406a of the receive signal path and the mixer circuitry 3406a may be arranged for direct downconversion and direct upconversion, respectively.
  • the mixer circuitry 3406a of the receive signal path and the mixer circuitry 3406a of the transmit signal path may be configured for super-heterodyne operation.
  • the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect.
  • the output baseband signals and the input baseband signals may be digital baseband signals.
  • the RF circuitry 3406 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 3404 may include a digital baseband interface to communicate with the RF circuitry 3406.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the
  • the synthesizer circuitry 3406d may be a fractional-N synthesizer or a fractional N/N+l synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable.
  • synthesizer circuitry 3406d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.
  • the synthesizer circuitry 3406d may be configured to synthesize an output frequency for use by the mixer circuitry 3406a of the RF circuitry 3406 based on a frequency input and a divider control input.
  • the synthesizer circuitry 3406d may be a fractional N/N+l synthesizer.
  • frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement.
  • VCO voltage controlled oscillator
  • Divider control input may be provided by either the baseband circuitry 3404 or the applications processor 3402 depending on the desired output frequency.
  • a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 3402.
  • Synthesizer circuitry 3406d of the RF circuitry 3406 may include a divider, a delay -locked loop (DLL), a multiplexer and a phase accumulator.
  • the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA).
  • the DMD may be configured to divide the input signal by either N or N+l (e.g., based on a carry out) to provide a fractional division ratio.
  • the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop.
  • the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line.
  • Nd is the number of delay elements in the delay line.
  • synthesizer circuitry 3406d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other.
  • the output frequency may be a LO frequency (fLO).
  • the RF circuitry 3406 may include an IQ/polar converter.
  • FEM circuitry 3408 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 3410, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 3406 for further processing.
  • FEM circuitry 3408 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 3406 for transmission by one or more of the one or more antennas 3410.
  • the amplification through the transmit or receive signal paths may be done solely in the RF circuitry 3406, solely in the FEM 3408, or in both the RF circuitry 3406 and the FEM 3408.
  • the FEM circuitry 3408 may include a TX/RX switch to switch between transmit mode and receive mode operation.
  • the FEM circuitry may include a receive signal path and a transmit signal path.
  • the receive signal path of the FEM circuitry may include an LNAto amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 3406).
  • the transmit signal path of the FEM circuitry 3408 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 3406), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 3410).
  • PA power amplifier
  • the PMC 3412 may manage power provided to the baseband circuitry 3404.
  • the PMC 3412 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion.
  • the PMC 3412 may often be included when the device 1100 is capable of being powered by a battery, for example, when the device is included in a UE.
  • the PMC 3412 may increase the power conversion efficiency while providing desirable implementation size and heat dissipation
  • FIG. 34 shows the PMC 3412 coupled only with the baseband circuitry 3404.
  • the PMC 34 35 may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry 3402, RF circuitry 3406, or FEM 3408.
  • the PMC 3412 may control, or otherwise be part of, various power saving mechanisms of the device 1100. For example, if the device 1100 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 1100 may power down for brief intervals of time and thus save power.
  • DRX Discontinuous Reception Mode
  • the device 1100 may transition off to an RRC Idle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc.
  • the device 1100 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again.
  • the device 1100 may not receive data in this state, in order to receive data, it must transition back to RRC Connected state.
  • An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.
  • Processors of the application circuitry 3402 and processors of the baseband circuitry 3404 may be used to execute elements of one or more instances of a protocol stack.
  • processors of the baseband circuitry 3404 may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of the application circuitry 3404 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers).
  • Layer 3 may comprise a radio resource control (RRC) layer, described in further detail below.
  • RRC radio resource control
  • Layer 2 may comprise a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer, described in further detail below.
  • Layer 1 may comprise a physical (PHY) layer of a UE/RAN node, described in further detail below.
  • FIG. 35 illustrates example interfaces of baseband circuitry in accordance with some embodiments.
  • the baseband circuitry 3404 of FIG. 34 may comprise processors 3404a-3404e and a memory 3404g utilized by said processors.
  • Each of the processors 3404a-3404e may include a memory interface, 3504a-3504e, respectively, to send/receive data to/from the memory 3404g.
  • the baseband circuitry 3404 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 3512 (e.g., an interface to send/receive data to/from memory external to the baseband circuitry 3404), an application circuitry interface 3514 (e.g., an interface to send/receive data to/from the application circuitry 3402 of FIG. 34), an RF circuitry interface 3516 (e.g., an interface to send/receive data to/from RF circuitry 3406 of FIG.
  • a memory interface 3512 e.g., an interface to send/receive data to/from memory external to the baseband circuitry 3404
  • an application circuitry interface 3514 e.g., an interface to send/receive data to/from the application circuitry 3402 of FIG. 34
  • an RF circuitry interface 3516 e.g., an interface to send/receive data to/from RF circuitry 3406 of FIG.
  • a wireless hardware connectivity interface 3518 e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components
  • a power management interface 3520 e.g., an interface to send/receive power or control signals to/from the PMC 3412.
  • FIG. 36 provides an example illustration of the wireless device, such as a user equipment (UE), a mobile station (MS), a mobile wireless device, a mobile communication device, a tablet, a handset, or other type of wireless device.
  • the wireless device can include one or more antennas configured to communicate with a node, macro node, low power node (LPN), or, transmission station, such as a base station (BS), an evolved Node B (eNB), a baseband processing unit (BBU), a remote radio head (RRH), a remote radio equipment (RRE), a relay station (RS), a radio equipment (RE), or other type of wireless wide area network (WWAN) access point.
  • BS base station
  • eNB evolved Node B
  • BBU baseband processing unit
  • RRH remote radio head
  • RRE remote radio equipment
  • RS relay station
  • RE radio equipment
  • the wireless device can be configured to communicate using at least one wireless communication standard such as, but not limited to, 3 GPP LTE, WiMAX, High Speed Packet Access (HSPA), Bluetooth, and WiFi.
  • the wireless device can communicate using separate antennas for each wireless communication standard or shared antennas for multiple wireless communication standards.
  • the wireless device can communicate in a wireless local area network (WLAN), a wireless personal area network (WPAN), and/or a WWAN.
  • the wireless device can also comprise a wireless modem.
  • the wireless modem can comprise, for example, a wireless radio transceiver and baseband circuitry (e.g., a baseband processor).
  • the wireless modem can, in one example, modulate signals that the wireless device transmits via the one or more antennas and demodulate signals that the wireless device receives via the one or more antennas.
  • FIG. 36 also provides an illustration of a microphone and one or more speakers that can be used for audio input and output from the wireless device.
  • the display screen can be a liquid crystal display (LCD) screen, or other type of display screen such as an organic light emitting diode (OLED) display.
  • the display screen can be configured as a touch screen.
  • the touch screen can use capacitive, resistive, or another type of touch screen technology.
  • An application processor and a graphics processor can be coupled to internal memory to provide processing and display capabilities.
  • Anon-volatile memory port can also be used to provide data input/output options to a user.
  • the non-volatile memory port can also be used to expand the memory capabilities of the wireless device.
  • a keyboard can be integrated with the wireless device or wirelessly connected to the wireless device to provide additional user input.
  • a virtual keyboard can also be provided using the touch screen.
  • Example 1 includes an apparatus of a user equipment (UE) operable to generate a demodulation reference signal (DM-RS) having a reduced peak-to-average power ratio (PAPR), the apparatus comprising: one or more processors configured to: generate, at the UE, a binary DM-RS sequence in a time domain; map, at the UE, the binary DM-RS sequence to a pi/2 binary phase shift keying (BPSK) constellation to form a pi/2 BPSK modulated binary DM-RS sequence; perform, at the UE, Discrete Fourier Transform (DFT) spreading and Orthogonal Frequency Division Multiplexing (OFDM) symbol generation on the pi/2 BPSK modulated binary DM-RS sequence to produce the DM-RS having the reduced PAPR; and encode, at the UE, the DM-RS having the reduced PAPR for transmission to a Next Generation NodeB (gNB) on a physical uplink shared channel (PUSCH) or a physical uplink control channel (PUCCH); and a memory
  • Example 2 includes the apparatus of Example 1, further comprising a transceiver configured to transmit the DM-RS to the gNB.
  • Example 3 includes the apparatus of any of Examples 1 to 2, wherein the DM- RS is Type 1 DM-RS for the PUSCH, or the DM-RS is for PUCCH format 3 and 4 with no comb structure.
  • Example 4 includes the apparatus of any of Examples 1 to 3, wherein the one or more processors are configured to use computer generated sequences for generation of the DM-RS for resource allocations up to four physical resource blocks (PRBs) for the PUSCH, corresponding to sequences of length 6,12,18,24 and for the PUCCH
  • PRBs physical resource blocks
  • Example 5 includes the apparatus of any of Examples 1 to 4, wherein the one or more processors are configured to use pseudo noise (PN) sequences for generation of the DM-RS for the PUSCH with greater than four PRB allocations and the PUCCH with greater than two PRB allocations.
  • PN pseudo noise
  • FD frequency domain
  • Example 7 includes the apparatus of any of Examples 1 to 6, wherein the one or more processors are configured to use sequences for generation of the DM-RS which are generated using extended or truncated binary Golay sequences.
  • Example 8 includes the apparatus of any of Examples 1 to 7, wherein the one or more processors are configured to generate additional sequences for the DM-RS having the reduced PAPR using one or more of: frequency domain (FD) or time domain (TD) cyclic shifts or TD or FD orthogonal cover codes.
  • FD frequency domain
  • TD time domain
  • Example 9 includes the apparatus of any of Examples 1 to 8, wherein the one or more processors are configured to generate the DM-RS having the reduced PAPR using one or more complementary sequences wherein the complementary sequence(s) are mapped to one or more time domain DM-RS symbols.
  • Example 10 includes the apparatus of any of Examples 1 to 9, wherein the one or more processors are configured to use non-pi/2 BPSK modulated sequences to generate the DM-RS having the reduced PAPR, wherein the non-pi/2 BPSK modulated sequences include sequences differentially modulated with M-phase shift keying (PSK).
  • PSK M-phase shift keying
  • Example 12 includes an apparatus of a user equipment (UE) operable to generate a demodulation reference signal (DM-RS) having a reduced peak-to-average power ratio (PAPR), the apparatus comprising: one or more processors configured to: generate, at the UE, a binary DM-RS sequence in a time domain; apply, at the UE, a pi/2 binary phase shift keying (BPSK) modulation and a Discrete Fourier Transform (DFT) spread Orthogonal Frequency Division Multiplexing (OFDM) waveform or transform precoding on the binary DM-RS sequence to produce the DM-RS having the reduced PAPR; and encode, at the UE, the DM-RS having the reduced PAPR for transmission to a Next Generation NodeB (gNB) on a physical uplink shared channel (PUSCH) or a physical uplink control channel (PUCCH); and a memory interface configured to send to a memory the binary DM-RS sequence.
  • a Next Generation NodeB gNB
  • PUSCH physical uplink
  • Example 13 includes the apparatus of Example 12, wherein the DM-RS is Type 1 DM-RS for the PUSCH, or the DM-RS is for PUCCH format 3 and 4 with no comb structure.
  • Example 14 includes the apparatus of any of Examples 12 to 13, wherein the one or more processors are configured to use computer generated sequences for generation of the DM-RS for resource allocations up to four physical resource blocks (PRBs) for the PUSCH, corresponding to sequences of length 6,12,18,24 and for the PUCCH corresponding to up to two PRB allocations with sequence lengths 12, 24.
  • PRBs physical resource blocks
  • Example 15 includes the apparatus of any of Examples 12 to 14, wherein the one or more processors are configured to use pseudo noise (PN) sequences for generation of the DM-RS for the PUSCH with greater than four PRB allocations and the PUCCH with greater than two PRB allocations.
  • PN pseudo noise
  • FD-PAPR frequency domain PAPR
  • Example 17 includes the apparatus of any of Examples 12 to 16, wherein the one or more processors are configured to generate additional sequences for the DM-RS having the reduced PAPR using frequency domain (FD) or time domain (TD) cyclic shifts.
  • FD frequency domain
  • TD time domain
  • Example 18 includes the apparatus of any of Examples 12 to 17, wherein the one or more processors are configured to generate the DM-RS having the reduced PAPR using one or more complementary sequences.
  • Example 19 includes the apparatus of any of Examples 12 to 18, wherein the one or more processors are configured to use non-pi/2 BPSK modulated sequences to generate the DM-RS having the reduced PAPR, wherein the non-pi/2 BPSK modulated sequences include sequences differentially modulated with M-phase shift keying (PSK).
  • PSK M-phase shift keying
  • Example 20 includes at least one machine readable storage medium having instructions embodied thereon for generating a demodulation reference signal (DM-RS) having a reduced peak-to-average power ratio (PAPR), the instructions when executed by one or more processors at a user equipment (UE) perform the following: generating, at the UE, a binary DM-RS sequence in a time domain; mapping, at the UE, the binary DM- RS sequence to a pi/2 binary phase shift keying (BPSK) constellation to form a pi/2 BPSK modulated binary DM-RS sequence; performing, at the UE, Discrete Fourier Transform (DFT) spreading and Orthogonal Frequency Division Multiplexing (OFDM) symbol generation on the pi/2 BPSK modulated binary DM-RS sequence to produce the DM-RS having the reduced PAPR; and encoding, at the UE, the DM-RS having the reduced PAPR for transmission to a Next Generation NodeB (gNB) on a physical uplink shared channel (PUSCH)
  • Example 21 includes the at least one machine readable storage medium of Example 20, wherein the DM-RS is Type 1 DM-RS for the PUSCH, or the DM-RS is for PUCCH format 3 and 4 with no comb structure.
  • Example 22 includes the at least one machine readable storage medium of any of Examples 20 to 21, further comprising instructions when executed perform the following: using computer generated sequences for generation of the DM-RS for resource allocations up to four physical resource blocks (PRBs) for the PUSCH, corresponding to sequences of length 6,12,18,24 and for the PUCCH corresponding to up to two PRB allocations with sequence lengths 12, 24.
  • PRBs physical resource blocks
  • Example 23 includes the at least one machine readable storage medium of any of Examples 20 to 22, further comprising instructions when executed perform the following: using pseudo noise (PN) sequences for generation of the DM-RS for the PUSCH with greater than four PRB allocations and the PUCCH with greater than two PRB allocations.
  • PN pseudo noise
  • Example 24 includes the at least one machine readable storage medium of any of Examples 20 to 23, further comprising instructions when executed perform the following: generating additional sequences for the DM-RS having the reduced PAPR using frequency domain (FD) or time domain (TD) cyclic shifts.
  • FD frequency domain
  • TD time domain
  • Example 25 includes the at least one machine readable storage medium of any of Examples 20 to 24, further comprising instructions when executed perform the following: using non-pi/2 BPSK modulated sequences to generate the DM-RS having the reduced PAPR, wherein the non-pi/2 BPSK modulated sequences include sequences differentially modulated with M-phase shift keying (PSK).
  • PSK M-phase shift keying
  • Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, compact disc-read-only memory (CD-ROMs), hard drives, non-transitory computer readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques.
  • the computing device may include a processor, a storage medium readable by the processor (including volatile and non volatile memory and/or storage elements), at least one input device, and at least one output device.
  • the volatile and non-volatile memory and/or storage elements may be a random-access memory (RAM), erasable programmable read only memory (EPROM), flash drive, optical drive, magnetic hard drive, solid state drive, or other medium for storing electronic data.
  • the node and wireless device may also include a transceiver module (i.e., transceiver), a counter module (i.e., counter), a processing module (i.e., processor), and/or a clock module (i.e., clock) or timer module (i.e., timer).
  • transceiver module i.e., transceiver
  • a counter module i.e., counter
  • a processing module i.e., processor
  • a clock module i.e., clock
  • timer module i.e., timer
  • selected components of the transceiver module can be located in a cloud radio access network (C-RAN).
  • C-RAN cloud radio access network
  • One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like.
  • API application programming interface
  • Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system.
  • the program(s) may be implemented in assembly or machine language, if desired.
  • the language may be a compiled or interpreted language, and combined with hardware implementations.
  • circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality.
  • ASIC Application Specific Integrated Circuit
  • the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules.
  • circuitry may include logic, at least partially operable in hardware.
  • modules may be implemented as a hardware circuit comprising custom very-large-scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.
  • VLSI very-large-scale integration
  • a module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
  • Modules may also be implemented in software for execution by various types of processors.
  • An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module may not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
  • a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices.
  • operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.
  • the modules may be passive or active, including agents operable to perform desired functions.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

L'invention concerne une technologie pour un équipement utilisateur (UE) utilisable pour générer un signal de référence de démodulation (DM-RS) ayant un rapport puissance crête/puissance moyenne réduit (PAPR). L'UE peut générer une séquence DM-RS binaire dans un domaine temporel. L'UE peut mapper la séquence DM-RS binaire sur une constellation (5) de modulation par déplacement de phase binaire (BPSK) de pi/2 pour former une séquence DM-RS binaire modulée BPSK de pi/2. L'UE peut effectuer un étalement de transformée de Fourier discrète (DFT) et une génération de symbole de multiplexage par répartition orthogonale de la fréquence (OFDM) sur la séquence DM-RS binaire modulée BPSK de pi/2 pour produire le DM-RS ayant le PAPR réduit. L'UE peut coder le DM-RS ayant (10) le PAPR réduit pour une transmission à un nœud b de prochaine génération (gNB) sur un canal partagé de liaison montante physique (PUSCH) ou sur un canal de commande de liaison montante physique (PUCCH).
EP19871391.9A 2018-10-08 2019-10-04 Conception de séquence de signal de référence de démodulation (dmrs) de rapport de puissance faible de crête à moyenne (papr) de liaison montante Pending EP3864791A4 (fr)

Applications Claiming Priority (3)

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US201862742780P 2018-10-08 2018-10-08
US201862755391P 2018-11-02 2018-11-02
PCT/US2019/054849 WO2020076656A1 (fr) 2018-10-08 2019-10-04 Conception de séquence de signal de référence de démodulation (dmrs) de rapport de puissance faible de crête à moyenne (papr) de liaison montante

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EP3864791A1 true EP3864791A1 (fr) 2021-08-18
EP3864791A4 EP3864791A4 (fr) 2022-07-06

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CN115606158A (zh) 2020-05-13 2023-01-13 三星电子株式会社（Kr） 用于应用了dft预编码的下行链路ofdma的方法和装置
EP3962010A1 (fr) * 2020-08-31 2022-03-02 Vestel Elektronik Sanayi ve Ticaret A.S. Réduction du rapport puissance de crête sur puissance moyenne utilisant une structure multi-numérologie
CN113225110B (zh) * 2021-03-18 2022-07-15 中国计量大学上虞高等研究院有限公司 基于改进遗传算法的stsk系统色散矩阵和3-d星座的联合优化方法
US11870629B2 (en) 2021-05-13 2024-01-09 Qualcomm Incorporated Enhanced phase tracking reference signal for digital post distortion assist
US11711186B2 (en) * 2021-05-13 2023-07-25 Qualcomm Incorporated Enhanced demodulation reference signal for digital post distortion assist

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CN101945074B (zh) * 2009-07-04 2014-03-19 中兴通讯股份有限公司 中间导频的发送方法
CN102823166B (zh) * 2010-02-22 2016-06-08 三星电子株式会社 对上行链路参考信号应用序列跳变和正交覆盖码
JP5781694B2 (ja) * 2011-08-16 2015-09-24 エルジー エレクトロニクス インコーポレイティド 無線通信システムにおけるアップリンク参照信号送信方法及び装置
US10945237B2 (en) * 2016-01-04 2021-03-09 Lg Electronics Inc. Method and apparatus for performing uplink transmission for NB-IoT in wireless communication system
US10285174B2 (en) * 2016-01-11 2019-05-07 Qualcomm Incorporated Uplink data channel design for narrowband devices
WO2017155275A1 (fr) * 2016-03-07 2017-09-14 엘지전자 주식회사 Procédé de transmission d'un signal de référence de démodulation dans un système de communication sans fil permettant de prendre en charge un iot à bande étroite, et dispositif associé
WO2018134850A1 (fr) 2017-01-20 2018-07-26 Wisig Networks Private Limited Procédé et système permettant de fournir une couverture de code à des symboles ofdm dans un système utilisateur multiple

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