EP3828655B1 - Method and device for detecting the cause of an error in an electrical circuit - Google Patents

Description

The invention relates to a computer-implemented method and a device for determining the cause of a fault in an electrical circuit using a graph-based circuit diagram simulation model.

During the operation of machine tools, machine failures can often occur where the cause of the failure lies in their electrical circuitry. A failure can be caused, for example, by a short circuit or a broken cable. Due to the complexity of an electrical circuit of a conventional machine tool, however, it is often difficult to determine the exact location and the logical and/or chronological relationship of the cause of the error. Determination of the cause of a fault is usually based on catalogs in which possible causes of faults are listed in connection with fault phenomena observed and/or on a comparison of the faulty machine tool with a model of the same construction. These approaches can be expensive or lead to a long downtime of the affected machine. EP3173991 discloses a system for automatically detecting similarities between faults in a network.

It is therefore the object of the invention to improve the search for the cause of a fault when a fault occurs in an electrical circuit.

1. a) Einlesen eines graphbasierten Schaltplansimulationsmodells der elektrischen Schaltung, wobei im graphbasierten Schaltplansimulationsmodell elektrische Anschlusspunkte von Schaltungskomponenten als Graphknoten und elektrische Verbindungen als Graphkanten modelliert sind,
2. b) Simulieren eines Fehlers in der elektrischen Schaltung mittels des graphbasierten Schaltplansimulationsmodells, wobei
   • eine Graphkante im graphbasierten Schaltplansimulationsmodell hinzugefügt oder entfernt wird,
   • resultierende Zusammenhangskomponenten anhand des modifizierten graphbasierten Schaltplansimulationsmodells und jeweilige Potentialwerte und/oder Phasenwerte der Graphknoten der resultierenden Zusammenhangskomponenten ermittelt werden,
   • und wobei auf Basis der ermittelten Potentialwerte und/oder Phasenwerte der Graphknoten das Schaltverhalten der elektrischen Schaltung durch weiteres Hinzufügen und/oder Entfernen von mindestens einer weiteren Graphkante abgebildet wird,
3. c) Ausgeben von resultierenden Potential- und/oder Phasenwerten vorgegebener Graphknoten als simulierte Ausgangssignale,
4. d) Vergleichen der simulierten Ausgangssignale mit bereitgestellten Referenzausgangssignalen der elektrischen Schaltung und
5. e) Ausgeben der den Fehler entsprechenden Fehlerursache, wenn die simulierten Ausgangssignale mit den Referenzausgangssignalen übereinstimmen.

The object is achieved by the measures described in the independent claims. Advantageous developments of the invention are presented in the dependent claims. According to a first aspect, the invention relates to a computer-implemented method for determining the cause of a fault in an electrical circuit, comprising the method steps:

1. a) reading in a graph-based circuit diagram simulation model of the electrical circuit, wherein electrical connection points of circuit components are modeled as graph nodes and electrical connections as graph edges in the graph-based circuit diagram simulation model,
2. b) simulating an error in the electrical circuit using the graph-based circuit diagram simulation model, wherein
   • a graph edge is added or removed in the graph-based circuit diagram simulation model,
   • resulting connected components are determined using the modified graph-based circuit diagram simulation model and respective potential values and/or phase values of the graph nodes of the resulting connected components,
   • and based on the determined potential values and/or phase values of the graph nodes, the switching behavior of the electrical circuit is mapped by further adding and/or removing at least one further graph edge,
3. c) Outputting the resulting potential and/or phase values of specified graph nodes as simulated output signals,
4. d) comparing the simulated output signals with provided reference output signals of the electrical circuit and
5. e) outputting the error cause corresponding to the error if the simulated output signals match the reference output signals.

It is an advantage of the present invention that a computer-aided simulation of an electrical circuit of a technical system for error analysis can be carried out quickly and with little effort. The graph-based circuit diagram simulation is particularly efficient and enables a switching process of the electrical circuit to be simulated in real time or almost in real time. This enables the coupling of the graph-based simulation model of the electrical circuit with the real hardware control.

In addition, a large number of error causes and their effects can be efficiently simulated, so that, for example, large error databases can be set up. In particular, the graph-based simulation model can easily be generated from existing drawings of the circuit diagram, so that modeling effort can be reduced. The graph-based simulation model also makes it possible, for example, to model and efficiently execute propositional logic for the abstract mapping of control logic.

The computer-aided simulation of a switching process, taking into account an induced error, is carried out on the basis of the graph-based circuit diagram simulation model of the electrical circuit. Starting from one or more output potential levels of the electrical circuit, a switching process can be simulated in a simple manner, namely by adding and/or removing at least one graph edge. The circuit diagram logic is represented in particular by the iterative determination of the potential levels.

In an embodiment of the computer-implemented method, if the simulated output signals deviate from the reference output signals, further errors can be iteratively simulated until the simulated output signals match the reference output signals.

To search for the cause of a fault, a large number of different faults can be simulated, for example, until the simulated output signals match the reference output signals of the faulty electrical circuit.

In one embodiment of the computer-implemented method, at least one attribute can be assigned to a graph edge and/or a graph node.

An attribute can be, for example, a value of the electrical potential or the phase.

In one embodiment of the computer-implemented method, a connection component can be determined using a union-find algorithm.

In particular, the well-known Union-Find algorithm enables an efficient and fast determination of the connected components of the graph, i.e. the graph-based circuit diagram simulation model and thus the determination of potential levels.

In one embodiment of the computer-implemented method, the attributes for potential and phase values of further graph nodes of a connected component can be determined on the basis of an attribute of a graph node of the corresponding connected component.

In one embodiment of the computer-implemented method, a respective output potential value of the read-in graph-based circuit diagram simulation model can be set on the basis of a measured input signal of the electrical circuit in a predetermined normal state of the electrical circuit.

For troubleshooting, it is advantageous to carry out the computer-assisted simulation on the basis of a normal state, preferably a fault-free state, of the electrical circuit.

In one embodiment of the computer-implemented method, the switching logic, the switching contacts and/or the circuit components of the electrical circuit can be hierarchically modeled in the graph-based circuit diagram simulation model.

In particular, a circuit component such as a relay with a coil and switch contacts can be modeled as a set of graph edges and graph nodes. This allows for easy removal and/or addition, for example of circuit components. The switching logic, ie in particular the interdependence of individual circuit components from one another, can in particular be mapped within such a group. For example, switching contacts as conditional graph edges depend on the coil voltage and thus the potential difference between the two graph nodes of the coil connections.

According to a second aspect, the invention relates to a device for determining the cause of a fault in an electrical circuit, comprising at least one processor, the device being set up in such a way that it carries out the steps of the method according to the invention.

In one embodiment, the device can be coupled to a real or simulated controller, with the output signals of the simulation being transmitted to the real or simulated controller.

Efficient graph-based simulation enables, for example, a connection to the real control of a machine tool. For example, a hardware-in-the-loop approach can be implemented. Alternatively, the graph-based simulation can be coupled with a simulated controller. The output signals of the controller can be processed in the simulation.

Furthermore, the invention relates to a computer program product which can be loaded directly into a programmable computer, comprising program code parts which, when the program is executed by a computer, cause the latter to carry out the steps of a method according to the invention.

A computer program product can, for example, be stored on a storage medium such as a memory card, USB stick, CD-ROM, DVD, a non-transitory storage medium or in the form of a downloadable medium File provided or delivered by a server on a network.

Fig. 1

ein Ablaufdiagramm eines computerimplementierten Verfahrens zur Fehlerursachenbestimmung eines Fehlers in einer elektrischen Schaltung;

Fig. 2

eine schematische Darstellung eines graphbasierten Schaltplansimulationsmodell; und

Fig. 3

eine schematische Darstellung einer Vorrichtung zur Fehlerursachenbestimmung eines Fehlers in einer elektrischen Schaltung.

Exemplary embodiments of the invention are shown as examples in the drawings and are explained in more detail with reference to the following description. Show it:

1

a flowchart of a computer-implemented method for determining the cause of a fault in an electrical circuit;

2

a schematic representation of a graph-based circuit diagram simulation model; and

3

a schematic representation of a device for determining the cause of an error in an electrical circuit.

Corresponding parts are provided with the same reference symbols in all figures.

In particular, the following exemplary embodiments only show exemplary implementation options of what such implementations of the teaching according to the invention could look like, since it is impossible and also not expedient or necessary for understanding the invention to name all of these implementation options.

figure 1 shows a flowchart of a computer-implemented method for determining the cause of a fault in a real electrical circuit. For example, there is a defect in the electrical circuitry of a machine tool. The cause and/or location of the defect can be efficiently determined using the computer-implemented method, for example parallel to the operation of the real machine tool.

In the first step S1 of the computer-implemented method, a graph-based circuit diagram simulation model of the electrical circuit is read. The graph-based circuit diagram simulation model can be generated from data from a circuit diagram or an electrical design, for example. The graph-based circuit diagram simulation model maps the circuit diagram of a technical system, e.g. a machine tool.

The graph-based circuit diagram simulation model is preferably configured in such a way that electrical connection points of the circuit components of the real circuit are modeled as graph nodes and electrical connections are modeled as graph edges. For example, graph nodes may be characterized by an electrical potential value, and phase value in the case of alternating current. The graph nodes that are connected via a common graph edge have, in particular, the same phase or potential value.

A potential value or phase value on a circuit component in the real circuit can change, for example, as a result of a switching process or a step of a switching process or as a result of an error that occurs. As explained below, this can be mapped using the graph-based circuit diagram simulation model.

The graph-based circuit diagram simulation model is initially preferably adjusted in such a way that output potential values correspond to a normal state, i.e. error-free state, of the electrical circuit. For example, the output potential values of graph nodes can be adjusted based on measured input signals of the electrical circuit in the normal state.

Attributes can be assigned to the graph edges and/or graph nodes. An attribute can be a potential value or a phase value, for example. For example, based on the respectively assigned attributes, the on a circuit component applied voltage can be determined as the difference between the potential values of the graph nodes of this circuit component related to the same reference ground.

Connected components of the graph are determined using the graph-based circuit diagram simulation model. The determination can preferably be made using the Union Find algorithm. A connected component represents a set of graph nodes, where any two of these graph nodes are connected via a path, i.e. at least one graph edge or a sequence of graph edges. Potential values can be determined for the graph nodes of a connected component. A context component preferably describes a potential level in the circuit diagram.

For example, potential values of the graph nodes of the connection components determined in each case can be determined as output potential values using the graph-based circuit diagram simulation model that has been read in. A switching process or switching behavior of the electrical circuit can be simulated by means of the graph-based circuit diagram simulation model based on these determined connection components and respectively determined output potential values.

In the next step S2, an error in the electrical circuit, such as a cable break at a specified location, is simulated using the graph-based circuit diagram simulation model. In other words, an error in the electrical circuit is modeled and a switching behavior of the electrical circuit is simulated taking this error into account.

To do this, the error is modeled by deleting an existing graph edge and/or saving or adding a new graph edge in the graph-based circuit diagram simulation model. For example, a broken cable can be modeled by removing a graph edge. A short circuit can be done, for example, by adding an additional graph edge be modeled. In this way, the graph-based circuit diagram simulation model is modified for fault simulation. Further steps are then performed based on this modified graph-based circuit diagram simulation model.

Then, using the modified graph-based circuit diagram simulation model, connected components are calculated using the Union-Find algorithm. These resulting connected components result in particular from the modification of the circuit diagram simulation model. Potential values and/or phase values of the graph nodes of these connected components are determined for these newly calculated connected components. The switching behavior or the switching logic of the electrical circuit is evaluated on the basis of the determined potential values and/or phase values of the graph nodes, with at least one further graph edge being added or deleted.

For example, for the opening of a switching contact by the switching logic, e.g. e.g. a make contact of a pick-up relay or a break contact of a drop-out relay, a graph edge can be added in the graph-based circuit diagram simulation model. The integration of the switching logic in the simulation can be done via logical building blocks that add and remove graph edges depending on potential levels at other points in the graph, e.g. to simulate the behavior of a contactor. Since these are simple logic modules, the speed of the simulation is not affected.

The potential values of the graph nodes of a connected component can all have the same potential value, for example. In other words, provided at least one graph node of a connected component has a potential value as an attribute and all other graph nodes of the connected component have either no or the same potential value as this graph node and, if present, the same phase value as this graph node as an attribute, defines the attribute of the potential value of this graph node and, if present, the attribute of the phase value of this graph node, the corresponding potential values and possibly the phase values of the respective connected component, ie all nodes of the respective connected component. If no graph node of a connected component has a potential value as an attribute, the potential and phase value attributes of all graph nodes of the connected component remain undefined. If the potential value and, if applicable, the phase value are defined by two different graph nodes of a connected component and the potential values or, if applicable, the phase values differ, there is an electrical short circuit in the connected component. The short circuit between these two graph nodes is output together with the potential and, if available, the phase values of these graph nodes.

The respective attribute values for potential and phase values of all graph nodes of the connected component or the "undefined" property can be output.

The circuit logic is simulated in particular iteratively, i.e. after a modification of the graph-based circuit diagram simulation model, the connection components are determined, then the potential values of the graph nodes are determined and, depending on the potential values, a switching process is mapped by adding or deleting graph edges until the potential and if necessary, phase values, and thus the states of the conditional graph edges dependent on the switching logic, no longer change.

In other words, during the simulation of the switching process, potential values and phase values of the graph nodes become iterative determined and the switching logic executed until a stable potential level is reached. The resulting graph, ie the resulting graph-based circuit diagram simulation model, is output.

In order to be able to map the real behavior of the technical system, the simulation is preferably carried out with a real controller of the technical system (hardware-in-the-loop), with a model of the controller (model-in-the-loop) or with a copy the control software, which, however, is not executed on the real hardware of the control (software-in-the-loop). Thus, the graph-based circuit diagram simulation model receives the output signals from the controller and returns the simulated input signals to the controller.

In the next step S3, the iteratively determined potential or phase values are output as simulated output signals for predetermined graph nodes of the resulting graph-based circuit diagram simulation model.

In the next step S4, these simulated output signals are compared with provided reference output signals of the real electrical circuit. The reference output signals are preferably measured on the faulty circuit. In other words, a faulty actual state of the electrical circuit of the technical system can be measured using a real controller. The measured output signals of the electrical circuit can be provided as reference output signals.

If the reference output signals match the simulated output signals at least partially, ie for example within a specified tolerance range, a cause of the error is output in step S5. The cause of the error is derived from the respective simulated error. For example, a technician can be given the location and cause "cable break" or "short circuit" of the error. If the reference output signals do not match the simulated output signals or the match is outside of the specified tolerance range, at least one further error can be simulated, see step S6. The search for the cause of the error can therefore be carried out iteratively, with the graph-based circuit diagram simulation model being modified accordingly for the simulation of a further error. A result of the previous simulation can, for example, provide information for deriving the next fault to be tested.

The search for the cause of the error is therefore carried out iteratively until the simulated output signals match the reference signals. The graph-based approach enables a quick iteration of different error causes.

figure 2 shows a schematic representation of a visualization of a graph-based circuit diagram simulation model SM of an electrical circuit. In particular, the electrical circuit can be mapped as an undirected graph.

The switching logic, the switching contacts and/or the circuit components are preferably hierarchically modeled in the graph-based circuit diagram simulation model SM. The structure of the graph-based circuit diagram simulation model SM is shown here as an example. Graphic edges 10 can be added and/or deleted in order to depict the circuit logic of a circuit diagram in the computer-aided simulation. For example, the logic of a switch can be modeled by adding or deleting at least one graph edge 10.

The electrical connection points of circuit components are modeled as graph nodes 20 and electrical connections, such as cables or conductor tracks, as graph edges 10 . Graph nodes 20 can be of the source 20' type, branch type, or port type. A graph node 20 can have a potential and be assigned phase value. In particular, the sources 20' can determine the potential and/or phase value.

Physical or electrical connections between the graph nodes 20 are modeled with the graph edges 10 . Accordingly, graph nodes 20 connected by a graph edge 10 have the same phase and potential value. In particular, graph edges 10 can be modeled as conditional graph edges 12 depending on a circuit component. Graph edges 10 can be added or removed. A graph edge 10' is shown, which can be removed, for example, to simulate an error.

Graph nodes 20 and graph edges 10, 12 can be grouped to map electrical circuit components 30, such as a contactor coil or switch contact. An electrical circuit component 30 can in particular comprise more than one of the connection components 50a,..., 50f. The connected components 50a, ..., 50f are each a connected set of graph nodes 20 with a potential and phase value. A connected component 50a, . . . , 50f can be determined in particular by Robert Endre Tarjan's Union-Find algorithm.

An electrical circuit component 30 thus forms a superordinate level in the circuit diagram simulation model. The electrical circuit components 30 can be connected to one another via a logical connection 11 . In particular, such a logical connection 11 is not represented by a graph edge.

figure 3 FIG. 1 shows a schematic representation of a device 100 for determining the cause of a fault in an electrical circuit. The device comprises at least one processor 101 and is set up in such a way that it executes the steps of a method for determining the cause of a fault in an electrical circuit, as described by way of example with reference to FIG. The device 100 can also include a simulation module 102 which is set up in such a way that an error in the electrical circuit is simulated by means of a graph-based circuit diagram simulation model that has been read in. In addition, the device 100 can include an analysis module 103, which is set up in such a way to carry out a comparison of the simulated output signals with provided reference output signals of the electrical circuit in order to determine the cause of the fault. Depending on the result of the comparison, the cause of the error determined thereby can be output via an output module 104, for example. The device 100 can be coupled to a real controller via a connection C, so that a hardware-in-the-loop simulation can be carried out, for example. The invention is defined by the appended claims.

Claims (10)

1. Computer-implemented method for determining the cause of a fault in an electrical circuit, comprising the following process steps:

   a) inputting (S1) of a graph-based circuit diagram simulation model (SM) of the electrical circuit, wherein, in the graph-based circuit diagram simulation model, electrical connection points of circuit components are modelled as graph vertices (20) and electrical connections are modelled as graph edges (10),

   b) simulation (S2) of a fault in the electrical circuit by means of the graph-based circuit diagram simulation model, wherein

   - one graph edge in the graph-based circuit diagram simulation model is added or removed,

   - resulting connected components, and respective potential values and/or phase values of the graph vertices of the resulting connected components, are determined by reference to the modified graph-based circuit diagram simulation model,

   - and wherein, on the basis of the potential values and/or phase values of the graph vertices thus determined, the switching behavior of the electrical circuit is represented by the further addition and/or removal of at least one further graph edge,

   c) outputting (S3) of resulting potential and/or phase values for specified graph vertices in the form of simulated output signals,

   d) comparison (S4) of the simulated output signals with reference output signals supplied for the electrical circuit, and

   e) outputting (S5) of the cause of the fault corresponding to said fault, if the simulated output signals coincide with the reference output signals.
2. Computer-implemented method according to Claim 1, wherein, if the simulated output signals differ from the reference output signals, further faults are simulated in an iterative manner, until the simulated output signals coincide with the reference output signals.
3. Computer-implemented method according to one of the preceding claims, wherein at least one attribute is assigned to one graph edge (10) and/or to one graph vertex (20).
4. Computer-implemented method according to one of the preceding claims, wherein a connected component (50a, ..., 50f) is determined by means of a union-find algorithm.
5. Computer-implemented method according to one of the preceding claims, wherein the attributes for potential and phase values of further graph vertices of a connected component are determined on the basis of one attribute of a graph vertex of the corresponding connected component.
6. Computer-implemented method according to one of the preceding claims, wherein a respective output potential value of the inputted graph-based circuit diagram simulation model is set on the basis of a measured input signal of the electrical circuit in a predefined normal state of said electrical circuit.
7. Computer-implemented method according to one of the preceding claims, wherein the switching logic, the switching contacts and/or the circuit components of the electrical circuit are hierarchically modelled in the graph-based circuit diagram simulation model.
8. Device (100) for determining the cause of a fault in an electrical circuit, comprising at least one processor (101), wherein the device is designed to execute the steps of the method according to one of Claims 1 to 7.
9. Device (100) according to Claim 8, which is coupled to an actual or a simulated controller, wherein the simulation output signals are transmitted to the actual or the simulated controller.
10. Computer program product, comprising program code elements which, during the running of the program by a processor, initiate the execution by the latter of the steps of the method according to one of Claims 1 to 7.

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