EP3782205A1

EP3782205A1 - Optoelectronic device having a diode put under tensile stress by an inverse piezoelectric effect

Info

Publication number: EP3782205A1
Application number: EP19744752.7A
Authority: EP
Inventors: Abdelkader Aliane; Luc Andre; Jean-Louis Ouvrier-Buffet
Original assignee: Commissariat a lEnergie Atomique CEA; Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Current assignee: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date: 2018-04-18
Filing date: 2019-04-15
Publication date: 2021-02-24
Also published as: FR3080489B1; WO2019202250A1; FR3080489A1; CN112055895A; US20210111205A1

Abstract

The invention relates to an optoelectronic device (1) comprising: - at least one diode (2) that has a semiconductor portion (20) in which a PN or PIN junction is formed; - a peripheral conductive layer (40) that extends in the main plane in such a way as to surround the semiconductor portion (20); - a peripheral piezoelectric portion (30) that extends in the main plane in such a way as to surround the semiconductor portion (20); - a first polarizing electric circuit (30) capable of generating an electric field in the peripheral piezoelectric portion (30) by applying an electric potential at least to the peripheral conductive layer (40) so as to induce a deformation of the peripheral piezoelectric portion (30) in the direction of the main plane, thus causing a tensile deformation of the semiconductor portion (20) in the main plane.

Description

OPTOELECTRONIC DEVICE WITH TENSION DIODE BY INVERSE PIEZOELECTRIC EFFECT

TECHNICAL AREA

[001] The field of the invention is that of optoelectronic devices comprising at least one diode made of a semiconductor compound strained in tension. The invention finds an application particularly in the field of the detection of a light radiation belonging for example to the near infrared, the diode or diodes of the optoelectronic device can then be made of germanium stress-stressed.

STATE OF THE PRIOR ART

In various microelectronic or optoelectronic applications, it may be advantageous to use a layer of a crystalline semiconductor compound, preferably monocrystalline, having a mechanical stress in tension. This is the case in particular of certain light sources whose material of the emissive layer presents, except constraint, a structure of bands of indirect energy, the structure of bands being then made direct by the application of a stress in tension sufficient. The crystalline semiconductor compound may be a compound based on germanium, for example germanium, germanium tin, or even silicon germanium.

[003] Thus, the document US2014 / 0291682 describes an avalanche photodiode whose absorption semiconductor layer is made of germanium strained in tension. The photodiode is then adapted to absorb light radiation up to a cut-off wavelength greater than issonm, which is the absorption cut-off wavelength of the relaxed germanium. For this, the germanium layer is coated with a stressing layer formed of a stack of sublayers of silicon nitride, silicon oxide and amorphous silicon. However, this photodiode has the particular disadvantage of being obtained by using engineering techniques of the mechanical stress by deposition of a stack of thin layers, which can make the manufacturing process complex.

[004] EP3151265 discloses an optoelectronic device with a diode having a voltage-constrained semiconductor layer and made of germanium. The semiconductor layer has been tensioned here by a prior localized structuring of the layer, then by suspending the structured layer above a substrate, followed by bonding to the latter by direct bonding. A consolidation annealing is finally implemented to improve the mechanical strength of the structured layer bonded bonded to the substrate. However, this optoelectronic device has the disadvantage of being obtained by a relatively complex manufacturing process. In addition, as in the previous document, controlling the value of the voltage stress actually experienced by the semiconductor layer can be particularly difficult.

[005] There is therefore a need for an optoelectronic device whose value of the mechanical stress in tension undergone by the diode (s) is controlled more simply and more precisely. There is also a need to have such an optoelectronic device capable of having a small footprint and a high spatial resolution when it comprises a matrix of diodes, and can be obtained by a simplified manufacturing process.

STATEMENT OF THE INVENTION

The invention aims to remedy at least in part the disadvantages of the prior art, and more particularly to provide an optoelectronic device having one or more diodes that can be actively tensioned. It also aims to provide an optoelectronic device with a small footprint, and can be obtained by a simplified manufacturing process. It also aims to provide an optoelectronic device comprising a matrix of high spatial resolution diodes.

[007] For this purpose, the object of the invention is an optoelectronic device comprising: at least one diode, comprising a semiconductor portion having:

A first face and a second opposite face, substantially parallel to a main plane, and connected to one another by a lateral edge, and

• a PN or PIN junction formed by:

^■ a first region doped to a first conductivity type, and

^■ a second region doped to a second conductivity type opposite the first type extending from the lateral edge;

a peripheral conductive layer, made of at least one electrically conductive material, extending along the main plane in contact with the second doped region so as to surround the semiconductor portion;

a peripheral piezoelectric portion, made of at least one piezoelectric material, extending in the main plane in contact with the peripheral conductive layer so as to surround the semiconductor portion; a first electrical polarization circuit of the peripheral piezoelectric portion, adapted to generate an electric field in the peripheral piezoelectric portion by applying an electrical potential to at least the peripheral conductive layer, so as to induce a deformation of the peripheral piezoelectric portion oriented according to the main plane then causing a voltage deformation of the semiconductor portion along the main plane.

[008] Some preferred but non-limiting aspects of this optoelectronic device are as follows.

[009] Preferably, the peripheral conductive layer and the peripheral piezoelectric portion surround the semiconductor portion continuously.

Preferably, the peripheral conductive layer completely covers the lateral edge of the semiconductor portion along an axis orthogonal to the main plane, and the peripheral piezoelectric portion completely covers the conductive layer along said orthogonal axis.

Preferably, the lateral edge extends substantially orthogonal to the main plane.

The peripheral piezoelectric portion may have a thickness at least equal to that of the semiconductor portion.

The optoelectronic device may comprise a second electrical circuit for biasing the diode, adapted to apply said electrical potential to the second doped region through the peripheral conductive layer and a different electrical potential to the first doped region.

The first doped portion may extend from the first face and is distant from the side edge.

The diode may comprise:

a PIN junction, the first doped region being surrounded in the main plane and in contact with an unintentionally doped region, or

a PN junction, the first doped region being surrounded in the main plane and in contact with the second doped region.

Preferably, the semiconductor portion is made of germanium.

Preferably, the peripheral piezoelectric portion is made of PZT.

Preferably, the peripheral piezoelectric portion extends along the main plane substantially coplanar with the diode. The optoelectronic device may comprise a matrix of coplanar diodes, whose semiconductor portions are electrically isolated from each other by a peripheral piezoelectric portion extending in the main plane continuously.

The optoelectronic device may comprise a metallization surrounding each semiconductor portion and resting on one end of the peripheral piezoelectric portion opening on the first face or the second face, the first circuit being adapted to apply an electrical potential difference between the metallization and the peripheral conductive layer of each diode, so as to cause a compressive deformation of the peripheral piezoelectric portion along the main plane.

The optoelectronic device may comprise a second peripheral conductive layer arranged so that the peripheral piezoelectric portion is interposed, in the main plane, between the second peripheral conductive layer and the peripheral conductive layer in contact with the semiconductor portion, the first circuit being adapted to apply an electrical potential difference between said peripheral conductive layers, so as to cause a deformation of the peripheral piezoelectric portion in the main plane in a direction opposite to the semiconductor portion.

The invention also relates to a method of manufacturing an optoelectronic device according to any one of the preceding features, comprising at least the following steps:

producing at least the semiconductor portion;

conformal deposition of the peripheral conductive layer on and in contact with the lateral edge of the semiconductor portion;

forming the peripheral piezoelectric portion by depositing a piezoelectric material on and in contact with a face of the peripheral conductive layer opposite to the side edge.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects, objects, advantages and features of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made by reference. in the accompanying drawings in which: FIG. 4A is a partial and schematic cross-sectional view of an optoelectronic device according to a first embodiment in which the optoelectronic device comprises at least one diode;

FIG. 1B is a partial and schematic cross-sectional view of an optoelectronic device according to a second embodiment in which the optoelectronic device comprises a matrix of diodes;

FIGS. 2A and 2B are top, partial and schematic views of variants of the optoelectronic device illustrated in FIG. 11A, of circular shape for one (FIG. 2A) and square for the other (FIG. and FIG. 2C is a top view, partial and schematic, of an optoelectronic device similar to that illustrated in FIG. 2C, comprising a matrix of square diodes;

FIGS. 3A and 3B are partial and schematic views, in cross-section, of an optoelectronic device according to two variants of the second embodiment;

FIGS. 4A to 4N illustrate, schematically and partially, and in cross-sectional view, various steps of a method of manufacturing an optoelectronic device according to the second embodiment similar to that illustrated in FIG.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

In the figures and in the following description, the same references represent identical or similar elements. In addition, the various elements are not represented on the scale so as to favor the clarity of the figures. Moreover, the various embodiments and variants are not exclusive of each other and can be combined with each other. Unless otherwise indicated, the terms "substantially", "about", "of the order of" mean within 10%. In addition, the expression "comprising a" must be understood as "containing at least one", unless otherwise indicated.

The invention relates generally to an optoelectronic device comprising at least one diode, and preferably a matrix of diodes, each comprising a semiconductor portion surrounded, in a main plane of the diode, by a peripheral piezoelectric portion. . The semiconductor portion of the diode is intended to be tensioned as a result of a deformation of the peripheral piezoelectric portion in the main plane of the diode. The peripheral piezoelectric portion is deformed by an inverse piezoelectric effect. The voltage stresses experienced by the semiconductor portion then result in a modification of the optical properties and / or diode electrodes, such as, for example, an enlargement of the spectral range of absorption of light radiation in the case of a photodiode. Stress stressing may also be sufficient to substantially direct the energy band structure of the semiconductor compound, in the case where the semiconductor compound exhibits an indirect band structure when in a relaxed state. The performance of the optoelectronic device can then be improved, especially in the case of a light emitting diode.

By constrained portion is meant a portion made of a crystalline semiconductor compound under mechanical stress or compression, causing deformation of the mesh of its crystal lattice. The portion is constrained in tension when it undergoes a mechanical stress which tends to stretch the meshes of the network in a plane. In the context of the invention, the semiconductor portion is intended to be voltage-stressed in a main plane of the diode. This results in the fact that its mesh parameter, in the main plane, has a so-called effective value greater than its natural value when the semiconductor compound is relaxed (i.e. unconstrained). In the remainder of the description, unless otherwise indicated, the constraint considered is oriented in the main plane of the diode.

The semiconductor compound, then subjected to mechanical stresses in voltage, thus has modified optical and / or electrical properties. In particular, it may have a decreased bandgap energy, especially that associated with the valley G (or direct valley). The bandgap energy can be estimated as a function of the voltage strain, as described in the case of a germanium layer publication by Guilloy et al. entitled Germanium under High Tensile Stress: Nonlinear dependence of direct band gap vs strain, ACS Photonics 2016, 3, 1907-1911. Moreover, the mechanical stress in tension experienced by the semiconductor portion may be sufficient for the energy band structure to become direct.

[0028] By direct band structure or substantially direct is meant that the minimum of energy E C _B, L of the conduction band of the L valley (valley or indirect) is greater than or substantially equal to the minimum energy E _B c, r of the conduction band of the valley G (or direct valley), in other words: DE = E _B C, L - E _B c, r> o. By substantially equal means here that this energy difference is of the order of magnitude or less than kT, where k is the Boltzmann constant and T the temperature of the material. Preferably, the semiconductor portion is made of germanium whose energy band structure is indirect in the relaxed state, in other words DE <0, and becomes direct when it suffers a sufficient voltage strain. As detailed below, the voltage setting of the semiconductor portion is obtained as a result of the deformation of the peripheral piezoelectric portion by inverse piezoelectric effect, in the main plane of the diode. By inverse piezoelectric effect is meant the physical phenomenon of deformation of the crystalline structure of the piezoelectric material, in expansion or compression, in response to the application of an electric field passing therethrough. In a known manner, the field T of the stresses undergone by the piezoelectric material depends on the electric field E and the piezoelectric coefficient e, and the stress tensor [T] is equal to - [e] [E].

[0030] Figure A is a partial and schematic view in cross section, of an optoelectronic device i according to a first embodiment. In this example, the optoelectronic device i comprises at least one germanium photodiode 2 adapted to detect a near infrared light radiation (SWIR, for Short Wavelength IR, corresponding to the spectral range from 0.8 pm to i, About 7pm, even about 2.5pm. As detailed below, the diode 2 is tensioned by dilating the peripheral piezoelectric portion 30 in the main plane of the diode in a direction opposite to the semiconductor portion 20.

For the rest of the description, a three-dimensional direct reference mark (C, U, Z) is defined here, in which the X and Y axes form a plane parallel to the main plane of the diode (s) 2 of the optoelectronic device 1, and where the Z axis is oriented according to the thickness of the semiconductor portion 20.

The optoelectronic device 1 comprises at least one diode 2 PN junction or PIN, the semiconductor portion 20 is surrounded by a peripheral piezoelectric portion 30. It also comprises an electrical bias circuit of the peripheral piezoelectric portion 30 for generating in the first embodiment, a deformation of the peripheral piezoelectric portion 30 in the main plane of the diode 2 and in a direction opposite to the semiconductor portion 20. As a result, the latter undergoes a mechanical stress in the same plane main. It also comprises an electrical circuit for biasing the diode 2.

The semiconductor portion 20 extends along a main plane, here parallel to the XY plane, and has a first face 21 and a second opposite face 22, which are substantially parallel to the XY plane. They are connected to one another by a lateral border 23 which laterally delimits the semiconductor portion 20 in the XY plane. In this example, the first and second faces 21, 22 are substantially planar, so that the semiconductor portion 20 has a substantially uniform thickness. The lateral edge 23 here advantageously extends parallel to the Z axis, that is to say that it is substantially orthogonal to the XY plane. As illustrated in Fig.2A and 2B, the semiconductor portion 20 may have various shapes in the XY plane, for example circular (fig.2A) or square (fig.2B). Other forms are possible.

The semiconductor portion 20 is made based on a crystalline semiconductor compound of interest, which is preferably monocrystalline. By "based on" is meant that the material is an alloy formed of at least the same chemical elements as the semiconductor compound of interest. The semiconductor portion 20 may thus be a layer or a substrate made of the same semiconductor compound of interest and have regions of different types of conductivity (homojunction) so as to form the PN or PIN junction. It may alternatively be a stack of sub-layers of different semiconductor compounds (heterojunction), which are alloys of the semiconductor compound of interest.

In general, the semiconductor compound of interest is advantageously selected germanium-based materials, such as germanium Ge, silicon germanium SiGe, germanium tin GeSn, and silicon germanium tin SiGeSn. Preferably, the semiconductor compound of interest has, in the absence of voltage strain of its crystal lattice, a first value of direct forbidden band energy, and, when it undergoes voltage strain, a second value less than the first value. In this example, the semiconductor portion 20 is derived from a layer made of the same semiconductor compound, namely here in germanium.

The semiconductor portion 20 has a thickness along the Z axis which can be between a few hundred nanometers and a few microns, for example between Ipm and spm approximately. In the case of a photodiode, the thickness is chosen so as to obtain good absorption in the wavelength range of the light radiation to be detected. It has a transverse dimension in the XY plane that can be between a few hundred nanometers and a few tens of microns, for example between 1pm and 1mim approximately.

A PN or PIN junction is formed in the semiconductor portion 20. It is formed by two regions of the semiconductor portion 20 having different conductivity types. More precisely, it comprises a first region 24 doped according to a first type of conductivity, for example of the n type, and a second region 25 doped according to a second type of conductivity opposite to the first type, for example of the p type.

The junction can thus be PN or PIN type. In the examples of FIGS. 1A and 3A, the junction is PIN type, so that the semiconductor portion 20 comprises an intrinsic region 26, that is to say unintentionally doped, which extends between and in contact with the first n-doped region 24 and the second p-doped region. In the example of the Fig.3B, the junction is PN type so that the first n-doped region 24 is surrounded and in contact with the second p-doped region.

The first n-doped region 24 extends here along the Z axis from the first face 21 and is distant from the side edge 23 in the XY plane. It thus forms a doped box n which is flush with the first face 21 and is spaced from a non-zero distance with respect to the lateral edge 23 as well as the second face 22. By flush, it is intended to arrive at the level of, or extends from. The first doped region 24 thus participates in defining the first face 21. It is electrically insulated from the side edge 23. The first region

24 doped n may have a doping that can be between 1.10 ¹⁹ and 1.10 ²⁰ at / crrU approximately.

The second p-doped region 25 extends from the lateral edge 23 in the XY plane, preferably continuously, that is to say it is flush with the lateral edge 23 preferably over the entire periphery of the the semiconducting portion 20. It extends here along the Z axis from the second face 22. It may have a substantially homogeneous thickness along the Z axis, as shown in Fig.iA, and thus flush with a lower zone 23. Alternatively, as illustrated in FIGS. 3A and 3B, the second region

The p-doped element may have a lateral zone that is flush with the entire surface of the lateral edge 23, both along the Z axis and over the entire periphery of the semiconductor portion 20. The second p-doped region 25 may have a doping that can be between 1.10 ¹⁹ and 1.10 ²⁰ at / cms approx. The second p-doped region is preferably overdoped so as to have good ohmic contact with the peripheral conductive layer 40 mentioned below.

The optoelectronic device 1 according to the first embodiment comprises two peripheral conductive layers 4O ₁ , 4O ₂ , concentric. A first conductive peripheral layer 4O ₁ is in contact with the lateral edge 23 of the semiconductor portion 20 and is adapted to participate in the electrical polarization of the diode 2 as well as in the electrical polarization of the peripheral piezoelectric portion 30. The second layer Peripheral conductor 40 ₂ is arranged such that the peripheral piezoelectric portion 30 is interposed, in the XY plane, between the two peripheral conductive layers 40 ₁ , 40 ₂ .

The first peripheral conductive layer 4O ₁ extends along the main plane in contact with the second doped region p so as to surround the semiconductor portion 20. It is therefore in contact with the lateral edge 23 of the semiconductor portion 20 , and more precisely of the second p-doped region 25 which is flush with the lateral edge 23, and thus allows the application of an electric potential V- to the second p-doped region 25. It thus at least partially covers the lateral edge 23, and preferably entirely as illustrated in fig.iA. It surrounds at least part of the semiconductor portion 20, and preferably entirely as illustrated in FIGS. 1B and 1C, so as to participate in making the mechanical stresses in tension undergone by the periphery of the semiconductor portion 20 more homogeneous. the semiconductor portion 20 due to the deformation of the peripheral piezoelectric portion.

The first conductive peripheral layer 4O ₁ is formed of one or more conductive sub-layers, and is made of at least one electrically conductive material, for example TiN. Ti, NiCr, Al, Au, Pt, W, Ni, Cu, Mo etc. It has a thickness preferably substantially constant along its surface area, for example between 1m and 1m. Preferably, it has a height along the Z axis at least equal to the thickness of the semiconductor portion 20, and thus completely covers the lateral edge 23 along the Z axis.

The optoelectronic device 1 comprises a peripheral piezoelectric portion 30, adapted to undergo here a deformation in the main plane of the diode 2 in a direction opposite to the semiconductor portion 20, by inverse piezoelectric effect, thereby causing the formation of mechanical stresses. voltage in the semiconductor portion 20 in the main plane of the diode, that is to say in the XY plane.

The peripheral piezoelectric portion 30 extends along the main plane in contact with the first peripheral conductive layer 4O ₁ so as to surround the semiconductor portion 20. There is therefore physical and electrical contact between the peripheral piezoelectric portion 30 and the first conductive peripheral layer 4O ₁ , which is therefore adapted to apply an electrical potential to the peripheral piezoelectric layer. It thus takes at least partly the first conductive layer 4O device ₁ along the Z axis, and preferably entirely as shown in fig.iA. It surrounds at least part of the semiconductor portion 20, and preferably entirely, as illustrated in FIGS. 1B and 1C, so as to participate in making the tensile mechanical stresses more homogeneous, depending on the periphery of the semiconductor portion 20. by the semiconductor portion 20 due to the deformation of the peripheral piezoelectric portion 30. It thus extends along all or part of the periphery of the semiconductor portion 20. Thus, the first peripheral conductive layer 4O ₁ is interposed, in the XY plane, between the semiconductor portion 20 and the peripheral piezoelectric portion 30.

The peripheral piezoelectric portion 30 is formed of at least one piezoelectric material, preferably of lead zirconate titanate PbZrTiO ₃ (PZT), but other materials may be used, such as BaTiO ₃ , GA1N, ZnO, LiNbO ₃ , Pb (Nb0 ₃ ) ₂ , PbTi0 ₃ , Pb (Mg _0.33 Nb _{0, 66} ) 0 ₃ , Pb (Sc _{o, 5} Ta _0.5 ) O ₃ or any other suitable piezoelectric material. The peripheral piezoelectric portion 30 preferably extends continuously around the semiconductor portion 20, so as to participate in making the mechanical stress stresses experienced by the latter substantially homogeneous, depending on the periphery of the semiconductor portion 20. Preferably, it has a thickness along the Z axis greater than or equal to that of the semiconductor portion 20, so as to participate in making substantially homogeneous, along the Z axis, the mechanical stresses in tension experienced by the semiconductor portion 20.

The optoelectronic device 1 here comprises a second peripheral conductive layer 40 ₂ , preferably made of the same material or materials as for the first peripheral conductive layer 4O ₁ . It extends in contact with an external lateral flank of the peripheral piezoelectric portion 30 so as to surround the latter in the XY plane. Thus, the peripheral piezoelectric portion 30 has an internal lateral flank, oriented towards the semiconductive portion 20 and in contact with the first peripheral conductive layer 4O ₁ , and an external lateral flank, opposite to the internal flank, in contact with the second peripheral conductive layer 4O ₂ .

The optoelectronic device 1 comprises a first electrical polarization circuit of the peripheral piezoelectric portion 30, which electrical polarization makes it possible to cause a deformation of the peripheral piezoelectric portion 30 in the main plane and in a direction opposite to the semiconductor portion 20. For this, the electric circuit comprises metallizations (not shown), in contact with the two peripheral conductive layers 4O ₁ , 40 ₂ , for applying a potential difference to the peripheral piezoelectric portion 30. The metallizations are preferably based on the first face 21, and are in electrical contact with one end of the peripheral conductive layers 4O ₁ , 40 ₂ . They may be studs whose dimensions in the XY plane may be of the same order as their thickness, or may be strips which extend longitudinally in contact with the peripheral conductive layers 4O ₁ , 40 ₂ , preferably over the entire length of that -this. A negative electric potential V- can thus be applied to the first peripheral conductive layer 4O ₁ , and a positive electrical potential Vp + can be applied to the second peripheral conductive layer 40 ₂ .

Thus, in operation, a bias voltage of the peripheral piezoelectric portion 30 is applied via the two peripheral conductive layers 4O ₁ , 40 ₂ , carrying the first to the electrical potential V- and the second to the electric potential. Vp +. An electric field is then generated within the peripheral piezoelectric portion 30 whose field lines extend substantially parallel to the XY plane. Due to the orientation of the peripheral conductive layers 4O ₁ , 4O ₂ along the axis Z along the peripheral piezoelectric portion 30, the generated electric field has a non-zero component in the XY plane, and thus induces a deformation in the XY plane of the peripheral piezoelectric portion 30 by an inverse piezoelectric effect, in a direction opposite to the semiconductor portion 20 (represented by arrows). Insofar as the peripheral piezoelectric portion 30 surrounds the semiconductor portion 20 on the one hand, and there is continuity of material between the peripheral piezoelectric portion 30 and the semiconductor portion 20 in the XY plane on the other hand, the constraints Mechanical forces experienced by the peripheral piezoelectric portion 30 are transmitted in the semiconductor portion 20, so that the semiconductor portion 20 then undergoes mechanical stresses in tension along the XY plane, that is to say along the main plane.

Figure 1B is a partial schematic view, in cross section, of an optoelectronic device 1 according to a second embodiment. In this example, the optoelectronic device 1 comprises a matrix of diodes 2 adjacent in the XY plane and substantially coplanar. The diodes 2 are here germanium photodiodes 2 adapted to detect a light radiation in the near infrared. As detailed below, the voltage setting of the diodes 2 is provided by a compression of the peripheral piezoelectric portion 30, in the main plane of the diode.

The optoelectronic device 1 according to this embodiment differs from that illustrated in FIG. IA essentially in that each diode 2 is associated with a peripheral conductive layer 40 interposed between the semiconductor portion 20 and the peripheral piezoelectric portion 30. The other peripheral conductive layer 40 illustrated in FIG. 1B is that associated with the adjacent diodes 2. Also, the adjacent conductive layers are preferably brought to the same negative electric potential V-. Moreover, the piezoelectric material is chosen from electrically insulating materials, so as to provide electrical insulation between the diodes 2.

It thus comprises a first polarization metallization (not shown) of the peripheral conductive layer 40, preferably resting on the first face 21 of the optoelectronic device 1 and the electrical contact of one end of said peripheral conductive layer 40.

It also comprises, in this example, a second metallization 42 (illustrated in dashed lines in FIG. 2C) of polarization of the peripheral piezoelectric portion 30, preferably resting on the first face 21 and in contact with the piezoelectric material. The second metallization 42 may be a plurality of pads arranged to surround the semiconductor portion 20, or may be a strip which extends so as to continuously surround the semiconductor portion 20. It is preferably located between each adjacent conductive layer 40 in the XY plane. A positive electrical potential Vp + can thus be applied to the peripheral piezoelectric portion 30 via this metallization.

Thus, in operation, a bias voltage is applied to the peripheral piezoelectric portion 30, thereby generating an electric field in the peripheral piezoelectric portion 30 whose field lines extend between the peripheral conductive layer 40 and the second metallization 42. Due to the orientation of the peripheral conductive layer 40 along the peripheral piezoelectric portion 30 along the Z axis, the generated electric field has a non-zero component in the XY plane, and thus induces a compression deformation of the peripheral piezoelectric portion 30 in the XY plane by inverse piezoelectric effect. Insofar as the peripheral piezoelectric portion 30 surrounds the semiconductor portion 20 on the one hand, and there is continuity of material between the peripheral piezoelectric portion 30 and the semiconductor portion 20 in the XY plane on the other hand, the constraints Mechanical forces experienced by the peripheral piezoelectric portion 30 are transmitted in the semiconductor portion 20, so that the semiconductor portion 20 is then subjected to mechanical stresses in tension along the XY plane.

The optoelectronic device 1 according to the first and second embodiments comprises a second electrical bias circuit of the diode or diodes 2, so as to allow the emission or detection of light radiation.

For this, the electrical circuit comprises metallizations (not shown) for biasing the diode or diodes 2 directly or in reverse, depending on the application of emission or detection of the diode. Thus, in the case of a photodiode, a first metallization is located on and in contact with the first n-doped region 24, and adapted to apply a positive electrical potential Vd + to the latter. The application of a negative potential V- to the second p-doped region 25 is effected via the peripheral conductive layer 40 with which it is in contact. Thus, the electric potential applied to the peripheral conductive layer 40 makes it possible both to polarize the peripheral piezoelectric portion 30 to induce a deformation in compression, and to polarize the diode 2 here in reverse.

Figure 2C is a top view, schematic and partial, of an optoelectronic device 1 identical to that shown in Fig.iB, the diodes 2 have a square shape. The diodes 2 are electrically isolated from each other by the peripheral piezoelectric portion 30 which here extends continuously in the XY plane. Each diode 2 comprises a peripheral conductive layer 40 interposed in the XY plane between the semiconductor portion 20 and the peripheral piezoelectric portion 30. The first electrical circuits comprise a metallization 42 (dotted line) of polarization of the peripheral piezoelectric portion 30, which extends longitudinally on the first face 21 around each diode 2. The metallization 42 is brought to a positive electrical potential Vp + and each peripheral conductive layer 40 is brought to a negative electric potential V-, thus making it possible to generate an electric field in the peripheral piezoelectric portion 30 capable of causing the compressive deformation of the latter. Moreover, each first n-doped region 24 is brought to a positive electrical potential Vd +. Thus, each diode 2 is here reverse biased, thereby allowing photodetection of the infrared light radiation. Each peripheral conductive layer 40 participates in polarizing at the same time the peripheral piezoelectric portion 30 as well as the corresponding semiconductor portion 20.

FIG. 3A is a partial and schematic cross-sectional view of a variant of the optoelectronic device 1 according to the second embodiment illustrated in FIG. 11A. The optoelectronic device 1 differs essentially in that the second doped region p has a lateral zone, preferably also overdoped, which is flush with the lateral edge 23 over the entire height thereof along the Z axis, and following the entire periphery of the semiconductor portion 20 in the XY plane. Thus, the polarization of the second p-doped region is improved insofar as the area of the ohmic contact with the peripheral conductive layer 40 is increased. In addition, such a configuration of the PIN junction makes it possible to prevent the space charge area between the n and p doped regions from extending to the lateral edge 23. Thus, the contribution of this zone is limited. (Potentially non-free from trenching defects) in the dark current. This variant also applies to the optoelectronic device 1 according to the first embodiment.

Figure 3B is a partial and schematic cross sectional view of a variant of the optoelectronic device 1 according to the second embodiment illustrated in Fig.3A. The optoelectronic device 1 differs in particular in that the diode 2 has a PN junction and not a PIN junction, as it could also be the case in the first embodiment of fig.iA. Moreover, the second p-doped region 25 may comprise an overdoped zone that is flush with the lateral border 23 and here the second face 22, and a zone with a lower p-doping level, which surrounds the n-doped well. It also differs in that an intermediate conductive layer 44 between the conductive peripheral layer 40 in contact with the semiconductor portion 20 considered and that in contact with the semiconductor portion 20 of a neighboring diode 2. This intermediate conductive layer 44 here extends substantially parallel to the peripheral conductive layer 40 along the Z axis, and surrounds the semiconductor portion 20 in the XY plane. It is brought to the positive electrical potential Vp +. Thus, the electric field generated between the intermediate conductive layer 44 and the peripheral conductive layer 40 essentially comprises a component parallel to the XY plane, thereby improving the compressional deformation intensity of the piezoelectric material, as well as the following deformation homogeneity. the Z axis. The semiconductor portion 20 is then subjected to a voltage stress whose homogeneity along the Z axis is also improved.

The optoelectronic device 1 then has the advantage of allowing the semiconductor portion 20 of the diode or diodes 2 to be energized in an active manner, that is to say by applying a polarization voltage. piezoelectric material. As detailed above, the polarization of the piezoelectric material can induce a deformation of the peripheral piezoelectric portion 30 in the XY plane in a direction opposite to the semiconductor portion 20 (first embodiment illustrated in FIG. IA), or compression deformation. in the XY plane (second embodiment illustrated in Fig.iB). The value of the voltage stress can be controlled in a precise and simplified manner, insofar as it depends essentially on the intensity of the polarization voltage of the piezoelectric material, and not on a strain-strain stressing technology. a stack of thin layers or a structuring of the semiconductor portion 20 followed by a suspension. Thus, an optoelectronic device 1 is obtained whose optical and / or electrical properties can be modified in a controlled manner, that is to say here in an active manner, during the operation of the optoelectronic device 1, by modulating the polarization voltage of the piezoelectric material. It is then possible to broaden the absorption spectral range of the optoelectronic device 1, for example up to a cut-off wavelength greater than 1550 nm in the case of a germanium photodiode 2. It is also possible, particularly in the context of telecom application, to modulate the signal-to-noise ratio associated with the photodiode, by varying the bias voltage of the piezoelectric material.

In addition, the optoelectronic device 1 has a small footprint, insofar as the peripheral piezoelectric portion 30 extends substantially coplanar with the semiconductor portion 20 of the diode or diodes 2. The piezoelectric material essentially covers the edge 23 of the semiconductor portion 20 and preferably does not take the first face 21 and / or the second face 22 of the diode. Such an arrangement of the peripheral piezoelectric portion 30 with respect to the diodes 2 also allows a high spatial density of diodes 2, and therefore a high spatial resolution of the optoelectronic device 1, in the case where the latter comprises a matrix of diodes 2.

By way of example, the optoelectronic device i may comprise a photodiode 2 whose semiconductive portion 20 is circular and made of germanium. The first n-doped region 24 may have a diameter of about 3 μm and the semiconductor portion 20 may have a diameter of about 8 μm. It is bordered by a peripheral piezoelectric portion 30 of PZT with a transverse dimension of approximately 1 μm. A peripheral conductive layer 40 made of TiN is interposed between the peripheral piezoelectric portion 30 and the peripheral conductive layer 40. A numerical simulation study has made it possible to show that a bias voltage of the peripheral piezoelectric portion of about +5 V makes it possible to provoke a deformation of o, 5nm in the XY plane of the semiconductor portion 20. Such a constraint then makes it possible to increase the cut-off wavelength of the germanium voltage to a value greater than issonm.

An example of a method of manufacturing an optoelectronic device 1 according to the second embodiment identical or similar to that illustrated in FIG. 1B is now described with reference to FIGS. 4A to 4N. In this example, the diodes 2 are PIN junction photodiodes made of germanium and are adapted to detect infrared radiation in the SWIR range.

In a first step (FIG. 4A), a first semiconductor sublayer 12.1 of monocrystalline germanium is produced. The first semiconductor sublayer 12.1 is secured to a support layer 10, here made of silicon, via a lower dielectric layer 11, here a silicon oxide. This stack takes the form of a GeOI substrate (for Germanium On Insulator, in English). This stack is preferably made using the method described in the publication of Reboud et al. Structural and optical properties of 200mm germanium-on-insulator (GeOI) substrates for Silicon photonics applications, Proc. SPIE 9367, Silicon Photonics X, 936714 (February 27, 2015). Such a method has the advantage of producing a semiconductor 12.1 semiconductor sublayer having a low level of structural defects such as dislocations. The germanium may be unintentionally doped or doped, for example p-type. The semiconductor sublayer 12.1 may have a thickness of between approximately 1 m and approximately 1 m, for example equal to approximately 300 nm, and may be covered with a protective layer (not shown) in a silicon oxide.

In a next step (FIG. 4B), the first germanium sub-layer 12.1 is doped according to the second type of conductivity, here of the p type, by implantation. ionic of a dopant such as boron. The protective layer, if any, has previously been removed by surface cleaning, and the first germanium sublayer 12.1 may be coated with a layer of preimplantation oxide having a thickness of a few tens of nanometers, for example equal to 2onm. The underlayer 12.1 germanium then has a doping level comprised between 1.10 ¹⁹ and 1.10 ²⁰ at / cm ³ approximately. A diffusion annealing of the dopant may then be carried out under nitrogen for a few minutes to a few hours, for example 1 h, at a temperature which may be between 600 ° C. and 800 ° C., for example equal to 8000 ° C. This step makes it possible to obtain an overdopulation of the germanium sublayer 12.1 improving the ohmic contact between the second p-doped region 25 and the peripheral conductive layer 40.

In a next step (FIG. 4C), a second semiconductor sublayer 12.2 of germanium is produced by epitaxy from the first underlayer 12.1. The two sublayers are intended to form the semiconductor germanium portions of the diode matrix 2. The second sub-layer 12.2 is formed by epitaxy, for example by chemical vapor deposition (CVD), for Chemical Vapor Deposition, in which English) or by any other epitaxial technique. The preimplementation oxide layer, if any, was previously removed by surface cleaning. The second sublayer 12.2 germanium here is intrinsic, that is to say unintentionally doped. It is intended to form the light absorption zone of the diodes 2. Its thickness depends on the wavelength range of the light radiation to be detected in the case of a photodiode. In the context of 2 SWIR photodiodes, the sub-layer 12.2 of intrinsic germanium has a thickness for example between 1pm and 3pm, preferably equal to 1.5 .mu.m.

In a next step (FIG. 4D), localized etching of the semiconductor layer of germanium formed by the two sub-layers is carried out in order to form a continuous trench 14 in the XY plane ensuring the pixelation of the diodes. 2. For this, an upper dielectric layer 13 is preferably previously deposited on the exposed face of the semiconductor layer. The upper dielectric layer 13 may have a thickness of a few tens to a few hundreds of nanometers, for example between 2onm and 300nm approximately, for example equal to about 1oonm. The trench 14 is made by conventional photolithography and etching techniques. A localized area of the upper dielectric layer 13, the second sub-layer 12.2 of intrinsic germanium and at least a portion of the thickness of the first underlayer 12.1 of overdopened germanium is thus etched. A plurality of semiconductor portions 20 made of germanium separated from each other by the continuous trench 14 are thus obtained. The trench 14 is preferably obtained by an anisotropic etching technique, so as to obtain a lateral border 23 of the portions semiconductors 20 substantially plane along the Z axis, and preferably substantially orthogonal to the XY plane. The trench 14 continues has a transverse dimension (width) in the XY plane may be between 300nm and 30 pm, for example between 1pm and 2pm approximately. It extends longitudinally in the XY plane so as to delimit the semiconductor portions 20. The latter may thus have a shape in the XY plane for example circular, oval, polygonal, for example square, or any other shape.

In this example, the first sub-layer 12.1 is etched locally over its entire thickness to lead to the lower dielectric layer 11. Alternatively (not shown), the first sub-layer 12.1 may be etched locally in part, of in order to keep a continuous lower portion of overdoped germanium, in order to increase the ohmic contact area between the second p-doped region and the peripheral conductive layer 40.

To obtain a second p-doped region 25 which has a lateral zone extending along the lateral edge 23 along the Z axis, and on the periphery of the semiconductor portion 20 in the XY plane, as illustrated in FIGS. FIG. 3A and 3B, an additional ion implantation, for example boron, may be performed with a non-zero inclination angle, so as to dope the lateral flank of the semiconductor portions 20.

In a next step (FIG. 4E), a continuous conductive layer 15 is conformally deposited on the exposed surface of the previously obtained structure. The conductive layer is made of at least one electrically conductive material, here in TiN. It can be deposited by chemical vapor deposition (CVD) and continuously covers the lateral edge 23 of the semiconductor portions 20, as well as the upper dielectric layer 13 and here the exposed surface of the lower dielectric layer 11. This continuous conductive layer 15 is intended to form the peripheral conductive layers which extend in contact with the lateral edge 23 in order to ensure the joint polarization of the second p-doped region and the peripheral piezoelectric portion 30. The continuous conductive layer 15 may have a thickness from about 1m to about 1m.

In a next step (FIG. 4F), the peripheral piezoelectric portion 30 is produced. For this purpose, a deposit of a piezoelectric material, for example here PZT, is produced so as to continuously cover the structure obtained. previously and thus to fill the trench 14. The piezoelectric material is then in contact with the continuous conductive layer. It can be deposited by physical vapor deposition (PVD, for Physical Vapor Deposition, in English) or by any other suitable technique. The conductive layer device 40, especially when made of TiN, provides good grip for the piezoelectric material, especially when in PZT. The piezoelectric material is preferably dielectric, thereby providing electrical insulation between the photodiodes 2. An annealing step may be carried out, for example between 300 ° C and 700 ° C, to optimize the piezoelectric properties of the material. A planarization step, for example mechano-chemical (CMP), is then implemented, with stopping on the upper part of the continuous conductive layer.

In a next step (FIG. 4G), zones for ion implantation of dopants are defined in order to form the first n-doped regions 24. For this purpose, a photosensitive resin 16 is deposited, the openings 17 of which are located opposite the semiconductor portion 20. A localized etching of an upper zone of the continuous conductive layer 15 and preferably of a portion of the layer is then carried out. The transverse dimensions, in the XY plane, of the localized etching correspond substantially to that of the first n-doped regions 24 that it is desired to obtain. These transverse dimensions thus depend on those of the semiconductor portion 20, and may be, for example, between 300 nm and 10 μm.

In a next step (FIG. 4H), the first n-doped portions are produced by ion implantation of a dopant such as phosphorus, through the openings 17. The first regions 24 are preferably overdoped, and can thus have a level of doping between 1.10 ¹⁹ and 1.10 ²⁰ at / cnU approximately. The first doped regions 24 thus form n-doped wells delimited in the XY plane and in the -Z direction by the second intrinsic germanium sub-layer 12.2. A resistive contact is thus formed at the interface between the peripheral conductive layer 40 and the intrinsic germanium of the second sublayer 12.2. A diffusion annealing of the dopants can be carried out, for example at a temperature of between 400 ° C. and 700 ° C. for a duration of a few seconds to a few tens of minutes, for example at 600 ° C. for 30 seconds.

In subsequent steps (Fig.41 and 4J), an additional dielectric layer 18 is deposited for the purpose of carrying out the polarization metallizations. For this purpose, the photosensitive resin 16 is removed and then the dielectric layer (FIG. 41) is made, for example made of a silicon oxide or a tetraethyl orthosilicate (TEOS), so as to completely cover the structure obtained. previously. The dielectric layer 18 may have a thickness of between 200 and 200 nm, for example. Then, by photolithography and etching, first through apertures 19.1 are made in the dielectric layer (FIG. 4 _< J) with etch stop on the peripheral conductive layer 40, in order to form the metallizations 41 of polarization of the peripheral conductive layer. . The openings thus open onto an upper zone of the peripheral conductive layer 40 which extends over the upper dielectric layer 13. Second through-openings 19.2 are also produced in order to form polarization metallizations 42 for the peripheral piezoelectric portion 30 and third openings 19.3 for the purpose of forming polarization metallizations 43 of the first n-doped regions 24. The second openings 19.2 may extend longitudinally so as to surround each diode 2 in the XY plane. In other words, each diode 2 is surrounded by a same second opening 19.2 which can extend longitudinally in a continuous or even discontinuous manner. The openings 19.1, 19.2, 19.3 may have transverse dimensions in the XY plane between a few hundred nanometers and a few microns, depending on the dimensions of the diodes 2 and the width of the peripheral piezoelectric portion 30.

In a next step (Fig.4K), the metallizations 41, 42, 43 are made through the through openings 19.1, 19.2, 19.3. The metallizations 41, 42, 43 are made of at least one metallic material, and may be formed of a barrier layer, for example of TiN deposited by CVD, followed by a layer of copper. A planarization step, for example by CMP, is then carried out with etching stop on the protective oxide top layer.

In a next step (FIG. 4L), the mechanical and electrical assembly, also called hybridization, is then carried out of the structure thus obtained at a control chip 3. Hybridization can be carried out by direct bonding. (or adhesion bond molecular bonding, in English) copper / copper type and / or oxide / oxide, or by any other hybridization technique.

In a next step (FIG. 4M), the support layer 10 is advantageously removed from silicon, for example by grinding, and / or by wet etching or plasma etching (FIG. RIE, ICP ...), with etching stop on the lower dielectric layer 11. It is also possible to perform localized etching of the lower dielectric layer 11 as well as the continuous conductive layer, so as to expose a face of the peripheral piezoelectric portion. 30. Thus, the lower dielectric layer 11 ensures the passivation of the semiconductor portion 20.

In a next step (FIG. 4N), it is possible to remove the lower dielectric layer 11 remaining, so as to also expose the second face 22 of the semiconductor portion 20, and then to deposit a dielectric layer 4 at least partially transparent. This layer 4 provides a protection for the diodes 2, the passivation of the second face 22 of the semiconductor portions 20, and can also provide an optical antireflection function when its thickness is a multiple of l / 4h, where l is a length of wave of the light radiation to be detected and n is the refractive index of the material of the antireflection layer. Such a layer 4 may be made of a silicon oxide or nitride, for example SiO ₂ , SiN, Si ₃ N ₄ , or aluminum, for example AlN or Al ₂ O ₃ . Its thickness can be, for example, between 20nm and 200nm approximately.

Thus, this manufacturing method makes it possible to obtain an optoelectronic device 1 comprising a matrix of diodes 2, the semiconductor portions 20 of which can be tensioned actively, that is to say by the application of FIG. a potential difference to the peripheral piezoelectric portion 30 surrounding each diode, causing the deformation thereof. Moreover, the optoelectronic device 1 may have a high spatial resolution, as well as a small bulk, insofar as the peripheral piezoelectric portion 30 extends coplanar with the diodes 2. In addition, the peripheral piezoelectric portion 30 defines, with the diodes 2, a substantially planar optoelectronic structure delimited along the Z axis by two substantially planar faces, which contributes to reducing the bulk of the optoelectronic device 1. Furthermore, the diodes 2 have good optical properties and / or particularly in so far as possible structural defects such as dislocations remain confined essentially in the second p-doped region and not in the intrinsic region 26.

Furthermore, it is advantageous for the first regions 24 to be n-doped and for the second regions 25 to be p-doped in terms of diffusion annealing time. In fact, the boron used for doping p diffuses more slowly than the phosphorus used for doping n. Thus, the diffusion annealing of phosphorus, which requires a short duration, is performed after the boron diffusion annealing, which requires a longer duration.

Specific embodiments have just been described. Various variations and modifications will occur to those skilled in the art.

Claims

An optoelectronic device (1), comprising:

at least one diode (2), comprising a semiconductor portion (20) having:

A first opposite face (21) and a second face (22), substantially parallel to a main plane, and connected to one another by a lateral edge (23), and

• a PN or PIN junction formed by:

^■ a first region (24) doped to a first conductivity type, and

^■ a second region (25) doped to a second conductivity type opposite the first type extending from the side edge (23);

a peripheral conductive layer (40), made of at least one electrically conductive material, extending in the main plane in contact with the second doped region (25) so as to surround the semiconductor portion (20); a peripheral piezoelectric portion (30), made of at least one piezoelectric material, extending in the main plane in contact with the peripheral conductive layer (40) so as to surround the semiconductor portion (20);

a first electrical bias circuit of the peripheral piezoelectric portion (30), adapted to generate an electric field in the peripheral piezoelectric portion (30) by applying an electrical potential to at least the peripheral conductive layer (40), so as to induce a deformation of the peripheral piezoelectric portion (30) oriented along the main plane then causing a voltage deformation of the semiconductor portion (20) along the main plane.

An optoelectronic device (1) according to claim 1, wherein the peripheral conductive layer (40) and the peripheral piezoelectric portion (30) surround the semiconductor portion (20) continuously.

Optoelectronic device (1) according to claim 1 or 2, wherein the peripheral conductive layer (40) completely covers the lateral edge (23) of the semiconductor portion (20) along an axis orthogonal to the main plane, and the piezoelectric portion. peripheral (30) completely covers the peripheral conductive layer (40) along said orthogonal axis.

Optoelectronic device (1) according to any one of claims 1 to 3, wherein the side edge (23) extends substantially orthogonal to the main plane.

5. Optoelectronic device (i) according to any one of claims i to 4, wherein the peripheral piezoelectric portion (30) has a thickness at least equal to that of the semiconductor portion (20).

Optoelectronic device (1) according to any one of claims 1 to 5, comprising a second electrical bias circuit of the diode (2), adapted to apply said electrical potential to the second doped region (25) through the peripheral conductive layer (40) and a different electrical potential to the first doped region

(24) ·

Optoelectronic device (1) according to any one of claims 1 to 6, wherein the first doped portion (24) extends from the first face (21) and is spaced from the side edge (23).

Optoelectronic device (1) according to any one of claims 1 to 7, wherein the diode (2) comprises:

a PIN junction, the first doped region (24) being surrounded in the main plane and in contact with an unintentionally doped region (26), or

a PN junction, the first doped region (24) being surrounded in the main plane and in contact with the second doped region (25).

9. Optoelectronic device (1) according to any one of claims 1 to 8, wherein the semiconductor portion (20) is made of germanium.

Optoelectronic device (1) according to any one of claims 1 to 9, wherein the peripheral piezoelectric portion (30) is made of PZT.

Optoelectronic device (1) according to any one of claims 1 to 10, wherein the peripheral piezoelectric portion (30) extends in the main plane substantially coplanar with the diode (2).

Optoelectronic device (1) according to any one of claims 1 to 11, comprising a matrix of coplanar diodes (2), whose semiconductor portions (20) are electrically insulated from each other by a peripheral piezoelectric portion (30). extending in the main plane continuously.

Optoelectronic device (1) according to claim 12, comprising a metallization (42) surrounding each semiconductor portion (20) and resting on one end of the peripheral piezoelectric portion (30) opening on the first face (21) or the second face (22), the first circuit being adapted to apply a difference of electrical potential between the metallization (42) and the peripheral conductive layer (40) of each diode (2), so as to cause compression deformation of the peripheral piezoelectric portion (30) along the main plane.

14. An optoelectronic device (1) according to any one of claims 1 to 12, comprising a second peripheral conductive layer (40 ₂₎ arranged so that the piezoelectric device portion (30) is interposed, according to the main plane between the second peripheral conductive layer (4O ₂ ) and said peripheral conductive layer (4O ₁ ) in contact with the semiconductor portion (20), the first circuit being adapted to apply an electrical potential difference between said peripheral conductive layers (4O ₁ , 40 ₂ ) , so as to cause a deformation of the peripheral piezoelectric portion (30) in the main plane in a direction opposite to the semiconductor portion (20).

A method of manufacturing an optoelectronic device (1) according to any one of the preceding claims, comprising at least the following steps:

- Realization of at least the semiconductor portion (20);

- conformal deposition of the peripheral conductive layer (40) on and in contact with the side edge (23) of the semiconductor portion (20);

- forming the peripheral piezoelectric portion (30) by depositing a piezoelectric material on and in contact with a face of the conductive layer (40) opposite the side edge (23).