EP3704595A4 - System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network - Google Patents

System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Download PDF

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Publication number
EP3704595A4
EP3704595A4 EP18874782.8A EP18874782A EP3704595A4 EP 3704595 A4 EP3704595 A4 EP 3704595A4 EP 18874782 A EP18874782 A EP 18874782A EP 3704595 A4 EP3704595 A4 EP 3704595A4
Authority
EP
European Patent Office
Prior art keywords
hybrid
interconnection network
configurable computing
computing elements
threading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP18874782.8A
Other languages
German (de)
French (fr)
Other versions
EP3704595A2 (en
Inventor
Tony M. Brewer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority claimed from PCT/US2018/058539 external-priority patent/WO2019089816A2/en
Publication of EP3704595A2 publication Critical patent/EP3704595A2/en
Publication of EP3704595A4 publication Critical patent/EP3704595A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
EP18874782.8A 2017-10-31 2018-10-31 System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Withdrawn EP3704595A4 (en)

Applications Claiming Priority (21)

Application Number Priority Date Filing Date Title
US201762579749P 2017-10-31 2017-10-31
US201862651132P 2018-03-31 2018-03-31
US201862651142P 2018-03-31 2018-03-31
US201862651140P 2018-03-31 2018-03-31
US201862651134P 2018-03-31 2018-03-31
US201862651131P 2018-03-31 2018-03-31
US201862651137P 2018-03-31 2018-03-31
US201862651135P 2018-03-31 2018-03-31
US201862651128P 2018-03-31 2018-03-31
US201862667699P 2018-05-07 2018-05-07
US201862667749P 2018-05-07 2018-05-07
US201862667717P 2018-05-07 2018-05-07
US201862667679P 2018-05-07 2018-05-07
US201862667792P 2018-05-07 2018-05-07
US201862667850P 2018-05-07 2018-05-07
US201862667760P 2018-05-07 2018-05-07
US201862667691P 2018-05-07 2018-05-07
US201862667780P 2018-05-07 2018-05-07
US201862667666P 2018-05-07 2018-05-07
US201862667820P 2018-05-07 2018-05-07
PCT/US2018/058539 WO2019089816A2 (en) 2017-10-31 2018-10-31 System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network

Publications (2)

Publication Number Publication Date
EP3704595A2 EP3704595A2 (en) 2020-09-09
EP3704595A4 true EP3704595A4 (en) 2021-12-22

Family

ID=71894498

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18874782.8A Withdrawn EP3704595A4 (en) 2017-10-31 2018-10-31 System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network

Country Status (2)

Country Link
EP (1) EP3704595A4 (en)
CN (1) CN111602126A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060150184A1 (en) * 2004-12-30 2006-07-06 Hankins Richard A Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
US20130138913A1 (en) * 2006-06-21 2013-05-30 Element Cxi, Llc Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US6766389B2 (en) * 2001-05-18 2004-07-20 Broadcom Corporation System on a chip for networking
WO2003102758A1 (en) * 2002-05-31 2003-12-11 University Of Delaware Method and apparatus for real-time multithreading
US7412588B2 (en) * 2003-07-25 2008-08-12 International Business Machines Corporation Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
US7424698B2 (en) * 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
JP4804829B2 (en) * 2005-08-24 2011-11-02 富士通株式会社 circuit
US7539845B1 (en) * 2006-04-14 2009-05-26 Tilera Corporation Coupling integrated circuits in a parallel processing environment
GB2471067B (en) * 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
GB2519813B (en) * 2013-10-31 2016-03-30 Silicon Tailor Ltd Pipelined configurable processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060150184A1 (en) * 2004-12-30 2006-07-06 Hankins Richard A Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
US20130138913A1 (en) * 2006-06-21 2013-05-30 Element Cxi, Llc Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
EUSTACE PAINKRAS ET AL: "SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 48, no. 8, 2 August 2013 (2013-08-02), pages 1943 - 1953, XP011520795, ISSN: 0018-9200, DOI: 10.1109/JSSC.2013.2259038 *
MELLETTE WILLIAM MAXWELL ET AL: "A Scalable, Partially Configurable Optical Switch for Data Center Networks", JOURNAL OF LIGHTWAVE TECHNOLOGY, IEEE, USA, vol. 35, no. 2, 15 January 2017 (2017-01-15), pages 136 - 144, XP011641222, ISSN: 0733-8724, [retrieved on 20170213], DOI: 10.1109/JLT.2016.2636025 *
See also references of WO2019089816A2 *
ZHANG TAO TAO ZHANG@SJTU EDU CN ET AL: "Buddy SM", ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, ASSOCIATION FOR COMPUTING MACHINERY, US, vol. 12, no. 2, 11 May 2015 (2015-05-11), pages 1 - 23, XP058493527, ISSN: 1544-3566, DOI: 10.1145/2744202 *

Also Published As

Publication number Publication date
CN111602126A (en) 2020-08-28
EP3704595A2 (en) 2020-09-09

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