EP3701276A1

EP3701276A1 - Integrated circuit and asic

Info

Publication number: EP3701276A1
Application number: EP18727717.3A
Authority: EP
Inventors: Stefan BRUCKLACHER; Heiko Fibranz; Roland Johann PEETZ; Thomas Wieja
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2017-06-28
Filing date: 2018-05-16
Publication date: 2020-09-02
Anticipated expiration: 2038-05-16
Also published as: DE102017210851A1; WO2019001836A1; EP3701276B1

Abstract

The invention relates to an integrated circuit (1). The integrated circuit (1) comprises a digital circuit region (10) which comprises a digital circuit (15). The integrated circuit (15) further comprises an analog circuit region (20) which is physically separated from the digital circuit region (10) and which comprises an analog circuit (25). The integrated circuit (1) additionally comprises a control line (S1) for transmitting a control signal (S[1]) from the digital circuit (15) to the analog circuit (25), and the integrated circuit (1) additionally comprises a test analysis unit (12) which is integrated into the digital circuit region (10). The integrated circuit (1) further comprises a test line (T1) which is connected to the control line (S1) in an electrically conductive manner within the analog circuit region (20) and which is connected to the test analysis unit (12) in an electrically conductive manner, wherein the test analysis unit (12) is designed to test the digital value of a signal returned via the test line (T1).

Description

Description title

Integrated circuit and ASIC

The present invention relates to an integrated circuit and an ASIC having such an integrated circuit.

State of the art

Modern integrated circuits such as ASIC consist of both analog and digital circuits. These are each combined into one area and integrated on one chip. Due to the small structures of the semiconductor process, especially in the digital

Circuit part very complex circuits are generated. Around

Typically, special test circuits are integrated, such as scan registers or special self-test circuits, the latter also commonly known as BIST (Build in Seif Test). In the field of digital circuit can be found by almost 100% of manufacturing errors. Also in the field of analog circuit test circuits can be realized. However, the test coverage is not as high as in the area of the digital circuit.

Starting from the digital part, for example, drivers or trim bits in the analog circuit area are controlled by means of control lines. With modern chips, several hundred of these control lines can be present.

In particular, checking the error-free operation of such control lines can be very difficult and can take a long time. This can even lead to the fact that testing the control lines is economically impossible. The problem can be explained by a concrete example. at a bandgap circuit is set by five control lines five associated trim bits for a precisely balanced voltage. For every

Configuration of the trim bits can be measured a corresponding analog voltage. The measurement of this analog voltage typically takes about 2 ms on a tester.

If you want to check the function of the trim bits, you can perform six measurements. For example, in a first measurement all trimming bits are set to "0" and then one bit is always set to "1". This then gives a total test duration of 12 ms. Calculating this, for example, a hundred control lines high, this results in a time of 600 ms, but then estimates a large proportion of the total estimated test time to test an entire chip.

Disclosure of the invention

According to the invention, an integrated circuit is provided. The integrated circuit comprises a digital circuit area, which comprises a digital circuit. Furthermore, the integrated circuit comprises an analog from the digital circuit area spatially separated

Circuit area, which includes an analog circuit. Furthermore, the integrated circuit comprises a control line for transmitting a control signal from the digital circuit to the analog circuit. In addition, the integrated circuit includes a test evaluation unit, which in the digital

Circuit area is integrated. Furthermore, the integrated circuit comprises a test lead which is electrically conductively connected to the control line within the analog circuit area and which is electrically conductive with the test lead

Test evaluation unit is connected, wherein the test evaluation unit is adapted to check a digital value of a fed back via the test line signal.

Preferably, this corresponds to the means of the test line recycled or

traceable signal to the control signal transmitted via the control line or even a modified control signal such as an amplified, delayed or attenuated control signal. Analog and digital circuit areas, which are spatially separated, but in integrated circuit or chip are often referred to as mixed-signal systems or mixed-signal circuits.

The integrated circuit according to the invention has the advantage that a digital test of the digital value of a signal is typically significantly faster than an analog measurement in the analog circuit area. The return of the signal for testing in the digital circuit area thus allows a much faster test of the control lines compared to the analogous measurement of voltage values described by way of example in the introduction. For example, the digital part of a chip can be tested at 50 MHz.

Even in slower applications, such as trimming bit control, where only low speed requirements are required, it is possible to test at 10 MHz, for example, which corresponds to a test time per digital value of 100 ns. This is well below the test time of an analog voltage of 2 ms and thus accounts for only a fraction of the test time. Such numerical examples are only examples and depend inter alia on the semiconductor process, the application or the structure of the integrated circuit or the chip.

Preferably, the control line comprises a first driver with level converter. This allows adaptation, in particular a boost, of the voltage level for corresponding applications in the analog circuit area.

For example, the level of 1.2V can be raised to a consumer voltage of, for example, 3V. The positioning can be both in the analog circuit area, but also alternatively in the digital circuit area.

The control line may also comprise a receiving circuit positioned before the connection to the test line. As a result, this receiving circuit can also be checked by means of the test line. For example, the

Reception circuit be at least one inverter, a Schmitt trigger or other logic circuit.

Advantageously, the test line comprises a second driver with level converter.

In this case, the voltage level can be reduced, for example, so that No overvoltage is generated in the digital circuit area, so that no damage is caused.

In a particular embodiment, the integrated circuit comprises N> 2 control lines for transmitting respective control signals from the digital circuit to the analog circuit, the analog circuit further comprising a data compression circuit configured to compress control signals transmitted over the control lines into a compressed test signal , wherein the test line is electrically conductively connected to the data compression circuit and wherein by means of the test line

compressed test signal is returned to the test evaluation unit for testing the digital value of the test signal. In other words, the compressed test signal is traceable by means of the test line to the test evaluation unit for testing the digital value of the test signal. In other words, the test line for returning the compressed test signal to the test evaluation unit for checking the digital value of the

Test signal formed. Advantageously, the number of returning test lines can thus be significantly reduced. Also the number of drivers with

Level converter can therefore be reduced accordingly. Instead of a doubling of the lines through the test leads is only one more

Test lead needed. The circuit complexity is thereby significantly reduced.

Preferably, the data compression circuit comprises at least one logic gate. This makes data compression particularly easy and efficient.

More preferably, the data compression circuit comprises at least one EXOR gate. The EXOR gate only shows a high level at the output if the two inputs have a different level. Typically, an EXOR gate may be constructed of various logic gates, which are also included in the invention.

In a preferred embodiment, the

Data compression circuit N-1 EXOR gates and 1 <n <N-1, where for n> 2, a first input of the n-th EXOR gate to the output of the (n-1) -th EXOR gate and a second input of the n-th EXOR gate is electrically conductively connected to the (n + 1) - th control line, wherein for n = 1, the first input of the 1-th EXOR gate with the 1-th control line and the second input of the 1 st EXOR gate is electrically conductively connected to the 2 nd control line, and wherein for n = (N-1) the output of the (N-1) th EXOR gate to the test line is further connected to Returning the compressed test signal is connected. This allows an efficient compression as well as a fast, systematic checking of the control lines by means of a simple test scheme. This can be done for example by a

successively raising the control signals to a high level

or a "1" with subsequent reset to the low level or "0". If all control lines are at "0", the test signal at the output of the data compression circuit is also "0". If exactly one arbitrary control signal is set to "1" or has a high level, then the compressed test signal at the output of the data compression circuit is also at "1" or has a high level. Upon successful comparison of these expected digital values by the test evaluation unit, the correct transmission of the control signal and thus the control lines are checked. For this purpose, N + 1 measurements are required, and in addition, the low level can be tested between these measurements.

Advantageously, the analog circuit can have a plurality of R

Comprising data compression circuits with R> 2, where each rth

Data compression circuit, with 1 <r <R, with a plurality of

Control lines electrically conductively connected and is adapted to compress the control signals transmitted via these control lines in an r-tes test signal. With a high number of control lines, for example for N = 150, the compression of the control signals can be time-consuming. Advantageously, by the described grouping, that is a division of the

Control line into individual groups of control lines, the time to

Compression reduces because the compression of the different

Compression units can be done in parallel and each correspondingly only less than N control signals must be compressed. Furthermore, the integrated circuit may comprise a plurality of R test lines, with each rth test line having the rth

Data compression circuit is electrically connected and

compressed rth test signals from the analog circuit to the

Test evaluation unit leads back. In other words, the rth test line is designed to return the rth compressed test signal to a test evaluation unit for testing the digital value of the rth test signal. In this case, for example, a single test evaluation unit can be provided, which checks all test signals, or else a test evaluation unit can be provided per test line. Advantageously, the test signals can thus also be tested in parallel, which reduces the test time, in particular with a high number of control lines.

Furthermore, the invention comprises an application-specific integrated circuit, ASIC, which comprises an integrated circuit according to one of the above embodiments.

Furthermore, the invention comprises a chip on which an integrated circuit or an ASIC according to previous embodiments is integrated.

Advantageous developments of the invention are specified in the subclaims and described in the description.

drawings

Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:

FIG. 1 shows an integrated circuit according to a first embodiment variant,

Figure 2 shows an integrated circuit according to a second embodiment, and

Figure 3 shows an integrated circuit according to a third embodiment.

Embodiments of the invention FIG. 1 shows an integrated circuit 1 according to a first embodiment variant. The integrated circuit 1 in this case comprises a digital circuit area 10 which comprises a digital circuit 1.

Furthermore, the integrated circuit 15 comprises an analog circuit area 20, which comprises an analog circuit 25. The analog circuit area is spatially separated from the digital circuit area 10.

Furthermore, the integrated circuit 1 comprises a control line S1 for transmitting a control signal S [1] from the digital circuit to the analogue circuit

Circuit 25. For this purpose, the control line S1 is electrically conductively connected to the analog circuit 25 and the digital circuit 15. Furthermore, the integrated circuit 1 comprises a test evaluation unit 12, which is integrated in the digital circuit area 10. In this embodiment, the

Test evaluation unit 12 thereby purely purely by way of example also integrated within the digital circuit 15. Furthermore, the integrated circuit 1 comprises a test line T1. This test line T1 is within the analog

Circuit area 20 electrically conductively connected to the control line S1. Furthermore, the test line T1 is electrically conductively connected to the test evaluation unit 12. The test evaluation unit 12 is designed to test a digital value of a signal fed back via the test line T1.

Via the control line S1, for example by means of the digital control signal, a trim bit, a local digital logic or a transistor in the analog

Circuit area 20 are controlled. A digital logic can

For example, include registers. But other electronic

Blocks come into consideration, which can be controlled by digital control signals.

In this case, the signal which is returned or traceable by means of the test line T1 preferably corresponds to the control signal S1 transmitted via the control line. But also a modified control signal such as an amplified, delayed or attenuated control signal such as a digital logic in the analog part changed or recoded signal can be fed back to the test. The testing of the correctly transmitted control signal S [1] thus takes place not in the analog circuit area 20 but in the digital circuit area 10. The test time for testing the digital value of the returned signal in the digital circuit area 10 may be 100 ns, for example at frequencies of 10 MHz, which is significantly faster than measuring an analog voltage value, which is for example in the order of magnitude of 2 ms. These numerical examples are only examples and may depend on the semiconductor process, the specific application of the control signals, the structure of the chip or the integrated circuit.

In a first embodiment, the control signal S [1] can be routed via the test line T1 for test evaluation. Thereby, the correct transmission of the control signal S [1] in the analog range can be checked. A test of the control line S1 can be carried out as follows. The control signal S [1] of the control line S1 is applied to a signal value of "0", that is to say to the low level, and transmitted to the analog circuit area 20 or to the analog circuit 25. The test evaluation unit 12 then checks whether the control signal S [1], which is returned via the test line T1, likewise has the digital value "0" by checking the digital value. The control signal S [1] of the control line S1 can then be raised or raised to "1", ie to the high level, then the test evaluation unit 12 checks whether the digital value of the control signal S [1 ] also has the value "1". If this is the case, the control line S1 has been successfully tested.

A measurement of a control line S1 at a frequency of 10 MHz thus takes only 100 ns. Compared to the prior art, see the introduction, thus a significant gain in time can be achieved. This

Time gain can be used, for example, to test the other

Circuit components or circuit modules are used in the integrated circuit 1 or on the chip.

A signal value of the control signal of "1" may correspond by way of example to a digital voltage of 1, 5 V. However, the invention is not limited thereto

deviating, usually higher voltage required, for example a Supply voltage of 3 V. For this purpose, the control line S1 may further comprise a first driver D1 with level converter. The driver D1 supports the reloading or pulling up from a low level to a higher level. The level converter causes the change of the

Voltage level on one in the analog switching range of the analog

Circuit 25 required voltage, for example, from 1, 5 V to 3 V.

Driver D1 and level converter can be integrated in the digital circuit area 10, for example in the digital circuit area 10, in which the control line S1 is driven out of the digital control area. Alternatively, the driver D1 with level converter can also be integrated on the input side to the analog circuit area 20 or in the analog circuit area 20. Further, by way of example, the control line S1 a

Receive circuit L1, which is positioned before the connection with the test line T1. The receiving circuit L1 may, for example, be two inverters or else a Schmitt trigger or another digital circuit, the invention not being limited thereto. This receiving circuit L1 may then advantageously be tested as described below. The test line T1 may also include a second driver D2 with level converter. In this way, for example, an elevated voltage level can be reduced to a voltage value acceptable for the digital circuit area 10 or the digital circuit 15. This protects, for example, the digital switching area or the digital circuit 15 from too high a voltage. The signal sent back via the test line T1 is the test signal T [1]. This can then differ from the control signal S [1] by a lower voltage level as a result of the function of the level converter, also called level converter. A check of the control line S1 by means of this returned test signal

T [1] takes place as already described above. The levels of the control signal S [1] are passed through and it is checked whether the test signal T [1] has the same level. In this embodiment, the circuit of the first driver D1 is also mitgeprüft with level converter. In embodiments with a second driver D2 and associated level converter also these

Circuits tested. FIG. 2 shows an integrated circuit 1 after a second one

Embodiment described. In comparison to the embodiment according to FIG. 1, the integrated circuit 1 comprises a plurality of N> 2 control lines S1, Sn, SN, which respectively form an electrically conductive connection between the digital circuit 15 and the analog circuit 25. These N> 2 control lines S1, ..., Sn, ..., SN serve to transmit N

Control signals S [1], S [n], S [N] from the digital circuit 15 in the digital circuit area 10 in the analog circuit 25 im from the digital

Circuit area 10 spatially separated analog circuit area 20. In this case, the 1-th control signal S [1] on the 1-th control line S1, the second control signal S [2] via the second control line S2, the third control signal S [3 ] are transmitted to the analog circuit 25 via the third control line S3.

Accordingly, the nth control signal S [n] is transmitted to the analog circuit 25 via the nth control line Sn.

By way of example, N trimming bits, N digital logic or N transistors can be controlled by the N> 2 control lines, the invention not being restricted to specific electronic components. For example, the analog circuit 25 may be a bandgap circuit in which N trimming bits are driven to accurately equalize a reference voltage. The number of control lines N in this embodiment may be, for example, 2, 3, 5, 15, 30 or even 150, but the invention is not limited to these examples.

In this second embodiment, the analog circuit 25 may be a

Data compression circuit 22 include. The

Data compression circuit 22 is electrically conductively connected to the N> 2 control lines S1, ..., Sn, ..., SN in the analog circuit area 20 or electrically conductive within the analog circuit 25. The

Data compression circuit 22 is designed to the N

Control signals S [1], ..., S [n], ..., S [N], which are connected via N control lines S1,..., Sn,

SN are transmitted to the analog circuit 25 to compress or summarize in a compressed test signal T [1]. Further, by way of example, the test line T1 with the output of

Data compression circuit 22 electrically conductively connected. The compressed test signal T [1] can then be returned to the test evaluation unit 12 via the test line T1 for checking the digital value of the compressed test signal T [1]. The advantage achieved with the data compression circuit 22 is sometimes that the number of test lines to be returned is limited to a single test line T1. The circuits for drivers and level converters are also reduced accordingly. The circuit complexity is therefore reduced from N-1 test leads to a test lead.

In this preferred embodiment, the

Data compression unit 22 Logic gates. In particular, the

Data compression unit 22 an EXOR gate E1, ..., E2, EN-1. In this specific embodiment, N-1 EXOR gates E1,..., E2, EN-1 are interconnected in an electrically conductive manner with one another, for example, which will be described in more detail below.

Further, for n> 2, where n <N-1 holds for the N-1 EXOR gates, a first input of the n-th EXOR gate En is connected to the output of the (n-1) -th EXOR gate and on second input of the nth EXOR gate En with the (n + 1) th control line

(Sn + 1) electrically conductively connected. For example, for n = 2, the first input of the second EXOR gate E2 is connected to the output of the 1st EXOR gate E1. Furthermore, the second input of the 1 st EXOR gate is electrically conductively connected to the 3 th control line S3.

For n = 1, furthermore, the first input of the first EXOR gate E1 is electrically conductively connected to the first control line S1 and the second input of the first EXOR gate E2 is electrically conductively connected to the second control line S2. Further, the output of the (N-1) -th EXOR gate (EN-1) is electrically conductively connected to the test line T1 for returning the compressed test signal T [1] to the test evaluation unit 12.

Alternatively, the EXOR gates can also be switched in the form of an EXOR gate tree, which links the control lines. Also other expedient embodiments in which other logic gates such as ON D gates and OR

Gates are used, are covered by the invention. This data compression unit 22 can be used as an example in the following manner for the systematic testing of the N control lines S1, Sn, SN. First, all the control signals S [1], S [n], S [N] are set at the low level, the "0", and then the test signal T [1] must also be at the low level "0". Then the 1-th

Control signal S [1] to the high level, the "1", are set, while the other control signals S [2], ... S [n], ... S [N] the low level, the "0" , respectively. Then, the test signal T [1] should have the high level, the "1", due to the logic circuit of the EXOR gates E1, En, EN.

Thereafter, the 1-th control signal S [1] is again set to "0" and following the 2 nd control signal S [2] to "1", while in turn all other control signals S [1], S [3], .. , S [n], ..., S [N] are the low level having "0." Thus, every nth control signal S [n] can be successively set to the high level, "1", while the rest of the control signals are at the low level, so that when correctly transmitted the signal due to the

Return results in an alternating sequence of "1" and "0" for the compressed test signal T [1]. By systematically passing through all control lines S1, Sn, SN are checked once. Upon successful testing by the test evaluation unit 12, all control lines S1,..., Sn, SN are checked.

Again, the control lines S1, ..., Sn, ..., SN respectively

Receive circuits L1 include, which before the

Data compression circuit 22 are positioned and can be checked by the test line T1 accordingly.

In the figure 3 is an integrated circuit 1 after a third

Embodiment shown. In this embodiment, N> 2 control lines are also provided for transmitting N control signals S [1], S [n], S [N] from the digital circuit 15 into the analog circuit 25. In contrast to the second embodiment, the analog circuit 25 may here comprise a plurality of R data compression circuits 22-1, 22-r, 22-R with R> 2. In this case, each rth data compression circuit 22-r, with 1 <r <R, is electrically conductively connected to a plurality of control lines SK, SL, the number of these associated control lines SK,..., SL being less than the total number of N control lines. Each rth data compression circuit 22-r in this embodiment is also designed to compress the control signals S [K], S [L] transmitted via these associated control lines SK, SL into an rth test signal T [r]. Every rth

Data compression circuit 22-r is thus electrically conductively connected to a respective group of control lines.

In the present embodiment, for example, the 1 st

Data compression unit 22-1, the 1st control line S1 to the Jth

Associated with a number of J control lines S1, SJ, with J> 2 and J <N. The rth data compression unit 22-r are therefore the Kth control line SK with the Kth to be transmitted

Control signal S [K] to the L-th control line SL associated with the L-th control signal S [L] to be transmitted, which corresponds to a number of L-K + 1, where L- K + 1> 2 and L, K < N. Accordingly, the Rth data compression unit 22-R is assigned the Mth control line S [M] to the Nth control line, which corresponds to N-M + 1> 2, where N-M + 1> 2 and M <N.

In summary, in this embodiment of the invention, therefore, all of the N> 2 control lines S1, ..., Sn, ..., SN are grouped such that each of the R data compression circuits 22-1, ..., 22-r, .. . 22-R are always less than N control signals to a respective compressed test signal T [1],

T [r], T [R] compressed. With a very high number of control lines, for example for N = 150, compression by means of the compression circuit into a compressed test signal can take a correspondingly long time. The advantage of this embodiment is thus that the time for compression is reduced by the grouping and can also be compressed in parallel.

In this case, each rth data compression circuit 22-r may be designed as described in connection with FIG. 2, which is not explicitly explained in this figure merely for reasons of clarity. The integrated circuit 1 according to this embodiment may further include a plurality of R test lines T1, Tr, TR. In this case, every rth test line Tr is electrically conductively connected to the assigned rth data compression circuit 22-r. The compressed rth test signals T [r] can then be returned from the analog circuit 25 to the test evaluation unit 12, which is integrated in the digital circuit area 10, via the corresponding rth test line Tr to the test evaluation unit 12.

Thus, advantageously, the various test signals can also be tested in parallel, that is, at the same time. For this purpose, a plurality of test evaluation units 12 or alternatively only one central test evaluation unit 12 can be integrated in the digital circuit area 10.

Claims

claims

An integrated circuit (1) comprising:

a digital circuit section (10) comprising a digital circuit (15);

an analog circuit area (20) spatially separated from the digital circuit area (10) and comprising an analog circuit (25);

a control line (S1) for transmitting a control signal (S [1]) from the digital circuit (15) to the analog circuit (25);

a test evaluation unit (12) integrated in the digital circuit area (10);

one within the analog circuit area (20) with the

Control line (S1) electrically conductively connected test line (T1), which is electrically conductively connected to the test evaluation unit (12), wherein the test evaluation unit (12) is adapted to check a digital value of a fed back via the test line signal.

2. Integrated circuit (1) according to claim 1, wherein the control line (S1) comprises a first driver (D1) with level converter.

3. Integrated circuit (1) according to one of the preceding claims, wherein the control line (S1) before the connection to the test line (T1) positioned receiving circuit (L1).

4. An integrated circuit according to claim 1, wherein the test line comprises a second driver with level converter.

5. Integrated circuit (1) according to one of the preceding claims, wherein the integrated circuit (1) N> 2 control lines (S1, ..., Sn, ..., SN) for transmitting respective control signals (S [1], S [n], S [N]) from the digital circuit (15) into the analog circuit (25), wherein the analog circuit (25) further comprises a data compression circuit (22) adapted to be compressed by the control lines (S1,

..., Sn, ..., SN) formed control signals (S [1], S [n], S [N]) in a compressed test signal (T [1]), wherein the test line (T1) with the data compression circuit (22) is electrically conductively connected and wherein by means of the test line (T1) a compressed test signal (T [1]) for the purpose of testing the digital value of the test signal (T [1])

Test evaluation unit (12) is returned.

An integrated circuit (1) according to claim 5, wherein said

Data compression circuit (22) comprises at least one logic gate.

An integrated circuit (1) according to claim 5 or 6, wherein the

Data compression circuit (22) comprises at least one EXOR gate (E1, En, EN-1).

An integrated circuit (1) according to claim 7, comprising N-1 EXOR gates (E1, En, ..., EN-1) and 1 <n <N-1, where for n> 2

a first input of the nth EXOR gate (En) to the output of the (n-1) th EXOR gate (En-1) and a second input of the nth EXOR gate (En) to the (n +1) -th control line (Sn + 1) is electrically conductively connected, wherein for n = 1

the first input of the 1 st EXOR gate (E1) with the 1 th

Control line (S1) and the second input of the 1 st EXOR gate (E1) to the second control line (S2) is electrically conductively connected, and wherein for n = (N-1) further, the output of the (N-1 ) EXOR gate (EN-1) to the test line (T1) for returning the compressed test signal (T [1]) is electrically conductively connected.

Integrated circuit (1) according to one of the preceding claims 4 to 8, wherein the analog circuit (25) comprises a plurality of R

Data compression circuits (22-1, 22-r, 22-R) with R> 2, wherein each rth data compression circuit (22-r), with 1 <r <R, with a plurality of control lines (SK, SL) electrically is conductively connected and designed to be connected via these control lines (SK, .., SL)

transmitted control signals (S [K], S [L]) in a r-th test signal (T [r]) to compress.

The integrated circuit (1) of claim 9, wherein the integrated circuit (1) further comprises a plurality of R test lines (T1, Tr, TR), each rth test line (Tr) being connected to the rth data compression circuit (22 -r) is electrically conductively connected and compressed rth test signals

(T [r]) from the analog circuit (25) to the test evaluation unit (12).

1 1. Application-specific integrated circuit, ASIC, which comprises an integrated circuit (1) according to one of claims 1 to 10.