EP3688449A1

EP3688449A1 - Nanoelectrode devices and methods of fabrication thereof

Info

Publication number: EP3688449A1
Application number: EP18861291.5A
Authority: EP
Inventors: Kazusuke MIHARA; Hisao Kawasaki; Valentin V. DIMITROV; Toshihiko HONKURA; Mark F. Oldham; Eric S. Nordman
Original assignee: Quantum Biosystems Inc
Current assignee: Quantum Biosystems Inc
Priority date: 2017-09-27
Filing date: 2018-09-27
Publication date: 2020-08-05
Also published as: EP3688449A4; TW201928340A; WO2019065904A1

Abstract

The present disclosure provides devices and methods for fabrication of nanoelectrode pairs which may be useful for use with tunneling labels. Devices fabricated as described may have good spacing tolerances, angular tolerances, surface uniformity, and may have reduced particulate contamination.

Description

NANOELECTRODE DEVICES AND METHODS OF FABRICATION THEREOF

CROSS-REFERENCE

This application claims the benefit of U.S. Provisional Patent Application Serial No. 62/563,859, filed September 27, 2017, which is entirely incorporated herein by reference.

Electrode gaps have been fabricated using a variety of different methods. But such devices, such as MCBJs (mechanical break junctions) and methods restrict the number of sensors which may be effectuated on a single chip, and have issues with respect to yields, tolerances, background levels and uniformity of gap width.

Electrode pairs and associated gaps may be useful as detectors for direct detection of tunneling currents, or detection using tunneling labels; electrode pairs and associated gaps may similarly be utilized for direct detection of electrochemical species, or of electrochemical labels.

Fabrication of the millions or billions of functioning sensors which may be desired on a single integrated circuit requires improvements in the process methods and resulting sensors.

Recognized herein is a need for high-throughput and fast measurement of native DNA bases with high accuracy and low costs.

Some aspects of the present disclosure provide an apparatus comprising at least two electrodes disposed on a substrate separated by a non-conductive gap. The electrodes and the gap may be configured to accommodate a moiety, such as a polymerase, reducing species, or any other appropriate moiety.

In some embodiments, an at least one electrical signal is at least in part non-faradaic current. In some embodiments, an at least one signal comprises a plurality of signals. In some embodiments, an at least one signal may comprise tunneling current, or tunneling current and hopping current. In some embodiments, one or more labeled nucleotide types may be labeled with one or more molecules and or other moieties that may facilitate a formation of a tunneling current and or a hopping current. In some embodiments, a one or more molecules and or other moieties may comprise a conductive portion. In some embodiments, a conductive portion permits an electrical current passing therethrough when a one or more molecules or other moieties are subjected to a potential. In some embodiments, an electrical current may be direct current (DC). In some embodiments, an electrical current may be alternating current (AC). In some embodiments, a molecule may comprise a tunneling label. In some embodiments, a tunneling label may be bound to a target moiety, and the target moiety may be detected using the tunneling label. In some embodiments, a tunneling label may comprise a nucleic acid sequence. In some embodiments, an at least one electrical signal may be detected at a signal-to-noise ratio greater than or equal to about 100-to-1. In some embodiments, a signal-to-noise ratio may be greater than or equal to about 1000-to-1. In some embodiments, an at least one electrical signal may be detected in real-time.

In some embodiments, a gap width or spacing may be less than or equal to about 20 nm. In some embodiments, a gap width or spacing may be greater than 20 nm. In some embodiments, a flow channel may have a depth greater than or equal to about 100 nm. In some embodiments, a sensor with at least two electrodes may have a first portion and a second portion adjoining and underneath a first portion. In some embodiments, a first portion may have a first width, and a second portion may have a second width smaller than a first width. In some embodiments, a sensor may have a cross sectional shape of an inverted cone.

Another aspect of the present disclosure provides a system for sequencing a nucleic acid molecule comprising: a substrate comprising at least two electrodes separated by a gap as part of a flow channel, wherein a substrate may be solid; and a computer processor operatively coupled to a substrate and programmed to perform steps as required for detection, which may further comprise chemical and or biochemical steps.

In some embodiments, an at least one electrical signal may be at least partly a non-Faradaic current. In some embodiments, an at least one signal may comprises a plurality of signals. In some embodiments, an at least one electrical signal may comprise tunneling current. In some embodiments, a label may comprise a molecule that may facilitate a formation of a tunneling current and hopping current. In some embodiments, a label may comprise a conductive portion. In some embodiments, a conductive portion may permit an electrical current passing therethrough when a label may be subjected to a potential. In some embodiments, an electrical current may be direct current (DC). In some embodiments, an electrical current may be alternating current (AC).

In some embodiments, an electrical current may be a combination of direct current and alternating current. In some embodiments, a molecule may comprise a tunneling label. In some embodiments, a tunneling label may be bound to a base portion of a given nucleotide type of one or more labeled nucleotide types. In some embodiments, a tunneling label may be bound to a phosphate chain of a given nucleotide of one or more labeled nucleotide types. In some embodiments, a tunneling label may be bound to any position of a ribose or other backbone molecule of a given nucleotide of a set of one or more labeled nucleotides types. In some embodiments, a tunneling label may be reversibly bound to a given nucleotide of one or more labeled nucleotide types. In some embodiments, one or more labeled nucleotide types may comprise at least two different types of nucleotides or modifications thereof. In some embodiments, each type of an at least two types of nucleotides or modifications thereof may be labeled with a different tunneling label.

In some embodiments, an at least one electrical signal may be detected with a signal-to-noise ratio greater than or equal to about 100-to-1. In some embodiments, a signal-to-noise ratio may be greater than or equal to about 1000-to-1. In some embodiments, an at least one electrical signal may be detected in real-time.

In some embodiments, a gap may be greater than or equal to about 1 nanometer (nm). In some embodiments, a gap width or spacing associated with a pair of nanoelectrode pairs as described hereinafter may be less than or equal to about 20 nm. In some embodiments, a flow channel has a depth greater than or equal to about 100 nm.

In some embodiments, a sensor comprising an electrode pair may have a first portion and a second portion adjoining and underneath a first portion. In some embodiments, a first portion may have a first width, and a second portion may have a second width smaller than a first width. In some embodiments, a polymerase may have a size that is greater than the second width and smaller than the first width. In some embodiments, a sensor comprising an electrode pair may have a cross sectional shape of an inverted cone.

In some embodiments, a system may further comprise a chip comprising a sensor, a sensor having a substrate. In some embodiments, an at least two electrodes may be coupled to an electric circuit. In some embodiments, a sensor may be coupled to an electric circuit that processes an at least one electric signal. In some embodiments, a chip may comprise a plurality of sensors, each comprising an individual pair of electrodes. In some embodiments, a chip may comprise at least about 10,000, 100,000, 1,000,000, 10,000,000, 100,000,000, 1,000,000,000, 10,000,000,000 or more than 10,000,000,000 sensors. In some embodiments, each of a plurality of sensors or plurality of sets of sensors may be independently addressable.

In some embodiments, an at least one electrical signal may be a non-Faradaic current. In some embodiments, an at least one signal may comprise a plurality of signals. In some embodiments, an at least one electrical signal may comprise a tunneling current. In some embodiments, one or more labeled nucleotide types may be labeled with a molecule and or other moiety that may facilitate a formation of a tunneling current or tunneling and hopping current

In some embodiments, an at least one electrical signal may be at least partly non-Faradaic current. In some embodiments, an at least one signal may comprise a plurality of signals. In some embodiments, an at least one electrical signal may comprise tunneling current. In some embodiments, one or more labeled nucleotide types may be labeled with a molecule that facilitates a formation of a tunneling current or tunneling and hopping current. In some embodiments, a molecule may comprise a tunneling label.

Additional aspects and advantages of the present disclosure will become readily apparent to those skilled in this art from the following detailed description, wherein only illustrative embodiments of the present disclosure are shown and described. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

INCORPORATION BY REFERENCE

All publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference.

The novel features of the invention are set forth with particularity in the appended claims. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description that sets forth illustrative embodiments, in which the principles of the invention are utilized, and the accompanying drawings of which:

[Rectified under Rule 91, 23.10.2018]
Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 1A-K show steps for a method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Fig. 2A-M show steps for another method of fabrication of a pair of nanoelectrodes associated with a nanogap sensor; Figs. 3A-3D show steps in another method of fabricating of a pair of nanoelectrodes associated with a nanogap sensor; Figs. 3A-3D show steps in another method of fabricating of a pair of nanoelectrodes associated with a nanogap sensor; Figs. 3A-3D show steps in another method of fabricating of a pair of nanoelectrodes associated with a nanogap sensor; Figs. 3A-3D show steps in another method of fabricating of a pair of nanoelectrodes associated with a nanogap sensor; Figs. 3E-3I show SEM and TEM images of sensors formed using the process shown in Figs. 3A-3D; Figs. 3E-3I show SEM and TEM images of sensors formed using the process shown in Figs. 3A-3D; Figs. 3E-3I show SEM and TEM images of sensors formed using the process shown in Figs. 3A-3D; Figs. 3E-3I show SEM and TEM images of sensors formed using the process shown in Figs. 3A-3D; Figs. 3E-3I show SEM and TEM images of sensors formed using the process shown in Figs. 3A-3D; Figs. 3J and 3K show another method for forming a nanogap sensor; Figs. 3J and 3K show another method for forming a nanogap sensor; Figs. 3L-3N show another method for forming a nanogap sensor; Figs. 3L-3N show another method for forming a nanogap sensor; Figs. 3L-3N show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Figs. 3O-3V show another method for forming a nanogap sensor; Fig. 3W depicts a nanogaps sensor with a narrower nanogap; Fig. 3X shows a chip with multiple fluidic pathways for sensor arrays and associated circuitry; Fig. 4 shows a nanogap sensor in use with a tunneling label; and Fig. 5 shows a TEM of a first metalization layer; and Fig 6A-6B show different methods of making nanogap sensors with smooth electrode surfaces. Fig 6A-6B show different methods of making nanogap sensors with smooth electrode surfaces.

DETAILED DESCRIPTION

While various embodiments of the invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, changes, and substitutions may occur to those skilled in the art without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed.
The term "gap," as used herein, generally refers to a volume, space, pore, channel or passage formed or otherwise provided in a material, or between electrodes. The material may be a solid state material, such as a substrate, or may be formed of different layers formed on a substrate. A gap may be disposed adjacent or in proximity to a sensing circuit or an electrode coupled to a sensing circuit. In some examples, a gap may have a characteristic width or diameter on the order of 0.1 nanometers (nm) to about 1,000 nm. A gap having a width on the order of nanometers may be referred to as a "nano-gap" (also "nano-gap" herein). In some situations, a nano-gap may have a width or spacing that may be from about 0.1 nanometers (nm) to about 50 nm, 0.5 nm to 30 nm, or 0.5 nm to 10 nm, 0.5 nm to 5 nm, or 0.5 nm to 2 nm, 5 to 30nm, 10nm to 20nm, 5nm to 20nm, 15nm to 25nm, or no greater than about 2 nm, 1 nm, 0.9 nm, 0.8 nm, 0.7 nm, 0.6 nm, or 0.5 nm. In some cases, a nano-gap has a width that is at least about 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 7.5nm, 10nm, 15nm, 20nm, 30nm or more than 30nm. In some cases, a width or spacing of a nano-gap can be more than a diameter of a biomolecule used in a sequencing reaction, or may be less than the diameter of a sample biomolecule or a subunit (e.g., monomer) of a sample biomolecule.
The term "adjacent" or "adjacent to" as used herein, includes 'next to', 'adjoining', 'in contact with', and 'in proximity to'. In some instances, adjacent to components are separated from one another by one or more intervening layers. For example, the one or more intervening layers can have a thickness less than about 10 micrometers ("microns"), 1 micron, 500 nanometers ("nm"), 100 nm, 50 nm, 10 nm, 1 nm, or less. In an example, a first layer is adjacent to a second layer when the first layer is in direct contact with the second layer. In another example, a first layer is adjacent to a second layer when the first layer is separated from the second layer by a third layer.
The term "tunneling," as used herein, generally refers to a movement of a particle, such as an electron, through a potential barrier which the particle does not have sufficient energy to overcome. This may be in contrast to standard conductance, wherein a particle may have sufficient energy to overcome any energy barriers.
The term "tunneling label," as used herein, generally refers to a moiety (such as a compound, a molecule, a particle, and combinations thereof) which may facilitate tunneling of electrons or holes within or through the moiety, or between one or more electrodes and the moiety. In some cases, tunneling may be measured as a tunneling and or hopping current.
The term "tunneling current," as used herein, generally refers to a current signal associated with tunneling of electrons or holes between two electrodes with a voltage (e.g., a bias voltage) applied thereto. The tunneling may be into, out of, through a tunneling label, or any combination thereof. In some cases, tunneling may be combined with portions of a conduction path wherein hopping may occur.
The present disclosure provides devices and methods relating to formation of devices with a gap or set of gaps formed by a pair or set of pairs of electrodes that may be utilized to identifying tunneling signals or electrochemical signals.

Sensor electrodes
A system of the present disclosure may be a highly scalable system. For example, millions or billions of sensors may be disposed on a single chip similar in size to current DNA sequencing electronic sensors, including two electrodes separated by a gap, with a very small pitch on a single device. In some cases, a chip may have a very high density of sensors. For example, a single chip may have a sensor density greater than or equal to about 5,000, 10,000, 20,000, 30,000, 40,000, 50,000, 60,000, 70,000, 80,000, 90,000, 100,000, 200,000, 300,000, 400,000, 500,000, 600,000, 700,000, 800,000, 900,000, 1,000,000, 2,000,000, 3,000,000, 4,000,000, 5,000,000, 6,000,000, 7,000,000, 8,000,000, 9,000,000, 10,000,000, 20,000,000, 30,000,000, 40,000,000, 50,000,000, 60,000,000, 70,000,000, 80,000,000, 90,000,000, 100,000,000, 200,000,000, 300,000,000, 400,000,000, 500,000,000, 600,000,000, 700,000,000, 800,000,000, 900,000,000, 1,000,000,000, 2,000,000,000, 3,000,000,000, 4,000,000,000, 5,000,000,000 or more sensors/inch². In some cases, older modes for circuit processing may be utilized, such that various custom chip designs can be fabricated without the cost of a state of the art high density mode such as 14 nm or the soon to be effectuated 10 nm modes. In some cases, a density of sensors may not be restricted by optical or diffusional crosstalk.
In some cases, a massively parallel design of a chip using lithographic processes may be used to place a large number of sensors on a substrate. Each sensor may have two electrodes separated by a gap. Individual sensors may be separated by a pitch size. A pitch size may be the same or different in X and Y axes. Each sensor may have an individual or multiplexed electronic path to place a bias voltage between electrodes on an electrode pair and or read out a tunneling current. As such, each electrode may be individually addressable and readable, or may be read out in groups, for example in rows, wherein an analog to digital converter may present for each column. In some cases, multiple analog to digital converters may be present associated with each column, for example at the opposing ends of a column, or may be interspersed within a column. Electrodes on each sensor may be made from gold, platinum, copper, palladium, silver, or other coinage or noble metals, or graphene. The use of coinage or noble metals may facilitate thiol bonding to electrodes.
In some cases, a gap size between electrodes comprised in sensors may be designed so that electrodes may be parallel or within 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 degrees of parallel. The electrodes may also be designed to have a spacing such that SAMs may be placed on electrodes, and an enzyme may fit between SAM layers bound to electrodes in a gap therebetween.
In some cases, as shown in Fig. 3W, electrodes, or a structure associated with electrodes may be angled with respect to each other, and may be formed using a KOH etch to create inverted truncated pyramids. Electrode pairs 342A and 342B associated thereto may be formed with an angle with respect to each other, or may be fabricated with facing sides parallel or essentially so as described hereinabove. A structure may have an entrance which may have a width sufficient to allow entrance for a polymerase or other enzyme 330, while having angled surfaces 340 which may be too narrow for a polymerase to fit therebetween, and may further have electrodes which may have a spacing which may be significantly narrower than a polymerase or other enzyme 330, such that a label shorter than a diameter of a polymerase or other enzyme may be utilized.
In some cases, a gap size between electrodes may be narrower or smaller than about 10 nm, allowing measurement of conductance using a nucleic acid label with about 30 base pairs. In some cases, a gap may be larger or wider than about 2-3 nm to avoid creation of TLF false positives and to ease manufacturing.
In some cases, a set of fluidic channels may be utilized to distribute reagent sets, enzymes and or polymerases to electrode pairs disposed on or adjacent to a substrate. In some cases, a fluidic channel may be a width corresponding to a physical readout configuration for a chip, such as a number of rows per multiplexed amplifier. A fluidic channel may be of a height sufficient to readily supply reagents and enzymes, which may be a height of 100nm to 200nm, 200nm to 500nm, 500nm to 1μm, 1μm to 5μm, 5μm to 10μm, 10μm to 50μm, 50μm to 250μm, or greater than 250μm. A width of a fluidic channel may be made to be fairly narrow, as it may be of a width which may correspond to hundreds or thousands of sensors, and thus a tolerance with a height may be significantly tighter than would be the case if a fluidic channel were to cover an entire chip. In other cases, a gap (e.g. a nanogap) associated with a sensor may be wider than a width of an enzyme or polymerase. A width of an enzyme or polymerase may be considered to be a minimum dimension of an enzyme or polymerase wherein an enzyme or polymerase may be complexed with a partly single stranded and partly double stranded nucleic acid, and the thumb of an enzyme or polymerase may be open with respect to the palm of an enzyme or polymerase. An axis of a nucleic strand along the length of a nucleic acid portion bound within or to an enzyme or polymerase and complexed within an enzyme or polymerase may be parallel with metallic surfaces which comprise a gap or nanogap.
In some cases, at least one electrode of an electrode pair may be covered, partially covered, or not covered with dielectric, and a second member of a pair may be covered, partially covered, or not covered with a dielectric.
In some cases, a sensor may comprise an electrode pair. An electrode pair may be configured to detect tunneling or tunneling and hopping labels, or may be used to detect target moieties directly. In further cases, rather than utilizing a gap as described hereinafter, an electrode pair may be formed without creating a gap or nanogap, but may otherwise be formed in a similar way, excepting that an RIE step to form the gap may not be performed. In such cases, the active areas of the electrodes may be substantially coplanar. In such cases wherein a polymerase, enzyme, or other moiety utilized in a measurement may be bound to a dielectric which may form a spacing between a sense and a bias electrode, a linker associated with a label and or length of a label may need to be formed in such a manner as to be longer than would be needed if a polymerase, enzyme or other moiety were bound at the midpoint between a sense and a bias electrode in order to take into account tolerances in positional binding and movement of the polymerase, enzyme or other moiety utilized in a measurement. Additional tolerances which may be considered may include for example, diffusion with respect to the binding point of a polymerase, enzyme or other moiety utilized in a measurement due to diffusional movement permissible due to a length of a linker by which a polymerase, enzyme or other moiety utilized in a measurement may allow, or rotation of a polymerase, enzyme or other moiety utilized in a measurement.
In some cases, instead of a pair of electrodes, triples, quads, or arrays (e.g., linear arrays) of electrodes may be used. Electrodes may be configured in an arrangement such that electrodes may be substantially coplanar with a same or with different distances between different electrodes.
In some cases, electrodes may be covered or partially covered with a dielectric, such that a DC current may be minimal, and may not be measureable in some cases, but an AC field may be applied and a tunneling current may be determined in addition to any capacitive currents. This may allow utilization of tunneling and or hopping current detection in conjunction with separation by another methods, such as electrophoretic separation, where fields associated with electrophoretic separation may otherwise influence tunneling currents and or binding to tunneling electrodes as potentials associated with an electrophoretic field may not be well determined or controlled, or may be variable.
In some cases, detection and quantitation may be achieved either using kinetic detection as described hereinabove, which may be kinetic detection of multiple molecules, or detecting a number of copies which may be fixedly bound. In some cases, a dynamic range may be increased by increasing a number and or size of electrode pairs.
In some embodiments as shown in Figures 1A to 1K, a sensor pair comprising a pair of electrodes and a nanogap may be formed, and may be formed in a manner that controls a metal deposition cone angle, such that an angle of the deposited metal may be more uniform at different metal deposits across a wafer, despite variations in the angles of metal being emitted from the metal source. In addition, the use of double layer resist masks on both sides of a metal region being deposited may minimize or eliminate the formation of metal nanoparticles.
Fig. 1A shows the initial steps for the fabrication of a two electrode and nanogap device, wherein a substrate 101 is covered with a first deposited dielectric layer 102, which may be silicon nitride layer or a silicon oxide layer or other desired dielectric layer, and then covered with a second dielectric layer 103, which may be a silicon oxide layer or a silicon oxide layer or other desired dielectric layer. The substrate may be a bare silicon wafer or other similar substrate, or may be a wafer on which integrated circuitry has been formed, and which may have then have had a silicon oxide layer applied and planarized, for example, using a CMP (chemical mechanical polishing) process or other process to provide an appropriately flat surface for the subsequent formation of the nanogap sensors. If the wafer is a nominally bare substrate, an oxidation process may be utilized to form a surface oxide.
Additional adhesion layer(s) (not shown) may be formed between or upon the substrate 101, first dielectric layer 102, or second dielectric layer 103, and may comprise any appropriate dielectric layer; an additional adhesion layer may include, but is not limited to, a chromium-based material (Cr, Cr₂O₃, etc.), a titanium-based material (e.g., Ti, TiO₂, etc.), Al, Al₂O₃, Ta, Cu, Pb, amorphous Si, GaAs, other semiconducting materials, Chalcogenide glasses (which may also be amorphous, metal doped, or rare earth metal doped), and indium tin oxide (ITO). Such an additional adhesion layer may be utilized as needed in association with the application of any layer as described herein, and different adhesion layers may be used at different steps in a method or process associated with different layers or materials to be adhered.
In Fig 1B, a double layer resist is formed, wherein the thickness of the first resist layer 104 may be used as an upper bound for the thickness of the subsequent first metalization layer. The second resist layer 105 may be made to have an opening aperture which may be essentially the same size as the top of the first metalization layer. The thickness of the second resist layer 105 combined with the width of the aperture in the second resist layer 105 which forms the width of the first metalization layer forms the cone angle of metal deposition. The cone angle may be set to any desired angle which may be less than the width of the initial cone angle of the deposition source.
First metalization layer 106 may then be deposited wherein a cone angle may correspond to a relationship between the aperture width and thickness of the second resist layer 105 as shown in Fig. 1C. The metalization layer may be thinner than the thickness of the first resist layer 104 so as to prevent the first metalization layer from reaching the bottom of the second resist layer 105 and thus potentially creating sharp edges from material (not shown) which may be inadvertently deposited on the sides of the aperture of the second resist layer 105. Fig. 5 shows a TEM of an exemplary first metalization layer; the angle was measured to have variation over a wafer of less than four degrees for the angle with respect to vertical of a surface which may thence be used for formation of a nanogap, significantly smaller variation then the variation without deposition metal deposition cone angle control; the TEM also shows a lack of metal nanoparticles as were previously observed without metal deposition cone angle control and shown in Fig. 3F.
The spacing of the first resist layer 104 may be made to be wider than the anticipated first metalization layer, and may be made to be wider than the width of the first metalization layer at the base of the first metal
Deposit on sides of first resist layer 104 by making same size or slightly less than width of bottom of trapezoid of first metalization layer 106 deposited.
A first metalization layer which may be deposited may comprise any metal as described hereinabove as being suitable for an electrode.
A standard removal of a double layer resist, which may comprise first resist layer 104 and second resist layer 105,may then be effectuated as shown in Fig.1D, removing any first metalization layer 106 which may have been deposited on the second resist layer 105, as well as the first resist layer 104 and second resist layer 105. Any first metalization layer which may have deposited on the sides of the aperture in second resist layer 105 will also be removed. A removal of a double resist layer may be effectuated using a wet process such as a combination of sulfuric acid and hydrogen peroxide, a combination of ammonia and hydrogen peroxide, or any other appropriate wet resist removal process, or may be a dry resist removal process, such as an plasma etching, reactive ion etching, or ion beam etching.
An oxide or dielectric layer may be etched using a wet etch, which may comprise a buffered hydrofluoric acid etch, a KOH etch, a hydrofluoric acid etch, a phosphoric acid etch or any other appropriate etchant.
An adhesion layer (not shown) may be applied using the double layer resist pattern, and may be applied prior to deposition of a first metalization layer 107 using a double layer resist which may comprise first resist layer 104 and second resist layer 105, or may be applied after deposition of a first metalization layer 107 using a double layer resist which may comprise first resist layer 104 and second resist layer 105, or may be applied both before and after a first metalization layer using a double layer resist which may comprise first resist layer 104 and second resist layer 105. Alternatively or in combination with the above methods of forming adhesion layers, an adhesion layer (not shown) may be applied prior to the formation of a first resist layer 104, and or after the formation of first resist layer 104, second resist layer 105 and first metalization layer 106 and removal of first resist layer 104, second resist layer 105 and any of first metalization layer 106 which may be deposited on second resist layer 105 or first resist layer 104.
In some embodiments wherein a metal deposition source which may be utilized with a double layer resist wherein an overhang of the second layer may otherwise be sufficiently large as to allow the formation of nanoparticles as a result of the variable rate of deposition versus angle of the source as shown at the bottom of the nanogap shown in Fig. 3F, metal particles formation may be prevented by control of cone angle, which may also set the angle of one or more sidewalls of first metalization layer 106. In some embodiments, a width to height ration may be 1 to 2 or larger, 1 to 3 or larger, 1 to 4 or larger, 1 to 5 or larger, 1 to 6 or larger, 1 to 8 or larger, or 1 to 10 or larger. A width of an aperture may be sized to the minimum capabilities of a lithography system, which may be an e beam lithography system, an optical lithography system, an X-ray lithography system, or any other appropriate lithography system. The width of an aperture may be less than 3nm, less than 5nm, less than 7 nm, less than 10nm, less than 15 nm, less than 20nm, less than 25nm, less than 35nm, less than 50nm, less than 70nm, less than 100nm, less than 150nm, less than 250nm, less than 500nm, less than 1000nm, or larger than 1000nm.
An aperture in a second resist layer 105 may have a square shape when viewed from the top, or may have a rectangular shape when viewed from the top wherein all four sides may have controlled slope angles and may have significantly reduced or eliminated stray metal particle formation, wherein different pairs of sides may have different slope angles and may have significantly reduced or eliminated stray metal particle formation. In other embodiments, a rectangular aperture may be sufficiently long in one axis so as to project under a well structure as described hereinafter, so that a slope angle and or stray metal particle formation may not be a consideration due to coverage by an oxide layer which may be a part of a well structure.
In further embodiments, an aperture in second resist layer 105 may not be rectangular, and portions of first metalization layer 106 which are covered by a well structure may be utilized, for example, to connect to a via to circuitry previously formed under nanogap electrode structures as described hereinabove, or may be connected to a transistor which may be a part of an output amplifier cell, or for any other appropriate purpose.
In further embodiments, an aperture in second resist layer 105 may not be rectangular, but may have a shape which may include portions of the shape which may have curved surfaces, which may have uniform radii, or may have uneven radii, and may also include portions of the shape which may have straight sections.
A second metalization layer 107, which may comprise any metal as described hereinabove as being suitable for an electrode and may further comprise any metal which may be appropriate for semiconductor fabrication such as aluminum or copper, may then be deposited as shown in Fig. 1E using any appropriate method, which may comprise a double resist process, or may comprise a single resist process, and may comprise additional metal layer processes such as ion milling or other standard additive or subtractive processes or methods. A second metalization layer 107 may be configured to overlap the first metalization layer 106, but may not have size and shape restrictions which may be needed for a first metalization layer 105 in order to have a controlled sidewall angle and minimization or elimination of metal particles which may otherwise be formed as a result of a first metalization layer 106. A second metalization layer 107 may be applied at any angle, rotationally with respect to a vertical axis as shown in Fig. 1D, with respect to a first metalization layer 106, and is not limited to the configuration shown in Fig. 1D, wherein a second metalization layer 107 is shown to extend to the right of a first metalization layer 106.
A second metalization layer 107 may at least partly overlay, or at least partly contact a first metalization layer 106, and may be shaped as needed or desired over or touching any part of first metalization layer 106 except for those portions of first metalization layer 106 which are to be utilized as a part of a nanogap. A second metalization layer 107 may further comprise additional metalization layers in contact with a second metalization layer 107 as needed or desired, for example to provide a shared bias potential between multiple sensors.
A second metalization layer 107 may have adhesion layers (not shown) utilized in association therewith, and may be applied prior to and or after deposition of a second metalization layer 107.
A second metalization layer 107 may have an associated resist structure (not shown) and any of a second metalization layer 107 which may have been deposited on the associated resist structure removed using any of the methods as described hereinabove with respect to the removal of the resist structure and first metalization layer 106 which may have been deposited upon the resist structure.
A dielectric layer 108 may then be applied as shown in Fig. 1F, wherein the dielectric layer 108, which may be silicon oxide, silicon nitride or any other appropriate dielectric or other material which can be preferentially etched with respect to the metal of a first, second or third metalization layer may be applied as a layer over an entire wafer, or may be applied using a resist pattern such that portions of a dielectric layer may be removed in some desired regions. A dielectric layer 108 may be deposited using sputtering, atomic layer film deposition or any other appropriate deposition method. A thickness of dielectric layer 108 may determine the width of a gap between two electrodes comprised of at least a first metalization layer 106 and a third metalization layer, either strictly as a function of a thickness of dielectric layer 108, or as a combination of dielectric layer 108 and any adhesion layers, which may comprise the full thickness of an adhesion layer or may comprise an effective thickness of an adhesion layer as a result of diffusion of an adhesion layer into metal(s) associated with a first metalization layer 106 or third metalization layer.
A third metalization layer 109, which may comprise any metal as described hereinabove as being suitable for an electrode and may further comprise any metal which may be appropriate for semiconductor fabrication such as aluminum or copper, may then be deposited as shown in Fig. 1G using any appropriate method, which may comprise a double resist process, or may comprise a single resist process, and may comprise additional metal layer processes such as ion milling or other standard additive or subtractive processes or methods. A second metalization layer 109 may be configured to overlap the first metalization layer 106, but may not have size and shape restrictions which may be needed for a first metalization layer 105 in order to have a controlled sidewall angle and minimization or elimination of metal particles which may otherwise be formed as a result of a first metalization layer 106. A third metalization layer 109 may be applied at any angle, 107 may be applied at any angle, rotationally with respect to a vertical axis as shown in Fig. 1D, with respect to a first metalization layer 106, and is not limited to the configuration shown in Fig. 1D, wherein a third metalization layer 109 is shown to extend to the left of a first metalization layer 106.
A third metalization layer 109 may at least partly overlay, or at least partly contact a first metalization layer 106, and may be shaped as needed or desired including over or touching any part of first metalization layer 106 covered by dielectric layer 105. A third metalization layer 109 may further comprise additional metalization layers in contact with a third metalization layer 109 as needed or desired, for example to provide a shared bias potential between multiple sensors.
A third metalization layer 109 may have adhesion layers (not shown) utilized in association therewith, and may be applied prior to and or after deposition of a third metalization layer 109.
A third metalization layer 109 may have an associated resist structure (not shown) and any of a third metalization layer 109 which may have been deposited on the associated resist structure removed using any of the methods as described hereinabove with respect to the removal of the resist structure and first metalization layer 106 which may have been deposited upon the resist structure.
An oxide layer 110 such as a silicon oxide, gallium oxide or any other appropriate oxide may then be deposited so as to create a relatively flat top surface as shown in Fig. 1H. Such an oxide layer 110 may be deposited using chemical vapor deposition or other known methods.
A CMP process may then be utilized to planarize metalization layers, which may comprise first metalization layer 106, second metalization layer 107, and third metalization layer 109, and to remove any gold which may have been deposited above a nominally vertical nanogap formed between a first metalization layer 106 and a third metalization layer 109 as shown in Fig 1I. A nominally vertical nanogap formed between a first metalization layer 106 and a third metalization layer 109 may be formed using a sidewall angle as determined by the sidewall angle of a first metalization layer 106 as formed using a controlled angle as described hereinabove.
A second oxide layer 111 such as a silicon oxide, gallium oxide or any other appropriate oxide may then be deposited so as to create a relatively flat top surface as shown in Fig. 1J. Such a second oxide layer may 111 be deposited using chemical vapor deposition or other known methods.
A well structure may be formed in second oxide layer 111 as shown in Fig. 1K, wherein a single layer resist (not shown) may be utilized in association with a wet etch as described herein of second oxide layer 111 so as to form a well structure in second oxide layer 111.
An etch may further be utilized to etch dielectric layer 108 wherein dielectric layer 108 may be exposed by the etching of second oxide layer 111, thereby forming a gap between first metalization layer 106 and third metalization layer 109. Etching of dielectric layer 108 may be effectuated by a same wet etch process utilized to etch second oxide layer 111 to expose dielectric layer 108, or may be an additional wet etch process as described herein which may utilize different etchants, or may be a dry etch process as described herein.
In some embodiments as shown in Figures 2A to 2M, a sensor pair comprising a pair of electrodes and a nanogap may be formed, and may be formed in a manner that controls a metal deposition cone angle, such that an angle of the deposited metal may be more uniform at different metal deposits across a wafer, despite variations in the angles of metal being emitted from the metal source. In addition, the use of a tapered resist mask may minimize or eliminate the formation of metal nanoparticles.
Fig. 2A shows the initial steps for the fabrication of a two electrode and nanogap device, wherein a substrate 201 is covered with a first deposited dielectric layer 202, which may be silicon nitride layer or a silicon oxide layer or other desired dielectric layer, and then covered with a second dielectric layer 203, which may be a silicon oxide layer or a silicon oxide layer or other desired dielectric layer. The substrate 201 may be a bare silicon wafer or other similar substrate, or may be a wafer on which integrated circuitry has been formed, and which may have then have had a silicon oxide layer applied and planarized, for example, using a CMP (chemical mechanical polishing) process or other process to provide an appropriately flat surface for the subsequent formation of the nanogap sensors. If the wafer comprises a nominally bare substrate, an oxidation process may be utilized to form a surface oxide. In some embodiments, a single dielectric layer may be utilized, wherein the single dielectric layer may comprise a different material a top surface of a substrate 201.
Subsequent to application of dielectric layers, which may comprise a first dielectric layer 202 and a second dielectric layer 203, inverse tapered silicon oxide layer 204 may be applied as shown in Fig. 2C.
After exposure, a tapered etch process may be utilized, such as a plasma ashing process or other dry etch process, or a photo resist tapering process such as that described in US4705597 which is hereby included by reference in its entirety, or a process to form a tapered waveguide as described in JP2010-181030 and US2008/0299468 which are hereby included by reference in its entirety, to form inverse tapered layer 204, which may be a silicon or other oxide or other dielectric as described herein as shown in Fig. 2D.
First metalization layer 205 may then be deposited wherein one or more edges associated wherein now inverse tapered layer 204 may be formed with an angle associated thereto as shown in Fig. 2E. First metalization layer 205 may be thinner than a thickness of inverse tapered layer 204, or may be thicker than inverse tapered layer 204 as shown in Fig. 2E.
Sputtering or plating technologies, or any other appropriate process may be utilized to form first metalization layer 205. Any desired combination of layers of adhesion layers and electrode metals may be utilized to form first metalization layer 205.
A CMP process may then be utilized to planarize first metalization layer 205 and inverse tapered layer 204 as shown in Fig. 2F.
Inverse tapered layer 204 may then be removed, using for example a buffered hydrofluoric acid or other appropriate etchant as described herein, leaving first metalization layer 205 as shown in Fig 2G.
A dielectric layer 206 may then be applied as shown in Fig. 2H, wherein the dielectric layer 108, which may be silicon oxide, silicon nitride or any other appropriate dielectric or other material which can be preferentially etched with respect to the metal of a first, second or third metalization layer may be applied as a layer over an entire wafer, or may be applied using a resist pattern such that portions of a dielectric layer may be removed in some desired regions. A dielectric layer 206 may be deposited using sputtering, atomic layer film deposition or any other appropriate deposition method. A thickness of dielectric layer 206 may determine the width of a gap between two electrodes comprised of at least a first metalization layer 205 and a second metalization layer, either strictly as a function of a thickness of dielectric layer 206, or as a combination of dielectric layer 206 and any adhesion layers, which may comprise the full thickness of an adhesion layer or may comprise an effective thickness of an adhesion layer as a result of diffusion of an adhesion layer into metal(s) associated with a first metalization layer 205 or second metalization layer.
A second metalization layer 207, which may comprise any metal as described hereinabove as being suitable for an electrode, may then be deposited as shown in Fig. 2I using any appropriate method, which may comprise a double resist process, or may comprise a single resist process, and may comprise additional metal layer processes such as ion milling or other standard additive or subtractive processes or methods. A second metalization layer 207 may be configured to overlap a first metalization layer 205, but need not have a tapered resist in order to have a controlled sidewall angle and minimization or elimination of metal particles which may otherwise be formed as a result of a first metalization layer 205. A second metalization layer 207 may be applied at any angle, 107 may be applied at any angle, rotationally with respect to a vertical axis as shown in Fig. 2I, with respect to a first metalization layer 205, and is not limited to the configuration shown in Fig. 2I, wherein a second metalization layer 207 is shown to extend to the left of a first metalization layer 205.
A second metalization layer 207 may at least partly overlay, or at least partly contact a first metalization layer 205 in a region formed by a tapered resist and covered by a dielectric layer 206, and may then be shaped as needed or desired. A second metalization layer 207 or first metalization layer 205 may further comprise additional metalization layers in contact with a second metalization layer 207 or first metalization layer 205 respectively as needed or desired, for example to provide a shared bias potential between multiple sensors.
A second metalization layer 207 may have adhesion layers (not shown) utilized in association therewith, and may be applied prior to and or after deposition of a second metalization layer 207.
A second metalization layer 207 may have an associated resist structure (not shown) and may be of any desired shape.
An oxide layer 208 such as a silicon oxide, gallium oxide or any other appropriate oxide may then be deposited so as to create a relatively flat top surface as shown in Fig. 2J. Such an oxide layer 208 may be deposited using chemical vapor deposition or other known methods.
A CMP process may then be utilized to planarize metalization layers, which may comprise first metalization layer 205, second metalization layer 207, and to remove any gold which may have been deposited above a nominally vertical nanogap formed between a first metalization layer 205 and a second metalization layer 207 as shown in Fig 2K. A nominally vertical nanogap formed between a first metalization layer 205 and a second metalization layer 207 may be formed using a tapered resist as formed using a controlled angle as described hereinabove.
A second oxide layer 208 such as a silicon oxide, gallium oxide or any other appropriate oxide may then be deposited so as to create a relatively flat top surface as shown in Fig. 2L. Such a second oxide layer may 208 be deposited using chemical vapor deposition or other known methods.
A well structure may be formed in second oxide layer 208 as shown in Fig. 2M, wherein a single layer resist (not shown) may be utilized in association with a wet etch as described herein of second oxide layer 209 so as to form a well structure in second oxide layer 209.
An etch may further be utilized to etch dielectric layer 206 wherein dielectric layer 206 may be exposed by the etching of second oxide layer 209, thereby forming a gap between first metalization layer 205 and second metalization layer 207. Etching of dielectric layer 206 may be effectuated by a same wet etch process utilized to etch second oxide layer 209 to expose dielectric layer 206, or may be an additional wet etch process as described herein which may utilize different etchants, or may be a dry etch process as described herein.
In some cases, a structure may be fabricated using a variety of standard semiconductor processing methodologies, which may include, for example and as shown in Figs. 3A to 3D:
1) starting with a planarized substrate;
2) applying a silicon oxide or silicon nitride layer or layers as needed to prevent pinholes which may result from a single layer, which may be applied using a chemical vapor deposition method;
3) applying a photoresist, which may be a UV sensitive mask or an ebeam mask;
4) exposing the photoresist, wherein the exposing may use a standard photomask, or may use a direct write method such as an ebeam;
5) developing the photoresist;
6) applying a metal layer, which may be applied utilizing a sputtering method, which may include adhesion layers above and or below the metal layer, as shown in the top view of Fig 3A;
7) removing the undesired portions of the metal layer, which may be removed using a lift off method;
8) applying a dielectric layer, which may be a silicon oxide or a nitride layer, and may be applied with a thickness which may be a desired electrode gap spacing as shown in the bottom view of Fig. 3A;
9) applying a photoresist, which may be a UV sensitive mask or an ebeam mask;
10) exposing the photoresist, wherein the exposing may use a standard photomask, or may use a direct write method such as an ebeam;
11) developing the photoresist;
12) applying a metal layer, which may be applied utilizing a sputtering method, which may include adhesion layers above and or below the metal layer;
13) removing the undesired portions of the metal layer, which may be removed using a lift off method as shown in Fig. 3B;
14) Applying an oxide layer, which may be a silicon oxide, or other oxides or dielectrics as described herein, and may be thicker than the thickness of the metal layers;
15) planarizing the surface, which may expose the desired portions of the electrode structure, and may be effectuated using a CMP method as shown in Fig 3C;
16) applying a dielectric, which may be a silicon nitride or silicon oxide layer, which may be applied using a chemical vapor deposition method;
17) applying a photoresist, which may be a UV sensitive resist or an ebeam resist;
18) exposing the photoresist, wherein the exposing may use a standard photomask, or may use a direct write method such as an ebeam;
19) developing the photoresist;
20) performing a dry etch or a wet etch, which may utilize any appropriate etch process or method as described herein, which may form a nanogap between the electrodes, and may form a well like structure above the electrodes; and
21) removing the photoresist, which may comprise step, and may comprise an acetone wash and may comprise an ashing step as shown in Fig. 3D
22) removing adhesion layers form within the nanogap using an SPM (sulfuric acid and hydrogen peroxide) etch or other etchant as appropriate for the selected adhesion layer.
In some embodiments, a wherein a controlled etch may be utilized, a controlled etch may not reach the bottom of a nanogap as shown in Fig. 3D. In some embodiments, thicker metal layers may be utilized, such as greater than 50 nm, greater than 100nm, greater than 150nm, greater than 200nm, greater than 400nm, or greater than 1000nm.
In some embodiments, wherein an adhesion layer may be utilized between a dielectric layer as described in step 8 above and a metal layer as described in step 12 above, enhanced etch rates may occur in conjunction with some adhesion materials, such as metal adhesion layers. In some embodiments it may therefore be desirable to apply such an adhesion layer in only some regions, for example masking the adhesion layer from those areas which might be exposed to a wet etch, thus preventing the wet etch from being able to have enhanced etch rate.
In other embodiments wherein a gap may be etched to the bottom and may expose stray nanoparticles which may be formed during the formation of a first metal layer, a solution which may have weak gold etching capabilities may be utilized to remove and or reduce the size of any stray metal nanoparticles which have been formed, while removing a small amount of metal from the exposed surfaces of the electrodes.
Such a structure is shown in Fig. 3E, which shows a cross section of a single sensor, in Fig 3F which shows a close-up view of a nanogap and two opposing electrodes, in Fig. 3G which shows a top well structure in the top oxide layer and two electrodes with a nanogap between with crystal grains being apparent in the electrodes, Fig. 3H which shows a number of sensors and metal interconnects, and in Fig. 3I which shows cross section of such a structure at different zoom levels.
In other cases, which may be utilized in order to improve orientation of crystal grains, and which may result in having opposing 111 crystal planes as opposing surfaces of electrodes in electrode gaps, wherein an initial layer may be a dielectric layer, upon which the first electrode forming metal layer may be formed, and thence the gap spacing dielectric, and then the second electrode forming metal layer, resulting the cross sectional view shown in Fig. 3J, wherein both electrodes are formed in the same depositional direction from the a face opposing the active surface of the first electrode, to the active surface of the first electrode, to the intermediate gap spacing dielectric, and then the active surface of the second electrode and finally the inactive second surface of the second electrode opposite the active surface area of the second electrode. A dielectric is then deposited, and the structure is planarized, resulting in the structure shown in cross section in Fig. 3K.
In some cases, in order to better center an enzyme, polymerase or other moiety which may be utilized as a part of a measurement or a moiety which may be a size of a moiety used as a part of a measurement, and wherein it may be desirable to prevent steric hindrance in the function of an enzyme, polymerase or other moiety, it may be desirable to create one or more layers over active surfaces of electrodes, which may be longer (thicker) than a SAM which may be utilized as a part of a later measurement. The length (or thickness) of a layer, which may be a metal layer which may be formed by electroplating, or a dielectric layer, or a SAM layer, may be formed prior to binding or attachment of an enzyme, polymerase, or other moiety used as a part of a measurement process; an enzyme, polymerase or other moiety may thence be bound or attached, for example to a dielectric layer which may form a gap spacing between electrodes, and an enzyme, polymerase or other moiety may thus be spaced away from electrodes; the layer used to space an enzyme, polymerase or other moiety from electrodes may then be removed, and if needed or desired, a SAM may thence be bound to electrodes.
In other cases, a structure may be formed in which may utilize a vertical electrode structure, rather than a horizontal electrode structure as described heretofore. For such a structure and as shown in Fig. 3L, first an oxide layer may be deposited, then a first electrode metal layer, then a gap spacing dielectric layer, then a second electrode metal layer, and then a covering dielectric layer.
Then as shown in Fig 3M, an etch pattern is formed which may cut vertically through the top dielectric, the second electrode metal layer, the gap spacing dielectric layer, and may cut through a portion or all of the second electrode metal layer, which etch may be performed using an ion milling process or any other appropriate anisotropic etch process. Then as depicted in Fig. 3N a wet etch may be performed which may preferentially etch a gap spacing dielectric, thereby forming electrode structures with opposing 111 crystal planes.
In other cases, a damascene or dual damascene process may be utilized; starting with a planarized substrate; applying an oxide layer, which may be applied using a chemical vapor deposition method; forming a patterned oxide layer with an opening for a desired metal volume may be formed and a metalization layer formed over the oxide layer. A CMP process may be utilized to remove excess metal leaving a structure as shown in Fig. 3O. The patterned oxide layer may then be removed, leaving the structure shown in Fig. 3P. A spacer layer, which may be a silicon nitride layer, may then be applied over the structure as shown in Fig. 3Q. A new patterned oxide layer may then be formed, wherein an opening is formed next to and over the first metal volume as shown in Fig. 3R. An additional metal layer may then be formed, including in the opening left in the second patterned dielectric layer as shown in Fig. 3S. The structure may then be planarized as shown in Fig. 3T. A third patterned oxide layer may then be formed using chemical vapor deposition followed by applying a resist layer and patterning the resist layer, and thence using a dry etch leaving a structure as shown in Fig. 3U. A photo resist may again be applied, a wet or dry etch may be utilized to form a structure as shown in Fig. 3V.
In some embodiments wherein a smother surface may be desired than that which may be achieved using a dry etch, a pair of electrodes and associated nanogap may be fabricated utilizing a siliciding approach as shown in Figs. 6A or a gap dielectric first approach as shown in 6B.
Initial steps for fabrication of a device as shown in Fig. 6A may be similar to that described hereinabove, wherein a substrate may have one or more dielectric layers deposited thereupon. Rather than directly depositing a metal layer upon the dielectric layers, a crystalline (epitaxial) or polycrystalline silicon layer may then deposited upon the dielectric layers. Alternatively, the substrate may be a silicon on insulator (SOI) waver.
The silicon layer is then patterned using an appropriate lithographic process, and may thence be etched, wherein the etch method may be a dry or wet etch as described hereinabove. A silicon nitride layer may then be applied over the wafer.
A polysilicon layer may then be deposited, and the resulting structure may be subjected to a CMP process as described hereinabove.
A dielectric may then be applied and patterned using an etch process which etches the dielectric, but does not significantly etch the polysilicon or silicon layers, or the silicon nitride layer, forming a recessed region. The polysilicon and/or silicon layer(s) may be purposely etched to create a recess needed to accommodate the volume expansion and maintain flatness of the surface after silicidation.
A layer of platinum, titanium or other appropriate metal may then be placed in the recessed region, and reacted with the poly silicon and silicon layers using a RTA (rapid thermal annealing) process, whereby a silicide may be formed from the silicon and platinum, titanium or other appropriate metal. Any remaining metal may then be removed.
An oxide layer with associated well may be formed, and the silicon nitride layer may be etched as described hereinabove.
In other embodiments as illustrated in Fig. 6B, in manner similar to that of the process described in association with Fig. 6A, a substrate may be fabricated with a dielectric layer(s) with a top layer of crystalline silicon.
The crystalline silicon may then be patterned using a dry etch or wet etch using, as an example tetramethylammonium hydroxide, KOH or other etchant which may etch along the crystal planes in silicon.
A layer of gold or other metal as desired for an electrode structure may then be applied and patterned as desired.
A CMP process as described hereinabove may then be performed to planarized the surface.
An oxide layer with associated well may be formed, and the gap forming crystalline silicon layer may be etched as described hereinabove.

Sensor electronics
Since an array of sensors may be made as an integrated semiconductor device in the present disclosure, it presents great advantages in terms of accuracy, integration and scaling. In some cases a high data bandwidth may not be required, particularly for a system utilizing a synchronous chemistry method. A system chip may be massively parallel and only sensors that register an incorporated nucleotide may be read out. A chip may initially be mapped to determine which sensors are providing useful data, and a map, which may exist in a flash memory on a chip, or may exist elsewhere as a part of other portions of a system. This makes a system throughput, including data throughput effectively much higher, and may aid in making calibration and accuracy very reliable. In some cases, a single measurement may be used. In some cases, an incorporated or bound labeled nucleotide may be measured multiple times until a desired accuracy is achieved.
In some cases, a sensor may be utilized to measure binding and or incorporation kinetics, so that epigenetic information may be determined as a part of a sequencing process, which may require reading a sensor multiple times, and potentially at a higher frequency than might otherwise be required. In such cases, only a portion of a chip may be utilized at a time, or a smaller chip may be utilized in accordance with a maximum data output capability.
In some cases, a sensor may be associated with a local amplifier, such as a 4T circuit, similar to that used in a CMOS imaging sensor. In some cases, a capacitor may be used to integrate a current produced by a tunneling electrode pair. A capacitor may serve to average variations due to binding and release of a label from an electrode pair. A capacitor may serve to average variations in binding locations which may cause variations in a magnitude of current produced by an electrode pair, as well as averaging a background, which may result from direct tunneling between electrodes, and or between SAM constituents, and or as a result of other moieties which may be transiently bound such as a target DNA, unbound nucleotides or other molecules which may be intended parts of a system, or other contaminants. Such an averaging capacitor may be useful to improve signal to noise, and or to allow a longer time between measurements than would otherwise be possible without a capacitor, while retaining charge from tunneling current.
In cases where a current combined with an integration time may be larger than may be desirable for a size and voltage associated with a charge integrating capacitor, a negative gain may be utilized as a part of an amplifier associated with each sensor or with a capacitor. Negative gain may be useful if e.g., significant variation in binding time, position may be a part of a measurement, or a long time is desired for other reasons between measurements. As shot noise may not be anticipated to play a significant role in a measurement, an increase in shot noise, which may result from a negative gain, may cause an insignificant decrease in signal to noise for a sensor.
In some cases, a gap size may be greater than or equal to about 5, 6, 7, 8, 9, 10, 15, 20, 30 or more nm or more. Such a gap size may provide additional advantages such as ease of manufacturing and greater tolerance to a size of the gap. In such cases, a tunneling label or tunneling and hopping label may be configured to be larger than the gap size so that an angle of a bound tunneling label with respect to the surface of the first electrode opposing the second electrode, may be 5-10 degrees, 11-20 degrees, 21-30 degrees, 31-40 degrees, 41-50 degrees or more than 51 degrees.. For instance, a 9nm-gap may be used with a label of double-stranded DNA of about 30 base pairs or greater. A 12 nm-gap may be used with a label of double-stranded DNA of about 40 base pairs. A 20nm-gap may be used with a label of double-stranded DNA of about 60 base pairs. A gap size may be configured to fit commercially available or readily constructible DNA oligos of specific lengths.
In some cases, a bias voltage may be turned off for most of a run while sequencing a polynucleotide. This may help minimizing molecules sticking or adsorbing to electrodes due to electrostatics which in turn could cause artifacts. In some cases, a bulk solution potential may be modified during a part of a run to minimize molecules sticking or adsorbing to electrodes. In some cases, a background signal (which may be due to an ion current) may be minimized due to a small exposed electrode metal surface area. In some cases the exposed metal surface area of each sensor may be less than 1,000,000 nm², less than 400,000 nm², less than 100,000 nm², less than 40,000 nm² or less than 10,000 nm². This may improve a signal to noise associated with measurement of tunneling current. A background signal may be determined form sensors which may not have bound enzymes, and may thus not have signals. In some cases, an electronic tag may be chosen in a way to optimize a tunneling current. A size of the molecule may be chosen to be slightly longer than a gap between two tunneling electrodes, which may include a tolerance associated with fabrication of the gap, or may be chosen to be slightly longer a binding position associated with SAM(s) bound to the tunneling electrodes, which may take into account variation in binding location of the SAM(s) on electrodes and or variation in a size of a gap between electrodes.
In some cases, a bias voltage may be used between two tunneling electrodes of a pair of tunneling electrodes wherein one electrode of a pair may have a positive voltage and the other electrode of a pair of electrodes may have a negative voltage with respect to each other.
In some cases, a single volume may be utilized as a part of a single chip, so that any input fluids may interact with any of electrode pairs on a chip. In other cases, several volumes which may be fluidically separate may be provided, so that different fluids, which may comprise different samples, may be introduced to or through any fluidically separate volumes. Valving may be provided integrally as a part of a chip design, or multiple input and output ports may be provided. In some cases, different parts of a chemistry may be performed in different volumes, so that a single chip may take data for a greater percentage of time. For example if four fluidic steps are required, each taking a minute, and a time needed to read out a volume is a minute, then five fluidic volumes may be provided, so that one volume may take data, and four other volumes may each be performing different fluidic deliveries. After a minute has transpired, each volume may then begin a different task. Thus data may be produced continuously.
In some cases, one or more reference electrodes may be supplied as a part of a chip so that a bulk fluid potential may be controlled with respect to a potential of electrodes of electrode pairs. Reference electrodes may be true reference electrodes, quasi reference electrodes, counter electrodes, auxiliary electrodes, or any combination thereof. In some cases, one or more electrodes may be placed outside a chip, for example through a fluidic line which interacts with a fluidic volume with electrode pairs.
In some cases, a reference and or counter electrode, or pseudo reference electrode may be utilized in a manner such that it effectively acts as a gate electrode, wherein, for example a tunneling label which may have different conductances depending upon an oxidation state, and a reference and or counter electrode, or pseudo electrode may be utilized to oxidize or reduce a label, particularly a portion of a label which may be bound to a bias or sense electrode; an oxidation or reduction of a label may result in a change in a tunneling current amplitude.

Chip fluidics
In some cases, a chip may have a single common sample volume, so that a single input fluid, which may comprise input samples, may interact with all sensors of a chip. Alternatively, a chip may have multiple volumes associated with different sets of sensors, and may have a valving mechanism or multiple input ports, so that different input fluids, which may comprise different input samples, may interact with different sets of samples.
In some cases, a single input fluid may comprise multiple different samples. The different samples may be differentiated as a result of having different bar codes associated thereto, or may have different cleavable tunneling labels affixed thereto. In some cases, different samples may be introduced at different times. Different samples may occupy a portion of different chip area while leaving other sensors available for a sample which may be introduced at a later time. After introduction of a subsequent sample, additional measurement(s) may be made to measure labels bound or associated with bound moieties. Additional sensors with bound moieties may be associated with the newly introduced samples and sensors which were previously associated with a previous sample may still be associated with a same sample to which a previous sensor was associated. In some cases, all sensors in association with a chip may undergo different steps at a same or at different times. In some cases, samples may be introduced at different times, but other fluids may be introduced to all sensors at a same time.
In some cases, a chip may have multiple input ports associated with different internal volumes, and a system may accommodate multiple chips simultaneously. Different fluids may be introduced to different volumes at different times. Different volumes may be different volumes of a single chip, different volumes may be on different chips. Different volumes may be different volumes associated with multiple chips, thereby allowing different steps in a process to occur at different times in the different volumes, which may for example, allow different volumes to have measurements done at different times, while other volumes may have other different steps occurring while measurements are occurring. By so doing, measurements may occur effectively continuously, thereby allowing analog to digital converters, integrators, digital communications channels, or any other portion of the electronics, which may otherwise be a limiting factor to the throughput of the system to be fully utilized, and not limited by waiting for a chemistry, biochemistry, wash or other step or steps to occur. In some cases, a coordinated set of measurements may be effectuated, whereby the measurements may not be effectively continuous, but may occur over an increased percentage or duty cycle in comparison to where all measurements of different areas were performed, prior to proceeding to a different step, which may be a chemistry step, a biochemistry step, a wash step, or any step other than a measurement step.
[Rectified under Rule 91, 23.10.2018]
In some cases as shown in Fig. 3X, a chip may have multiple fluidic channels 370, which may be interconnected such that a single sample may be utilized, or may have separate fluidic ports (not shown) so that different samples may be utilized in different sections of the chip. Sense circuitry 360, which may include integrating capacitors, current mirrors and analog to digital converters may be placed in sections between fluidic regions which may have two sets of 100 rows or some other appropriate number of rows, such that each region between fluidic channels may support a cover to the fluidic channel, and permit a much lower fluidic volume to be utilized. Row select circuitry 380 may be positioned to one side, while digital input output circuitry 390, which may comprise one or more LVDS (Low Voltage Differential Signals) interface may be utilized.
In some cases, a system and associated chemistry may be configured for comparatively slower but more accurate detection. A system of this case may be made to be massively parallel to improve throughput, such as utilizing a chip with 10 million (M), 20M, 30M, 40M, 50M, 60M, 70M, 80M, 90M, 100M, 200M, 300M, 400M, 500M, 600M, 700M, 800M, 900M, 1billion (B), 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B,10B, 15B, 20B or more sensors.
In some cases, different readout schemes may be employed for different regions of a device, or at different times in one or more regions of a device. In some cases, one type of detection chemistry may be utilized in one or more regions or at one or more times, while a second or multiple additional chemistries may be utilized in other portions of a chip.
In some cases, a field-programmable gate array (FPGA) or other programmable logic within a chip may be used to permit changes in readout pattern and or timing.
In some cases, a storage device may be used to store positions of active sites, where memory may be used as part of readout process to determine which locations are active. A storage device may be selected as a flash memory or a ram. A storage device may be used by an onboard microprocessor, or may be used in conjunction with an FPGA or other programmable logic in order to determine a pattern of sensor location to read and or a pattern of locations to not read. In some embodiments, different patterns may be utilized in different regions, whereby, different timings may be utilized between reads, for example when one region is utilized for one chemistry method reads, and another region is used for a different chemistry method reads.

Tunneling and Electrochemical Labels
As provided herein, a tunneling label may be a compound through which a tunneling current may provide a large number of electrons from a single polymer molecule with a low background level. For example, in 1 second, 1 nA of current may generate 6.2 M electrons. In the presence of a background of 5 pA, this may result in a shot noise limit S/N level of > 1000:1.
In some cases, a tunneling label may provide currents corresponding to conductances of less than 10-11, 10-11 to 10-10, 10-10 to 10-9, 10-9 to 10-8, or 10-8 to 10-7 or more Siemens. Thus with nominal bias potentials such as less than 10mV, 10mV to 100mV, 100mV to 250mV, or greater than 250mV, significant currents may be created such that shot noise, may be considered to be insignificant in many systems.
In some cases, electrons or holes interacting with a tunneling label may tunnel into a tunneling label or may tunnel through, and may hop through a tunneling label. Electrons or holes may tunnel through part of a tunneling label, and hop through other parts of the tunneling label. Electrons or holes may repeatedly transition between some regions of a tunneling label wherein tunneling may occur, and regions wherein hopping may occur. An exemplary label 402 is shown in use with a pair of electrodes 401A and 401B in Fig. 4.
In some cases, electrochemical labels may be utilized. Electrochemical labels may be utilized such that a bound nucleotide may produce a current as a result of oxidation and reduction at two different electrodes of an electrode pair, which may be maintained at a voltage appropriate for the oxidation and reduction. In some cases, a same electrochemical label may be utilized for more than one type of nucleotide. A difference in diffusion may result in a different average current being generated for the different nucleotide types, as a result, for example, of different diffusion rates for the different nucleotides. Different diffusion rates may result from associating a same electrochemical label with different additional moieties. Different additional moieties may be electrochemically inactive. Different additional moieties may slow diffusion of an electrochemical label which may be linked to a nucleotide.
In some cases, different tunneling and or electrochemical labels may be utilized, and a current associated with an electrode pair may be measured at different times. A different potential may be utilized for one or both electrodes with respect to a bulk solution potential, such that currents associated with different electrode pairs may be used to differentiate different electrochemical labels.
In some cases, more than one electrode pair may be utilized. More than one electrode pair may be associated with an enzyme binding site, such that more than one set of electrode pairs may be accessible by labeled nucleotides. Labeled nucleotides (e.g., labels associated with nucleotides) may be bound by an enzyme. Different electrode pairs may have one or both electrodes at different potentials with respect to a bulk solution, such that currents associated with different electrode pairs may be used to differentiate different tunneling and or electrochemical labels.
In some cases, a combination of multiple sets of different electrodes may be used, such that such that currents associated with different electrode pairs may be used to differentiate different tunneling and or electrochemical labels. Different nucleotides which may have a same tunneling and or electrochemical label may further comprise one or more additional moieties, such as nucleic acids and or proteins. The one or more additional moieties may or may not be the same. In some cases, one or more additional moieties may be different such that a same electrochemical label may have different diffusion rates and thus different currents.

Sensor chip: general usage
In some cases, systems and methods of the present disclosure may utilize a chip. A chip may comprise a reusable chip. A chip may have at least some of target analytes, enzymes, and SAMs removed between different runs. Removal may be effectuated by e.g., raising temperature, decreasing ion concentration, chemical cleaning, plasma cleaning, enzymatic cleaning, electropotential cleaning, any other type of cleaning procedure, or combinations thereof. Such cleaning may include nucleases, proteinases such as proteinase K. Cleaning may comprise changes of potential between electrodes and bulk solution, such that thiolated SAMs may be removed, or any other methods may be utilized.
In some cases, a system as described herein may be used for DNA sequencing, RNA sequencing, and may measure or interrogate each base more than once depending of the application and if deemed helpful for overall accuracy in a particular measurement. In some cases, a system may use a single sample to perform one or more tasks, including sequencing DNA, sequencing RNA, determining epigenetics of DNA with or without chemical modification, determining epigenetics of RNA with or without chemical modification, determining copy numbers of DNA which include determination of aneuploidy, determining expression level of different transcripts, determining the presence and quantity of different proteins, and determining the presence and quantity of other biological molecules of interest.
In some cases, a system may comprise a chip with electrode structures, and may not comprise an amplifier or row and or column select associated with different sensors., Circuits needed for measurement may not be a part of a chip, but may be a part of an additional chip or circuit. In other cases, local amplifiers, and optionally row and or column select circuits may comprise a part of a chip, while integration, double correlation, analog to digital conversion and digital input output ports may not be a part of the chip, but may be a part of an additional chip or circuit.
While preferred embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

A method comprising:
a. using a polymerase adjacent to two electrodes on a substrate to bind a nucleotide complementary to a base being interrogated of a sample nucleic acid, the nucleotide having a tunneling label attached thereto;
b. measuring a tunneling current between the two electrodes caused by the localization of the tunneling label to the two electrodes; and
c. identifying a nucleotide from the binding of the complementary base to the base being interrogated, as a function of the tunneling current measurement.
The method of claim 1 wherein the tunneling label is slightly larger than the size of a gap between the two electrodes.
The method of claim 2 wherein the tunneling label comprises a zwitterionic compound.
The method of claim 1 wherein the tunneling label comprises a nucleic acid strand.
The method of claim 4 wherein the nucleic acid strand is more than 10 bases long.
The method of claim 4 wherein the nucleic acid strand has a double stranded portion and a single stranded portion.
The method of claim 1, further binding the polymerase to a dielectric between the two electrodes.
The method of claim 1, further binding the polymerase to one of the two electrodes.
The method of claim 1, wherein the gap has a wider portion that is greater than the width of the polymerase and a smaller portion which is smaller than the size of the polymerase.
The method of claim 1, wherein a self assembled monolayer is bound to the electrodes.
The method of claim 10, wherein the self assembled monolayer is bound by a thiol to the electrodes.
The method of claim 4 or 10, wherein the self assembled monolayer comprises at least in part a nucleic acid which may bind to at least a part of the tunneling label nucleic acid strand.
The method of claim 12, wherein said binding is transient.
The method of claim 13, wherein said transient binding may occur more often than would otherwise occur without the high local concentration due to binding of said nucleobase with a tunneling label attached thereto.
The method of claim 1, wherein said tunneling label is bound to the 5' of the ribose of the nucleobase.
The method of claim 1, wherein the tunneling label is bound to the base of the nucleobase.
The method of claim 1, wherein said nucleobase further comprises a terminator.
The method of claim 18, wherein said terminator is bound to the 3' of the ribose.
The method of claim 15, wherein said method is a synchronous chemistry method.
An apparatus comprising:
a. two electrodes disposed on a substrate separated by a non-conductive gap
b. the two electrodes and the gap configured to accommodate a polymerase in the vicinity of the two electrodes
c. the two electrodes and the gap further configured for detecting a tunneling current due to at least one of incorporation and binding of a nucleotide with a tunneling label complementary to an interrogated base of a sample nucleic acid.
The apparatus of claim 20, further configured for the polymerase to be disposed in the non-conductive gap, wherein said gap is etched down between said electrodes to a depth of 10nm or more.
The apparatus of claim 21, further configured such that the non-conductive gap size is smaller than a size of the polymerase and configured for the polymerase to be disposed over the non-conductive gap, wherein said non-conductive gap may be etched to a depth of a 10 nm or less.
The apparatus of claim 20, where in the non-conductive gap has a wider portion and a narrower portion.
A method comprising:
a. using a polymerase adjacent to two electrodes on a substrate to bind a nucleobase having an tunneling label attached thereto, complementary to an interrogated base of a sample nucleic acid
b. measuring a combination of at least one of tunneling current and hopping current between the two electrodes caused by the localization of the tunneling label to the two electrodes
c. identifying a matching nucleobase on the single stranded portion of the polynucleotide based on electron current measurement.
A method for finding biological information associated with a nucleic acid polymer, the method comprising:
a. localizing the nucleic acid polymer between two electrodes on a substrate, wherein localizing is effectuated by hydrogen binding
b. applying a bias voltage between the two electrodes
c. measuring a tunneling current between the two electrodes
d. determining the biological information based on the conductance
The method of claim 25 wherein the length of the nucleic acid polymer is less than or equal to the size of a gap between the two electrodes.
The method of claim 25 wherein the length of the nucleic acid polymer is larger than the size of a gap between the two electrodes and wherein a portion of the oligo is hybridized onto either or both of the electrodes, and wherein a portion of the oligo spans a gap between the two electrodes.
The method of claim 25 wherein a certain measured conductance indicates methylation of a certain site on the oligo.