EP3607454A4 - General-purpose parallel computing architecture - Google Patents

General-purpose parallel computing architecture Download PDF

Info

Publication number
EP3607454A4
EP3607454A4 EP18780648.4A EP18780648A EP3607454A4 EP 3607454 A4 EP3607454 A4 EP 3607454A4 EP 18780648 A EP18780648 A EP 18780648A EP 3607454 A4 EP3607454 A4 EP 3607454A4
Authority
EP
European Patent Office
Prior art keywords
general
computing architecture
parallel computing
purpose parallel
architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18780648.4A
Other languages
German (de)
French (fr)
Other versions
EP3607454A1 (en
Inventor
Paul BURCHARD
Ulrich Drepper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Goldman Sachs and Co LLC
Original Assignee
Goldman Sachs and Co LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/481,201 external-priority patent/US11449452B2/en
Application filed by Goldman Sachs and Co LLC filed Critical Goldman Sachs and Co LLC
Publication of EP3607454A1 publication Critical patent/EP3607454A1/en
Publication of EP3607454A4 publication Critical patent/EP3607454A4/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/047—Probabilistic or stochastic networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/084—Backpropagation, e.g. using gradient descent
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/088—Non-supervised learning, e.g. competitive learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/01—Probabilistic graphical models, e.g. probabilistic networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/082—Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
EP18780648.4A 2017-04-06 2018-04-04 General-purpose parallel computing architecture Pending EP3607454A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/481,201 US11449452B2 (en) 2015-05-21 2017-04-06 General-purpose parallel computing architecture
PCT/US2018/026108 WO2018187487A1 (en) 2017-04-06 2018-04-04 General-purpose parallel computing architecture

Publications (2)

Publication Number Publication Date
EP3607454A1 EP3607454A1 (en) 2020-02-12
EP3607454A4 true EP3607454A4 (en) 2021-03-31

Family

ID=63712341

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18780648.4A Pending EP3607454A4 (en) 2017-04-06 2018-04-04 General-purpose parallel computing architecture

Country Status (6)

Country Link
EP (1) EP3607454A4 (en)
JP (2) JP7173985B2 (en)
CN (1) CN110720095A (en)
AU (2) AU2018248439C1 (en)
CA (1) CA3059105A1 (en)
WO (1) WO2018187487A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112068942B (en) * 2020-09-07 2023-04-07 北京航空航天大学 Large-scale parallel system simulation method based on single-node simulation
CN114356541B (en) * 2021-11-29 2024-01-09 苏州浪潮智能科技有限公司 Configuration method, device and system of computing core and electronic equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130036426A1 (en) * 2010-04-30 2013-02-07 Nec Corporation Information processing device and task switching method
US20150261535A1 (en) * 2014-03-11 2015-09-17 Cavium, Inc. Method and apparatus for low latency exchange of data between a processor and coprocessor
US20160342568A1 (en) * 2015-05-21 2016-11-24 Goldman, Sachs & Co. General-purpose parallel computing architecture

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US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
JPH0535867A (en) * 1990-09-06 1993-02-12 Matsushita Electric Ind Co Ltd Image processor
JPH05242065A (en) * 1992-02-28 1993-09-21 Hitachi Ltd Information processor and its system
JP2561028B2 (en) * 1994-05-26 1996-12-04 日本電気株式会社 Sidelobe canceller
US6829697B1 (en) * 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
TWI234737B (en) * 2001-05-24 2005-06-21 Ip Flex Inc Integrated circuit device
US8756264B2 (en) * 2006-06-20 2014-06-17 Google Inc. Parallel pseudorandom number generation
WO2009146267A1 (en) * 2008-05-27 2009-12-03 Stillwater Supercomputing, Inc. Execution engine
US8949577B2 (en) * 2010-05-28 2015-02-03 International Business Machines Corporation Performing a deterministic reduction operation in a parallel computer
JP6058221B2 (en) * 2014-05-30 2017-01-11 三菱電機株式会社 Steering control device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130036426A1 (en) * 2010-04-30 2013-02-07 Nec Corporation Information processing device and task switching method
US20150261535A1 (en) * 2014-03-11 2015-09-17 Cavium, Inc. Method and apparatus for low latency exchange of data between a processor and coprocessor
US20160342568A1 (en) * 2015-05-21 2016-11-24 Goldman, Sachs & Co. General-purpose parallel computing architecture

Also Published As

Publication number Publication date
JP2020517000A (en) 2020-06-11
CN110720095A (en) 2020-01-21
JP7173985B2 (en) 2022-11-17
AU2018248439B2 (en) 2021-06-03
AU2021203926B2 (en) 2022-10-13
AU2018248439C1 (en) 2021-09-30
EP3607454A1 (en) 2020-02-12
AU2018248439A1 (en) 2019-10-17
AU2021203926A1 (en) 2021-07-08
WO2018187487A1 (en) 2018-10-11
CA3059105A1 (en) 2018-10-11
JP2023015205A (en) 2023-01-31

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