EP3568757A1 - Verfahren zur erzeugung von quellcode - Google Patents
Verfahren zur erzeugung von quellcodeInfo
- Publication number
- EP3568757A1 EP3568757A1 EP18737311.3A EP18737311A EP3568757A1 EP 3568757 A1 EP3568757 A1 EP 3568757A1 EP 18737311 A EP18737311 A EP 18737311A EP 3568757 A1 EP3568757 A1 EP 3568757A1
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- European Patent Office
- Prior art keywords
- block
- blocks
- variable
- region
- variables
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/43—Checking; Contextual analysis
- G06F8/433—Dependency analysis; Data or control flow analysis
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- G06F8/30—Creation or generation of source code
- G06F8/35—Creation or generation of source code model driven
-
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F8/41—Compilation
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
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Definitions
- the invention relates to the generation of executable code from a block diagram, in particular for the programming of control devices.
- Controllers are used in a variety of applications to detect and / or by means of physical quantities of a process
- control devices to act on a process; For example, it may be a Antibiockierregeiung a braking operation.
- the time constants determining the dynamic behavior of the process often require cycle times of 1 ms or shorter, so that a real-time capability of the control unit is required.
- control devices often have microcontrollers with low memory and limited computing power, which is why the size and efficiency of the executable code is of great importance.
- control strategies are often based on models in a computing environment such as
- models may be block diagrams that include blocks that perform operations such as calculations, where a block may compute an output signal from, for example, multiple input signals.
- block diagrams are executed cyclically, with all blocks held permanently in memory and each block executed once per time step.
- a block may apply one or more operations to input signals from the last step to generate output signals of the current step. From the models can by means of a code generator directly source code for the
- variable in several blocks can lead to unwanted side effects, in particular by a change in the data flow in the source code.
- Block diagram comprises a model of a dynamic system with at least one signal connection between two blocks and can be executed to simulate the dynamic system.
- the block diagram is defines at least one region in which one or more blocks reside, the block diagram comprising a first block and a second block, the first block having a first block variable and the second block having a second block variable, each block variable of the block diagram having an identifier, wherein the identifier of the first block variable is compared to the identifier of the second block variable, checking to see if the first block and the second block are in the same region, and wherein the first block variable and the second block variable are implemented in the source code as a single variable if the identifiers
- Data or signals can be transmitted via a signal connection;
- a first block outputs a value or, depending on the definition, a plurality of associated values, and a second block receives them and takes them into account in the determination of one or more associated output values of the second block.
- Signals can be scalar
- Contain variables and / or structured data types such as arrays, as is the case for example with a bus.
- Block variables can be defined explicitly in the block or generated automatically, for example by means of a signal connection.
- the identifiers or names of block variables can be predefined or defined on the basis of generation rules or generation rules with or without predetermined evasion behavior.
- the identifier may include the name of the port in the block from which the signal originates.
- block diagrams are hierarchically defined, wherein a higher-level block may comprise a plurality of lower-level blocks, with lower-level blocks associated with a higher-level block. Conveniently, therefore, each block belongs to one
- Blocks can be defined by associated blocks in subordinate levels or can be simple blocks without substructures.
- a hierarchical structure of the block diagram improves the overview.
- the block diagram includes one or more
- Definition blocks wherein a region is defined on the basis of a definition block such that the block comprising the definition block of the
- next highest level and all blocks associated with this comprehensive block lie in the region.
- the comprehensive block of the next higher level can be designed in particular as a subsystem.
- blocks that are not in a region spanned by a definition block are assigned to an additional region such that each block of the
- Block diagram is located in a region. Alternatively, it may also be provided that only those blocks which are in one of a definition block
- Definition blocks can be dedicated only to the definition of a region. However, it may also be provided to assign the property of a definition block to certain semantic blocks at the same time. In particular these may be function blocks, which thus indicate that the surrounding subsystem is to be implemented in the source code as a function and preferably define further properties of the function. Since a function forms a unit in the source text, it is expedient, for example for reasons of clarity, to limit the grouping of variables to this unit.
- a runnable block for defining a runnable as a stand-alone subunit of the software component can also be assigned the property of a definition block.
- the block diagram comprises at least two definition blocks comprised of a common higher level block, wherein a first definition block is located in a first level and a second definition block is located in a second level subordinate to the first level, the first block comprising a first level defines the first region and wherein the second block defines a second region such that the block comprising the second definition block is the level higher than the second level and all blocks associated with that block are in the second region.
- the second level can be arranged a plurality of hierarchy levels below the first level. This allows a more targeted control over which regions variables can be grouped together.
- first definition block there may be at least two types of definition blocks, wherein one type of excellent definition blocks is defined, and in the case that the first definition block is an excellent definition block, the first region and the second region are combined into a common region, and otherwise first region and the second region are treated as separate regions.
- a functional block or a runnable block may be considered an excellent one
- Definition block are defined. By splintering the clearly circumscribed uniformity of a function or a runnable is prevented, the optimizability of the block diagram is maintained.
- the identifier of a block variable prefferably be determined on the basis of an evaluation of at least one generation rule, the generation rule including the identifier of the block variable based on the block of a higher level in which the block comprising the block variable and / or on the basis of the region, in which the block variable block is located determined. It is advantageous if the
- the identifier may be at least partially given in the form of a name macro such as $ (Scope) _ $ B.
- the generation rule or the name macro is evaluated at the time of code generation, where $ (scope) is replaced by the name of the region, in particular a comprehensive subsystem, and $ B by the name of the block. In principle, more can
- Name macros or wildcards defined and included in the name of one or more identifiers can also be provided that a fallback rule is assigned to a name macro in each case in order to enable automatic resolution in the case of name collisions.
- escape rules can be assigned to a block or region.
- the identifier can expediently also have a fixed name component. If two block variables have the same name based on the name macros, or if a name collision occurs, different ones can be used
- Dodge rules are applied. For example, it may be provided to supplement the name obtained by evaluating the name macro with a counting component (such as "VarName_a”, “VarName_b”,
- Name equality occurs.
- the name of a region which initially only contains local information on the basis of the name macro, in order to expand context information, For example, prepend a file name or the name of one or more hierarchically superior blocks, such as comprehensive subsystems, to the name of the region.
- the user specifies a possible name component, which in the event of a name collision additionally or instead of one in the
- Name macro defined name component is inserted.
- Dodge rule can check additional constraints, and especially in case of exceeding a given maximum length also include a reduction rule.
- a reduction rule For example, in the case of hierarchically composed names, which contain several consecutive regions, the associated one can be provided
- Block diagram may be present. Conveniently, in the event that there are multiple instances of a block in the block diagram, either an independent region is defined for each instance, or a common function for the instances and a common function for each instance
- the complete content of the library block or the referenced model is not copied, but an instance-independent function of the block is combined with an instance-specific data structure.
- This makes it possible to keep the generated source code very compact.
- it is appropriate to store the data in a structure, which is referenced by a pointer. This allows an arbitrary frequent use of the instructions, with only the data must be multiple times in memory. Thus, the usually limited memory of a controller is less busy.
- the complete content of the library block or the referenced model is not copied, but an instance-independent function of the block is combined with an instance-specific data structure.
- This makes it possible to keep the generated source code very compact.
- it is appropriate to store the data in a structure, which is referenced by a pointer. This allows an arbitrary frequent use of the instructions, with only the data must be multiple times in memory. Thus, the usually limited memory of a controller is less busy.
- the complete content of the library block or the referenced model is not copied, but an instance-independent function of the block is combined
- each block variable has an allowance flag which may be set or not set, and two block variables are implemented in a common variable only if both
- the allowability flag can be set indirectly for one or more variables, for example, by referring back to a definition data collection, in particular by assigning a variable class or a variable
- Variable type that defines one or more properties common to different variables.
- the setting of a mark of admissibility allows a direct influence on the optimization by the user.
- Admissibility marking may be unconditional or may allow optimization only in conjunction with the fulfillment of an additional condition.
- each block variable or the blocks can also be assigned an unconditional additional marking as well as one or more check marks. More preferably, each block variable has at least one check mark which may be set or not set, and two block variables are implemented in a common variable only if the check mark is set in both block variables and additionally
- test condition associated with the checkmark At least one test condition associated with the checkmark is met. Thus, it can be automatically ensured that the optimization in the present model produces meaningful results. It is expedient to check one or more of the following test conditions:
- variable definition is assigned.
- a variable definition can be
- the specification of a basic data type, the minimum and / or maximum value and / or a scaling include. ⁇ Whether the block variables are located at a same specified directed connection.
- a directed connection between two blocks expediently indicates the exchange of signals; Signals may have a scalar data type or be composed of several scalar data types, such as a bus. The signal is transmitted from an output block to one or more destination blocks.
- Block variables fulfill the condition, in particular if one is defined in the starting block and the other in a target block.
- Test condition is assigned, or a check mark several
- Test conditions are assigned, wherein a summarization of variables only takes place if all the test mark associated conditions. There may also be more than one check mark, with each check mark then having one or more test conditions
- one or more parameters can be assigned to a block variable, whereby two block variables only in a common Variable to be implemented if one or more of the following
- the names of block variables are determined by means of generation rules, whereby only those block variables whose names have been determined with the same generation rule are combined.
- At least one block variable is automatically generated based on directed links between blocks, and in the case where a first block is connected to a second block and the second block is connected to a third block, a block variable of the first block for those outgoing from the first block Connection is generated and a block variable of the second block for the connection originating from the second block is generated, the two block variables then being used as a common block
- Variables are implemented in the source code if the first block and the second block are in the same region.
- Block variables of blocks that are in the separation region are always implemented as separate variables in the source code.
- the outermost region may be predefined as a separation region, with definition blocks in subordinate hierarchical levels then defining individual regions in which block variables may be grouped together.
- the invention further relates to a method for configuring a
- control unit wherein the control unit comprises at least one arithmetic unit and preferably has at least one sensor and / or at least one actuator to detect data of a physical process and / or act on this, the method comprising the steps
- the invention relates to a computer program product having a computer-readable storage medium embedded with instructions which, when executed by a processor, cause the computer to perform the
- Processor is adapted to a method according to one of
- the invention relates to a computer system comprising a man-machine interface, a nonvolatile memory and a processor, wherein the processor is adapted to carry out a method according to the invention.
- Figure 2 is a schematic representation of preferably on a
- Figure 3 is a general scheme of generating source code
- Figure 4 is a schematic representation of the review of
- Figure 5 is a schematic representation of an exemplary
- Figure 6 is a schematic flow diagram of a preferred embodiment
- Figure 7 is a detailed embodiment of a block diagram.
- FIG. 1 shows a preferred embodiment of a computer system PC.
- This has a processor CPU, which can be implemented in particular as a multi-core processor, a main memory RAM and a bus controller BC.
- the computer system PC is preferably designed to be operated manually by a user directly, with a GPU via a graphics card
- the computer system further includes a non-volatile one
- Data storage HDD which may be designed in particular as a hard disk and / or solid state disk, and an interface NET, in particular a network interface. Via the interface NET, a control unit ES can be connected. In principle, one or more arbitrary
- Interfaces in particular wired interfaces, on the
- the Interface NET can also be designed wirelessly, in particular as a WLAN interface or according to a standard such as Bluetooth.
- the control unit ES can be designed as a production control unit or as an evaluation board for a target platform. Conveniently, it comprises an interface NET for connection to the computer system PC, a microcontroller MCR with an architecture deviating from the processor of the computer system, a random access memory RAM and a nonvolatile memory NVM.
- FIG. 2 shows a schematic of the software components preferably installed on the computer system PC. These use mechanisms of the operating system OS, for example to access the non-volatile memory HDD or to establish a connection to an external computer via the network interface NET.
- a technical computing environment TCE allows the creation of models and the generation of source code from the models.
- models of a dynamic system can preferably be created via a graphical user interface.
- These may in particular be block diagrams which comprise a plurality of blocks and describe the temporal behavior and / or internal states of a dynamic system. At least some of the blocks are connected via signals, that is, directed connections for exchanging data which may be scalar or compound.
- Blocks can be atomic, providing a predefined functionality in one step. When block diagrams are hierarchical, a plurality of blocks at a subordinate level can describe the structure of a block at a higher level. Conveniently, atomic blocks may then also comprise a plurality of blocks at a subordinate level.
- compound blocks can be subsystems
- Subsystems may have additional properties, such as Implementation in a separate function and / or triggering of the execution of the subsystem via a dedicated signal.
- special blocks may be arranged to match the properties of the
- the computing environment TCE comprises one or more libraries BIB, from which blocks or building blocks for the construction of a model can be selected.
- libraries BIB from which blocks or building blocks for the construction of a model can be selected.
- statements can be entered interactively or through a batch file to perform calculations or to modify the model.
- the computing environment TCE further includes a simulation environment SIM that is adapted to interpret the block diagram to examine the temporal behavior of the system. These calculations are preferably done with high precision floating point numbers on one or more cores of the computer system microprocessor CPU.
- a source code can preferably be generated in a programming language such as C using a code generator PCG.
- a definition data collection DDT expediently contains additional information about the model, in particular about the block variables.
- value ranges and / or scalings are assigned to the block variables to aid in calculating the model with fixed-point instructions. Also desired properties of
- Source codes for example conformity to a standard such as MISRA, can be set or stored in the DDT definition data collection.
- each block variable is assigned to a given variable type and one or more desired properties, such as the permissibility of optimizations such as summarizing variables, are set.
- the code generator PCG preferably evaluates the settings of the definition data collection DDT and takes these into account when generating the source code.
- the definition data collection DDT can have a tree structure or as a simple file in one
- the definition data collection may include a program interface and / or import / export functions.
- the computer system PC has a compiler COM and a linker LIN, which are expediently set up for the generation of binary files executable on a control device ES and / or the computer system PC.
- a large number of compilers can be present
- Figure 3 shows a general scheme of generating source code by means of a code generator.
- the method may be performed entirely by a processor of a preferred embodiment of the computer system PC; However, it can also be provided for execution in a client-server environment with an operating computer and one or more servers connected via a network, wherein in particular computer-intensive steps are performed on the servers.
- a transformation the selected model is transformed from one or more blocks of the block diagram BLD into an intermediate representation IR, preferably one or more
- Hierarchical graphs This can in particular be a data flow graph, a control flow graph or a tree structure.
- additional information from a definition data collection DDT is expediently taken into account or incorporated into the generation of the intermediate representation. This can also include situations in which elements are generated based on information in the definition data collection DDT or properties of elements or settings relevant for code generation, such as
- a second step S2 an optimization, the hierarchical graphs are optimized to the number of required variables and / or a
- Memory consumption such as a stack occupancy, and / or the number of operations or processor instructions and / or the
- This optimization can include a multitude of intermediate steps, in which further intermediate representations between model / block diagram and source code / program text are generated.
- it may be provided to convert a set of original hierarchical graphs into a different set of changed hierarchical graphs in each intermediate step, using one or more optimization rules.
- step Sl Apply transformation of step Sl, especially if they can be performed on a block diagram representation easier.
- step S2 it is in principle possible for several variables generated in step S1 to be combined in step S2, and for several variables of the block diagram to be combined in step S1 in such a way that the first intermediate representation already contains only one variable.
- warnings that are stored in the definition data collection can be used, for example, to influence a compilation of the generated source code or to provide meta-information for other tools, such as calibration information in the ASAP2 format or information for
- Alternate embodiments of the invention may be provided to generate from the block diagram code in a hardware description language or a configuration of a programmable hardware device.
- Figure 4 shows a schematic representation of the verification of the generated source code based on the block diagram.
- a block diagram BLD or a subsystem consisting of three blocks is shown schematically, which has an input port for receiving an input signal and an output port for transmitting an output signal.
- the block diagram can
- the block diagram expediently describe a predetermined or desired behavior of a control program. If the block diagram is executed in the simulation environment not shown here, the behavior for successive time steps is calculated; In particular, the block diagram BLD can be interpreted directly here. From the specification or the intended application, a number of test cases were determined in advance, in particular stimuli STIM as input signals for the control program comprise, wherein the stimuli associated with a corresponding output signal RESP.
- a stimulus STIM is shown in the example shown as a diagram which indicates a specific temporal behavior of the input signal.
- a current value of the stimulus STIM is applied to the input port of the block diagram BLD for a plurality of time steps, and the operations corresponding to the blocks are calculated to be an internal state and / or to determine an output signal of the control program.
- a target response RESPl can be determined in a model-in-the-loop simulation. Since all arithmetic operations are calculated with high accuracy, for example by having variables always of the double data type and thus floating point calculations, the correct behavior of the model can be verified on the one hand and on the other hand this can be
- Simulation result sufficiently accurate to use the stored output signal or the target response RESPL as reference data.
- Code generator PCG source code from blocks of the block diagram corresponding to the control program.
- the generated source code is then compiled with a compiler COM to object code OBJ, which expediently contains instructions for the processor of the target system.
- object code is transferred from a linker to an executable file in the
- settings may be a conversion of the model operations in fixed-point representation, which also include a corresponding scaling, or in general transformations are used to reduce the computational effort to enable real-time execution even on lower performing hardware such as a microcontroller of an embedded system ES.
- a software-in-the-loop simulation in which the target system corresponds to the computer system PC, or a
- the executable file with the object code OBJ is supplied with the stimulus STIM during the predetermined execution duration and the output signal of the generated source code resulting from the calculations is recorded in order to obtain the actual response RESP2.
- the set response RESPl of the model-in-the-loop simulation can be found on the
- Computer system are presented simultaneously to the actual response RESP2 of the generated code to allow the user a visual comparison.
- a comparison of setpoint response RESP1 and actual response RESP2 can also be calculated in a comparison program CMP. This allows, for example, the determination of a deviation measure and / or the checking of one or more test conditions, for example the calculation of a pointwise difference between the actual response and the setpoint response and the comparison with a threshold value or a maximum permissible deviation.
- FIG. 5 is a schematic illustration of an exemplary embodiment
- Block diagrams are shown with multiple hierarchical levels, with blocks of a hierarchical level are represented in a rectangular border.
- the blocks BI, B2, B3 and B5 may be atomic or simple or not having shown substructure.
- Block B4 is a composite block whose functionality is defined by blocks in a second (subordinate) hierarchical level E2.
- the shown section of a second hierarchical level E2 comprises a
- Plurality of blocks B2j, j 1..4, a definition block D2 and two ports for exchanging signals with the higher-level hierarchy, an input port P21 and an output port P22.
- the blocks B21, B22 and B24 may be atomic or one or not
- Block B23 is a composite block whose functionality is represented by blocks in a third (lowest)
- Hierarchy level is defined.
- the blocks B31, B32, B33 and B34 may be atomic or have a substructure, not shown. In principle, block diagrams may have any number of hierarchy levels; For better clarity, no further hierarchy levels have been displayed here.
- different blocks can be used as definition blocks; Conveniently, composite blocks, which may be called from other model parts and comprise a contiguous functionality or code unit, should form a self-contained region. These may preferably be functions, in particular at the top level of the block diagram.
- a runnable may conveniently be a standalone region.
- the block comprising the region, or preferably a block arranged in the region can serve as a definition block. It can be provided that dedicated blocks are used to define a region, For example, a scope block is predefined. According to one
- blocks which specify the properties of the function or of the runnable are simultaneously defined as a definition block.
- a defined region comprises all hierarchically subordinate blocks.
- definition block Dl defines a first region
- port blocks it may also be preferred that they are part of the encompassing region.
- Definition block and normal definition blocks is distinguished.
- D2 were an excellent definition block
- normal definition blocks only define a region if there is no excellent definition block in a higher level.
- normal definition blocks define a new region from a standard definition block
- the first region defined by Dl may comprise the blocks BI, B2, B3, B5, while block B4 may form the second region defined by definition block D2 Region then comprises blocks B21, B22 and B24, while block B23 forms the third region defined by definition block D3.
- D2 should be a regular definition block, which defines in particular a subfunction
- D3 should be a regular
- Definition block in particular define a library block without defining its own function.
- the region spanned by a definition block will be denoted by the same name as the definition block.
- block variables of B2, B3, B21, B24, B31 and B33 are each assigned the generation specification or the name macro "$ (Scope) _X"
- code generation for blocks B2, B3 results in variables with the identifier "D1_X” , for blocks B21, B24 variables with the identifier "D2_X” and for blocks B31, B33 variables with the identifier "D3_X”.
- the variables of block B2 may be combined with those of block B3. It may also be envisaged that a production rule distinguishes between award-winning regions or excellent definition blocks and regular regions or definition blocks. Is that
- Block variables of the blocks Bl, B22 and B32 respectively assigned to the generation rule or the name macro "$ (Scope: ParentFunction) _Y", so taking into account the surrounding function, so obtained in a
- a generation rule may only have references to a region comprising the associated block. This further increases the reliability of the generated programs.
- FIG. 6 is a schematic flow chart of a preferred one
- Embodiment of the inventive method shown in which case only the procedure for a first and a second block variable is shown.
- a list of the block variables present in the block diagram is first of all created, whereby all block variables are checked consecutively. Preferably, all possible pairs of block variables are checked.
- Block variables selected so in step 101, a first block variable and in step 102, a second block variable.
- step 103 it is checked whether the first and second block variables have the same identifier. This can be the evaluation of
- step 109 Production rules. If the block variables have different identifiers, a transition is made to step 109.
- step 104 If the block variables are identically named, it is checked in step 104 whether an allowance flag is set in both variables. If the marker is only set in one of the block variables, it is expedient to create a separate variable in the source code for the block variable without an admissibility marking, and instead select a new block variable for the comparison. Unless one or both block variables
- step 108 If there is a validity mark, a transition is made to step 108. It is then checked in step 105 whether the block variables are arranged in the same region and thus there is a sufficient local reference. If this is not the case, a transition to step 108 takes place.
- step 106 it is checked whether the block variables fulfill an additional condition. For example, it may be necessary for the first and second block variables in the definition data collection to have one or more
- step 108 If the additional condition is not met, a transition to step 108 occurs.
- the first and the second block variables are combined in step 107 into a variable in the source code, ie a variable is generated. If the two block variables have the same identifier, but at least one of the other conditions is not satisfied, it is checked in step 108 whether it is possible to avoid it, ie for one of the block variables in the program code a differently named variable can be generated. It is advantageous if in a production rule also a possible
- Rename or an alternative rule is defined. If, in the specific case, no evasion is possible, an error message is output to the user in step 110. In addition, it can optionally be provided to cancel the code generation, so that first necessary adjustments to the model are made.
- step 108 one or (in step 109) two variables in
- Source code were generated, the method is advantageously carried out with the other block variables to be checked.
- the order of the conditions checked can be changed, and it can also be provided to check several conditions in one step, if, for example, the identifiers of the block variables also contain information about the region.
- the optimization takes place in several steps, that is to say initially a multiplicity of variables are created in the source text and these are then combined on the basis of a comparison of the associated block variables.
- Figure 7 shows a detailed embodiment of a block diagram which provides the functionality of a reset-enabled buffer. This serves, in particular, to implement a block with the corresponding functionality in a higher-level model, not shown, wherein the block diagram can be referenced one or more times, that is, if necessary, represents a complex library block.
- the two blocks are DetermineValue and StoreOverwrite atomic subsystems, which are implemented in a subordinate hierarchical level, but are executed in one computing step.
- the respective implementation in the block itself is shown here, wherein the connection between the signal connected to the respective block and the arrow is shown by dashed arrows
- a definition block DR1 is arranged which defines a region R1 comprising all blocks shown.
- the block diagram shown has the input port In, which receives a scalar signal, the input port ResetValue, which receives a vector signal with a width of 11, and the input port Reset, which receives a scalar or Boolean signal. It also has an output port Out which sends a scalar signal.
- Two unconnected MemBuf and Memldx blocks define memory blocks (DataStoreMemory) that can be accessed through special read / write blocks.
- the memory blocks can between several calls of the functionality implemented in the block diagram retain their value and thus represent states.
- the memory block MemBuf is read with the block ReadBuf and described with the block WriteBuf. Accordingly, the memory block Memidx is read with the block Readldx and described with the block Writeldx.
- An externally applied vector signal ResetValue is applied to the switch input of the block ResetBuf in the atomic subsystem Determine Value; this also receives the externally applied signal Reset and the current value of the memory block MemBuf. This is read out via the block ReadBuf and suitably converted by means of the block RBuf (Convert).
- the block ResetBuf supplies either the actual value of the output signal as output signal depending on the applied changeover value
- the scalar value can be extracted from the bus signal with the index Idx and output via the output port Out.
- the entire vector signal is next passed to the output port CurBuf.
- the value currently stored in the memory block Memidx is read out by means of the block Readldx, suitably converted by the block RIdxl (Convert) and then via the input port in_Idx to the atomic subsystem
- the output port out_Idx is connected to a first input of the sum block Incrldx, the second input of which is supplied with the fixed value 1 via a constant block Constant.
- the output of Incrldx is applied to one input of the block Normalize_Idx and to a first input of comparison block Rel.
- the value NDelaySize is applied to the second input of the comparison block Rel via constant block Constantl, so that the comparison block Rel outputs the value 1 or 0 depending on whether the output signal of Incrldx is smaller than NDelaySize.
- the output of Comparison block Rel is connected to a switching input of the block Normalizeldx.
- a constant block Constant2 is the block
- Normalizeldx to 0.
- the output of the block Normalizeldx is connected to the block Writeldx for writing to the memory block Memldx and to the input port Idx of the atomic subsystem DetermineValue.
- the output port is overwrite with an index input of the
- a value input from ReplaceOverwrite receives via an input port into an externally applied scalar value. Furthermore, a vector input of the
- Assignment block to which a vector signal is applied is with the block
- allocation block ReplaceOverwrite can change the current value of the scalar sub-signal located at the position given by Overwrite on the bus.
- Listing 1 can be generated from the block diagram shown in FIG. 7 (here in the language C).
- Idx Idx + 1;
- the block variables of the blocks MemBuf, ReadBuf, WriteBuf, RBuf and ResetBuf have been combined into an array variable BufBWR [] and the block variables of the blocks Memldx, Readldx, Writeldx, RIdxl and Incrldx into a scalar variable IdxBWR.
- the instance-specific variables are defined in a structure that can be addressed via a pointer to allow convenient reuse of the function.
- the method according to the invention enables particularly great optimization.
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Abstract
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EP17183987.1A EP3438817A1 (de) | 2017-07-31 | 2017-07-31 | Verfahren zur erzeugung von quellcode |
PCT/EP2018/068986 WO2019025155A1 (de) | 2017-07-31 | 2018-07-12 | Verfahren zur erzeugung von quellcode |
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EP3568757A1 true EP3568757A1 (de) | 2019-11-20 |
EP3568757B1 EP3568757B1 (de) | 2022-09-07 |
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EP18737311.3A Active EP3568757B1 (de) | 2017-07-31 | 2018-07-12 | Verfahren zur erzeugung von quellcode |
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EP (2) | EP3438817A1 (de) |
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CN (1) | CN110506256B (de) |
DE (1) | DE102018116911A1 (de) |
WO (1) | WO2019025155A1 (de) |
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US10860298B2 (en) * | 2018-03-21 | 2020-12-08 | Dspace Digital Signal Processing And Control Engineering Gmbh | Method and system for editing a block diagram model |
CN111444618B (zh) * | 2020-03-30 | 2023-06-30 | 北京润科通用技术有限公司 | 一种基于变量字典的仿真方法及装置 |
CN112783505B (zh) * | 2021-01-28 | 2023-07-18 | 东北大学 | 一种用于源代码的函数智能重命名方法 |
DE102022116011A1 (de) * | 2021-09-10 | 2023-03-16 | Dspace Gmbh | Verfahren zur Erzeugung von Quellcode |
CN116820419A (zh) | 2022-03-22 | 2023-09-29 | 瑞昱半导体股份有限公司 | 源代码校验方法及非暂态计算机可读存储介质装置 |
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US8196056B2 (en) * | 2001-07-24 | 2012-06-05 | The Mathworks, Inc. | Handling parameters in block diagram modeling |
US7493595B2 (en) * | 2003-12-19 | 2009-02-17 | The United States Of America As Represented By The Secretary Of The Navy | Multiple-user graphical programming and analysis environment |
US7650574B2 (en) * | 2004-05-11 | 2010-01-19 | National Instruments Corporation | Visually indicating problems found during programmatic analysis of a graphical program |
US20060136181A1 (en) * | 2004-12-22 | 2006-06-22 | John Masse | Method and system for optimising at least one parameter characteristic of a physical system that is to be subjected to variable external conditions |
US7703027B2 (en) * | 2005-01-13 | 2010-04-20 | National Instruments Corporation | Merging graphical programs |
US7934194B2 (en) * | 2006-10-17 | 2011-04-26 | The Mathworks, Inc. | User-defined hierarchies of user-defined classes of graphical objects in a graphical modeling environment |
US8448155B2 (en) * | 2009-06-01 | 2013-05-21 | National Instruments Corporation | Automatically creating parallel iterative program code in a graphical data flow program |
US8667474B2 (en) * | 2009-06-19 | 2014-03-04 | Microsoft Corporation | Generation of parallel code representations |
US8555130B2 (en) * | 2011-10-04 | 2013-10-08 | Cleversafe, Inc. | Storing encoded data slices in a dispersed storage unit |
CN102426550B (zh) * | 2011-10-26 | 2014-05-14 | 中国信息安全测评中心 | 源代码解析方法和系统 |
US9081900B2 (en) * | 2012-10-15 | 2015-07-14 | Toyota Motor Engineering & Manufacturing North America, Inc. | Systems and methods for mining temporal requirements from block diagram models of control systems |
CN104375875B (zh) * | 2013-08-15 | 2017-08-25 | 国际商业机器公司 | 用于应用程序的编译优化的方法以及编译器 |
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- 2018-07-12 EP EP18737311.3A patent/EP3568757B1/de active Active
- 2018-07-12 CN CN201880024640.2A patent/CN110506256B/zh active Active
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US10884715B2 (en) | 2021-01-05 |
DE102018116911A1 (de) | 2019-01-31 |
CN110506256B (zh) | 2023-09-01 |
JP6861844B2 (ja) | 2021-04-21 |
US20200050434A1 (en) | 2020-02-13 |
CN110506256A (zh) | 2019-11-26 |
JP2020529053A (ja) | 2020-10-01 |
EP3568757B1 (de) | 2022-09-07 |
WO2019025155A1 (de) | 2019-02-07 |
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