EP3564944B1

EP3564944B1 - Goa circuit, and liquid crystal display

Info

Publication number: EP3564944B1
Application number: EP17886895.6A
Authority: EP
Inventors: Longqiang SHI; Shu-Jhih CHEN
Original assignee: Shenzhen China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2016-12-30
Filing date: 2017-01-16
Publication date: 2023-05-03
Anticipated expiration: 2037-01-16
Also published as: KR102222921B1; US10204584B2; EP3564944A4; CN106531109A; KR20190091367A; US20180211623A1; EP3564944A1; WO2018120316A1; JP2020501196A; PL3564944T3; JP6773305B2

Description

FIELD OF THE DISCLOSURE

The present disclosure relates to liquid crystal display technologies, and more particularly to a gate driver on array (GOA) circuit and a liquid crystal display.

BACKGROUND OF THE DISCLOSURE

Gate driver on array (GOA) technologies have been widely used and research because they advantage display products to have a narrow frame or be borderless, and reduce a binding process of an external integrated circuit (IC) to enhance productivity and reduce product costs.
lndium gallium zinc oxide (IGZO) has been widely used in a production of GOA circuits to reduce the complexity of the GOA circuits because of its high mobility and good device stability. In detail, the IGZO has advantage over production of a narrow frame display because of its high mobility for producing a thin film transistor with a smaller size relative to a size of a thin film transistor fabricated by amorphous silicon (a-Si) in the process of manufacturing thin film transistors in the GOA circuits. Meanwhile, due to good device stability, the IGZO can use for producing a relatively simple GOA circuit and reduce power consumption by means of reduced numbers of power and thin-film transistor used for stabilizing performance of the thin-film transistor. However, a threshold voltage Vth of the thin-film transistor manufactured by the IGZO is liable to be a negative value, resulting in a failure of the GOA circuit.
Document CN106128409 A discloses a scanning driver for driving scan lines row by row, wherein a pull-down holding module 14 is connected to a constant low voltage supply VSS. It is considered to be the closest prior art document, and in its Figure 3 it discloses all the features of the embodiment of the present invention, except for the seventh switch transistor (T7) of the first pull-down circuit (14), the tenth switch transistor (T10) of the second pull-down circuit (16), and the provision of both a third level (Vss1) and fourth level (Vss2) voltage, where the third level (Vss1) is higher than the fourth level (Vss2). Document EP3531411 A1 discloses a GOA driving circuit and a liquid crystal display device, wherein a pull-down maintaining assembly 103 comprises two pull-down maintaining elements having a same structure. Document EP3531410 A1 discloses a GOA driver circuit and a liquid crystal display, wherein a fourth transistor T4 in a pull-down holding module 103 is connected to a first low supply voltage VSS1 and a third transistor T3 in the pull-down holding module 103 is connected to a second low supply voltage VSS2. Document EP3531413A1 discloses a GOA driver circuit includes a pull-up control module 101, a pull-up module 102, a pull-down holding module 103, a transferring module 105, and a bootstrap capacitor module 104.

SUMMARY OF THE DISCLOSURE

The present disclosure solves the above-mentioned problems and provides a gate driver on array (GOA) circuit and a liquid crystal display device preventing from erroneously turning on or off of a transistor and causing a problem of circuit output error due to drift of threshold value.
ln order to solve the above technical problem, the disclosure provides a GOA as defined in claim 1. Additional refinements are presented in the dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic structural view of the first illustrative example of the GOA circuit of the present disclosure;
Figure 2 is a schematic structural view of the second illustrative example of the GOA circuit of the present disclosure;
Figure 3 is a schematic structural view of the third illustrative example of the GOA circuit of the present disclosure;
Figure 4 is a schematic circuit diagram of an embodiment of the GOA circuit of the present disclosure;
Figure 5 is a schematic diagram of the clock signal of an embodiment of the GOA circuit of the present disclosure;
Figure 6 is a schematic diagram of the output signal of an embodiment of the GOA circuit of the present disclosure;
Figure 7 is a schematic structural view of an embodiment of the liquid crystal display of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 1, FIG. 1 is a schematic structural view of the first illustrative example of the GOA circuit of the present disclosure, the GOA circuit includes:
a pull-up circuit 11 including a first switch transistor T1.
A scan output terminal G(N) coupled to the second connection terminal of the first switch transistor T1.
Wherein, the first connection terminal of the first switch transistor T1 is connected with the first clock signal CK, when the control terminal of the first switch transistor is at the high level, the first switch transistor T1 is turned on and the first clock signal CK is outputted through the scan output terminal G (N).
A pull-up control circuit 12 includes:
a second switch transistor T2.
A third switch transistor T3 having a first connection terminal coupled to the second connection terminal of the second switch transistor T2, a second connection terminal coupled to the control terminal of the first switch transistor T1.
A fourth switch transistor T4 having a control terminal coupled to the control terminal of the first switch transistor T1, a first connection terminal coupled to the first connection terminal of the third switch transistor T3, a second connection terminal coupled to the scan output terminal G(N) for controlling the control terminal level of the second switch transistor T2 to be lower than the first connection terminal level of the second switch transistor T1 when the first level is outputted at the scan output terminal.
Wherein, the first connection terminal of the second switch transistor T2 is connected with the level-transmission signal ST(N-n) outputted by the GOA circuit on the upper stage (or upper n stage), the control terminal of the second switch transistor T2 and third switch transistor T3 are connected with the second clock signal XCK.
It is understood that the XCK is high level during the scanning preparation stage of the GOA circuit of the stage (i.e., the previous stage of the scanning phase), the stage signal ST (N-n) outputted from the GOA circuit of the upper stage is high level, and the CK is low level.
In detail, at the high level of XCK, T2 and T3 turn on and the high-level ST (N-n) charge the Q (N) to raise the level of Q (N). In Q (N) under the action of high, the T1 is turned on, but this time the CK is low, so the G (N) output low.
In the scanning phase, the XCK is low, the CK is high.
ln detail, at the XCK low level, T2 and T3 are turned off, the Q (N) continue to maintain high. In the Q (N) under the action of high, the T1 continues to turn on, this time CK is high, so G (N) output high.
It should be noted that at this stage, T4 turns on and the high level of G (N) goes to the first connection terminal of T3 under the effect of Q (N) high, so that the first connection terminal of T3 level T3 higher than the control side, to prevent the T3 at this stage threshold drift and conduction.
Different from the prior art, the GOA circuit of the present disclosure includes: a pull-up circuit including a first switch transistor; a scan output terminal coupled to the second connection terminal of the first switch transistor; a pull-up control circuit including: a second switch transistor; a third switch transistor having a first connection terminal coupled to the second connection terminal of the second switch transistor and a second connection terminal coupled to the control terminal of the first switch transistor; a fourth switch transistor having a control terminal coupled to the control terminal of the first switch transistor, a first connection terminal coupled to the first connection terminal of the third switch transistor and a second connection terminal coupled to the scan output terminal. In this way, the level of the first connection terminal of the third switch transistor can be raised in the scanning phase by the action of the fourth switch transistor so that the control terminal level of the third switch transistor is smaller than the first connection terminal level, avoid the third switch transistor threshold drift error affect the output of the scan terminal.
Referring to FIG. 2, FIG. 2 is a schematic structural view of the second illustrative example of the GOA circuit of the present disclosure, the GOA circuit includes a pull-up circuit 11, a pull-up control circuit 12, a passing down circuit 13, a first pull-down circuit 14, a clamping circuit 15, a scan output terminal G(N) and a level-transmission output terminal ST(N).
Wherein, the pull-up circuit 11 and the pull-up control circuit 12 are connected in the same manner as in the above-described first illustrative example and will not be described here.
The passing down circuit 13 includes a fifth switch transistor T5 having a control terminal coupled to the second connection terminal of the third switch transistor T3 and a second connection terminal coupled to the level-transmission output terminal ST(N).
Wherein, the level-transmission output terminal ST(N) is similar to the scan output terminal G(N), which also outputs the CK signal when T5 is turned on, but the outputted signal is used to input the next stage or lower n-stage GOA circuit pull-up control circuit.
Wherein, the first pull-down circuit 14 includes:
a sixth switch transistor T6 having a first connection terminal coupled to the scan output terminal G(N).
A seventh switch transistor T7 having a first connection terminal coupled to the level-transmission output terminal ST(N);
a eighth switch transistor T8 having a first connection terminal coupled to the second output terminal of the third switch transistor T3.
A clamping circuit 15 coupled to the control terminal and second connection terminal of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8 for controlling the control terminal level of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8 to be lower than the second connection terminal level of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8, when the first level is outputted at the scan output terminal G(N) and for controlling the control terminal level of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8 to be higher than the second connection terminal level of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8, when the second level is outputted at the scan output terminal, the first level being higher than the second level.
It is understood that, in the G (N) output high, T1, T5 open, Q (N) is high; At this time, should ensure that T6, T7, T8 completely cut-off, in order to prevent the conduction threshold drift of T6, T7, T8, the clamping circuit 15 supplies Vss2 to the control terminals of T6, T7 and T8, and Vss1 to the second terminals of T6, T7 and T8, where Vss1 > Vss2, and T6, T7 and T8 are completely turned off.
When G (N) outputs a low level, T6, T7, and T8 are turned on, and the level of G (N) is pulled low by the low level Vss1. Accordingly, the clamping circuit 15 supplies the control terminal of T6, T7, T8 a high level, supplies the Vss1 to the second connection terminal of T6, T7, T8, ensure the T6, T7, T8 are turned on.
Referring to FIG. 3, FIG. 3 is a schematic structural view of the third illustrative example of the GOA circuit of the present disclosure, the GOA circuit includes a pull-up circuit 11, a pull-up control circuit 12, a passing down circuit 13, a first pull-down circuit 14, a clamping circuit 15, a second pull-down circuit 16, a scan output terminal G(N) and a level-transmission output terminal ST(N).
Wherein, the pull-up circuit 11, the pull-up control circuit 12, the passing down circuit 13, the first pull-down circuit 14, the clamping circuit 15 are connected in the same manner as in the above-described second illustrative example and will not be described here.
Wherein, the second pull-down circuit 16 includes:
a ninth switch transistor T9 having a first connection terminal coupled to the second connection terminal of the third switch transistor T3.
A tenth switch transistor T10 having a first connection terminal coupled to the level-transmission output terminal ST(N).
A eleventh switch transistor T11 having a first connection terminal coupled to the scan output terminal G(N).
the clamping circuit 15 coupled to the control terminal and second connection terminal of the ninth switch transistor T9, the tenth switch transistor T10, the eleventh switch transistor T11 for controlling the control terminal level of the ninth switch transistor T9, the tenth switch transistor T10, the eleventh switch transistor T11 to be lower than the second connection terminal level of the ninth switch transistor T9, the tenth switch transistor T10, the eleventh switch transistor T11, when the scan output terminal outputted the first level, and for controlling the control terminal level of the ninth switch transistor T9, the tenth switch transistor T10, the eleventh switch transistor T11 to be higher than the second connection terminal level of the ninth switch transistor T9, the tenth switch transistor T10, the eleventh switch transistor T11, when the scan output terminal outputted the second level.
It will be understood that the second pull-down circuit 16 of the present embodiment is the same as the first pull-down circuit 14 and will not be described again.
Alternatively, in the present illustrative example the clamping circuit 15 controls the first pull-down circuit 14 and the second pull-down circuit 16 to operate alternately.
Referring to FIG. 4, FIG. 4 is a schematic circuit diagram of an embodiment of the GOA circuit of the present disclosure, the GOA circuit includes a pull-up circuit 11, a pull-up control circuit 12, a passing down circuit 13, a first pull-down circuit 14, a clamping circuit 15, a second pull-down circuit 16, a scan output terminal G(N) and a level-transmission output terminal ST(N).
Wherein, the pull-up circuit 11, the pull-up control circuit 12, the passing down circuit 13, the first pull-down circuit 14, and the second pull-down circuit 16 are the same as in the above-described illustrative example and will not be described here.
Wherein, the clamping circuit 15 includes a first control circuit, a second control circuit, a first clamp terminal, a second clamp terminal.
The first clamp terminal is connected with the third level Vss1, coupled to the second connection terminal of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8, the second clamp terminal is connected with the fourth level Vss2, the third level Vss1 is higher than the fourth level Vss2.
The first control circuit includes:
a twelfth switch transistor T12 having a control terminal and a first connection terminal connected with a first control signal LC1.
A thirteenth switch transistor T13 having a control terminal coupled to the second connection terminal of the twelfth switch transistor T12, a first connection terminal connected with the first control signal LC1, a second connection terminal coupled to the control terminal of the sixth switch transistor T6, the seventh switch transistor T7 and the eighth switch transistor T8.
A fourteenth switch transistor T14 having a control terminal coupled to the second connection terminal of the third switch transistor T3, a first connection terminal coupled to the second connection terminal of the twelfth switch transistor T12, a second connection terminal coupled to the second clamp terminal.
A fifteenth switch transistor T15 having a control terminal coupled to the second connection terminal of the third switch transistor T3, a first connection terminal coupled to the second connection terminal of the thirteenth switch transistor T13, a second connection terminal coupled to the second clamp terminal.
Wherein, the control terminal level of the sixth switch transistor T6, the seventh switch transistor T7, and the eighth switch transistor T8 is defined as P(N).
The second control circuit includes:
a sixteenth switch transistor T16 having a control terminal and a first connection terminal connected with the second control signal LC2.
A seventeenth switch transistor T17 having a control terminal coupled to the second connection terminal of the sixteenth switch transistor, a first connection terminal connected with a second control signal LC2, a second connection transistor coupled to the control terminal of the ninth switch transistor T9, the tenth switch transistor T10 and the eleventh switch transistor T11.
An eighteenth switch transistor T18 having a control terminal coupled to the second connection terminal of the third switch transistor T3, a first connection terminal coupled to the second connection terminal of the sixteenth switch transistor T16, a second connection terminal coupled to the second clamp terminal.
A nineteenth switch transistor T19 having a control terminal coupled to the second connection terminal of the third switch transistor T3, a first connection terminal coupled to the second connection terminal of the seventeenth switch transistor T17, a second connection terminal coupled to the second clamp terminal.
Wherein, the control terminal level of the ninth switch transistor T9, the tenth switch transistor T10, and the eleventh switch transistor T11 is defined as K (N).
Optionally, the pull-up circuit 11 further includes a capacitor Cb coupled between the scan output terminal G (N) and the control terminal of the first switch transistor T1.
Alternatively, the present embodiment will be described below with reference to a specific embodiment:
ln the present embodiment, the first connection terminal of the first switch transistor T1 is connected with the first clock signal CK, the control terminal of the second switch transistor T2 and the third switch transistor T3 are connected with the second clock signal XCK, the first connection terminal of the second switch transistor T2 is connected with the level-transmission signal ST(N-4); the first clock signal CK is opposite to the second clock signal XCK.
ln particular, as shown in FIG. 5. The present embodiment uses eight clock signals CK, that is, the CK signal of the Nth GOA circuit is the same as the CK signal of the (N + 8) th GOA circuit and opposite to the CK signal of the (N + 4) th GOA circuit. LC1, LC2 is the opposite of a set of low-frequency AC power supply, 100 frame reversal time. Vss1, Vss2 are two DC power supplies, Vss1> Vss2.
With the above-mentioned waveform into the circuit, the following in conjunction with FIG. 6, with the 32th GOA (G32) as an example to illustrate the circuit operation.
Assume that LC1 is high level H and LC2 is low level L in this frame.
When G (N) = G (32), ST (N-4) = ST (28), G (32) is controlled by CK8, ST (28) is controlled by CK4 and XCK is CK4.
When ST (28) is high, CK4 is high level, T2, T3 open, the high level of ST (28) to Q (32), Q is high level. At the same time, T1, T5 open, this time, CK8 is low, so G (32), ST (32) is low; at the same time, since Q is high, T14, T15, T18, T19 open, Vss2 makes P (32), K (32) are low, T6, T7, T8, T9, T10, T11 are off, at this time, the control terminal of T6, T7, T8, T9, T10, T11 is Vss2, the second connection end is Vss1, Vss1 is greater than Vss2, therefore, T6, T7, T8, T9, T10, T11 will not turn on erroneously due to the conduction threshold drift and will not affect the level of G (N).
Then, ST (28) is low, CK4 is low, T2, T3 closed, this time, CK8 is high, G (32) output high, Q (32) by the coupling effect of capacitance Cb, is raised to a higher level; P (32), K (32) continue to remain low.
Then, CK4 is high, the low level of ST(28) is to Q(32), the Q(32) is pulled low; at the same time, K(32) is low level, P(32) is high level, T6, T7, T8 are opened, Q(32), G(32), ST(32) are pulled low.
It will be appreciated, by those skilled in the art that the first and second connection terminals of the above-described switch transistor do not represent the order of the pin of the switch transistor but rather the specific designation of the pin of the switch pin. The switch transistor mentioned in each of the above embodiments is a TFT (Thin Film Transistor) fabricated by IGZO, alternatively, the TFT in the above-described embodiment is N-type, the control terminal is a gate, the first connection terminal is a source and the second connection terminal is a drain; or the control terminal is a gate, the first connection terminal is a drain and the second connection terminal is a source.
in other embodiments, a P-type TFT may be used for connection of the circuits, and it is only necessary to adjust the control terminal level or the order of the source and drain electrodes in accordance with the above-described embodiment.
Referring to FIG. 7, FIG. 7 is a schematic structural view of an embodiment of the liquid crystal display of the present disclosure, the liquid crystal display includes the display panel 71 and the driving circuit 72, wherein, the driving circuit 72 is arranged at the side of the display panel 71, is used to drive the display panel 71.
In detail, the driving circuit 72 is a GOA circuit as described in the above embodiments, and operates similarly to the circuit configuration, and will not be described again.

Claims

A GOA circuit, wherein the GOA circuit comprises:
a pull-up circuit (11) comprising a first switch transistor (T1);

a scan output terminal (G(N)) coupled to a second connection terminal of the first switch transistor (T1);

a pull-up control circuit (12) comprising:
a second switch transistor (T2);

a third switch transistor (T3) comprising a first connection terminal coupled to a second connection terminal of the second switch transistor (T2) and a second connection terminal coupled to a control terminal of the first switch transistor (T1); and

a fourth switch transistor (T4) comprising a control terminal coupled to the control terminal of the first switch transistor (T1), a first connection terminal coupled to the first connection terminal of the third switch transistor (T3), and a second connection terminal coupled to the scan output terminal (G(N));

a passing down circuit (13) comprising a fifth switch transistor (T5), wherein a control terminal of the fifth switch transistor (T5) is coupled to the second connection terminal of the third switch transistor (T3), a second connection terminal of the fifth switch transistor (T5) is coupled to a level-transmission output terminal (ST(N)), and the level-transmission output terminal (ST(N)) is configured to output a signal to a pull-up control circuit of a next n-stage GOA circuit;

a first pull-down circuit (14), comprising:
a sixth switch transistor (T6) comprising a first connection terminal coupled to the scan output terminal (G(N));

a seventh switch transistor (T7) comprising a first connection terminal coupled to the level-transmission output terminal (ST(N)); and

an eighth switch transistor (T8) comprising a first connection terminal coupled to the second connection terminal of the third switch transistor (T3);

a second pull-down circuit (16), comprising:
a ninth switch transistor (T9) comprising a first connection terminal coupled to the second connection terminal of the fourth switch transistor (T4) and the scan output terminal (G(N));

a tenth switch transistor (T10) comprising a first connection terminal coupled to the level-transmission output terminal (ST(N)); and

an eleventh switch transistor (T11) comprising a first connection terminal coupled to the second connection terminal of the third switch transistor (T3), wherein a third level (Vss1) is coupled to a second connection terminal of the sixth switch transistor (T6), a second connection terminal of the seventh switch transistor (T7), a second connection terminal of the eighth switch transistor (T8), a second connection terminal of the ninth switch transistor (T9), a second connection terminal of the tenth switch transistor (T10), and a second connection terminal of the eleventh switch transistor (T11); and

a clamping circuit (15) comprising a first control circuit and a second control circuit, wherein
the first control circuit comprises:
a twelfth switch transistor (T12) comprising a control terminal and a first connection terminal connected to a first control signal (LC1);

a thirteenth switch transistor (T13) comprising a control terminal coupled to a second connection terminal of the twelfth switch transistor (T12), a first connection terminal connected to the first control signal (LC1), and a second connection terminal coupled to a control terminal of the sixth switch transistor (T6), a control terminal of the seventh switch transistor (T7), and a control terminal of the eighth switch transistor (T8);

a fourteenth switch transistor (T14) comprising a control terminal coupled to the second connection terminal of the third switch transistor (T3), a first connection terminal coupled to the second connection terminal of the twelfth switch transistor (T12), and a second connection terminal coupled to a fourth level (Vss2); and

a fifteenth switch transistor (T15) comprising a control terminal coupled to the second connection terminal of the third switch transistor (T3), a first connection terminal coupled to the second connection terminal of the thirteenth switch transistor (T13), and a second connection terminal coupled to the fourth level (Vss2); and the second control circuit comprises:
a sixteenth switch transistor (T16) comprising a control terminal and a first connection terminal connected with a second control signal (LC2);

a seventeenth switch transistor (T17) comprising a control terminal coupled to a second connection terminal of the sixteenth switch transistor (T16), a first connection terminal connected to the second control signal (LC2), and a second connection terminal coupled to a control terminal of the ninth switch transistor (T9), a control terminal of the tenth switch transistor (T10), and a control terminal of the eleventh switch transistor (T11);

an eighteenth switch transistor (T18) comprising a control terminal coupled to the second connection terminal of the third switch transistor (T3), a first connection terminal coupled to the second connection terminal of the sixteenth switch transistor (T16), and a second connection terminal coupled to the fourth level (Vss2); and

a nineteenth switch transistor (T19) comprising a control terminal coupled to the second connection terminal of the third switch transistor (T3), a first connection terminal coupled to the second connection terminal of the seventeenth switch transistor (T17), and a second connection terminal coupled to the fourth level (Vss2), wherein the third level (Vss1) is higher than the fourth level (Vss2).
The GOA circuit according to claim 1, wherein the clamping circuit (15) controls the first pull-down circuit (14) and the second pull-down circuit (16) to operate alternately.
The GOA circuit according to claim 1, wherein the pull-up circuit (11) further comprises a capacitor (Cb) coupled between the scan output terminal (G(N)) and the control terminal of the first switch transistor (T1).
The GOA circuit according to claim 1, wherein:
a first connection terminal of the first switch transistor (T1) is connected to a first clock signal (CK);

a control terminal of the second switch transistor (T2) and a control terminal of the third switch transistor (T3) is connected to a second clock signal (XCK);

a first connection terminal of the second switch transistor (T2) is connected to a previous n-stage level-transmission signal (ST(N-n)); and

the first clock signal (CK) is in antiphase to the second clock signal (XCK).
A liquid crystal display wherein the liquid crystal display comprises the GOA circuit according to at least one of claims 1 to 4.