EP3559998A2 - Strained-channel normally-off hemt transistor - Google Patents

Abstract

The invention relates to a high-electron-mobility field-effect transistor (1) of the normally-off type, comprising: - a channel layer (14) and a barrier layer (15) stacked to form an interfacial electron gas layer (16); first and second conduction electrodes (21, 22); a control grid (23) formed above the channel layer (14); a strained layer (32) in contact with the barrier layer (15), exhibiting a normal strain in a direction from the first conduction electrode to the second conduction electrode, where said strained layer (32) is not in contact with the barrier layer vertically in line with the control grid, such that the elastic relaxation of the strained layer (32) at the grid generates negative electrostatic charges under the control grid.

Description

 HEMT TRANSISTOR NORMALLY BLOCKED

 CANAL CONSTRAINTED

The invention relates to electron mobility high-mobility field effect transistors based on element III nitrides, and in particular to improving the performance of enrichment-type transistors.

Element III nitrides are considered very promising candidates for the emergence of a new generation of high power and high frequency electronic devices. These large-gap semiconductor materials have a strong critical electric field that opens the way to high voltages. On the other hand, the polarization properties of the III-N materials allow the formation of a two-dimensional electron gas with high electron density and high electron mobility which allows a significant reduction of the on-resistance RON, S _P HEMTs compared to power devices on silicon, such as MOSFETs and IGBTs.

 A standard HEMT III-N has a depletion type operation related to the 2DEG formation mode. However, obtaining an enrichment power transistor, for which the VTH threshold voltage is positive, is highly desirable because this type of transistor greatly simplifies the circuit design and improves the reliability of the systems.

 To achieve the goal of removing 2DEG under the grid at VGS = 0V, two main strategies emerged. A first strategy implements the addition of a P-doped III-N layer between the heterostructure and the gate metal in order to locally deplete the 2DEG at the control gate. A second strategy is to burn the lll-N layers to remove the 2DEG.

 The main problem then consists in obtaining a method for obtaining the highest possible positive threshold voltage, the implementation of which would minimize the degradation of the specific on-state resistance.

 The invention aims to solve one or more of these disadvantages. Based on the strong piezoelectric properties of the III-N layers, the present invention advantageously employs an inherently stressed layer deposited above the heterostructure to improve the performance of enrichment HEMTs.

 The invention aims to solve one or more of these disadvantages.

The invention thus relates to a normally-blocked type high-mobility electronic field effect transistor as defined in appended claim 1.

The invention also relates to the variants detailed in the dependent claims. The skilled person will understand that each of the The features of the variants of the dependent claims may be independently combined with the features of claim 1, without constituting an intermediate generalization.

 Other characteristics and advantages of the invention will emerge clearly from the description which is given hereinafter, by way of indication and in no way limitative, with reference to the appended drawings, in which:

Summary of Figures

 FIGS. 1a and 1b illustrate the creation of polarization charges in the layers III-N at the level of the gate under the effect of the elastic relaxation of the constrained film for two different topologies;

 FIG. 2 represents a schematic piezoelectric model on which the invention is based to improve the performance of transistors;

 FIG. 3 is a diagrammatic sectional view of an example of an embodiment of the HEMT transistor according to the invention;

 FIG. 4 illustrates the effect of the constrained film on a band diagram in the thickness at the center of the grid;

 FIG. 5 illustrates the impact of the stress of the film on the level of the conduction band, along the channel of the transistor formed by the electron gas;

 FIG. 6 illustrates the impact of the film stress on the current IDS drain / VGS gate voltage transfer characteristic for a gate length transistor LG equal to 0.50 μιτι;

 FIG. 7 is a diagram illustrating the threshold voltage variation of the transistor relative to a reference, as a function of the stress in the dielectric film for different gate lengths;

 FIG. 8 is a diagrammatic sectional view of another exemplary embodiment of an HEMT transistor according to the invention.

Definition of concepts

 By mechanical deformation of a material is meant a material which has its parameter (s) elongated crystal (s) or shortened (s). In the case where the deformed mesh parameter is larger than the so-called "natural" parameter of a crystalline material, it is said to be in tension strain. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be compressive deformation or compression.

An orientation in a layer of GaN in which the gallium and nitrogen atoms are arranged during growth according to the gallium polarity or Ga (along the axis [0001]) with the oriented link Ga-N pointing to the surface. An orientation in a layer of GaN in which the gallium and nitrogen atoms are arranged during a growth according to the polarity N (along the axis [0001]) will be referred to as N-orientation. Detailed description of the invention

 The invention proposes to use the elastic energy transfer of a constrained film to the heterostructure 11 lN of the transistor, to locally generate in the layers 11 lN located under the control gate of a HEMT transistor fixed charges of negative sign polarization. This local engineering of the polarization in the layers l l -N allows a significant improvement of the performances of the transistors.

Detailed description of the figures

 FIGS. 1a and 1b illustrate the creation of negative polarization charges in the layers of materials 11-N at the gate under the effect of a compression-deposited deposited film.

 FIGS. 1a and 1b schematically illustrate a heterostructure 11-V 91 and a Ga-face orientation grid 111, coated with a film 93 deposited in a state of compressive stress, and the negative polarization charges created. in the layers of materials ll lN at the gate under the effect of the forced film. The inventors have highlighted two distinct ways to create these loads:

 When the film is deposited on the grid, the topology of the structure causes an elastic relaxation of the constrained film and a transfer of elastic energy to the layers 91 and 92 in materials 11-N (see FIG. 1 a);

 When the constrained film is etched at the level of the grid (cf. FIG. 1b), the relaxation of the constrained film is amplified at the level of the free edges 94 during the etching. The transfer of elastic energy from the forced film to the layers 91, 92 formed of materials 11-1 N results in the appearance of non-uniform mechanical stress fields at the grid. These stress fields, due to the strong piezoelectricity of the materials of the layers 91 and 92, allow the generation of negative polarization charges at the channel and positive polarization charges outside the channel, as shown in FIG. Figure 2 is a schematic illustration of the piezoelectric model for improving the performance of the transistor through the deposition of a constrained film.

FIG. 2 schematically illustrates the piezoelectric model on which the invention is based which makes it possible to determine the polarization charges created in the volume of the layers of materials 11 lN from the modification local stress fields induced by the forced film. This local modification of the polarization at the gate allows an improvement of the transistor performance, in particular an improvement in the VTH / (RON XA) ratio.

 Considering as negligible the piezoelectric inverse effect

(stress from the electric field), the effect of stress modification on the polarization in the structure can be obtained by expressing the piezoelectric polarization as the matrix product of the piezoelectric coefficients and the mechanical stress tensor according to the relation below. The x axis corresponds to the direction of conduction, the y axis corresponds to the direction along the grid width, the z axis corresponds to the axis of growth.

p _z ^sp corresponds to the spontaneous polarization along a growth axis and does not depend on the state of mechanical stress of the system.

By the application of the Gaussian theorem, a polarization gradient induces the appearance of electrostatic charges, called polarization charges, in the layers of material III-N, and whose density is given according to the following relation: p _P = - V. P

Polarization of the charges induced by the bias gradient in the volume of the III-N layers are typically between 10 ¹⁶ cm ^-3 and 10 ¹⁸ cm ^"3. The terms of sign is opposite in the layers according to whether they are located under the gate or outside the gate of the transistor.

FIG. 3 is a schematic cross sectional view of an example of HEMT type transistor 1 (also referred to as a high electron mobility field effect transistor) according to one embodiment of the invention. A forced insulating film, deposited on the layers of materials III-N, is etched before the deposition of the metal grid: it is with this structure that the simulations, and the numerical results presented thereafter, were obtained.

Transistor 1 is here of the type obtained by a grid-type manufacturing method last (for Gâte Last in English). The gate 23 has thus been deposited after the deposition of a constrained dielectric layer 30. A dummy gate may be formed in a manner known per se prior to the deposit of the dielectric layer 30. The method may thus comprise depositing the dielectric layer 30 on a dummy gate, opening access to the dummy gate, removing the dummy gate, and then forming the gate 23.

 The transistor 1 comprises a substrate 1 1, optionally an adaptation or transition layer 12 disposed on the substrate 1 1, a semiconductor buffer layer 13 (including for example a type III-V semiconductor layer, for example). element nitride III, typically unintentionally doped GaN) formed on the matching layer 12, a channel layer here formed of a layer 14 of a semiconductor material (including, for example, a semiconductor layer). type III-V conductor, for example element III nitride, typically GaN) formed on the buffer layer 13, a barrier layer here formed of a layer 15 of another semiconductor material (including for example a layer type III-V semiconductor, for example ternary nitride element III, typically undoped AIGaN) formed on the layer 14 and a layer of electron gas 16 intrinsically formed in a manner known per se at the level of the interface between the layers 14 and 15. The electron gas layer 16 is for conduction of the transistor 1 in the on state.

 Since the channel layer is formed solely of the semiconductor layer 14 in this embodiment, it will be assimilated to this layer 14. The barrier layer being formed solely of the semiconductor layer 15 in this embodiment, it will be assimilated to this layer 15. A thin layer of another semiconductor material (not shown) may advantageously be interposed between the layers 14 and 15, in a manner known per se (for example an AlN layer of 1 nm thick between a layer of GaN 14 and a layer of AIGaN 15).

 The substrate 1 1 may be an insulator or a semiconductor intrinsic or doped silicon type. The substrate 1 1 may for example be silicon-type mesh orientation (1 1 1). The substrate 1 1 may also be (not limited to) silicon carbide, sapphire, GaN or ΑΙΝ. The substrate 1 1 may have a thickness of the order of 650 μιτι, typically between 500 μιτι and 2 mm.

 An adaptation layer 12 may be deposited between the substrate 1 1 and the buffer layer 13, to allow mesh matching between the substrate 1 1 and the buffer semiconductor layer 13. The buffer layer 13 may typically be nitride nitride. aluminum.

The buffer semiconductor layer 13 may typically have a thickness between 100 nm and 5 μιτι. The semiconductor layer 13 may be formed in a known manner either by epitaxy or chemical vapor deposition on an adaptation layer 12 or on the substrate 11. The semi layer Conductor 13 is typically a binary element III nitride, for example GaN, of unintentionally doped type.

 The channel semiconductor layer 14 may typically have a thickness between 5 nm and 2 μιτι. The channel layer 14 may be formed in known manner by epitaxy on the buffer layer 13. The channel layer 14 is typically a binary element III nitride, for example GaN, typically unintentionally doped type.

 The semiconductor layer 15, typically forming the barrier layer, can typically have a thickness between 5 nm and 40 nm, for example 25 nm. The semiconductor layer 15 may be formed in known manner by epitaxial growth on the channel semiconductor layer 14. The semiconductor layer 15 is typically a ternary alloy of element III nitride, for example AIGaN or binary alloy element nitride III, for example AlN, or quaternary alloy III element nitride, for example AlxGaylnci-x-yjN (with x + y≤1), keeping a bandgap greater than that of the layer 14. Typically, x may be between 10 and 20%, and may for example be equal to 12%.

An undoped or P-doped semiconductor layer 231 (for example undoped or P-doped GaN) is placed on the semiconductor layer 15. The layer 231 may for example have a thickness of between 10 and 200 nm. The layer 231 may for example have P-type doping with a concentration of between 10 ¹⁷ and 10 ²¹ cm ^-3 .

 A dielectric layer 30 is deposited above the barrier layer 15 and the semiconductor layer 231. The dielectric layer 30 is in contact with the layer 15 and with the semiconductor layer 231.

 According to the invention, the layer 30 advantageously has a biaxial residual stress, plane, so that the elastic relaxation of this layer at the gate edge 23 induces a spatial variation of the polarization in the gate semiconductor layers 231, barrier 15 and channel 14 and the creation of negative volumic electrostatic charges in these layers over the width of the gate 23, as illustrated in Figure 1b. Thus the layer 30 increases the electronic confinement in the channel area 160. The residual stress in the film is negative for Ga-face (compression) and positive for N-face (voltage).

The total residual stress of the thin film is the sum of the thermal stress, related to the difference between the deposition temperature and the ambient temperature, and the so-called intrinsic stress resulting from the deposit itself. Advantageously, the residual stress in the dielectric layer 30 is in absolute value at least equal to 200 MPa, preferably at least equal to 500 MPa. The layer 30 advantageously has a thickness of at least 20 nm, preferably at least 150 nm.

 The dielectric layer 30 comprises a superposition of at least two layers 31 and 32 of dielectric (in the vertical direction) of different composition.

 The layer 31 typically plays the role of a passivation layer, and is for example preferably selected from the group consisting of silicon nitrides, silicon oxynitrides, ΑΙ2Ο3 and silicon oxides. The layer 31 is for example deposited by an LPCVD (chemical vapor phase deposition at low pressure), PEVCD (plasma chemical vapor deposition) or ALD (atomic layer deposition). The layer 31 is optimized to passivate the upper face of the layer 15, and serves in particular to minimize the reduction of the output current observed during operation of the transistor (phenomenon known as current collapse) known from the skilled person.

 The layer 31 advantageously has a thickness of less than 25 nm, so that the elastic energy transfer from the layer 32 to the heterostructure is maximized.

 The second layer 32 is formed on the layer 31. The layer 32 has a residual stress. The residual stress in the dielectric layer 30 is in absolute value at least equal to 300 MPa, preferably at least 500 MPa, preferably at least 1 GPa, in order to induce sufficient elastic deformation in the heterostructure located under the layer 31. The second layer 32 is typically a layer selected from the group consisting of silicon nitrides, silicon oxynitrides, silicon oxides, amorphous carbon, and ΑΙ2Ο3. The layer 32 is optimized to have a cohesion with the layer 31, so as to maximize an elastic energy transfer between the layer 32 and the heterostructure located under the layer 31. Advantageously, the thickness of the layer 32 is at least equal to 20 nm, in order to promote maximizing an elastic energy transfer between the layer 32 and the heterostructure located under the layer 31. Advantageously, the thickness of the layer 32 is at least two times greater than that of the layer 31.

 The layer 31 is preferably etched following the etching of the layer 32 before the deposition of the metal gate 232.

 The layer 32 is optimized to present a cohesion with the barrier

15 and the semiconductor layer 231, so as to allow a transfer of elastic energy between the latter and the semiconductor layers 231, 15 and 14.

The dielectric layer 32 is typically a layer selected from the group consisting of silicon nitrides, silicon oxynitrides, silicon oxides, amorphous carbon, and Al2O3 alumina. advantageously, the properties of the layer 32 are slightly altered by the increase of the temperature during the subsequent steps.

 In order to optimize different properties, the layers 31 and 32 advantageously have different chemical compositions.

 The transistor 1 comprises, in a manner known per se, metallic contacts

21 and 22, forming conduction electrodes electrically connected to the electron gas layer 16. The metal contacts 21 and 22 are here arranged on the semiconductor layer 15. The metal contacts 21 and 22 are arranged in line with the the electron gas layer 16. The metal contacts 21 and 22 are here electrically connected to the electron gas layer 16, via a vertical electrical connection. The metal contact 21 will be considered as a source contact, the metal contact 22 being considered as a drain contact of the transistor 1. The contacts 21 and 22 may for example be made of Ti, Si, Ni, Au, Al, Ta, Mo, TiN or WSiN or Pt (or a stack of layers of these materials).

 Advantageously, the mode of formation, and in particular the thermal budget of the ohmic contacts 21 and 22 does not decrease the amplitude and does not modify the sign of the residual stress of the dielectric layer 32.

 With the SiN used, it should not exceed 550 ° in the rest of the process. The temperatures used must not change the amplitude of the stress by more than 50%.

 An opening is created after formation of the ohmic contacts in the dielectric layer 32 at the upper face of the semiconductor layer 231 so that free edges are formed.

 A gate metal layer 232 is disposed on the semiconductor layer 231. The layers 231 and 232 form the control gate 23. The gate metal 232 may for example be made of Ta, TaN, TiN, Pd, W or WS12. Optionally, the control gate 23 may comprise a dielectric layer (not shown) interposed between the semiconductor layer 231 and the gate metal 232. The upper part of the gate metal layer 232 overhangs the edges of the gate layer 232. dielectric 32.

A channel zone 160 is formed in line with the gate 23, at the level of the electron gas layer 16. In a manner known per se, this channel zone 160 is selectively turned on (forming a continuity of the electron gas layer 16) or the insulating layer, as a function of the state of the polarization on the gate 23. Due to the presence of the P-type doped semiconductor 231 in line with this channel zone 160, the electron gas 16 is interrupted in this zone 160 when the voltage on the gate 23 is lower than the threshold voltage of the transistor 1, in particular in the absence of bias on the gate 23. In a manner known per se , including with parameters as described in the Mr. Uemoto's paper titled "Injection Transistor-A Normally-Off AIGaN / GaN Power Transistor Conductivity Modulation" and published in 2008 in No. 12 Electron Devices IEEE Trans. on pages 3393-3399, the semiconductor 231 generates an electromagnetic field large enough to deplete the channel zone 160, in the absence of a voltage at least equal to the threshold voltage on the gate 23.

Figure 4 illustrates the impact of the film stress on the tape diagram, in a vertical section, in the center of the grid.

 FIG. 4 is a band diagram in the thickness, below the center of the grid 23, as a function of different residual stress values in the layer 32. The dashed curve corresponds to a layer 32 having a residual compressive stress of 2 GPa, the dotted curve corresponds to a layer 32 having a compressive residual stress of 1 GPa, the solid curve corresponds to a layer 32 having no residual stress after deposition, and the dash-dot curve corresponds to a layer 32 having a tensile residual stress of 1 GPa.

 The invention makes it possible by creating negative polarization charges under the gate to increase the potential barrier in the III-N layers below the gate.

Figure 5 illustrates the impact of the film stress on the level of the conduction band at the channel of the transistor.

FIG. 5 is a one-dimensional profile of the conduction band as a function of the position between the source and the drain, at a depth of 1 nm under the interface between the layers 14 and 15. The dashed curve corresponds to a layer 32 having a compressive residual stress of 2 GPa, the dotted line curve corresponds to a layer 32 having a compressive residual stress of 1 GPa, the solid line curve corresponds to a layer 32 having no residual stress after deposition, and the dash-dot curve corresponds to a layer 32 having a residual tensile stress of 1 GPa. Under the gate 23, it is found that the energy of the conduction band is substantially raised for a layer 32 having a compressive residual stress, and substantially reduced for a layer 32 having a residual tensile stress. For a compressive stress, the increase of the potential barrier makes it possible to delay a breakdown phenomenon by piercing (leakage of electrons from the source to the drain under the gate, in the normally blocked state), also called breakdown phenomenon. by punch-through in English language. For a grid voltage given, the breakdown voltage by piercing between source and drain is increased. Likewise, the leakage current between source and drain is reduced. The invention makes it possible to increase and widen the potential barrier under the gate. FIG. 6 is a transfer characteristic I DS (VGS) for LG = 0.50 μιτι.

FIG. 6 illustrates the current drain / gate voltage transfer characteristic for a gate length 23 equal to 0.50 μιτι, as a function of the residual stress in the layer 32. The dashed curve corresponds to a layer 32. The dashed line curve corresponds to a layer 32 having a compressive residual stress of 2 GPa, the dashed line corresponds to a layer 32 having a compressive residual stress of 1 GPa, the solid line corresponds to a layer 32 not having no residual stress after deposition, and the dash-dot curve corresponds to a layer 32 having a residual tensile stress of 1 GPa. The simulations were performed with a potential difference between source and drain of 10 V.

 In this configuration, the threshold voltage of the transistor 1 is here increased by the increase of a residual compressive stress in the layer 32. Conversely, the threshold voltage of the transistor is reduced by increasing a residual stress. in tension in the layer 32. The deposition of a layer having a residual compressive stress also results in a reduction of the drain leakage current of several orders of magnitude, in the off state. Figure 7 illustrates the influence of the film stress on the variation of the threshold voltage for different gate lengths;

 The influence of the residual stress in the layer 32 on the threshold voltage of the transistor 1 is further illustrated in FIG. 7, representing, as a function of the residual stress of the film, the shift of the threshold voltage, with respect to a transistor 1 in which the layer 32 is not constrained. The different curves correspond to different LG grid lengths.

The influence of the compressive stress of the layer 32 on the threshold voltage VTH is particularly preponderant for short gate lengths (LG ≤ 0.50 μιτι). The invention thus advantageously applies to grid lengths Lg <0.9 μιτι, preferably for Lg <0.7 μιτι, and still more preferably for Lg <0.5 μιτι. The interaction between the constrained film and the heterostructure is amplified by the decrease in the gate length, which results in an increase in the density of polarization charges in the volume of the III-N layers under the metal gate and increases the effect. from that one. Thus, a film having a residual stress after deposit of -2 GPa allows an increase of the threshold voltage of the transistor by +0.7 V for a gate length of 0.35 μιτι, whereas this increase is only +0.3 V for a gate length LG equal to 1 μιτι. FIG. 8 is a transistor 1 according to another exemplary embodiment: the constrained film is not etched on the grid, the grid topology allows the elastic relaxation of the film.

 Figure 8 is a schematic cross sectional view of a transistor 1 according to another exemplary embodiment of the invention. Transistor 1 is here of the type obtained by a grid-type manufacturing method first (for Gatte First in the English language). A grid 23 has thus been deposited and shaped by etching, before the deposition of a dielectric layer 32 detailed thereafter.

 With respect to the first embodiment, the transistor 1 here takes the same structure and substrate geometry 1 1, adaptation layer 12, buffer semiconductor layer 13, channel layer 14, barrier layer 15. A Electron gas layer 16 is here also intrinsically formed at the interface between layers 14 and 15. Transistor 1 here comprises the same structures and contact geometry 21 and 22 as in the first embodiment.

The control gate 23 comprises a nondoped or P-doped semiconductor layer 231 (for example undoped or P-doped GaN) disposed on the semiconductor layer 15. The layer 231 may for example have a thickness of between 10 and 200 nm. The layer 231 may for example have P-type doping with a concentration of between 10 ¹⁷ and 10 ²¹ cm ^-3 . A gate metal layer 232 is disposed on the semiconductor layer 231. The gate metal 232 may for example be made of Ta, TaN, TiN, Pd, W or WSi ₂ .

 A dielectric layer 30 extends here continuously in contact on the layer 15, between the source 21 and the control gate 23 on the one hand, and between the drain 22 and the control gate 23 on the other hand. The energy transfer here is as shown in Figure 1a. The dielectric layer 30 includes a superposition of a first dielectric layer 31 and a second dielectric layer 32. The dielectric layer 31 here continuously extends in contact with the layer

15, between the source 21 and the control gate 23 on the one hand, and between the drain 22 and the control gate 23 on the other hand. The dielectric layer 31 extends here on the side walls and the upper wall of the grid 23.

The first layer 31 typically plays the role of a passivation layer, for example selected from the group consisting of silicon nitrides, oxynitrides siliciunn, ΑΙ2Ο3 and oxides siliciunn. The layer 31 is for example deposited by a LPCVD (low pressure chemical vapor deposition) or PEVCD (plasma enhanced chemical vapor deposition) method. The layer 31 is optimized to passivate the upper face of the layer 15, and serves in particular to limit leakage at the upper face of the layer 15.

 The second layer 32 is formed on the layer 31. The second layer 32 is typically a layer selected from the group consisting of silicon nitrides, silicon oxynitrides, silicon oxides, amorphous carbon, and ΑΙ2Ο3. The layer 32 is optimized to have a cohesion with the layer 31, so as to allow an elastic energy transfer between it and the layer 31.

 The layers 31 and 32 may have the same compositions and thicknesses as those described with reference to FIG.

Claims

1. A normally-blocked electron-mobility field effect transistor (1) comprising:  a channel layer including a first semiconductor layer (14); a barrier layer including a second semiconductor layer (15), the first and second semiconductor layers (14, 15) being superimposed to form a layer of electron gas (16) at their interface; first and second conduction electrodes (21,22) electrically connected to the electron gas layer (16);  a control gate (23) formed above the channel layer (14) between said first and second conduction electrodes (21, 22);  Characterized in that it further comprises:  a stressed layer (30) extending in contact on the barrier layer (15) between the first conduction electrode (21) and the control gate (23) on the one hand, and between the second conduction electrode (22); ) and the control gate (23) on the other hand, said strained layer (30) not being in contact with the barrier layer in line with the control gate so that the elastic relaxation of the strained layer ( 30) at the gate generates electrostatic charges of negative sign in at least one of the barrier layer, the channel layer or in said control gate;  said constrained layer (30) including a passivation layer (31) in contact with the barrier layer (15), having a thickness of less than 25 nm, and  said constrained layer (30) including another layer (32) covering said passivation layer, said other layer (32) having a thickness of at least 20 nm and having a normal stress having an amplitude of at least 300 MPa. The field effect transistor (1) according to claim 1, wherein said control gate (23) comprises a layer of p-type doped semiconductor material (231) formed on the barrier layer (15), and a metal layer (232) formed on the layer of p-type doped semiconductor material. A field effect transistor (1) according to claim 2, wherein the P-type doped semiconductor material layer (231) is GaN type doped GaN. A field effect transistor (1) according to any one of the preceding claims, wherein said strained layer (30) has at least one normal stress in a direction from the first conduction electrode to the second conduction electrode of whereby the elastic relaxation of the stress layer (30) at the gate generates electrostatic charges of negative sign in at least said layer among the barrier layer, the channel layer or in said control gate. The field effect transistor (1) according to any one of the preceding claims, wherein said passivation layer (31) and said other layer (32) have different chemical compositions. A field effect transistor (1) according to any one of the preceding claims, said other layer being formed of a material selected from the group consisting of silicon nitrides, silicon oxynitrides, SiO 2 or A Os . A field effect transistor (1) according to any one of the preceding claims, wherein the stress in said other layer (32) has an amplitude at least twice that in said passivation layer (31). A field effect transistor (1) according to any one of the preceding claims, wherein the first semiconductor layer is GaN facing Ga-oriented along the [0 0 0 1] axis with a Ga-oriented bond. N pointing to the surface, the constraint of the strained layer (30) being negative, said strained layer being said to be deposited in compression, inducing a compressional lateral deformation in the channel layer and the barrier layer under the control gate. 9. field effect transistor (1) according to any one of claims 1 to 7, wherein the first semiconductor layer is GaN oriented N-axis along the axis [0 0 0 1], the constraint of the strained layer (30) being positive, said strained layer being said voltage-deposited, inducing a lateral strain in voltage in the channel layer and the barrier layer under the control gate. The field effect transistor (1) according to any one of the preceding claims, wherein said electrostatic charge of negative sign is a continuous volume load extending over the entire length of the control grid (23). 1 1. A field effect transistor according to any one of the preceding claims, wherein Lg is less than or equal to 1, δμιτι. A field effect transistor according to any one of the preceding claims, wherein said strained layer extends continuously between the control gate and the first conduction electrode on the one hand, and between the control gate and the second conduction electrode on the other hand.