EP3555916A2 - Method for the integration of power chips and bus-bars forming heat sinks - Google Patents

Method for the integration of power chips and bus-bars forming heat sinks

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Publication number
EP3555916A2
EP3555916A2 EP17817810.9A EP17817810A EP3555916A2 EP 3555916 A2 EP3555916 A2 EP 3555916A2 EP 17817810 A EP17817810 A EP 17817810A EP 3555916 A2 EP3555916 A2 EP 3555916A2
Authority
EP
European Patent Office
Prior art keywords
blank
low
bus
electronic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP17817810.9A
Other languages
German (de)
French (fr)
Inventor
Friedbald KIEL
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institut Vedecom
Original Assignee
Institut Vedecom
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Filing date
Publication date
Application filed by Institut Vedecom filed Critical Institut Vedecom
Publication of EP3555916A2 publication Critical patent/EP3555916A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]

Definitions

  • the invention generally relates to the field of power electronics. More particularly, the invention relates to a method for integrating power electronic chips and interconnecting bus bars forming heat sinks in electronic power devices such as converters and power modules. The invention also relates to electronic power devices obtained by the implementation of the aforementioned method.
  • Power electronic devices such as power converters
  • power electronics With the desired energy transition towards renewable and less carbon-intensive energy sources, power electronics will become more widespread and will have to respond to increasing economic and technological constraints.
  • Current research and developments focus on reducing costs, increasing power density, increasing reliability, reducing parasitic elements and heat transfer of dissipated energy.
  • HDI technology "High Density Interconnect” in English
  • PCB printed circuit boards
  • TLP welding transient liquid phase welding
  • sintering of metal nanoparticle powder it is usual to use the so-called HDI technology, "High Density Interconnect” in English, to increase the level of integration and reduce the size of the power circuits.
  • the HDI technology generally implemented on printed circuit boards known as PCB, from the "Printed Circuit Board” in English, is based on an optimization of the spatial implantation of the components, in particular by using ribbons and ceramic plates carrying a copper trace circuit. lead frames, to interconnect surface-mounted components or, in a more advanced, micro-holes called “microvias” filled with copper to interconnect embedded components. It is used laser beam drilling as well as various welding techniques such as for example brazing, transient liquid phase welding known as TLP welding or sintering of metal nanoparticle powder.
  • HDI technology finds its limits in the face of cost reductions that are necessary for mass production, and increasing the level of integration and compactness.
  • the level of integration that can be achieved is limited by the volume occupied by the interconnections with ribbons and microvias. Interconnections with ribbons or cables introduce parasitic inductances that oppose higher switching or switching frequencies. However, the increase in switching frequencies is generally favorable to compactness, particularly in power converters.
  • the reduction of parasitic inductances is also necessary to reduce the generated heat, protect the circuits against potentially destructive overvoltages and improve the control of electromagnetic radiation.
  • High performance cooling is necessary to keep the active and passive components temperatures below critical values, to achieve thermal equilibrium and to guarantee the reliability of the power circuits.
  • the architecture of the power circuits and the technology used must ensure an extraction of the energy dissipated closer to the components. It is necessary to optimize the thermal path between the heat sources constituted by the components and the heat sinks constituted by the heat dissipation means.
  • the heat must pass through different layers such as solder, the dielectric substrate plated with copper, the plate base metal, the thermal interface material and the mass of the heat sink, before being transferred to air or a coolant.
  • the invention relates to a method for integrating power electronic chips and bus bars forming heat sinks for producing an electronic power circuit.
  • the method comprises:
  • the production of the blank comprises a laminating step of two laminates having dielectric layers of resin prepreg comprising between them the electronic chip, and outer faces of the laminates being formed of a sheet of metal.
  • the embodiment of the blank comprises a step of removing material by machining to make at least one cavity in the blank and release at least one contact face of the electronic chip.
  • the embodiment of the blank comprises a step of electrolytic deposition of a conformal layer of metal.
  • the embodiment of the blank comprises a step of electrolytic deposition of metal filler.
  • the embodiment of the blank comprises a step of precise definition of connection patterns by photolithography and wet etching.
  • the invention relates to an electronic power circuit obtained by the implementation of the method as briefly described above, the metal used for the various manufacturing steps of the process being copper.
  • the invention relates to an electronic power device comprising at least two circuits as mentioned above, a first so-called top circuit being stacked on a second circuit said low, the high and low circuits being mechanically and electrically connected by their respective bus bars, at least one central coolant circulation space being located between the high and low circuits, and the central coolant circulation space being formed between sections of the bus bars.
  • the device also comprises at least one high liquid coolant circulation space which is located in an upper part of the device, and the high space of circulation of cooling liquid being formed between sections of a high bus bar of the high circuit and a high dielectric layer.
  • the device also comprises at least one low coolant circulation space which is located in a lower part of the device, and the low space for circulation of coolant being formed between sections. a bottom bus low circuit bus and a low dielectric layer.
  • the bridge branch comprises a high transistor and a low transistor, respectively "low side” and “high side” in English, and associated diodes.
  • Such devices may be associated to form complete switching bridges or associated in parallel to pass the desired current.
  • Figures 1 and 2 show an initial step of manufacturing a laminate LA1 formed of a dielectric layer CD1 coated with a conductive foil FC1.
  • the dielectric layer CD1 is a thick sheet of prepreg typically composed of a woven glass fiber dielectric coated with an epoxy type resin and partially polymerized.
  • the conductive foil FC1 is typically a copper foil which is laminated on the dielectric layer CD1, as shown in Fig.2.
  • chips of components for example, in the form of a power transistor MT and a diode MD, are transferred to the dielectric layer CD1 of the laminate LA1 to predetermined locations. Indexing means, not shown, are used here for the implementation of the chips.
  • the step of FIG. 4 shows the stratification of the LA1 laminate carrying the chips MT and MD with another laminate LA2 obtained by the steps of FIGS. 1 and 2.
  • the dielectric layers CD1 and CD2 do not are still only partially cured.
  • the chips MT and MD are then sandwiched between the laminates LA1 and LA2, more precisely between the dielectric layers CD1 and CD2 of the laminates.
  • Laminating LA1 and LA2 laminates between them is typically achieved by pressing and vacuum laminating.
  • a blank EB1 in which the chips MT and MD are buried in a dielectric layer CD, completely polymerized and from the stratification of the layers CD1 and CD2.
  • the copper foils FC1 and FC2 constitute opposite high and low sides of the blank EB1.
  • step of Fig.6 material removal operations by machining, for example by laser, are performed on the upper and lower faces of the blank EB1
  • CA1 cavities and CA5 are made of both sides of the blank to release contact faces of the MT and MD chips.
  • step of Fig.7 there is provided a metal layer CF conform on the machined high and low faces of the blank EB1.
  • the CF layer is typically a copper layer made by electrolytic deposition.
  • an electrolytic filling deposit is performed to completely fill the cavities CA1 to CA5 and all the opposite faces high and low of the blank EB1.
  • the upper and lower faces of the blank EB1 are then completely flat and covered with copper.
  • Figs.9 and 10 relate to the precise definition of the electrical connection patterns of the chips MT and MD.
  • a photoresist PS resin was coated on the upper and lower faces of the blank EB1 and the surface portions to be etched in wet etching were then defined and released in a conventional manner. using a silkscreen mask and exposure to ultraviolet radiation.
  • Fig.9 shows the blank EB1 ready for wet etching copper and copper portions CP1 to CP8 to remove.
  • Figs.1 1 to 13 show the BBH bus bar high bus interconnection and BBL low on the opposite high and low sides of the blank EB1.
  • BBH high bus bars and BBL low are here intended to form heat sinks located on the opposite sides high and low EB1 blank.
  • the busbars BBH, BBL are typically made of copper.
  • the BBH and BBL busbars are each formed of several bus sections BB1H, BB2H, BB3H and BB1L, BB2L, BB3L which have been previously cut, for example, by mechanical machining, or possibly obtained by molding.
  • Dielectric portions of prepreg PP1 H, PP2H, PP3H are reported on corresponding faces bus sections BB1 H, BB2H, BB3H intended to be plated on the upper face of the blank EB1.
  • Dielectric portions of prepreg PP1L, PP2L, PP3L are plotted on corresponding faces of bus sections BB1L, BB2L, BB3L intended to be plated on the lower face of the blank EB1.
  • the dielectric portions of prepreg PP1 H, PP2H, PP3 and PP1 h L> L PP2, PP3 L are intended to come fill the upper and lower cavities of the EB1 blank and join with the exposed portions PD1-PD4 and PD5 to PD8 of the underlying dielectric CD layer.
  • the blank EB1 is sandwiched between bus sections BB1 H, BB2 h , BB3H and BB1 L , BB2 L , BB3 L.
  • the bus sections BB1 H, BB2 H, BB3H and BB1 L, BB2L, BB3L are pressed, with the dielectric portions prepreg PP1 H, PP2H, PP3 h and PP1 L> PP2 L, PP3 L, against the upper and lower faces of the EB1 draft.
  • the lamination of the assembly is obtained by passing through the vacuum lamination oven.
  • Fig.12 shows the state of the blank EB1 with the assembled bus sections, when it is removed from the vacuum lamination oven.
  • the bus sections have been mechanically fixed to the circuit by the complete polymerization of the dielectric portions.
  • the dielectric circuit isolation patterns are finalized at this stage.
  • the step of Fig.13 is a metallization and soldering step which finalizes the interconnection of the conductive elements of the circuit and bus bars forming heat sinks of the blank EB1.
  • the copper layer MEH is deposited on the upper part of the blank EB1 is interconnected bus sections BB1 H, BB2H and BB3H bus bar BBH and the upper faces of the corresponding transistor chips MT and diode MD, for example, to drain and cathode electrodes.
  • the copper layer MELL is deposited on the lower part of the blank EB1 and interconnects the bus sections BB1 L, BB2L and BB3L BBL bus bus and low faces of transistor chips MT and diode MD corresponding to source and anode electrodes.
  • the method according to the invention allows the manufacture of elementary circuit bricks that can be assembled to constitute electronic power devices of greater or lesser complexity, with a sandwich architecture.
  • the assembly of the elementary bricks is typically carried out in press and in the oven.
  • the mechanical and electrical connections between the two bricks are made by welding. It will be noted that a parallelization of the manufacturing is possible by producing the elementary circuit bricks on several manufacturing lines.
  • the architecture of the elementary circuit bricks according to the invention allows a direct copper contact between the heat sinks, formed of the bus bars, and the electrodes of the electronic chips.
  • the heat sinks made of copper masses located on both sides of the electronic chips and in direct contact with them allows efficient extraction of calories.
  • the lengths of the connecting conductors are minimized, which promotes the reduction of parasitic inductances and more compactness.
  • Fig.14 shows a first EM1 embodiment of an electronic power device which is built by stacking two elementary bricks circuit BCHS and BCLS.
  • the device EM1 here is a bridge branch of transistors composed of two MOSFET transistors and two freewheeling diodes.
  • the mechanical and electrical connection of the two stacked elementary bricks BCHS and BCLS is performed at an IP junction plane by assembling the bus bars.
  • the assembly can be made, for example, by a transient liquid phase welding known as TLP or other welding techniques.
  • the EM1 device is here an embodiment with mixed cooling, by coolant and by air.
  • the assembly of the elementary bricks BBHS and BBLS creates in the central part of the device central spaces for circulating coolant, here CCi and CC2.
  • These coolant circulation spaces CC1 and CC2, located closer to the electronic chips, are provided for the pressurized circulation of a coolant coolant.
  • slotted profiles BBH and BBL bus bars, forming heat sinks increase the heat exchange surfaces with the surrounding air and promote cooling of the device.
  • Fig.15 shows a second EM2 embodiment of an electronic power device.
  • the EM2 device is provided with complete liquid cooling and is suitable for higher power applications than the EM1 device.
  • the device EM2 differs from the EM1 device in that it is equipped with control circuits CTRLHS and CTRLLS which are integrated in the upper and lower parts of the device EM2, respectively.
  • the control circuits CTRLHS and CTRLLS are mechanically fixed and electrically insulated from the top and bottom portions of the elementary bricks BCHS and BCLS by DLHS and DLLS dielectric layers, respectively.
  • the circuits CTRLHS and CTRLLS each comprise several stratified layers, made according to known techniques. Active and passive components may, if necessary, be buried between the internal layers of the CTRLHS and CTRLLS circuits, OR may be surface-mounted on the circuit in conventional manner by brazing or conducting glue.
  • the integration at the top and bottom of the device EM2 of the control circuits CTRLHS and CTRLLS with the insulating dielectric layers DLHS and DLLS allows the formation of high and low circulation spaces of additional coolants CH1, CH2 and CL1, CL2.
  • additional spaces CH1, CH2 and CL1, CL2 located on either side of the central spaces CC1 and CC2 allow increased cooling of the device EM2.
  • the electronic chips are thus cooled more efficiently by the circulation of a coolant near their upper and lower faces.
  • Other embodiments of electronic power devices according to the invention are of course possible.
  • the upper part and / or the lower part of the device can be closed with just a dielectric layer, without implanting a control circuit at this location.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

The method comprises: 1) producing a preform (EB1) integrating at least one electronic chip (MT, MD) included between insulating and/or conductive laminated internal layers; 2) mechanically securing metal bus-bar segments (BB1, BB2, BB3) at given spaced-apart positions on opposing upper and lower faces of the preform, using dielectric portions of resin prepreg (PP1, PP2, PP3); and 3) for each of the upper and lower opposing faces, electrodepositing a metal layer (ME) in order to interconnect bus-bar segments secured to the face in question and an electrode of the electronic chip, thereby forming an electronic power circuit comprising bus-bars forming heat sinks (BBH, BBL).

Description

PROCÉDÉ D'INTÉGRATION DE PUCES DE PUISSANCE ET DE  METHOD FOR INTEGRATION OF POWER CHIPS AND
BUS BARRES FORMANT DISSIPATEURS THERMIQUES  BUS BAR FORMING THERMAL DISSIPATORS
[001 ] La présente invention revendique la priorité de la demande française 1662804 déposée le 19 décembre 2016 dont le contenu (texte, dessins et revendications) est ici incorporé par référence. [001] The present invention claims the priority of the French application 1662804 filed December 19, 2016 whose content (text, drawings and claims) is here incorporated by reference.
[002] L'invention concerne de manière générale le domaine de l'électronique de puissance. Plus particulièrement, l'invention se rapporte à un procédé d'intégration de puces électroniques de puissance et d'interconnexion de bus barres formant dissipateurs thermiques dans des dispositifs électroniques de puissance tels que des convertisseurs et des modules de puissance. L'invention se rapporte aussi à des dispositifs électroniques de puissance obtenus par la mise en œuvre du procédé susmentionné. [002] The invention generally relates to the field of power electronics. More particularly, the invention relates to a method for integrating power electronic chips and interconnecting bus bars forming heat sinks in electronic power devices such as converters and power modules. The invention also relates to electronic power devices obtained by the implementation of the aforementioned method.
[003] Les dispositifs électroniques de puissance, tels que les convertisseurs de puissance, sont très présents dans de nombreux domaines d'activité comme les transports, les industries, l'éclairage, le chauffage, etc. Avec la transition énergétique souhaitée vers des sources d'énergie renouvelables et moins productrices d'émissions de CO2, l'électronique de puissance est appelée à se généraliser encore davantage et devra répondre à des contraintes économiques et technologiques croissantes. [004] Les recherches et développements actuels se concentrent sur la réduction des coûts, l'augmentation de la densité de puissance, l'augmentation de la fiabilité, la réduction des éléments parasites et le transfert thermique de l'énergie dissipée. [003] Power electronic devices, such as power converters, are very present in many fields of activity such as transport, industry, lighting, heating, etc. With the desired energy transition towards renewable and less carbon-intensive energy sources, power electronics will become more widespread and will have to respond to increasing economic and technological constraints. [004] Current research and developments focus on reducing costs, increasing power density, increasing reliability, reducing parasitic elements and heat transfer of dissipated energy.
[005] Dans l'état actuel de la technique, il est habituel de faire appel à la technologie dite HDI, de « High Density Interconnect » en anglais, pour augmenter le niveau d'intégration et réduire la taille des circuits de puissance. La technologie HDI implémentée généralement sur des circuits imprimés dit PCB, de « Printed Circuit Board » en anglais, est fondée sur une optimisation de l'implantation spatiale des composants en utilisant notamment des rubans et des plaques de céramiques portant un circuit de traces en cuivre, dit « lead frames », pour interconnecter des composants montés en surface ou, dans une technologie plus avancée, des micro-trous dits « microvias » remplis de cuivre pour interconnecter des composants encastrés. Il est utilisé le perçage par rayon laser ainsi que différentes techniques de soudure telles que par exemple le brasage, la soudure en phase liquide transitoire dite soudure TLP ou le frittage de poudre de nanoparticules métalliques. [005] In the current state of the art, it is usual to use the so-called HDI technology, "High Density Interconnect" in English, to increase the level of integration and reduce the size of the power circuits. The HDI technology generally implemented on printed circuit boards known as PCB, from the "Printed Circuit Board" in English, is based on an optimization of the spatial implantation of the components, in particular by using ribbons and ceramic plates carrying a copper trace circuit. lead frames, to interconnect surface-mounted components or, in a more advanced, micro-holes called "microvias" filled with copper to interconnect embedded components. It is used laser beam drilling as well as various welding techniques such as for example brazing, transient liquid phase welding known as TLP welding or sintering of metal nanoparticle powder.
[006] La technologie HDI trouve cependant ses limites face aux réductions de coût qui sont nécessaires pour des productions de masse, et à l'augmentation du niveau d'intégration et de la compacité. Le niveau d'intégration qu'il est possible d'obtenir est limité par le volume occupé par les interconnexions avec rubans et microvias. Les interconnexions avec rubans ou câbles introduisent des inductances parasites qui s'opposent à des fréquences de découpage ou de commutation plus élevées. Or l'augmentation des fréquences de commutation est généralement favorable à la compacité, notamment dans les convertisseurs de puissance. La réduction des inductances parasites est nécessaire aussi pour réduire la chaleur générée, protéger les circuits par rapport à des surtensions potentiellement destructrices et améliorer la maîtrise des rayonnements électromagnétiques. [006] HDI technology, however, finds its limits in the face of cost reductions that are necessary for mass production, and increasing the level of integration and compactness. The level of integration that can be achieved is limited by the volume occupied by the interconnections with ribbons and microvias. Interconnections with ribbons or cables introduce parasitic inductances that oppose higher switching or switching frequencies. However, the increase in switching frequencies is generally favorable to compactness, particularly in power converters. The reduction of parasitic inductances is also necessary to reduce the generated heat, protect the circuits against potentially destructive overvoltages and improve the control of electromagnetic radiation.
[007] Un refroidissement performant est nécessaire pour maintenir les températures les composants actifs et passifs en dessous de valeurs critiques, pour atteindre un équilibre thermique et garantir la fiabilité des circuits de puissance. La disponibilité de puces en silicium ayant des surfaces de plus en plus réduites et les nouveaux semi-conducteurs de puissance, comme le carbure de silicium, autorisent des densités de courant supérieures et une augmentation de la fréquence de découpage, ce qui permet une compacité encore supérieure des circuits de puissance. Mais pour cela, l'architecture des circuits de puissance et la technologie utilisée doivent assurer une extraction de l'énergie dissipée au plus près des composants. Il est nécessaire d'optimiser le chemin thermique entre les sources de chaleur constituées des composants et les puits de chaleur constitués des moyens de dissipation thermique. [008] Dans les technologies connues, la chaleur doit traverser différentes couches comme la soudure, le substrat diélectrique plaqué de cuivre, la plaque métallique de base, le matériau d'interface thermique et la masse du dissipateur de chaleur, avant d'être transférée dans l'air ou dans un liquide de refroidissement. [007] High performance cooling is necessary to keep the active and passive components temperatures below critical values, to achieve thermal equilibrium and to guarantee the reliability of the power circuits. The availability of silicon chips with increasingly smaller surface areas and the new power semiconductors, such as silicon carbide, allow higher current densities and increased chopping frequency, allowing for even more compactness. superior power circuits. But for this, the architecture of the power circuits and the technology used must ensure an extraction of the energy dissipated closer to the components. It is necessary to optimize the thermal path between the heat sources constituted by the components and the heat sinks constituted by the heat dissipation means. [008] In known technologies, the heat must pass through different layers such as solder, the dielectric substrate plated with copper, the plate base metal, the thermal interface material and the mass of the heat sink, before being transferred to air or a coolant.
[009] Il apparaît aujourd'hui nécessaire de proposer une technologie nouvelle pour la fabrication de dispositifs électroniques de puissance ayant des performances supérieures de dissipation thermique et autorisant une meilleure optimisation par rapport aux différentes contraintes qui s'appliquent. [009] It now appears necessary to propose a new technology for the manufacture of electronic power devices having higher heat dissipation performance and allowing better optimization with respect to the different constraints that apply.
[0010] Selon un premier aspect, l'invention concerne un procédé d'intégration de puces électroniques de puissance et de bus barres formant dissipateurs thermiques pour la réalisation d'un circuit électronique de puissance. Conformément à l'invention, le procédé comprend : According to a first aspect, the invention relates to a method for integrating power electronic chips and bus bars forming heat sinks for producing an electronic power circuit. According to the invention, the method comprises:
- une réalisation d'une ébauche intégrant au moins une puce électronique comprise entre des couches internes stratifiées isolantes et/ou conductrices ; an embodiment of a blank incorporating at least one electronic chip between insulating and / or conductive laminated inner layers;
- une fixation mécanique, par l'intermédiaire de portions diélectriques de préimprégné de résine, de tronçons de bus barre en métal à des emplacements espacés prédéterminés sur des faces opposées haute et basse de l'ébauche ; et a mechanical fixing, by means of dielectric portions of resin prepreg, of metal bar bus sections at predetermined spaced locations on opposite high and low sides of the blank; and
- pour chacune des faces opposées haute et basse, une interconnexion par dépôt électrolytique de couche de métal des tronçons de bus barre fixés sur la face considérée et d'une électrode de la puce électronique, formant ainsi le circuit électronique de puissance comportant des bus barres formant dissipateurs thermiques. for each of the opposite high and low faces, an interconnection by electrolytic deposition of the metal layer of the busbar sections fixed on the face in question and of an electrode of the electronic chip, thus forming the power electronic circuit comprising bus bars; forming heat sinks.
[001 1 ] Selon une caractéristique particulière du procédé de l'invention, la réalisation de l'ébauche comporte une étape de stratification de deux stratifiés ayant des couches diélectriques de préimprégné de résine comprenant entre elles la puce électronique, et des faces extérieures des stratifiés étant formées d'une feuille en métal. [001 1] According to a particular characteristic of the process of the invention, the production of the blank comprises a laminating step of two laminates having dielectric layers of resin prepreg comprising between them the electronic chip, and outer faces of the laminates being formed of a sheet of metal.
[0012] Selon une autre caractéristique particulière, la réalisation de l'ébauche comporte une étape de retrait de matière par usinage pour réaliser au moins une cavité dans l'ébauche et dégager au moins une face de contact de la puce électronique. [0013] Selon encore une autre caractéristique particulière, la réalisation de l'ébauche comporte une étape de dépôt électrolytique d'une couche conforme de métal. According to another particular feature, the embodiment of the blank comprises a step of removing material by machining to make at least one cavity in the blank and release at least one contact face of the electronic chip. According to yet another particular characteristic, the embodiment of the blank comprises a step of electrolytic deposition of a conformal layer of metal.
[0014] Selon encore une autre caractéristique particulière, la réalisation de l'ébauche comporte une étape de dépôt électrolytique de remplissage de métal. According to yet another particular characteristic, the embodiment of the blank comprises a step of electrolytic deposition of metal filler.
[0015] Selon encore une autre caractéristique particulière, la réalisation de l'ébauche comporte une étape de définition précise de motifs de connexion par photolithographie et gravure humide. According to yet another particular characteristic, the embodiment of the blank comprises a step of precise definition of connection patterns by photolithography and wet etching.
[0016] Selon un autre aspect, l'invention concerne un circuit électronique de puissance obtenu par la mise en œuvre du procédé tel que décrit brièvement ci- dessus, le métal utilisé pour les différentes étapes de fabrication du procédé étant le cuivre. In another aspect, the invention relates to an electronic power circuit obtained by the implementation of the method as briefly described above, the metal used for the various manufacturing steps of the process being copper.
[0017] Selon encore un autre aspect, l'invention concerne un dispositif électronique de puissance comprenant au moins deux circuits tels que mentionnés ci-dessus, un premier circuit dit haut étant empilé sur un deuxième circuit dit bas, les circuits haut et bas étant liés mécaniquement et électriquement par leurs bus barres respectifs, au moins un espace central de circulation de liquide de refroidissement étant situé entre les circuits haut et bas, et l'espace central de circulation de liquide de refroidissement étant formé entre des tronçons des bus barres. According to yet another aspect, the invention relates to an electronic power device comprising at least two circuits as mentioned above, a first so-called top circuit being stacked on a second circuit said low, the high and low circuits being mechanically and electrically connected by their respective bus bars, at least one central coolant circulation space being located between the high and low circuits, and the central coolant circulation space being formed between sections of the bus bars.
[0018] Selon une caractéristique particulière, le dispositif comprend également au moins un espace haut de circulation de liquide de refroidissement qui est situé dans une partie haute du dispositif, et l'espace haut de circulation de liquide de refroidissement étant formé entre des tronçons d'un bus barre haut du circuit haut et une couche diélectrique haute. According to a particular feature, the device also comprises at least one high liquid coolant circulation space which is located in an upper part of the device, and the high space of circulation of cooling liquid being formed between sections of a high bus bar of the high circuit and a high dielectric layer.
[0019] Selon une autre caractéristique particulière, le dispositif comprend également au moins un espace bas de circulation de liquide de refroidissement qui est situé dans une partie basse du dispositif, et l'espace bas de circulation de liquide de refroidissement étant formé entre des tronçons d'un bus barre bas du circuit bas et une couche diélectrique basse. [0020] D'autres avantages et caractéristiques de la présente invention apparaîtront plus clairement à la lecture de la description détaillée ci-dessous de plusieurs formes de réalisation particulières de l'invention, en référence aux dessins annexés, dans lesquels : les Figs.1 à 13 sont des vues en coupe simplifiées montrant des étapes du procédé d'intégration de puces électroniques de puissance et de bus barres formant dissipateurs thermiques selon l'invention ; et les Figs.14 et 15 sont des vues en coupe simplifiées montrant des première et deuxième formes de réalisation d'un dispositif électronique de puissance selon l'invention, avec une dissipation thermique par air et par liquide de refroidissement. According to another particular feature, the device also comprises at least one low coolant circulation space which is located in a lower part of the device, and the low space for circulation of coolant being formed between sections. a bottom bus low circuit bus and a low dielectric layer. Other advantages and features of the present invention will appear more clearly on reading the detailed description below of several particular embodiments of the invention, with reference to the accompanying drawings, in which: Figs.1 13 are simplified sectional views showing steps of the method of integrating power electronic chips and bus bars forming heat sinks according to the invention; and Figs. 14 and 15 are simplified sectional views showing first and second embodiments of an electronic power device according to the invention, with heat dissipation by air and coolant.
[0021 ] Un mode de réalisation particulier du procédé selon l'invention est maintenant décrit ci-dessus dans le cadre de la réalisation d'un dispositif ou module électronique de puissance sous la forme d'une branche de pont, ou demi- pont, de commutation à transistors. De manière classique, la branche de pont comprend un transistor haut et un transistor bas, dits respectivement «low side» et «high side» en anglais, et des diodes associées. De tels dispositifs peuvent être associés pour former des ponts complets de commutation ou associés en parallèle pour passer le courant voulu. A particular embodiment of the method according to the invention is now described above in the context of the realization of an electronic device or power module in the form of a bridge branch, or half-bridge, switching transistor. Conventionally, the bridge branch comprises a high transistor and a low transistor, respectively "low side" and "high side" in English, and associated diodes. Such devices may be associated to form complete switching bridges or associated in parallel to pass the desired current.
[0022] De manière générale, il est utilisé dans l'invention des techniques de fabrication connues et bien maîtrisées des circuits imprimés pour l'intégration des puces électroniques. Ainsi, il pourra être fait appel dans le procédé selon l'invention à une combinaison de différentes techniques de fabrication comprenant la stratification, la photolithographie, le dépôt électrolytique de métal et la gravure humide. Le dépôt électrolytique de métal sera notamment utilisé pour l'interconnexion des puces électroniques et des bus barres. In general, it is used in the invention known manufacturing techniques and well-mastered printed circuits for the integration of electronic chips. Thus, it will be possible to use in the process according to the invention a combination of different manufacturing techniques including stratification, photolithography, electrolytic deposition of metal and wet etching. The electrolytic deposition of metal will be used in particular for the interconnection of electronic chips and bus bars.
[0023] En référence aux Figs.1 à 13, il est maintenant décrit en détail différentes étapes de fabrication intervenant dans le procédé d'intégration de puces électroniques de puissance et d'interconnexion de bus barres selon l'invention. [0024] Les Figs.1 et 2 montrent une étape initiale de fabrication d'un stratifié LA1 formé d'une couche diélectrique CD1 revêtue d'une feuille métallique conductrice FC1 . Referring to Figs.1 to 13, it is now described in detail different manufacturing steps involved in the method of integration of power electronic chips and bar bus interconnection according to the invention. Figures 1 and 2 show an initial step of manufacturing a laminate LA1 formed of a dielectric layer CD1 coated with a conductive foil FC1.
[0025] La couche diélectrique CD1 est une feuille épaisse de préimprégné composée typiquement d'un diélectrique en fibres de verre tissées enduit d'une résine de type époxy et partiellement polymérisé. La feuille métallique conductrice FC1 est typiquement une feuille de cuivre qui est stratifiée sur la couche diélectrique CD1 , comme montré à la Fig.2. The dielectric layer CD1 is a thick sheet of prepreg typically composed of a woven glass fiber dielectric coated with an epoxy type resin and partially polymerized. The conductive foil FC1 is typically a copper foil which is laminated on the dielectric layer CD1, as shown in Fig.2.
[0026] A l'étape de la Fig.3, des puces de composants, par exemple, sous la forme d'un transistor de puissance MT et d'une diode MD, sont reportées sur la couche diélectrique CD1 du stratifié LA1 à des emplacements prédéterminés. Des moyens d'indexation, non représentés, sont utilisés ici pour la mise en place des puces. In the step of FIG. 3, chips of components, for example, in the form of a power transistor MT and a diode MD, are transferred to the dielectric layer CD1 of the laminate LA1 to predetermined locations. Indexing means, not shown, are used here for the implementation of the chips.
[0027] L'étape de la Fig.4 montre la stratification du stratifié LA1 portant les puces MT et MD avec un autre stratifié LA2 obtenu par les étapes des Figs.1 et 2. A ce stade, les couches diélectriques CD1 et CD2 ne sont encore que partiellement polymérisées. Les puces MT et MD sont alors prises en sandwich entre les stratifiés LA1 et LA2, plus précisément entres les couches diélectriques CD1 et CD2 des stratifiés. La stratification entre eux des stratifiés LA1 et LA2 est typiquement obtenue par pressage et passage au four de stratification sous vide. The step of FIG. 4 shows the stratification of the LA1 laminate carrying the chips MT and MD with another laminate LA2 obtained by the steps of FIGS. 1 and 2. At this stage, the dielectric layers CD1 and CD2 do not are still only partially cured. The chips MT and MD are then sandwiched between the laminates LA1 and LA2, more precisely between the dielectric layers CD1 and CD2 of the laminates. Laminating LA1 and LA2 laminates between them is typically achieved by pressing and vacuum laminating.
[0028] En sortie du four de stratification sous vide, à la Fig.5, il est obtenu une ébauche EB1 dans laquelle les puces MT et MD sont enterrées dans une couche diélectrique CD, totalement polymérisée et provenant de la stratification des couches CD1 et CD2. Les feuilles de cuivre FC1 et FC2 constituent des faces opposées haute et basse de l'ébauche EB1 . At the outlet of the vacuum laminating oven, in Fig.5, there is obtained a blank EB1 in which the chips MT and MD are buried in a dielectric layer CD, completely polymerized and from the stratification of the layers CD1 and CD2. The copper foils FC1 and FC2 constitute opposite high and low sides of the blank EB1.
[0029] A l'étape de la Fig.6, des opérations de retrait de matière par usinage, par exemple au laser, sont effectuées sur les faces haute et basse de l'ébauche EB1 et des cavités CA1 à CA5 sont réalisées des deux côtés de l'ébauche pour dégager des faces de contact des puces MT et MD. [0030] A l'étape de la Fig.7, il est réalisé une couche métallique CF conforme sur les faces haute et basse usinées de l'ébauche EB1 . La couche CF est typiquement une couche de cuivre réalisée par dépôt électrolytique. In the step of Fig.6, material removal operations by machining, for example by laser, are performed on the upper and lower faces of the blank EB1 CA1 cavities and CA5 are made of both sides of the blank to release contact faces of the MT and MD chips. In the step of Fig.7, there is provided a metal layer CF conform on the machined high and low faces of the blank EB1. The CF layer is typically a copper layer made by electrolytic deposition.
[0031 ] A l'étape de la Fig.8, un dépôt électrolytique de remplissage est effectué pour remplir complètement de cuivre les cavités CA1 à CA5 et la totalité des faces opposées haute et basse de l'ébauche EB1 . Les faces haute et basse de l'ébauche EB1 sont alors complètement planes et recouvertes de cuivre. In the step of Fig.8, an electrolytic filling deposit is performed to completely fill the cavities CA1 to CA5 and all the opposite faces high and low of the blank EB1. The upper and lower faces of the blank EB1 are then completely flat and covered with copper.
[0032] Les étapes des Figs.9 et 10 concernent la définition précise des motifs de connexion électrique des puces MT et MD. [0033] A l'étape de la Fig.9, une résine photorésist PS a été enduite sur les faces haute et basse de l'ébauche EB1 et les parties de surface à attaquer en gravure humide ont ensuite été définies et dégagées de manière classique en faisant appel à un masque de sérigraphie et une exposition à un rayonnement ultraviolet. La Fig.9 montre l'ébauche EB1 prête pour la gravure humide du cuivre et des portions de cuivre CP1 à CP8 à retirer. The steps of Figs.9 and 10 relate to the precise definition of the electrical connection patterns of the chips MT and MD. At the step of Fig.9, a photoresist PS resin was coated on the upper and lower faces of the blank EB1 and the surface portions to be etched in wet etching were then defined and released in a conventional manner. using a silkscreen mask and exposure to ultraviolet radiation. Fig.9 shows the blank EB1 ready for wet etching copper and copper portions CP1 to CP8 to remove.
[0034] A l'étape de la Fig.10, les portions de cuivre CP1 à CP8 ont été retirées par gravure humide et le motif de connexion est alors défini avec précision. Le retrait des portions de cuivre CP1 à CP8 des cavités PD1 à PD8 qui laissent apparaître des portions de la couche diélectrique CD sous-jacente. [0035] Les Figs.1 1 à 13 montrent l'interconnexion de bus barres haut BBH et bas BBL sur les faces opposées haute et basse de l'ébauche EB1 . Outre leurs fonctions électriques habituelles d'alimentation électrique ou autres, les bus barres haut BBH et bas BBL sont ici destinés à former des dissipateurs thermiques implantés sur les faces opposées haute et basse de l'ébauche EB1 . Les bus barres BBH, BBL sont typiquement en cuivre. In the step of Fig.10, the copper portions CP1 to CP8 were removed by wet etching and the connection pattern is then defined accurately. The removal of the copper portions CP1 to CP8 cavities PD1 PD8 which reveal portions of the underlying dielectric layer CD. Figs.1 1 to 13 show the BBH bus bar high bus interconnection and BBL low on the opposite high and low sides of the blank EB1. In addition to their usual electric power supply or other functions, BBH high bus bars and BBL low are here intended to form heat sinks located on the opposite sides high and low EB1 blank. The busbars BBH, BBL are typically made of copper.
[0036] Comme montré à la Fig.1 1 , les bus barres BBH et bas BBL sont formés chacun de plusieurs tronçons de bus BB1 H, BB2H, BB3H et BB1 L, BB2L, BB3L qui ont été préalablement découpés, par exemple, par usinage mécanique, ou éventuellement obtenus par moulage. [0037] Des portions diélectriques de préimprégné PP1 H, PP2H, PP3H sont reportées sur des faces correspondantes des tronçons de bus BB1 H, BB2H, BB3H destinées à être plaquées sur la face haute de l'ébauche EB1 . Des portions diélectriques de préimprégné PP1 L, PP2L, PP3L sont reportées sur des faces correspondantes des tronçons de bus BB1 L, BB2L, BB3L destinées à être plaquées sur la face basse de l'ébauche EB1 . Les portions diélectriques de préimprégné PP1 H, PP2H, PP3h et PP1 L> PP2L, PP3L sont prévues pour venir remplir les cavités hautes et basses de l'ébauche EB1 et adhérer avec les portions apparentes PD1 à PD4 et PD5 à PD8 de la couche diélectrique CD sous-jacente. [0038] L'ébauche EB1 est ainsi prise en sandwich entre les tronçons de bus BB1 H, BB2h, BB3H et BB1 L, BB2L, BB3L. Les tronçons de bus BB1 H, BB2H, BB3H et BB1 L, BB2L, BB3L sont pressés, avec les portions diélectriques de préimprégné PP1 H, PP2H, PP3h et PP1 L> PP2L, PP3L, contre les faces haute et basse de l'ébauche EB1 . [0039] La stratification de l'ensemble est obtenue par passage au four de stratification sous vide. La Fig.12 montre l'état de l'ébauche EB1 avec les tronçons de bus assemblés, lorsque celle-ci est sortie du four de stratification sous vide. A ce stade, les tronçons de bus ont été fixés mécaniquement au circuit par la polymérisation complète des portions diélectriques. Les motifs diélectriques d'isolation du circuit sont finalisés à ce stade. As shown in FIG. 1, the BBH and BBL busbars are each formed of several bus sections BB1H, BB2H, BB3H and BB1L, BB2L, BB3L which have been previously cut, for example, by mechanical machining, or possibly obtained by molding. Dielectric portions of prepreg PP1 H, PP2H, PP3H are reported on corresponding faces bus sections BB1 H, BB2H, BB3H intended to be plated on the upper face of the blank EB1. Dielectric portions of prepreg PP1L, PP2L, PP3L are plotted on corresponding faces of bus sections BB1L, BB2L, BB3L intended to be plated on the lower face of the blank EB1. The dielectric portions of prepreg PP1 H, PP2H, PP3 and PP1 h L> L PP2, PP3 L are intended to come fill the upper and lower cavities of the EB1 blank and join with the exposed portions PD1-PD4 and PD5 to PD8 of the underlying dielectric CD layer. The blank EB1 is sandwiched between bus sections BB1 H, BB2 h , BB3H and BB1 L , BB2 L , BB3 L. The bus sections BB1 H, BB2 H, BB3H and BB1 L, BB2L, BB3L are pressed, with the dielectric portions prepreg PP1 H, PP2H, PP3 h and PP1 L> PP2 L, PP3 L, against the upper and lower faces of the EB1 draft. The lamination of the assembly is obtained by passing through the vacuum lamination oven. Fig.12 shows the state of the blank EB1 with the assembled bus sections, when it is removed from the vacuum lamination oven. At this stage, the bus sections have been mechanically fixed to the circuit by the complete polymerization of the dielectric portions. The dielectric circuit isolation patterns are finalized at this stage.
[0040] L'étape de la Fig.13 est une étape de métallisation et soudure qui permet de finaliser l'interconnexion des éléments conducteurs du circuit et des bus barres formant dissipateurs thermiques de l'ébauche EB1 . The step of Fig.13 is a metallization and soldering step which finalizes the interconnection of the conductive elements of the circuit and bus bars forming heat sinks of the blank EB1.
[0041 ] Comme montré à la Fig.13, des couches de cuivre MEH et MEL sont déposées par électrolyse sur les parties haute et basse de l'ébauche EB1 . As shown in Fig.13, copper layers MEH and MEL are electrolytically deposited on the upper and lower parts of the blank EB1.
[0042] La couche de cuivre MEH est déposée sur la partie haute de l'ébauche EB1 est interconnecte les tronçons de bus BB1 H, BB2H et BB3H du bus barre BBH et des faces hautes des puces de transistor MT et de diode MD correspondant, par exemple, à des électrodes de drain et de cathode. La couche de cuivre MELL est déposée sur la partie basse de l'ébauche EB1 et interconnecte les tronçons de bus BB1 L, BB2L et BB3L du bus barre BBL et des faces basses des puces de transistor MT et de diode MD correspondant à des électrodes de source et d'anode. The copper layer MEH is deposited on the upper part of the blank EB1 is interconnected bus sections BB1 H, BB2H and BB3H bus bar BBH and the upper faces of the corresponding transistor chips MT and diode MD, for example, to drain and cathode electrodes. The copper layer MELL is deposited on the lower part of the blank EB1 and interconnects the bus sections BB1 L, BB2L and BB3L BBL bus bus and low faces of transistor chips MT and diode MD corresponding to source and anode electrodes.
[0043] Le procédé selon l'invention, tel que décrit plus haut en référence aux Figs.1 à 13, autorise la fabrication de briques élémentaires de circuit qui peuvent être assemblées pour constituer des dispositifs électroniques de puissance de complexité plus ou moins grande, avec une architecture en sandwich. L'assemblage des briques élémentaires est typiquement réalisé sous presse et passage au four. Les liaisons mécaniques et électriques entre les deux briques sont faites par soudure. On notera qu'une parallélisation de la fabrication est possible en produisant les briques élémentaires de circuit sur plusieurs lignes de fabrication. The method according to the invention, as described above with reference to Figs.1 to 13, allows the manufacture of elementary circuit bricks that can be assembled to constitute electronic power devices of greater or lesser complexity, with a sandwich architecture. The assembly of the elementary bricks is typically carried out in press and in the oven. The mechanical and electrical connections between the two bricks are made by welding. It will be noted that a parallelization of the manufacturing is possible by producing the elementary circuit bricks on several manufacturing lines.
[0044] L'architecture des briques élémentaires de circuit selon l'invention permet un contact en cuivre direct entre les dissipateurs thermiques, formés des bus barres, et les électrodes des puces électroniques. Les dissipateurs thermiques constitués de masses de cuivre situées de part et d'autre des puces électroniques et en contact direct avec celles-ci autorise une extraction efficace des calories. De plus, les longueurs des conducteurs de connexion sont minimisées, ce qui favorise la réduction des inductances parasites et davantage de compacité. The architecture of the elementary circuit bricks according to the invention allows a direct copper contact between the heat sinks, formed of the bus bars, and the electrodes of the electronic chips. The heat sinks made of copper masses located on both sides of the electronic chips and in direct contact with them allows efficient extraction of calories. In addition, the lengths of the connecting conductors are minimized, which promotes the reduction of parasitic inductances and more compactness.
[0045] La Fig.14 montre une première forme de réalisation EM1 d'un dispositif électronique de puissance qui est construit par empilement de deux briques élémentaires de circuit BCHS et BCLS. Le dispositif EM1 est ici une branche de pont de transistors composée de deux transistors MOSFET et deux diodes de roue libre. Fig.14 shows a first EM1 embodiment of an electronic power device which is built by stacking two elementary bricks circuit BCHS and BCLS. The device EM1 here is a bridge branch of transistors composed of two MOSFET transistors and two freewheeling diodes.
[0046] La liaison mécanique et électrique des deux briques élémentaires empilées BCHS et BCLS est réalisée au niveau d'un plan de jonction IP par assemblage des bus barres. L'assemblage pourra être fait, par exemple, par une soudure à phase liquide transitoire dite TLP ou d'autres techniques de soudure. The mechanical and electrical connection of the two stacked elementary bricks BCHS and BCLS is performed at an IP junction plane by assembling the bus bars. The assembly can be made, for example, by a transient liquid phase welding known as TLP or other welding techniques.
[0047] Le dispositif EM1 est ici une forme de réalisation à refroidissement mixte, par liquide de refroidissement et par air. [0048] Comme montré à la Fig.14, l'assemblage des briques élémentaires BBHS et BBLS crée en partie centrale du dispositif des espaces centraux de circulation de liquide de refroidissement, ici CCi et CC2. Ces espaces de circulation de liquide de refroidissement CC1 et CC2, situés au plus près des puces électroniques, sont prévus pour la circulation sous pression d'un liquide de refroidissement caloporteur. Dans les parties haute et basse du dispositif EM1 , des profils en créneau des bus barres BBH et BBL, formant dissipateurs thermiques, augmentent les surfaces d'échange thermique avec l'air environnant et favorisent le refroidissement du dispositif. [0049] La Fig.15 montre une deuxième forme de réalisation EM2 d'un dispositif électronique de puissance. Le dispositif EM2 est prévu avec un refroidissement liquide complet et est adapté pour des applications de plus forte puissance que celles du dispositif EM1 . The EM1 device is here an embodiment with mixed cooling, by coolant and by air. As shown in Fig.14, the assembly of the elementary bricks BBHS and BBLS creates in the central part of the device central spaces for circulating coolant, here CCi and CC2. These coolant circulation spaces CC1 and CC2, located closer to the electronic chips, are provided for the pressurized circulation of a coolant coolant. In the upper and lower parts of the EM1 device, slotted profiles BBH and BBL bus bars, forming heat sinks, increase the heat exchange surfaces with the surrounding air and promote cooling of the device. Fig.15 shows a second EM2 embodiment of an electronic power device. The EM2 device is provided with complete liquid cooling and is suitable for higher power applications than the EM1 device.
[0050] Le dispositif EM2 se distingue du dispositif EM1 en ce qu'il est équipé de circuits de commande CTRLHS et CTRLLS qui sont intégrés en parties haute et basse du dispositif EM2, respectivement. Les circuits de commande CTRLHS et CTRLLS sont fixés mécaniquement et isolés électriquement des parties haute et basse des briques élémentaires BCHS et BCLS par des couches diélectriques DLHS et DLLS, respectivement. Les circuits CTRLHS et CTRLLS comportent chacun plusieurs couches stratifiées, réalisées selon des techniques connues. Des composants actifs et passifs pourront si nécessaire être enfouis entre les couches internes des circuits CTRLHS et CTRLLS, OU bien implantés en surface sur le circuit de manière classique par brasure ou colle conductrice. The device EM2 differs from the EM1 device in that it is equipped with control circuits CTRLHS and CTRLLS which are integrated in the upper and lower parts of the device EM2, respectively. The control circuits CTRLHS and CTRLLS are mechanically fixed and electrically insulated from the top and bottom portions of the elementary bricks BCHS and BCLS by DLHS and DLLS dielectric layers, respectively. The circuits CTRLHS and CTRLLS each comprise several stratified layers, made according to known techniques. Active and passive components may, if necessary, be buried between the internal layers of the CTRLHS and CTRLLS circuits, OR may be surface-mounted on the circuit in conventional manner by brazing or conducting glue.
[0051 ] Comme cela apparaît à la Fig.15, l'intégration en partie haute et basse du dispositif EM2 des circuits de commande CTRLHS et CTRLLS avec les couches diélectriques isolantes DLHS et DLLS permet la formation d'espaces haut et bas de circulation de liquide de refroidissement supplémentaires CH1 , CH2 et CL1 , CL2. Ces espaces supplémentaires CH1 , CH2 et CL1 , CL2 situés de part et d'autre des espaces centraux CC1 et CC2 autorisent un refroidissement accru du dispositif EM2. Les puces électroniques sont ainsi refroidies de manière plus efficace par la circulation d'un liquide caloporteur à proximité de leurs faces haute et basse. [0052] D'autres formes de réalisation de dispositifs électroniques de puissance selon l'invention sont bien entendu possibles. Ainsi, par exemple, la partie haute et/ou la partie basse du dispositif pourra être fermée avec simplement une couche diélectrique, sans pour autant implanter un circuit de commande à cet emplacement. As shown in FIG. 15, the integration at the top and bottom of the device EM2 of the control circuits CTRLHS and CTRLLS with the insulating dielectric layers DLHS and DLLS allows the formation of high and low circulation spaces of additional coolants CH1, CH2 and CL1, CL2. These additional spaces CH1, CH2 and CL1, CL2 located on either side of the central spaces CC1 and CC2 allow increased cooling of the device EM2. The electronic chips are thus cooled more efficiently by the circulation of a coolant near their upper and lower faces. Other embodiments of electronic power devices according to the invention are of course possible. Thus, for example, the upper part and / or the lower part of the device can be closed with just a dielectric layer, without implanting a control circuit at this location.
[0053] L'invention ne se limite pas aux formes de réalisation particulières qui ont été décrites ici à titre d'exemple. L'homme du métier, selon les applications de l'invention, pourra apporter différentes modifications et variantes qui entrent dans la portée des revendications ci-annexées. The invention is not limited to the particular embodiments which have been described here by way of example. Those skilled in the art, according to the applications of the invention, may make various modifications and variations which fall within the scope of the appended claims.

Claims

REVENDICATIONS
1 ) Procédé d'intégration de puces électroniques de puissance et de bus barres formant dissipateurs thermiques pour la réalisation d'un circuit électronique de puissance, caractérisé en ce qu'il comprend : 1) A method for integrating power electronic chips and bus bars forming heat sinks for producing an electronic power circuit, characterized in that it comprises:
- une réalisation d'une ébauche (EB1 ) intégrant au moins une puce électronique (MT, MD) comprise entre des couches internes stratifiées isolantes et/ou conductrices ; - A realization of a blank (EB1) incorporating at least one electronic chip (MT, MD) between insulating and / or conductive laminate inner layers;
- une fixation mécanique, par l'intermédiaire de portions diélectriques de préimprégné de résine (PP1 , PP2, PP3), de tronçons de bus barre en métala mechanical fixing, by means of dielectric portions of resin prepreg (PP1, PP2, PP3), of bar bus sections made of metal
(BB1 , BB2, BB3) à des emplacements espacés prédéterminés sur des faces opposées haute et basse de ladite ébauche (EB1 ) ; et (BB1, BB2, BB3) at predetermined spaced locations on opposite high and low faces of said blank (EB1); and
- pour chacune desdites faces opposées haute et basse, une interconnexion par dépôt électrolytique de couche de métal (ME) desdits tronçons de bus barre (BB1 , BB2, BB3) fixés sur la face considérée et d'une électrode de ladite puce électronique (MT, MD), formant ainsi ledit circuit électronique de puissance comportant des bus barres (BBH, BBL) formant dissipateurs thermiques. for each of said opposite high and low faces, an interconnection by electrolytic deposition of metal layer (ME) of said busbar sections (BB1, BB2, BB3) fixed on the face in question and of an electrode of said electronic chip (MT , MD), thereby forming said power electronic circuit comprising busbars (BBH, BBL) forming heat sinks.
2) Procédé selon la revendication 1 , caractérisé en ce que ladite réalisation de l'ébauche (EB1 ) comporte une étape de stratification de deux stratifiés (LA1 , LA2) ayant des couches diélectriques de préimprégné de résine (CD1 , CD2) comprenant entre elles ladite puce électronique (MT, MD), des faces extérieures desdits stratifiés (LA1 , LA2) étant formées d'une feuille en métal (FC1 , FC2). 2) Method according to claim 1, characterized in that said embodiment of the blank (EB1) comprises a laminating step of two laminates (LA1, LA2) having dielectric layers of resin prepreg (CD1, CD2) comprising them said electronic chip (MT, MD), outer faces of said laminates (LA1, LA2) being formed of a metal sheet (FC1, FC2).
3) Procédé selon la revendication 1 ou 2, caractérisé en ce que ladite réalisation de l'ébauche (EB1 ) comporte une étape de retrait de matière par usinage pour réaliser au moins une cavité (CA1 à CA5) dans ladite ébauche (EB1 ) et dégager au moins une face de contact de ladite puce électronique (MT, MD). 4) Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que ladite réalisation de l'ébauche (EB1 ) comporte une étape de dépôt électrolytique d'une couche conforme de métal (CF). 3) Method according to claim 1 or 2, characterized in that said embodiment of the blank (EB1) comprises a step of removing material by machining to make at least one cavity (CA1 to CA5) in said blank (EB1) and disengaging at least one contact face of said electronic chip (MT, MD). 4) Process according to any one of claims 1 to 3, characterized in that said embodiment of the blank (EB1) comprises a step of electrolytic deposition of a conformal layer of metal (CF).
5) Procédé selon l'une quelconque des revendications 1 à 4, caractérisé en ce que ladite réalisation de l'ébauche (EB1 ) comporte une étape de dépôt électrolytique de remplissage de métal. 5) Process according to any one of claims 1 to 4, characterized in that said embodiment of the blank (EB1) comprises a step of electrolytic deposition of metal filler.
6) Procédé selon l'une quelconque des revendications 1 à 5, caractérisé en ce que ladite réalisation de l'ébauche (EB1 ) comporte une étape de définition précise de motifs de connexion par photolithographie et gravure humide. 7) Circuit électronique de puissance, caractérisé en ce qu'il est obtenu par la mise en œuvre du procédé selon l'une quelconque des revendications 1 à 6, le métal utilisé pour les différentes étapes de fabrication du procédé étant le cuivre. 6) Process according to any one of claims 1 to 5, characterized in that said embodiment of the blank (EB1) comprises a step of precise definition of connection patterns by photolithography and wet etching. 7) electronic power circuit, characterized in that it is obtained by the implementation of the method according to any one of claims 1 to 6, the metal used for the various manufacturing steps of the process being copper.
8) Dispositif électronique de puissance, caractérisé en ce qu'il comprend au moins deux circuits selon la revendication 7, un premier circuit dit haut (BCHS) étant empilé sur un deuxième circuit dit bas (BCLS), lesdits circuits haut et bas (BCHS, BCLS) étant liés mécaniquement et électriquement par leurs bus barres respectifs (BBH, BBL), et en ce qu'il comprend au moins un espace central de circulation de liquide de refroidissement (CCi, CC2) qui est situé entre lesdits circuits haut et bas (BCHS, BCLS), ledit espace central de circulation de liquide de refroidissement (CC1, CC2) étant formé entre des tronçons (BB1 H, BB2H, BB3H; BB1 L, BB2L, BB3L) desdits bus barres (BBH, BBL). 8) An electronic power device, characterized in that it comprises at least two circuits according to claim 7, a first so-called high circuit (BCHS) being stacked on a second so-called low circuit (BCLS), said circuits up and down (BCHS). , BCLS) being mechanically and electrically connected by their respective bus bars (BBH, BBL), and in that it comprises at least one central coolant circulation space (CCi, CC2) which is located between said high and low (BCHS, BCLS), said central space for coolant circulation (CC1, CC2) is formed between the sections (BB1 H, BB2H, BB3 H; BB1 L, BB2 L, BB3 L) of said bus bars (BBH, BB L ).
9) Dispositif électronique de puissance selon la revendication 8, caractérisé en ce qu'il comprend également au moins un espace haut de circulation de liquide de refroidissement (CH1, CH2) qui est situé dans une partie haute du dispositif (EM2), ledit espace haut de circulation de liquide de refroidissement (CH1, CH2) étant formé entre des tronçons (BB1 H, BB2H, BB3H) d'un bus barre haut (BBH) dudit circuit haut (BCHS) et une couche diélectrique haute (DLHS). 9) An electronic power device according to claim 8, characterized in that it also comprises at least one high cooling liquid circulation space (CH1, CH2) which is located in an upper part of the device (EM2), said space coolant circulation top (CH1, CH2) being formed between sections (BB1 H, BB2H, BB3H) of a high busbar (BBH) of said high circuit (BCHS) and a high dielectric layer (DLHS).
1 0) Dispositif électronique de puissance selon la revendication 8 ou 9, caractérisé en ce qu'il comprend également au moins un espace bas de circulation de liquide de refroidissement (C , CL2) qui est situé dans une partie basse du dispositif (EM2), ledit espace bas de circulation de liquide de refroidissement (Cl_i , CL2) étant formé entre des tronçons (BB1 L, BB2L, BB3L) d'un bus barre bas (BBL) dudit circuit bas (BCLS) et une couche diélectrique basse (D s). 1 0) electronic power device according to claim 8 or 9, characterized in that it also comprises at least one low space of coolant circulation (C, CL2) which is located in a lower part of the device (EM2), said low coolant circulation space (Cl_i, CL2) being formed between sections (BB1 L, BB2L, BB3L) a low bus bus (BBL) of said low circuit (BCLS) and a low dielectric layer (D s).
EP17817810.9A 2016-12-19 2017-12-06 Method for the integration of power chips and bus-bars forming heat sinks Withdrawn EP3555916A2 (en)

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PCT/FR2017/053408 WO2018115625A2 (en) 2016-12-19 2017-12-06 Method for the integration of power chips and bus-bars forming heat sinks

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