Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
  • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
  • G01T1/29—Measurement performed on radiation beams, e.g. position or section of the beam; Measurement of spatial distribution of radiation
  • G01T1/2914—Measurement of spatial distribution of radiation
  • G01T1/2985—In depth localisation, e.g. using positron emitters; Tomographic imaging (longitudinal and transverse section imaging; apparatus for radiation diagnosis sequentially in different planes, steroscopic radiation diagnosis)
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V10/00—Arrangements for image or video recognition or understanding
  • G06V10/94—Hardware or software architectures specially adapted for image or video understanding
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B6/00—Apparatus or devices for radiation diagnosis; Apparatus or devices for radiation diagnosis combined with radiation therapy equipment
  • A61B6/02—Arrangements for diagnosis sequentially in different planes; Stereoscopic radiation diagnosis
  • A61B6/03—Computed tomography [CT]
  • A61B6/037—Emission tomography
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B6/00—Apparatus or devices for radiation diagnosis; Apparatus or devices for radiation diagnosis combined with radiation therapy equipment
  • A61B6/52—Devices using data or image processing specially adapted for radiation diagnosis
  • A61B6/5211—Devices using data or image processing specially adapted for radiation diagnosis involving processing of medical diagnostic data
  • A61B6/5217—Devices using data or image processing specially adapted for radiation diagnosis involving processing of medical diagnostic data extracting a diagnostic or physiological parameter from medical diagnostic data
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V2201/00—Indexing scheme relating to image or video recognition or understanding
  • G06V2201/03—Recognition of patterns in medical or anatomical images

Definitions

• HEP High Energy Physics
• Medical Imaging It is flexible, scalable, programmable, modular, and technology-independent since it is able to migrate to the most advanced and cosf ⁇ f&cii ve .techiioiog -
• the 3D-Flow instrumentation for fast, real-time Object Pattern Recognition (OPRA) on data arriving in parallel from thousands of sensors at a very high speed with its accessories such as LHC TER DSU, 3D-CBS/DSU, RAU, ATCA-PRAI, etc. is like an Oscilloscope or Logic State Analyzer with their accessories such as a Trimode differential probe, a DDR3 SODIMM Interposer, etc.
• oscilloscope To understand the difference between the new 3D-Flow OPRA, an oscilloscope and a Logic State Analyzer, instrumentations existing for many years, I provide here a short description of each one - what is it and what it is used for. What is an oscilloscope? It is a type of electronic instrument that allows observation of constantly varying signal voltages, usually as a two-dimensional plot of one or more signals as a function of time. Modern digital instruments may calculate and display these properties directly. However, oscilloscopes are somewhat limited with only two or four input channels to correlate a small number of digital, analog and serial signals.
• a transducer is a device that creates an electrical signal in response to physical stimuli, such as sound (microphone), mechanical stress, pressure, light, or heat.
• a logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. It may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system. A logic analyzer can be triggered on a complicated sequence of digital events, then capture a large amount of digital data from the system under test.
• Logic analyzers provide an ideal tool to verify and debug complex designs for electrical engineers. Logic analyzers are useful when multiple signals must be observed simultaneously, as well as when you need to look at a system's signals in the same way its hardware does. The biggest difference from the oscilloscope is the extra input channels it offers.
• the 3D-Flow architecture allows the execution of trillions of different algorithms like a generic processor, but has the advantage over any Pentium, ARM, SPARC, Hypercube, etc., processor/architecture in that it can execute specialized instructions (or "OPRA steps” for an optimized Object Pattern Recognition Algorithm) to identify particles with the capability to execute at each "step” up to 26 operations such as add, subtract, compare with 24 values, etc., in less than 3 nanoseconds.
• the 3D-Flow performance is further increased by its bypass switch and NEWS communication channels with neighbors.
• the logical investigation is to look at the best signals provided by the mutation of the very first normal cells into cancerous cells and accurately detect those signals to obtain an effective early detection.
• the measurements of the few characteristics (or variables) of these photons are controllable. They are: photon's total energy, arrival time, coordinates of the impact point in the detector, high signal-to- noise ratio and the capability to capture as many signals as possible at a very high input data rate and filtering them from the many other signals from radiation.
• the challenge in High Energy Physics experiments is to identify good events at the lowest cost per each good event captured from data relative to over a billion collisions per second arriving from the detector at a rate higher than 40 million events per second.
• bacteria typically have a number of shapes, ranging from spheres to rods and spirals.
• the 3D-Flow system is basically a "decision box” or “Trigger” having the task to process accurately and at great speed each high resolution image and decide whether to keep it or trash it without the possibility to store all of them because in one day the data would fill all the hard drives on the planet.
• the challenge is to extract all valuable information from radiation (emitting hundred millions signals per second) related to tumor markers (or other biological processes) in order to reduce the radiation dosage to the patient and identify the smallest irregular biological process at the lowest cost per valid signal captured from these tumor markers.
• Trigger The challenge for both applications is to design a "decision box” called Trigger that can analyze each frame in real-time and can find the rare object or new particle in physics (or anomalous biological process in medicine).
• Crosetto's basic invention is the 3D-Flow architecture capable of executing experimenters' desired programmable complex Object Pattern Real-Time Recognition Algorithms (OPRA), while sustaining an input data rate of over 80 million events per second from over a billion collisions per second, with zero dead-time, and a lower cost per each event captured than other approaches.
• OPRA Object Pattern Real-Time Recognition Algorithms
• Crosetto has explained his basic invention in one page. (See FIG.s 9, 10 and 11) and used a practical analogy to explain his inventive concept to middle school students in a book [36] and to high school students in a video &&] .
• Crosetto's goal is to reduce cancer deaths and cost.
• PET Positron Emission Technology
• 3D-CBS Three Dimensional Complete Body Screening
• the table allows searching and sorting data on: 1. Projects that provide the highest estimate, supported by scientific arguments, of cancer deaths, 2. Active projects that have received conspicuous funding without providing an estimate of results as far as cancer death reduction, 3. Projects ended without providing results in reduction of cancer deaths, and other information.
• the 3D-Flow OPRA is a new electronic instrument and device to solve target application problems of fast, real-time multi -dimension Object Pattern Recognition (OPRA) on data arriving in parallel from a matrix of thousands of sensors (or transducers) at a very high speed that are sent to an equivalent matrix of thousands of 3D-Flow processors.
• OPRA Object Pattern Recognition
• the 3D-Flow architecture provides data exchange (2x2, 3x3, 4x4, 5x5, ... ) with neighboring processors, while its bypass switch allows the execution of uninterruptable algorithms for a time longer than the interval between two consecutive input data sets.
• Each 3D-Flow processor can execute several different programmable "OPRA steps,” called OPRAS, each consisting of up to 26 operations such as adding, subtracting, comparing to 24 values, etc., in less than 3 nanoseconds.
• the result is that it can execute users' desired programmable complex Object Pattern Real-Time Recognition Algorithms (OPRA) comparing the desired object (shape and detailed characteristics) with billions of objects per second, while sustaining an input data rate of several million frames per seconds, with zero dead -time.
• OPRA Object Pattern Real-Time Recognition Algorithms
• a shape of different colors For example, a shape of different colors, a shape of different levels of heat, a shape of different levels of sound volume and frequencies, a shape of different energies, a shape of different mechanical stress, a shape of different pressure, a shape of different light, the characteristics of a specific subatomic particle measured from signals generated by CCD, APD, PMT, SiPM, PADs, silicon strip detectors, wire- chambers, drift-chambers, etc.
• each channel carries the information of 8-14 bit color, 8- 14 bit heat (infrared light), other bits for the radar and Lidar information, etc.
• each channel carries 8-bit energy information, a few bits of time information and spatial resolution, etc.
• Data from a matrix of different types of sensors or transducers are transferred to an equivalent matrix of 3D-Flow processors at the maximum rate of 1.28Gbps per channel.
• the maximum transfer rate for a 5, 120 channel VME crate 3D-Flow OPRA system is 6.5Tbps and for a 10,240 channels VXI 3D-Flow OPRA system is 13.1Tbps.
• the 3D-Flow OPRA has advanced triggering capabilities, and are useful when a user needs to find a specific object or multiple objects with a specific timing relationship between them, or needs to see the timing relationship between several objects in a digital system. It can trigger on a specific multidimensional object which has been identified by measuring different kinds of phenomena that create an electrical signal. It can trigger on a complicated sequence of digital events.
• trigger conditions When trigger conditions are met, it can save the data of the event(s) with the rare object(s) and time- stamp for subsequent visualization by the user.
• this 3D-Flow OPRA system or instrumentation can be used for Level-1 Trigger to extract all valuable information from radiation to capture the new desired particle theorized by physicists.
• this 3D-Flow OPRA system or instrumentation can be used to extract all valuable information from radiation to enable the detection of cancer and many other diseases at an early curable stage, as well as allowing a significant reduction in the radiation dose given to the patient. Its effectiveness will save many lives f 1 ] and the low examination cost will reduce healthcare costs.
• the 3D -Flow OPRA system or instrumentation can be used to recognize objects from data arriving from thousands of movie cameras each looking at tiny details with a very small field of view.
• FIG. 2, FIG. 3, FIG. 4, 1 have selected VXI 490 495 for the large boards and in FIG. 5, VME 300 for the smaller boards; however, if there is a specific requirement from CERN or another user, they can be implemented in any form factor because the backplane is custom designed.
• VXI and VME are more economical per volume of electronic circuits implemented, that there are already many of these crates at CERN that can be reused from dismissed electronics, and that the 43,008 x 3D-Flow processors for a 8,192 channel 3D-Flow system fit into a compact VXI volume 36cm x 36cm x 24cm, and 25,600 x 3D-Flow processors for 4,096 channels fit into a compact VME cube 16cm x 16cm x 16cm minimizing the distance to exchange data between neighboring processors in different chips and boards.
• the budgetary quote of the mainframe 3D -Flow system in a VXI and VME form factor and its accessories reported below when ordered with this R&D proposal is based on the estimates received in the quotes provided in the budget justification of this proposal.
• the price will be determined by the manufacturing company according to the market value.
• Oscilloscope 33 GHz (Tektronix DPS77004SX) $479,000 S119,750 4 ch.
• Oscilloscope 23 GHz (Tektronix MSO72304DX) $203,000 S50,750 4 ch.
• Oscilloscope 4 GHz (Tektronix MSO070404C) $44,900 SI 1,225 136 ch., Logic State Analyzer (Tektronix TLA7BB4 + TLA7012) $99,600
• DDR3 SODIMM interposer (Nexus Technologies NEX- $57,700 $318.78
• Pattern Generator & Event Recorder @ 320MHz (640Mbps) $40,000 S4.8S per channel, LHC TER/DSU for testing the 3D-Flow OPRA for a
• FIG. 12, FIG. 34 and FIG. 38 illustrates the invention process flow from concept, to simulation, to the design of details, to the verification in hardware of the different parts, to the testing on a sample population.
• VERIFICATION The 3D-Flow System has been proven feasible and functional in hardware in two modular boards. Over ten companies with a record of products showing competence have provided quotes to build all parts showing feasibility. Efficacy of the 3D-Flow system in extracting ALL information from radiation can be verified on a test bench with the DSU.
• the proposed implementation of the 3D-Flow system is verifiable for any implementation selected.
• the left section of FIG. 39, FIG. 41 and FIG. 42 shows the Detector Simulator Unit (DSU) 200
• the left column of FIG. 39 shows the LHC TER-Trigger Event-Recording and Simulator 200
• This 256GB (or 2T) of raw-data recorded at CERN or other accelerator sites by a TER/DSU unit Trigger Event Recorder, the same DSU unit working in acquisition mode rather than generating signals to be sent to the 3D-Flow System in Simulator mode
• a TER/DSU unit Trigger Event Recorder, the same DSU unit working in acquisition mode rather than generating signals to be sent to the 3D-Flow System in Simulator mode
• This precious data will provide the Scientific Associates at the remote university the means to not only test the functionality and performance of the 3D-Flow System in real-time, but to also check that their electronics installed on the detector at CERN (or other site) are working properly.
• the data can be analyzed to check that the electronics of all 8, 192 channels are generating expected data or to identify any dead channels. If an electronic channel or module is shown to be defective, the experimenters can efficiently plan a trip from their university to CER or other accelerator site with a working module to replace the defective one.
• TER/DSU unit at CERN is to use the TER/DSU unit at the accelerator-detector site to record 256GB (or 2T) of trigger raw data with an LHC beam at different known energies (or the detectors can be stimulated with LED light or other known sources that will generate an electrical signal from the detector of a known energy and duration in time).
• This recorded trigger raw data from different stimuli to the detectors at known energy values will be very useful to the scientific associates at different universities to determine the pedestal values to be subtracted for each channel and the gain they have to store in the lookup tables of each of the 8,192 channels of their electronics. This will be essential for the calibration of all parts of the instruments (CMS, Atlas, etc.) to avoid discrepancies in data such as the Higgs boson -like particle whose energy was recorded as 125.3 GeV and 126.5 GeV in different experiments.
• the center column of FIG. 39 shows the 3D-Flow OPRA system for 8, 192 channels capable of extracting from 8-64 million events (32-bit x 8, 192) arriving at a rate of 1.3TB/sec, ALL valuable information from radiation using up to 40 steps of Object Pattern Real-Time Recognition Algorithms executed in parallel on each of the 32,768 x 3D-Flow processors @ $1 each (10,240 x 3D-Flow processors out of the total 43,008 processors in the system are used by the 3D-Flow pyramid to funnel data to a single output channel).
• the right column of FIG. 39 shows the Results Analyzer Unit (RAU) which verifies that the 3D-Flow system has extracted all valuable information from radiation. (The rare particles found by the 3D-Flow system satisfying experimenters' Level-1 Trigger algorithm). See FIG. 39.
• RAU Results Analyzer Unit
• the 3D-Flow invention used in the 3D-CBS (3-D Complete Body Screening) benefits humanity with the potential to save millions of lives and reduce healthcare costs when used in Medical Imaging as an early detection tool on asymptomatic people and to accurately prognoses and efficiently monitor the treatment of many diseases
• the left column of FIG. 40 shows the 3D-CBS ER-Event Recording- and Simulator (generically known as: DSU - Detector Simulator Unit):
• the 3D-Flow invention breaks the speed barrier in real-time applications; it is flexible, scalable, programmable, modular, technology-independent; it can be built in different platforms (e.g. VME, VXI, VPX, ATCA, ⁇ TCA, etc.); it can extract all valuable information from the most noisy and rough radiation environment
• FIG. 1 Breakthrough invention.
• 3D-Flow OPRA -a revolutionary electronic instrument for multiple applications: advancing science, saving lives, fighting terrorism, ...
• the figure illustrates 3D- Flow OPRA electronic instrument that can be implemented in a 36 cm cube of electronics, which is capable of executing pattern recognition algorithms in real-time of multidimensional objects (different ideas, or algorithms are represented as a light bulb) by analyzing all data arriving at ultra-high speed from a matrix of thousands of transducers at over 20TB/seconds with zero dead time.
• the PRAI-ATCA crate 180 in the center of the figure receives trigger raw data events from the detectors 105, 110, 115, 120 on different connectors, speeds, protocols and formats on electronic board PRAI-B 130, synchronizing them, formatting each event into 8,192 channels x 16-bits and sending it via a dual backplane 135, using the board PRAI-B 140 every 25ns, or 12.5ns @1.3TB/sec through 64 x 128 channels to the 3D-Flow system 9U x 400 mm boards 410, or 420 housed in crate 490.
• FIG. 3 Many crates of electronics in HEP experiments would be replaced by a single VXI 3D- Flow crate 490 providing a much more powerful tool to uncover the unknown and to confirm or exclude the existence of a subatomic particle predicted by theoretical physicists.
• the one crate 3D-Flow system has the capability of executing experimenters' desired programmable complex Object Pattern Recognition Algorithm (OPRA) for the Level-1 Trigger, while sustaining an input data rate over 80 million events per second from over a billion collisions per second, with zero dead-time, at a lower cost (compared to current approaches) per each good event captured. .
• OPRA programmable complex Object Pattern Recognition Algorithm
• FIG. 4 Details of the VXI implementation of 8, 192 channels 3D-Flow OPRA system for Level-1 Trigger.
• the system extracts all valuable information using Object Pattern Real-Time Recognition Algorithms (OPRA) from 80 million events/second (radiation) at 1.3TB/second transfer rate from over a billion collisions/second, using 43,008 x 3D-Flow processors @ $1 each.
• Data are received at the front end of the 3D-Flow OPRA boards 410 or 420 inserted in crate 490 via 512 x 16 Twinax (see FIG. 48 and FIG 49) ribbon cables 145 which are soldered on a small board 645 at the receiving end of crate 490 and are soldered on a small board 646 (see FIG. 59) at the sending crate 180.
• OPRA Object Pattern Real-Time Recognition Algorithms
• FIG. 5 show the details of the layout of the two VME crates 300, each housing 16 x 3D-Flow, 256 channels boards 310 or 320 connected to eight ATCA blades, each with 1024 channels received from detectors such as Atlas CMS, etc.
• Data are received at the front end of the 3D-Flow OPRA boards 310 or 320 inserted in two VME crates 300 via 2 x 256 x 16 Twinax (see FIG. 48 and FIG 49) ribbon cables 145 which are soldered on a small board 545 at the receiving end of crate 300 and are soldered on a small board 546 (see FIG. 58) at the sending crate 180.
• FIG. 6 Details of the VME implementation of the 2,304 channels, 14,400 x 3D-Flow processors System for the 3D-CBS. Center figures represent the nine VME boards, 2 cm wide housed in the "3D- FLOW SYSTEM" crate connected through 2,304 Twinax ribbon cables to the "FRONT-END
• the 3D-CBS has the capability to extract ALL valuable information from radiation, reduces considerably the amount of radiation required to be administered to each patient, and enables for the first time an effective early detection of cancer and other diseases in a single examination covering all organs of the body in just four minutes. Because it gives doctors very precise information, they are better equipped to make accurate diagnoses, prognoses and efficiently monitor treatment. Additional benefits are a reduction in the cost of screening examinations and the cost of healthcare.
• FIG. 7 the 3D-Flow architecture from concept (left) to implementation in two FPGA 715 (Field Programmable Gate Array) to board 700 with 68 x 3D-Flow processors implemented in FPGA, to an ASIC 750 with 64 x 3D-Flow processors in a chip, to a VME board 310 with 1,600 x 3D-Flow processors, to the electronic system for the 3D-CBS with 14,400 x 3D-Flow processors in a crate 300.
• FPGA 715 Field Programmable Gate Array
• FIG. 8 The 3D-Flow Logical Unit 710 assembled in layers and stack 720 architecture for a pipeline process of frames, each frame entirely processed in one processor
• FIG. 9 - Description of the first 4 steps of a 12 steps sequence of the 3D-Flow parallel-processing architecture for one input/output channel of a stack of 3D-Flow processors as shown in FIG. 34.
• FIG. 10 Illustration of the 12 steps sequence of the flow of the input data and output results in the 3D-Flow parallel-processing architecture for one input/output channel of a stack of 3D-Flow processors as shown in FIG. 34.
• FIG. 11 - Description of the last 4 steps of a 12 steps sequence of the 3D-Flow parallel-processing architecture for one input/output channel of a stack of 3D-Flow processors as shown in FIG. 34.
• FIG. 12 Illustrates the conceptual interrelation between components of the 3D-Flow system for application in medical imaging and in physics experiments (input data from different detectors, possibility to execute different algorithms, and generation of different results) and the flow of the data in the system.
• FIG. 13 - 3D-Flow software tools Simulator for a 3D-Flow System with thousands of processors.
• FIG. 14 Photo of the 3D-Flow DAQ-DSP IBM PC modular board with 68 x 3D-Flow processors suitable to build 3D-Flow systems for detector of any size and proving feasibility and functionality.
• FIG. 18 VME 3D-Flow mother board, 256 channels, 832 x 3D-Flow processors
• FIG. 19 VME 3D-Flow daughter board, 256 channels, 768 x 3D-Flow processors
• FIG. 21 - VME 3D-Flow daughter board tentative components layout for a 256 channels, 768 x 3D-Flow processors.
• FIG. 22 VXI 3D-Flow board, 84 ASICs, 1,024 channels, 5,376 x 3D-Flow processors.
• FIG. 23 VXI 3D-Flow board, 40 ASICs, tentative components layout on the front of the board for a 1,024 channels, 2,560 x 3D-Flow processors.
• FIG. 25 VXI 3D-Flow board, 68 ASICs, 1,024 channels, 4,352 x 3D-Flow processors.
• FIG. 26 VXI 3D-Flow board 430, 66 ASICs, 512 channels, 4,224 x 3D-Flow processors.
• FIG. 29 layout of the backplane carrying the connections between neighboring processors in the 3D-Flow array located in different boards. This implementation is similar for VME and VXI crates.
• FIG. 30 Experimental data over half century show that we are not winning the war on cancer with a reduction of mortality rate of less than 5%, while for the heart disease for the same period was over 50%, while the cost of cancer has increased over 100 fold.
• FIG. 31 Illustration why it is important to extract ALL valuable information from radiation which is related to visualizing abnormal biological processes enabling early cancer detection.
• FIG. 32 - 3D-CBS for measuring anatomical and functional parameters
• FIG. 33 The 3D-CBS on the right provides precise information on the minimum abnormal biological process with a number (top of the fraction) measured versus a number (bottom of the fraction) considered normal of the metabolic activity (or any biological process useful to the physician to identify abnormalities leading to degenerative diseases such as cancer). On the left of the figure is shown the information provided to the physicians from current PET.
• FIG. 34 - 3D-CBS Logical Design with its functions split for engineering them into hardware.
• FIG. 35 Technological advantages of the 3D-CBS compared to current PET
• Fig. 36 The 3D-CBS a single examination replacing mammogram, PAP -Test, colonoscopy and PSA examination.
• FIG. 38 Illustrates the physical layout of the different components from the DSU unit 205 generating radiation data recorded from a PET detector 102 in the left column, the 3D-Flow OPRA under test (crate 300 housing data processing boards 310 and the coincidence board 360) with the task to extract all valuable information from the radiation data (tumor markers) in the center column and the RAU unit 240 to the right, analyzing the results found and measuring the efficiency of the system.
• the lower layer from left to right shows the components related to the application of improving medical imaging.
• FIG. 39 3D-FLOW VERIFIABLE SYSTEM for 8, 192 Channels 20 OPRA steps/ 16 -bit-channel @ 80MHz.
• Detector Simulator see crate 200 housing boards 210 or 220 using SODIMM 205. See FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 48, FIG. 49, FIG. 50, FIG. 51, FIG. 52) with the capability to generate up to 131,072-bit/event sent at 1.3TB/sec transfer rate to the 3D-Flow System.
• 3D-Flow System crate 410 (center) housing data processing boards 410 or 420 and the channel reduction board 460 extracts all valuable information from radiation events arriving every 12.5 ns from 8, 192 detector channels, 16-bit/channel, executing max 20 OPRA steps/event.
• Result Analyzer unit 215 in crate 240 (right) verifying all events containing valuable information have been extracted from radiation by the 3D- Flow System.
• Detector Simulator see crate 200 housing boards 210 or 220 using SODIMM 205. See FIG. 41, FIG. 42, FIG. 43, FIG. 41, FIG. 44, FIG. 45, FIG. 46, FIG. 47) with the capability to generate up to 32,544-bit/event sent at 368GB/sec transfer rate to the 3D-Flow System.
• 3D-Flow System crate 300 (center) housing data processing boards 310 or 320 and the channel reduction board 360 extracts all valuable information from radiation events arriving every 50 ns from 2,304 detector channels, 64- bit/channel, executing max 120 OPRA steps/event.
• Result Analyzer unit 218 in crate 240 (right) verifying all events containing valuable information have been extracted from radiation by the 3D-Flow System.
• Detector Simulator (left) generating 131,072 -bit/event sent at 1.3TB/sec transfer rate to the 3D-Flow System.
• 3D-Flow System (center) extracts all valuable information from radiation events arriving every 12.5 ns from 8, 192 detector channels, 16-bit/channel, executing max 30 OPRA steps/event.
• Result Analyzer unit (right) verifying all events containing valuable information have been extracted from radiation by the 3D -Flow System.
• Detector Simulator see crate 200 housing boards 210 or 220 using SODIMM 205. See FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 45, FIG. 46, FIG. 47) with the capability to generate up to 131,072- bit/event sent at 1.3TB/sec transfer rate to the 3D-Flow System.
• 3D-Flow System crates 495 (center) housing data processing boards 430 and the channel reduction board 460 extracts all valuable information from radiation events arriving every 12.5 ns from 8,192 detector channels, 16-bit/channel, executing max 35 OPRA steps/event.
• Result Analyzer unit 215 in crate 240 (right) verifying all events containing valuable information have been extracted from radiation by the 3D-Flow System.
• FIG. 43 - Specification logical drawing VME ER DSU board using Altera FPGA for a 320MHz, 512-bit long word, DDR: 640 Mbps x 512 40.96GB/sec Transfer rate.
• FIG. 44 Specification and tentative layout of the components on the PCB for the 320MHz VME ER DSU board (front of the board).
• FIG. 45 Specification and tentative layout of the components on the PCB for the LHC TER/DSU board (back of the board).
• FIG. 47 Specification and tentative layout of the Altera FPGA components on the PCB for the VME ER/DSU board (back of the board).
• FIG. 48 Micro Twinax 2-16 ribbon ribbon cable 145 specifications.
• FIG. 49 Micro Twinax ribbon cable 145 performance data and insertion loss & return loss graphs.
• the small board is 59.62 mm wide and 70 mm long. It has pads on one side, at one end of the small PCB to accommodate the 400-pin connector. At the other end of the small PCB on both sides has two columns and two rows of 16 x 2 pads to solder four Micro Twinax 16 x 2 ribbons.
• the connector is secured with four screws to the larger application PCB.
• FIG. 51 Pin assignment for SEAM connectors at 36Gbps LVDS signals
• FIG. 52 SamTec SEAF8, 0.80 mm pitch connectors specifications
• FIG. 53 Pin assignment of the LVDS signals to SamTec connector SEAM -40-03.5-S-10-2 -A.
• FIG. 54 Details of how the eight Micro Twinax 16 x 2 ribbon cables are assembled to the small boards at both ends of the ribbon which house SamTec SEAF8-40-05.0-S-10-2-K, 0.80 mm pitch connector on each board.
• the small board is 37.84 mm wide and 75 mm long. At one end of the small PCB there are pads on one side to accommodate the 400-pin connector. At the other end of the small PCB on both sides are four columns of 16 x 2 pads to solder four Micro Twinax 16 x 2 ribbons.
• the connector is secured with four screws to the larger application PCB.
• the eight 16 x 2 ribbons and the small PCB are tightened together with a strain reliever and this assembly is tightened to the larger application PCB with a second strain reliever.
• Connectors SEAM8-40-S02.0-S-10-2-K mating with SEAF8-40-05.0-S-10- 2-K have a stacking height of 6.9 mm, mounted 80 mm from the edge of the larger application PCB board.
• FIG. 55 Details of how the eight Micro Twinax 16 x 2 ribbon cables are assembled to the small 90° shaped boards at both ends of the ribbon which house SamTec SEAF8-40-05.0-S-10-2-K, 0.80 mm pitch connector on each board.
• the small 90° shaped board is 37.84 mm wide and 100 mm long along the connector end and 62 mm along the ribbon cable end.
• pads on one side At one end of the small PCB there are pads on one side to accommodate the 400-pin connector.
• At the other end at 90° with respect to the connector on both sides there are four columns of 16 x 2 pads to solder four Micro Twinax 16 x 2 ribbons.
• the connector is secured with four screws to the larger application PCB.
• connector SEAF8-40-05.0-S-10-2-K should be assembled at both ends of the small PCB connected to the ribbon cables; while at the edge of the larger application PCB board the mating connector SEAM8-40- S02.0-S-10-2-K should be assembled providing a stacking height of 7.0 mm; while at 25 mm from the edge of the larger application PCB board the mating connector SEAM8-40-S05.0-S-10-2-K should be assembled providing a stacking height of 10 mm.
• FIG. 56 Details of how the eight Micro Twinax 16 x 2 ribbon cables are assembled to the small boards at both ends of the ribbon which house a SamTec SEAF8-40-05.0-S-10-2-K, 0.80 mm pitch connector on each board.
• the small board is 38 mm wide and 128 mm long.
• At one end of the small PCB there are pads on one side to accommodate the 400-pin connector.
• At the other end of the small PCB on both sides at 90° with respect to the connector there are two columns of two rows of 16 x 2 pads to solder four Micro Twinax 16 x 2 ribbons at 90° with respect to the connector.
• the connector is secured with four screws to the larger application PCB.
• the eight 16 x 2 ribbons and the small PCB are tightened together with a strain reliever.
• connector SEAF8- 40-05.0-S-l 0-2 -K should be assembled at both ends of the small PCB connected to the ribbon cables; while at the edge of the larger application PCB board the mating connector SEAM8-40-S02.0-S-10-2-K should be assembled providing a stacking height of 7.0 mm; while at 25 mm from the edge of the larger application PCB board the mating connector SEAM8-40-S05.0-S-10-2-K should be assembled providing a stacking height of 10 mm.
• FIG. 57 Details of how the eight Micro Twinax 16 x 2 ribbon cables are assembled to the small boards at both ends of the ribbon which house SamTec SEAF8-40-05.0-S-10-2-K 0.80 mm pitch connector on each board.
• the small board is 38 mm wide and 180 mm long.
• At one end of the PCB there are pads on one side to accommodate the 400-pin connector.
• At the other end of the small PCB on both sides at 90° with respect to the connector is one column of four rows of 16 x 2 pads to solder four Micro Twinax 16 x 2 ribbons at 90° with respect to the connector.
• the connector is secured with four screws to the larger application PCB.
• the eight 16 x 2 ribbons and the small PCB are tightened together with a strain reliever.
• connector SEAF8-40- 05.0-S-10-2-K should be assembled at both ends of the small PCB connected to the ribbon cables; while at the edge of the larger application PCB board the mating connector SEAM8-40-S02.0-S-10-2-K should be assembled providing a stacking height of 7.0 mm; while at 25 mm from the edge of the larger application PCB board the mating connector SEAM8-40-S05.0-S-10-2-K should be assembled providing a stacking height of 10 mm.
• FIG. 58 Details of how the eight Micro Twinax 145 16 x 2 ribbon cables are assembled to the small boards at both ends of the ribbon which house SamTec SEAF8-40-05.0-S-l 0-2 -K 0.80 mm pitch connector on each board.
• the small board 545 and 546 is 38 mm wide and 210 mm long. It has a cut on one side of the PCB board as long as the width of the four ribbon cables to create a window on adjacent PCBs assemblies where the four ribbon cables can cross from one side of the PCBs to the other side. At one end of the small PCB there are pads on one side to accommodate the 400-pin connector.
• the connector is secured with four screws to the larger application PCB.
• the side of the small PCB board opposite the connector has a hole at the corner in order to secure the board to a frame relieving any mechanical strain on the connector, on the four screws tightening the connector to the board, and to hold the weight of the ribbon cables.
• the eight 16 x 2 ribbons and the small PCB are tightened together with a strain reliever.
• connector SEAF8-40-05.0-S-10-2-K should be assembled at both ends of the small PCB connected to the ribbon cables; while at the edge of the larger application PCB board the mating connector SEAM8-40-S02.0-S-10-2-K should be assembled providing a stacking height of 7.0 mm; while at 25 mm from the edge of the larger application PCB board the mating connector SEAM8-40-S05.0-S-10-2-K should be assembled providing a stacking height of 10 mm.
• FIG. 59 Details of how the eight Micro Twinax 145 16 x 2 ribbon cables are assembled to the small boards at both ends of the ribbons which house SamTec SEAF8-40-05.0-S-10-2-K 0.80 mm pitch connector on each board.
• the small board 645 and 646 is 38 mm wide and 300 mm long. It has a cut on one side of the PCB board as long as the width of the four ribbon cables to create a window on adjacent PCBs assemblies where the eight ribbon cables can cross from one side of the PCBs to the other side. At one end of the small PCB there are pads to accommodate the 400-pin connector.
• the connector At the other end of the PCB at 90° with respect to the connector there is one column of eight rows of 16 x 2 pads to solder eight Micro Twinax 16 x 2 ribbons at 90° with respect to the connector.
• the eight ribbons are soldered on the same side of the connector, while on the other board they are soldered on the side opposite the connector.
• the connector is secured with four screws to the larger application PCB.
• the side of the small PCB board opposite the connector has a hole at the corner in order to secure the board to a frame to relieve any mechanical strain on the connector, on the four screws tightening the connector to the board and to hold the weight of the ribbon cables.
• the eight 16 x 2 ribbons and the small PCB are tightened together with a strain reliever.
• connector SEAF8-40-05.0-S-10-2-K should be assembled at both ends of the small PCB connected to the ribbon cables; while at the edge of the larger application PCB board the mating connector SEAM8-40- S02.0-S-10-2-K should be assembled providing a stacking height of 7.0 mm; while at 25 mm from the edge of the larger application PCB board the mating connector SEAM8-40-S05.0-S-10-2-K should be assembled providing a stacking height of 10 mm.
• FIG. 60 Details of how the eight Micro Twinax 16 x 2 ribbon cables are assembled to the small boards at both ends of the ribbon which house SamTec SEAF8-40-05.0-S-10-2-K, 0.80 mm pitch connector on each board.
• the small board is 38 mm wide and 300 mm long. It has a cut on one side of the PCB board as long as the width of the four ribbon cables to create a window on adjacent PCBs assemblies where the eight ribbon cables can cross from one side of the PCBs to the other side. At one end of the small PCB there are pads to accommodate the 400-pin connector.
• At the other end of the PCB at 90° with respect to the connector is one column of eight rows of 16 x 2 pads to solder eight Micro Twinax 16 x 2 ribbons at 90° with respect to the connector.
• the eight ribbons are soldered on the same side of the connector, while on the other board they are soldered on the side opposite the connector.
• the connector is secured with four screws to the larger application PCB.
• the side of the small PCB board opposite the connector has a hole at the corner in order to secure the board to a frame to relieve any mechanical strain on the connector, on the four screws tightening the connector to the board, and to hold the weight of the ribbon cables.
• the eight 16 x 2 ribbons and the small PCB are tightened together with a strain reliever.
• connector SEAF8-40- 05.0-S-10-2-K should be assembled at both ends of the small PCB connected to the ribbon cables; while at the edge of the larger application PCB board the mating connector SEAM8-40-S02.0-S-10-2-K should be assembled providing a stacking height of 7.0 mm; while at 25 mm from the edge of the larger application PCB board the mating connector SEAM8-40-S05.0-S-10-2-K should be assembled providing a stacking height of 10 mm.
• FIG. 61 - 3D-CBS detector assembly 102 with a length of the detector (FOV longer than lm, consisting of the crystal 330 with slits of equal length, or a solid crystal 331 with no slits (cuts) with rectangular or pyramidal shape (larger face external to the cylinder, smaller face internal to the cylinder, the crystal may have a dimension larger than the sensor 324), one element SiPM 334 with a surface smaller than the crystal coupled to the inner face of the crystal through a pyramid shape light-guide, a PMT, SiPM or APD with a single sensor or an array of sensors 324 coupled to the external face of the crystal.
• FIG. 62 Detail of the assembly of one electronic channel of the detector consisting of an APD or SiPM 334 coupled to the inner face of the crystal through a pyramid shape light-guide and an outer sensor 324 (PMT, SiPM or APD) coupled to the outer face of the crystal.
• an APD or SiPM 334 coupled to the inner face of the crystal through a pyramid shape light-guide and an outer sensor 324 (PMT, SiPM or APD) coupled to the outer face of the crystal.
• the detector may consist of a crystal 330 with slits of equal length, or a solid crystal 331 with no slits (cuts) with rectangular or pyramidal shape (larger face external to the cylinder, smaller face internal to the cylinder, the crystal may have a dimension larger than the sensor 324), one element SiPM 334 with a surface smaller than the crystal coupled to the inner face of the crystal through a pyramid shape light-guide, a PMT, SiPM or APD with a single sensor or an array of sensors 324 coupled to the external face of the crystal.
• FIG 63 Detail of the same crystal assembly as in FIG. 62, showing 330 crystals with slits (cuts) of equal length, with adjacent crystals and the center of gravity algorithm for better spatial resolution.
• FIG. 64 Different shapes and lengths of the 3D-CBS detector optimized for low cost and maximum efficiency.
• FIG. 65 Photon detection programmable algorithm with the 3D-Flow processor.
• Each processor gathers the information from its detector element and the 8 neighbors and acts like the head of a cluster without boundary limitation. Any further operations can be executed upon the 9 data (the one received from the detector and its 8 neighbors) by the CPU of the 3D -Flow processor, which can, in a single cycle, execute up to 26 operations, including all normal arithmetic and logic operations from a standard computer to greatly improve signal-to-noise ratio.
• FIG. 66 Photon detection programmable algorithm with the 3D-Flow processor.
• Each processor gathers the information from its detector element and the 24 (5 x 5) neighbors and acts like the head of a cluster without boundary limitation. Any further operations can be executed upon the 25 data (the one received from the detector and its 24 neighbors) by the CPU of the 3D-Flow processor, which can, further improve signal-to-noise ratio.
• FIG. 67 Specification of the electronics of the alternative Explorer project with limited efficiency and higher cost than the 3D-CBS
• FIG. 68 Specification of the detector and sensors assembly of the alternative Explorer project with limited efficiency and higher cost than the 3D-CBS
• FIG. 69 Comparison table between the Explorer project and the 3D-CBS
• FIG. 70 Estimated lives saved and variable revenue plan for 30 years for the MasSpec Pen
• FIG. 71 Timeline for the development of the 3D-Flow OPRA and the 3D-CBS systems
• FIG. 72 Estimated lives saved and variable revenue plan for 30 years for the 3D-CBS (3-D Complete Body Screening).
• the 3D-Flow System provides a very powerful tool to the HEP community because it extracts all valuable information from radiation.
• the 3D-Flow architecture provides data exchange with neighboring processors while its bypass switch allows the execution of uninterruptable algorithms for a time longer than the interval between two consecutive input data. The result is it can execute experimenters '1 desired programmable complex Object Pattern Recognition Level-1 Trigger Algorithms (OPRA), while sustaining an input data rate of over 80 million events per second from over a billion collisions per second, with zero dead-time, at a lower cost per each good event captured than other approaches.
• OPRA programmable complex Object Pattern Recognition Level-1 Trigger Algorithms
• a patch panel PRAI-ATCA receives events from the detectors, synchronizes and formats each event into 8,192 channels x 16-bit and sends them to the 3D-Flow system -one every 12.5ns (or 1 every 25ns with a longer 32-bit word).
• the Level-1 Trigger has the most important and challenging task of capturing rare events (one out of 10 billion in the case of the Higgs boson-like particle), if they are missed all the work of analyzing data by thousands of people will be meaningless and the entire money and effort of building for more than 20 years the LHC collider and detectors would be wasted. It would therefore be prudent to thoroughly test the efficacy of the Level-1 Trigger and give the opportunity to more than one group of experimenters/scientists to test their ideas.
• Level-1 Triggers of the large experiments at LHC CMS Atlas, Alice and LHCb do not provide zero dead-time; CMS and Atlas have found only 40 Higgs boson-like events during analysis of data captured randomly instead of intelligently, by the Level-1 Trigger; their leaders recognize they must trash the current Level-1 Trigger electronics because they do not have the capability to execute Object Pattern Recognition Algorithms.
• Level-1 Trigger responsible for making the first very important decision of which events among the trillions of events generated by the LHC, have important information valuable enough to capture. If Level-1 Trigger does not have the capability to capture these valuable events, then thousands of scientists will analyze garbage data and billions of dollars and many years of work will be wasted.
• This proposal is providing instrumentation satisfying those requirements and going beyond them to satisfy requirements for future LHC upgrades.
• Trigger Tower 108 granularity is increased from 8, 192 channels to 32,768, one could use 4 x crates, each with 8, 192 channels and 43,000 x 3D-Flow processors; however, the OPRA algorithm will increase in complexity (will be longer) because each processor will have to handle more neighboring data from the impact of the particle in the detector, affecting more elements in a smaller granularity.
• the Trigger Towers 108 in FIG. 2, FIG. 4 and FIG. 5 generates 16-bits, 32-bits, 64-bits,... then the Level-1 trigger should have the capability to process more data.
• the 3D-Flow OPRA new instrument can satisfy any additional requirements in a very cost-effective manner. It is important to assess the future needs of instrumentation in HEP in order to optimize the cost-performance.
• the proposed project and budget to build the 8,192 channel 3D-Flow OPRA system described in FIG. 4 will achieve Level A and Level B.
• Level-1 trigger system To upgrade the performance of the entire Level-1 trigger system to Level B, it will only be necessary to have the 1.28Gbps LHC TER/DSU costing about $120,000.
• Each 3D-Flow processor can execute programmable, complex Object Pattern Real-Time Recognition Algorithms by exchanging data with neighboring processors and manipulating any field or group of bits of the 16-bit, 32-bit, 64-bit... or 250-bit word with OPRA steps (OPRAS), each with the capability to execute up to 26 operations such as, addition, subtraction, comparison with 24 values, etc. in less than 3 nanoseconds.
• ORAS OPRA steps
• the 3D-Flow architecture can satisfy experimenters' requirements to execute longer algorithms when the input word is increased from 16-bit to many more bits by adding the number of 3D- Flow processor layers, do we really need lOGbps to carry 250-bit information from each Trigger Tower or is a compromise between 32-bit of the proposed 3D-Flow processor with 1.28Gbps input/output and lOGbps acceptable? Perhaps a 2.56Gbps offering 64-bit word input from each Trigger Tower would be sufficient and the 3D-Flow processor NRE at the Silicon Foundry will not quadruple.
• SAV!NG TAXPAYER MONEY The 3D-Flow System can replace many crates of electronics in HEP experiments with a single crate, providing a much more powerful tool to discover new particles or to disprove a theory
• LHC Large Hadron Collider
• These 40 Higgs boson-like events out of the estimated 100,000 indicate a casual recording of those events rather than an informed decision made by the Level-1 Trigger matching desired conditions.
• the 3D-Flow has the capability to execute on each of the 40,000 plus processors in parallel a different programmable sequence of steps/instructions with a high-speed, short latency and low power consumption data exchange capability between adjacent processors and executing up to 26 operations such as add, subtract, compare with 24 values, etc. in less than 3 nanoseconds.
• Level-1 Trigger system built using FPGA would not fit in a crate, the power consumption and cost would be exorbitant, and it would never come close to having the capability to execute Object Pattern Recognition Algorithms with the same complexity as the 3D-Flow system, directly on raw trigger data received at high speed at each of the thousands of processor nodes.
• the 3D-Flow In Medical Imaging applications (see FIG. 6), the 3D-Flow, one of the basic inventions of the 3 ⁇ CBS (3-D Complete Body Screening), together with other inventions I conceived after the year 2000, offers a powerful, cost-effective very low radiation diagnostic tool capable of extracting all valuable information from radiation (radioisotope) associated with biological processes, and provides an unprecedented means to effectively detect anomalies such as cancer and many other diseases in those biological processes at an early curable stage. This has the potential to save millions of lives and significantly reduce Healthcare costs. If the current DOE HEP budget does not allow the funding of large generic R&D projects like the 64x 3D-Flow chip, oaids and : . . n;;>. because our duty is to serve our leaders and together serve humanity, separate funding should be sought to implement innovations beneficial to civilization that are supported by calculations and scientific evidence in order not to miss again this opportunity to save money, lives, and to create a powerful tool to advance ' HEP research.
• the most difficult task that I had to face for over a decade is to make people aware of the benefits to civilization of a Medical Imaging device capable of cost-effectively extracting ALL valuable information from radiation that could have already saved many lives and reduced healthcare costs.
• the people include political leaders, health care organizations, doctors, hospital administrators, cancer organizations, funding agencies, philanthropists, foundations supporting humanitarian causes, cultural groups and anyone who cares to defeat the most deadly and costly calamity, cancer, and who cares to advance health care with better diagnostic devices that give less radiation to the patient and provide more accurate information to doctors to helping them diagnose, prognoses and monitor treatment.
• Radiation is related to biological processes, therefore by accurately extracting all valuable information from radiation (on spatial resolution, time resolution, energy and sensitivity) it allows a reduction in the radiation dose to the patient, reduces costs and provides valuable information to doctors on anomalies in morphological changes and in biological processes, enabling improved diagnoses, prognoses and monitoring of the treatment of many diseases, while reducing healthcare costs.
• the 3D-Flow architecture is capable of executing uninterruptable complex algorithms for a time longer than the time between two consecutive input data sets by adding layers of 3D-Flow processors communicating through a bypass switch assuring zero dead-time. I then minimized the time required to exchange data between neighboring elements necessary for the execution of typical 3x3, 4x4, 5x5, ... Object Pattern Real-Time Recognition
• the number of layers of 3D-Flow processors needed is calculated by dividing the time to execute an algorithm by the time interval between two consecutive input data and rounding the result up to the next integer. Because longer cables increase the algorithm's execution time (e.g. exchanging data between processors on different PCB boards connected through a 30 cm cable adds more than 1,000 picoseconds), this proposed system of 14,000 x 3D-Flow processors is confined to a 16 cm x 16 cm x 16 cm cube which keeps the number of layers of processors low and consequently lowers the power consumption of the system.
• the performance of this 3D-Flow system in recognizing objects by analyzing data arriving at a very high speed is far superior to any alternative system built with FPGA (Field Programmable Gate Array). This is because in FPGA a lot of silicon area with electronic circuits which are not optimized for OPRA consume power, requiring a larger system and longer cables, thus never able to achieve the performance and lower cost of the 3D-Flow.
• the proposed project is justified from the need to create a powerful tool with the capability to extract all valuable information from radiation more specifically to execute experimenters' programmable complex Object Pattern Real-Time Recognition Algorithm at the Level-1 trigger with neighboring data exchange while sustaining an input data rate of 80MHz from 8,000 channels, each receiving a 16-bit word (or 40MHz with a 32-bit word, or 20MHz with 64-bit word) with zero dead-time.
• This proposed project is also justified by the need to develop a similar powerful tool capable to extract all valuable information from radiation in the application of medical imaging to reduce the radiation dose to the patient, to enable an effective early cancer detection and reduce healthcare cost.
• the 3D- Flow architecture is capable of executing experimenters' desired progf S MS. complex Object Pattern Recognition Level- 1 Trigger (OPR T) algorithms, while sustaining an input data rate of over 80 million events per second from over a billion collisions per second, with zero dead-time, at lower cost (compared to current approaches) per each good event captured and fully meeting 1994 LRC experiment requirements, 2 ( ⁇ 12, today and future requirements for a higher IMC luminosity.
• ORR T complex Object Pattern Recognition Level- 1 Trigger
• the 3D-Flow as one of the basic inventions of the t£MS , (3-D Complete Body Screening), offers a powerful, diagnostic tool capable of extracting all valuable information from radiation (radioisotope) associated with biological processes and provides an unprecedented means to effectively detect anomalies in biological processes such as cancer and many others diseases at an early curable stage, administering a very low radiation dose and a very low examination cost. This has the potential to save millions of lives and significantly reduce Healthcare costs. This is not propaganda or advertisement Each statement above is supported by the 3D ⁇ Flow feasibility and functionality proven in hardware, by calculations, by correct equations, by scientific evidence.
• the boards consist of eight 9U VME Readout-Processing boards with partial pyramid for channel reduction and one 9U VME Global Trigger board with the final section of the pyramid, the calculation of the global quantities that are provided to the Global Trigger for the final Level-1 trigger decision.
• the global 3D-Flow system can sustain 80 million events per second from over a billion collisions per second, with zero dead-time.
• Each of the 8000 input channels receive 16-bit data every 12.5 ns.
• Each 3D-Flow program step has the capability to perform up to 26 operations of addition, subtraction, compare with multiple values, etc. This provides a complete, thorough Object Pattern Recognition capability using information from multiple detectors (calorimeter, tracking, etc.).
• the boards consist of sixteen 9U VME Readout-Processing boards with partial pyramid for channel reduction and one 9U VME Global Trigger board with the final section of the pyramid, the calculation of the global quantities that are provided to the Global Trigger for the final Level-1 trigger decision.
• the global 3D-Flow system can sustain 80 million events per second from over a billion collisions per second, with zero dead-time.
• Each of the 8000 input channels receive 16-bit data every 12.5 ns.
• Each 3D-Flow program step has the capability to perform up to 26 operations of addition, subtraction, compare with multiple values, etc. This provides a complete, thorough Object Pattern Recognition capability using information from multiple detectors (calorimeter, tracking, etc.).
• the boards consist of thirty-two 6U VME Readout-Processing boards with partial pyramid for channel reduction and one 6U VME Global Trigger board with the final section of the pyramid, the calculation of the global quantities that are provided to the Global Trigger for the final Level-1 trigger decision.
• the global 3D-Flow system can sustain 80 million events per second from over a billion collisions per second, with zero dead-time.
• Each of the 8000 input channels receive 16-bit data every 12.5 ns.
• Each 3D-Flow program step has the capability to perform up to 26 operations of addition, subtraction, compare with multiple values, etc. This provides a complete, thorough Object Pattern Recognition capability using information from multiple detectors (calorimeter, tracking, etc.).
• the 3D-Flow is able to extract all valuable information from radiation to discover new particles and save billions of dollars in physics research with a box of electronics containing 50,000 x 3D-Flow processors costing less than $1 each.
• the 3D-Flow architecture would have also surpassed the 20 MHz requirements of the LHC for most of the runs in 2011 - 2012 with the 3D-Flo FPGA boards running at 31 MHz, and the 3D-Flow version in 350 nm standard cell technology running at 61 MHz compiled with Synopsys tools in 1996 (but without funding it was never built in silicon) would have fully satisfied with zero-dead-time the requirements of the few runs of the LHC in late 2012 at 40 MHz bunch crossings. All the 3D-Flow versions in FPGA or Standard cell 350 nm technology had the capability of analyzing ALL billion collisions per second.
• the 3x3 can provide more accurate information on the photon's total energy, rejecting more efficiently scatter events and capturing more good 511 keV pairs of photons. It would also allow an increase in spatial resolution interpolating the location of the incident photon in the crystal with information from detector elements to the left and to the right (up and down for "y" coordinate calculation) of the position where the photon hit the detector.
• improving particle detection is key to improving early detection of cancer and other diseases that can save many lives, then it is essential to address in depth what is improving particle detection to provide benefits to civilization in saving lives and reducing Healthcare costs.
• the specifications and requirements for the Level- 1 Trigger of the largest, billion dollars experiments at LHC consist of 8,000 trigger towers (or channels) which were each receiving up to 10-bit information every 50 ns (20 MHz) until 2012, then 25 ns (40 MHz) in the current run with the prospect of up to 12.5 ns bunch crossings (80 MHz) in future upgrades.
• the 30-FIow system exceeds all current requirements of the Level- 1 Trigger for LHC experiments but because it is technology-independent, it can increase its performance as needed to satisfy future upgrade requirements, increasing the Triggers' power to discover new particles.
• the 3D-Flow system can be designed to handle 24-bit or 32-bit words received from each of the 8000 channels every 12.5 ns.
• 3D-Flow DAQ-DSP IBM PC modular board with 68x 3D-Flow processors, 2,211 components, over 20,000 contact pins connected through only 8 layers printed circuit board for signals and 6 layers for power and ground.
• the 68x 3D-Flow processors are housed in 17 large FPGA from Altera, each with 4x 3D-Flow processors.
• the board and the system worked at the first prototype.
• the signals transmitted over LVDS connections provide stability and noise immunity to the system even when several signals switch at the same time.
• the board designed and built by Crosetto in 2003 had unprecedented performance in guaranteeing the clock distribution to the pin of every component in a system made of several of these modular boards in different crates with a maximum difference between any two pins of 40 picoseconds.
• the major IC design houses and silicon foundry in the world were contacted to ensure all options were considered.
• the optimization was achieved in selecting 64x processors per chip with 112 pins carrying signals to/from each group of processors facing the North, East, West and South (NEWS) sides, 256 pins for signals sent out from the Bottom port, 256 pins receiving signals from the Top port and 26 control signals.
• NEWS North, East, West and South
• the system consists of nine 6U VME Readout-Processing boards with partial pyramid for channel reduction and one 6U VME Coincidence Detection board with the final section of the pyramid to further reduce the number of channels and the detection of 511 keV pairs of photons in time coincidence.
• the global 3D-Flow system can sustain the highest possible data rate which is limited by the speed of the crystal detector capable of capturing millions of pairs of photons in time coincidence per second, with zero dead time.
• Each of the 2,304 input channels receive up to 64-bit data every 50 ns.
• Each 3D-Flow program step has the capability to perform up to 26 operations, such as addition, subtraction, comparisons of multiple values, etc. This provides a complete, thorough Object Pattern Recognition capability using information from multiple sensors (SiPM front and back, or PMT).
• the 3D-CBS is a safe revolutionary device for Early Detection and Prognosis of cancer, and to screen for cancer on asymptomatic people when it is most curable
• my breakthrough invention is a 64x 3D-Flow processors chip that is over 13 times faster, consumes less than 1/10 and costs less than 1/200 the previous 64x 3D-Flow processors version which was already proven feasible and functional in a board.
• FIG. 15 See FIG. 15, FIG. 16, FIG. 17, FIG. 18, FIG. 19, FIG. 20, FIG. 21.
• Table 4 Excel spreadsheet provided to the companies interested in bidding for the 3D-Flow VME form factor electronic board.
• FIG. 22 See FIG. 22, FIG. 23, FIG. 24, FIG. 25, FIG. 26, FIG. 27, FIG. 28, FIG. 29.
• Table 5 Excel spreadsheet provided to the companies interested in bidding for the 3D-Flow VXI form factor electronic board for 84 ASICs per board.
• Table 6 Excel spreadsheet provided to the companies interested in bidding for the 3D-Flow VXI form factor electronic board for 66 ASICs per board
• NDA Non-Disclosure Agreement
• the primary feature of the 320MHz ER/DSU board is to transfer data from onboard DDR memory at a maximum rate of 40.96GB/sec to 512 LVDS DDR channels, for an effective throughput of 640Mbps for each LVD channel. All 512 bits on the 512 LVDS channels will be presented at the same time, with new being clocked out at a rate of 1.56ns per bit on the front panel connector. In addition to transmitting data at this speed, the board will be capable of receiving data over the 512 LVDS channels and writing the data to the onboard DDR memory at a rate of 640Mbps per channel without missing any data.
• the 512 LVDS data lines on the front panel are grouped in four connectors, each with 128 LVDS data lines.
• a separate connector provides control lines such as: External clock, Start transfer and Stop transfer.
• the clock determines at which speed the data is transferred.
• a continuous increment from lMHz to 320MHz (640Mbps at each channel, presenting at the same time 512-bits on the 512 LVDS channels at a max speed of a new data every 1.56 ns) will not be required, but some frequencies will not be possible if they will be in conflict with the synchronization between read/write with RAS/CAS and other control signals at the DDR3 memory.
• the "Start Transfer" signal will initiate the transfer to/from the memory of its entire content. At any time the device receiving data can issue a "Stop Transfer".
• the ER/DSU board While the ER/DSU board is required to transfer data continuously from/to the front panel to/from the memory with no interruption and without missing any data, its interface to the VME bus or to a PCIe host will allow a host computer connected to the same interface to access the memory randomly and/or read and write via a DMA.
• the amount of data that can be sent or received is limited by the amount of onboard DDR memory.
• the data in the onboard DDR memory can be transmitted once as a single-shot output, or it can be sent repeatedly in a continuous loop until stopped by the host. In the case that a different data set needs to be transmitted, the host computer will stop transmission and reload the memory with new data.
• the receive mode will write incoming data to memory until the memory is full, at which point, the receive logic will stop receiving data and will alert the host that the memory buffer is full. The host computer can then read all of the data from the onboard DDR memory at a reduced data rate before starting to receive new data.
• VME or PCIe
• the ER/DSU board is either communicating with VME (or PCIe, depending which host is connected to the crate) or it is transferring/receiving data to/from the front panel connector.
• VME or PCIe
• the VME bus or PCIe must take control of the memory and disable the communication with the front panel connector.
• the ER/DSU board should be accessed from a driver developed for VxWorks and/or from Windows 7 (8 or 10) and should have JTAG.
• the driver is not a part of this project estimate.
• the 640MHz ER/DSU board is similar to the 320MHz board, with the following differences:
• the maximum data speed is increased from 320MHz DDR (640Mbps/channel) to approximately 640MHz DDR (1200-1280Mbps/channel).
• Each 640MHz board will only have 2 front panel data connectors instead of 4, each outputting 128 LVDS data channels, for a total output of 256 LVDS channels per 640MHz board.
• VME board housing 25 chips each with 64 x 3D-Flow processors, the VXI board with 66 of these chips and one with 84 chips.
• FIG. 43 See FIG. 43, FIG. 44, FIG. 45, FIG. 46, FIG. 47.
• This speed of data arriving at each channel every 781 ps satisfies the requirements for extracting all valuable information from radiation with a system like the 3D -Flow having the capability to execute Object Pattern Real-Time Recognition Algorithms on multiple data arriving at this speed. It satisfies the need for future upgrades of the LHC either running at frequency higher than the actual 40 MHz or at a higher luminosity. According to articles published by CERN, the LHC could not run at 80 MHz due to beam heating, however, it is planned to run at a higher luminosity.
• FIG. 39 See FIG. 39 for an overview of the test bench system implemented using the VXI form factor and FIG. 41 implemented using the VME form factor that will allow experimenters' to test their Level-1 Trigger system (3D-Flow system or any other Level-1 Trigger approach).
• the planned workflow of this proposal that will optimize the use of resources and taxpayer money to build a system that can provide measurable results on a test bench of a laboratory and easily integrate into applications such as LHC, Medical Imaging, etc., is to advance from purchasing instrumentation available on the market to generate and record/display signals similar to those generated by radiation at LHC, medical imaging, video cameras, etc. for two signals and create instrumentations to generate and record/display 8,192 signals.
• This DSU 8, 192 channel instrument replaces the Tektronix waveform generator and becomes the signal generator to test an equivalent 8, 192 channel TER unit (Trigger Event Recorder).
• the Scientific Associates can even edit the raw data and create very difficult conditions such as adding pileup events, adding noise generated by spurious particles, etc., to verify the efficacy of the 3D- Flow system (or any other trigger system) to filter the particles matching the characteristics set by the theoretical physicists or experimenters for the new particle.
• DON E I have identified a commercially available instrument made by Tektronix, Model AWG5012C, 1.2 Gsamples per second, 14-bit that can generate signals on 2 channels similar to those generated by the radiation at LHC, a PET device, a CT scan, multi-lens movie cameras, etc.
• the instrument costs approximately $55,000.
• DONE I have identified an oscilloscope made by Tektronix, model MSO70404C, 4 GHz with 4 analogue channels and 16 digital channels that could record and display all parameters relative to signals with an "eye" of 781 picoseconds.
• the instrument and probes cost approximately $65,000.
• This DSU is a valuable instrument for experimenters to create a low-cost controlled environment in their lab capable of not only using raw trigger data recorded at the CERN experiments but also having the possibility to edit the data manually, adding the most difficult patterns they may think could occur to test the efficacy of the 3D -Flow Trigger system (or the Level-1 Trigger system they have developed).
• This DSU is a valuable instrument for experimenters to create a low -cost controlled environment in their lab capable of not only using raw trigger data recorded at the CERN experiment, but also have the possibility to edit data manually, adding the most difficult pattern they may thing could occur to test the efficacy of the 3D-Flow trigger system (or the Level-1 Trigger system they have developed).
• the Associates, members of the large LHC experiments, will have the great advantage of being able to recreate in their lab with only $100,000 the real-time environment of particle events that will be generated from the detectors at CERN costing billions of dollars even before its construction. They could use raw trigger data from real experiments previously recorded at CERN, edit manually the data to include even more difficult situations like high background noise and pileup events, test the functionality and efficiency of their hardware by implementing the Level-1 trigger, improve their electronics and algorithms to assure they have the capability to identify new particles having the characteristics sought by experimenters or provide conclusive test results disproving a theory. . Demonstrate the 3D ⁇ Flow invention is technology-independent, easily migrating to future technologies having the advantage of lowering the price and increasing performance as technology improves.
• An optimized modularity of LVDS channels per connector, connectors per board, boards per system is: 128 LVDS channels per connector, 2 to 4 connectors per VME board, 8 connectors per VXI or ATCA board, 8 or 16 VME boards per VME crate, and 8 boards per ATCA and VXI crate.
• I gained space by orderly placing bundles of ribbon cables one next to the other and making the 90° cables turn on the small PCB as I drew in the next FIG. .
• the connector SEAF8-40-05.0-S-10-2-K of one assembly mates with connector SEAM8-40-S02.0-S-10-2-K at the larger PCB soldered at the edge, giving a stacking height of 7 mm, while another mates with connector SEAM8-40-S05.0-S-10-2-K, placed at 25 mm from the edge giving a stacking height of 10 mm. This will allow to increase the I/O to the board as also detailed in the caption of FIG. 55.
• the assembly of FIG. 55 helps to better utilize the available space; it can be useful in some applications with a small number of boards, but the thickness of the bundle of ribbon cables of approximately 12 mm is still too high when more than one connector is needed to connect VME boards with an interconnector distance of 20 mm.
• the cable assembly of FIG. 56 helped to solve the problem of the limited space to place ribbon cables between crates for some applications; however, placing four ribbon cables side by side and further reducing the thickness of the ribbon cables going from crate to crate as shown in FIG. 57, helps to solve more challenging problems requiring a high data transfer rate.
• FIG. 57 Further analytical verification of FIG. 57 made me realize that if a customer needs to place one of these little PCB boards next to the other because there is limited space on the front panel of the application board, then I should cut a piece of PCB along the width of the 4 ribbon cables as I did in FIG. 58 to create a window where the four ribbon cables can cross from one side of the PCB to the other side. I should also provide a hole at the corner of the small PCB board opposite to where the connector is assembled that will be used as shown in FIG. 6.
• This assembly satisfies all needs for very large boards, crates and systems to achieve maximum transfer rate. It not only satisfies all system requirements in the three applications described in FIG. 4, FIG. 5 and FIG. 6 but exceeds them when staggered as show in FIG. 60 accommodate up to 16 of these 400-pin connector-cable assemblies in an ATCA board and up to 18 in a VXI board.
• the size of the 3D-Flow system will increase, requiring longer cables for each chip in one board to communicate to its logical neighboring chip (in the global map of the detector array which is transferring data to the 3D-Flow processor array) on another board.
• the component cost of 1048 Ethernet cables at lOGbps is over $120,000 calculated as follows:
• HEP is different because it is mainly unidirectional.
• 70 details how 2048 LVDS differential signals can be received by an ATCA board using a column of connectors at the edge of the board SEAM8-40-S02.0-S-10-2-K providing a stacking height of 7.0 mm, and at 25 mm from the edge of the ATCA board a column of connector SEAM8-40-S05.0-S-10-2-K, which provide a stacking height of 10 mm which would allow two connector-cable assemblies to be staggered.
• Ethernet connector cannot fit 128 connectors on one ATCA blade or VXI board, the electronics will increase the number of boards and number of crates needed, increasing the overall cost. (See dimension of the lOGbps Ethernet connector at
• the 0.8 mm pitch connector has many technical advantages including increased system performance because it allows four 0.8 mm pitch connectors to be placed on the front panel of a VME board and 8 connectors in the VXI and ATCA boards. This will reduce the size of the system and the power consumption and increase the performance while greatly reducing the overall cost.
• FIG. 59 Implementing FIG. 59 with eight Micro Twinax 16 x 2 ribbon cables assembled all on one side of the small PCB is best for the larger VXI and ATCA boards.
• This assembly requires a deeper mounting frame occupying more space in front of the crate to support the weight of the cables as shown in FIG. 4.
• the price of all connector-cable assemblies will be the same - approximately $16,320.
• FIG. 58 with four Micro Twinax 16 x 2 ribbon cables assembled on both sides of the small PCB is be the best for the smaller VME, VPX boards.
• This assembly requires a smaller mounting frame occupying less space in front of the crate to support the weight of the cables as shown in FIG. 6.
• the price of all connector-cable assemblies will be the same - approximately $13,600.
• the maximum data transfer rate achievable between 2 VXI crates with 13 slots assuming 18 connector-cable assemblies per board, and each channel having a transfer rate of lOGbps will be 29TB/se € (or 234Tbps). This is a very conservative estimate because SamTec catalogue provides the performance of these connectors at 22Gbps and 0.5 m Twinax can provide >HMHz at -3dB insertion loss. In fact the transfer rate can be tested from 29TB/sec up to 5lTB sec to see when it fails. The price of all connector-cable assemblies will be approximately $39,000.
• Doctors and journalists who claim that screening can cause unnecessary risky procedures should work to identify the incompetent doctors who diagnose false positives and help to improve training of medical personnel.
• an astronaut or engineer at NASA makes a mistake and a Shuttle crashes we do not abolish NASA.
• NASA When a pilot makes a mistake, journalists not write articles to ban air transportation.
• drivers make an error and cause an accident journalists do not write articles to ban motor vehicles traveling faster than 20 mph but we ail help to improve car safety and better train drivers.
• An analytical thinker would start by looking at the number of channels from different subdetectors participating to Level- 1 Trigger (calorimeter, tracker, muon... , etc.), the timing relation between them, and whether those with a larger number of channels can be funneled to 8,000 channels of the calorimeter Trigger Tower. They should then ask themselves how many bits are necessary for each subdetector Trigger Tower or generally speaking, for all detectors within a certain view angle, and what is the total size of the words per channel needing to be transferred to the Trigger Processor every 25 ns; is 16-bit sufficient, or is 32-bit or 64-bit necessary? What kind of operation is necessary to perform on those bits or group of bits? Do we need to exchange data with neighboring processors to execute object pattern recognition? How efficient is FPGA to perform these operations?
• the entire 3D-Flow system made of thousands of 3D-Flow processors is monitored in real-time through the USB port at each chip that is accessing the status bits of each of the 64x 3D-Flow processors in the chip.
• this fault-tolerant monitoring program loads a modified program into each neighboring processor where there is a broken cable or broken processor.
• This fault tolerant monitoring program also saves time diagnosing the problem because it can point out the chip ID or location of the broken cable.
• the 3D-Flow OPRA has the capability to extract and optimize cost-effectively the measuring of all characteristics of the sought objects analyzing signals from detectors of different shape (circular, elliptical, etc.) and of different types (different crystals such as LSO, BGO, LYSO, solid state detectors, etc.) from detectors of the 3D-CBS (3-D Complete Body Screening).
• Fig. 61 shows a simple implementation of a cylindrical detector 102 made of crystals (e.g. BGO) 330 with slits (cuts between crystals) of equal length as shown in FIG. 63 with light-sharing for the portion of the crystals without slits, or made of a solid crystal 331 with light sharing with adjacent crystals as shown in FIG. 62.
• crystals e.g. BGO
• slits cuts between crystals
• the crystal can have a dimension larger than the larger sensor 324 PMT, SiPM or APD, coupled at the external surface of the cylinder.
• the shape of the crystal can be rectangular 6 cm x 2.5 cm x 20 cm, or other dimensions or trapezoidal of dimensions up to 6 cm x 20 cm on the outer face, 4 cm x 20 on the inner face and 2.5 cm thick, or other dimensions.
• the outer sensors can be APD or PMT 1", 1 1 ⁇ 2" or 2", or other dimensions.
• SiPM single sensor or array of sensors for example from Hamamatsu MPPC S 13361-3050NE-04, or similar series with 4 x 4 number of channels, each channel area 3 mm x 3 mm, or 6 mm x 6 mm, or other dimensions and/or other number of channels.
• the inner sensor 334 of FIG. 61, FIG. 62, FIG. 63 must be a SiPM or APD with a single sensor with a dimension smaller that the corresponding outer sensor to limit the cost.
• the inner sensor is coupled to the inner face of the crystal with a light-guide.
• the function of the outer sensor 324 is to provide the best photon arrival time, energy and signals to be interpolated with signals from adjacent sensors to calculate the "x", "y", and "z” coordinates of the photon's impact point in the crystal.
• the function of the inner sensor 334 is to provide the signal to the 3D -Flow processor to calculate the Depth of Interaction. It should be thin and not very large to minimize the obstruction of the path of the photon toward the crystal.
• the detector shape After having built, characterized and measured the efficiency and performance of at least three 3D- CBS devices with a cylindrical detector with BGO crystals, the detector shape will be modified for a smaller cylinder 108 for the head and an elliptical shape-like detector of FIG. 64 with an elliptical detector 107 for the torso of the body, having the crystals 109 at the edge of the head and at the legs, more inclined pointing toward the center of the cylinder-detector.
• These modifications of the 3D-CBS detector shape are aimed to improve efficiency, by reducing the path travelled by the photons before hitting the crystal which contributes to reduce Randoms and Multiple events and also to reduce cost in a smaller volume of crystals and a smaller number of sensors.
• FIG. 65 illustrates some examples of real-time Object Pattern Recognition Algorithms executed by each 3D-Flow processor. The specific example is suitable for particle and photon detection and measurement on a 3 x 3 sensors array.
• FIG. 66 is describing a real-time 3D-Flow algorithm receiving and processing information from a 5 x 5 sensors array.
• the inventive step of this invention is not limited to the current instruction set of the 3D-Flow processor capable to execute up to 26 operations in 3 nanoseconds such as add, subtract, compare with 24 values, etc. but this instruction set can be changed to more efficiently execute specific instructions needed for finding specific objects (for example the 3D-Flow processor, in addition to the normal arithmetic and logic instructions of a standard computer, has an instruction to compare 24 values in one cycle which is specific for finding a center of gravity in particle detection.
• the detailed timeline for the development of the 3D-Flow OPRA and the 3D-CBS is reported in FIG . 71. It is based on 59 quotes of different components received from industries (for each component I recei ved two to three quotes) The phases of the work plan synchronizing the delivery of the different components assembled by a team of 12 people, estimates it will take 2 years.
• the 3D-CBS (3-D Compete Body Screening) outperforms the Explorer which was funded by NUT for $15.5 million in October 2015.
• the 3D-CBS intense computation (goo .gl/XqgnNf) capability at the front-end using 3D-Flow OPRA provides more accurate measurements with less than 3,000 economical BGO crystals compared to 500,000 expensive LSO crystals used by the Explorer project.
• the Explorer consumes 60KW compared to 3D-CBS's 4KW, can process only 40TB of data in one day by a farm of computers compared to 40,000TB per day by just 9 3D-Flow OPRA boards; plus the Explorer is ten times more expensive than the 3D-CBS.
• the Explorer less efficient that the 3D-CBS, costing 25 to 35 times the current PET cannot create a paradigm change in biomedical imaging because it cannot implement a plan to save millions of lives in 30 years as described in the table of FIG. 70 and at goo.gl/4vEEW6. There is nothing new in the Explorer, just more of everything as it was commented by several top experts in the field.
• FIG. 67 is reporting the characteristics of the electronics and FIG. 68 of the detector of the Explorer project published by their authors which was also the design submitted to the National Institute of Health that granted $15.5 million for its construction.
• the table reported in FIG. 69 compares the features of the Explorer with the 3D-CBS features.
• the MasSpec Pen is a useful accessory to have during surgery, however, they cannot defeat cancer.
• the 3D-CBS the first true paradigm change in biomedical imaging and the most competitive technology that can defeat cancer
• This device is the 3D-CBS (3-D Complete Body Screening), an advanced PET with a 1.5m detector covering all organs of the body (see trifold at "goo.gj/YcAJDy", more details at “goo.gl/JMKyek” and video at goo.gl/tKGUivv) that shows competitiveness in results not only with all other technologies such as drugs for late detection, Genomic, Immunotherapy, CICD, etc., but also within all diagnostic medical imaging devices such as MRI, CT, Ultrasound, which measure tissue density and require many normal cells to change into cancerous cells before tissue morphological changes can be detected.
• 3D-CBS 3-D Complete Body Screening
• the 3D-CBS benefits cancer patients by ensuring all cancer cells are removed surgically, with radiation or chemotherapy and detects cancer early and effectively on asymptomatic people.
• My basic 3D-Flow parallel -processing architecture summarized in one page at 'goo.gl/NOSCek'. recognized valuable by academia, industry and research centers at a major official, formal, international scientific, review, held at Fermilab in 1993 (goo.g.l/zP76Tc . proven feasible and functional in FPGA hardware, when in synergy with the implementation in its different parts using 2015 technology is summarized in two pages at 'goo ; gl/Aos . Q " and detailed at 'goo.gl/wJXIZ.1 ' .
• My 3D-Flow invention could have replaced hundreds of crates containing 4,000 electronic boards of CERN CMS L-l Trigger Experiment at a fraction of the cost, while providing more performance, and could have replaced the trigger at many other experiments at CERN.
• Results can be measured using the ER/DSU unit
• the ER/DSU unit FIG. 39, FIG. 40, FIG. 41, FIG. 42, FIG. 43, FIG. 44, FIG. 45, FIG. 46, FIG. 47 costing only $40,000 would be able to record raw data from the LHC (Large Hadron Collider) apparatus and then replay the same data to the 3D-Flow OPRA system and to the CMS Level-1 Trigger (or other trigger system) proving their enormous difference in efficiency and cost-effectiveness.
• LHC Large Hadron Collider
• the 3D-Flow OPRA invention When used in the 3D-Flow OPRA invention is used in the 3D-CBS (3-D Complete Body Screening) technology, it makes it hundreds of times more efficient than the over 10,000 PET (Positron Emission Tomography) devices used in hospitals providing for the first time a true paradigm change in biomedical imaging.
• 3D-CBS 3-D Complete Body Screening
• This proposal/invention/project is to create a general purpose 3D-Flow OPRA (Object Pattern Real-Time Algorithm) instrumentation that can identify objects in real-time, display their characteristics, and provide flexible triggering features using fast neighboring data exchange and by analyzing data for a time longer than the time interval between two consecutive input data which arrive in parallel from a matrix of thousands of transducers at ultra-high speed.
• 3D-Flow OPRA Object Pattern Real-Time Algorithm
• the 3D-Flow OPRA instrument can also solve multiple applications in different fields where the requirements are to identify among millions of other non-relevant signals cluttering the good information, the signals related to specific objects such as pairs of 51 IkeV photons, the profile and details of a face among thousands of faces, the signals characterizing the Higgs boson particle, etc.
• the 3D-Flow OPRA instrument for example can recognize a shape of different colors, a shape of different levels of heat, a shape of different levels of sound volume and frequencies, a shape of different energies, a shape of different mechanical stress, a shape of different pressure, a shape of different light, the characteristics of a specific subatomic particle measured from signals generated by CCD, APD, PMT, SiPM, PADs, silicon strip detectors, wire-chambers, drift-chambers, etc.
• this proposal/project is also providing the method and apparatus to build an instrument, the ER/DSU (Event Recorder and Detector Simulator Unit) with the capability to record in a memory, raw data, and replay them at the real-time speed to the 3D-Flow OPRA or 3D-CBS systems under test to measure their performance in finding unknown objects.
• ER/DSU Event Recorder and Detector Simulator Unit
• My patents are protecting investors who care to make a difference in the world.
• My basic inventions have been proven feasible and functional in hardware.
• My latest improvements give an additional advantage in lower cost and higher efficiency compared to my original design of the 3D-CBS from the year 2000.
• My patented invention has the capability to accurately capture all possible signals from the tumor markers at the lowest cost per valid signal captured compared to alternative approaches.
• My patent protects the investor with a large margin in competitivity which goes from the component costs to build my 3D-CBS to the component cost for the competitors to build their Explorer.
• the cost of the components for the 3D-CBS is less than $2 million, while for the Explorer cost is more than $20 million.
• the selling price can be set anywhere below the Explorer's price which they would have to be set at over $20 million - their component cost - if they want to make a profit.
• the same criteria can be used for the examination cost that I selected as $400 but could be increased to over $1000 and still remain competitive.
• 3D-CBS units located in different countries (USA, Canada, Italy) will constantly measure performance to confirm or modify the estimates in this table as follows: each unit screening 10,000 people in the age group 55 to 74 taken from a location where, in the previous 20 years, the mortality rate was constant (e.g. 0.5%) and reporting every year changes in the death rate.
• inventive steps of the method and apparatus of this invention is the synergy and combinations of several inventions I made in the past with new ones which together allow to achieve enormous performance increase in several fields of applications. Described herein are for high energy physics experiment applications and for medical imaging.

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