EP3532933A4 - Hybrid memory module - Google Patents

Hybrid memory module Download PDF

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Publication number
EP3532933A4
EP3532933A4 EP17865589.0A EP17865589A EP3532933A4 EP 3532933 A4 EP3532933 A4 EP 3532933A4 EP 17865589 A EP17865589 A EP 17865589A EP 3532933 A4 EP3532933 A4 EP 3532933A4
Authority
EP
European Patent Office
Prior art keywords
memory module
hybrid memory
hybrid
module
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP17865589.0A
Other languages
German (de)
French (fr)
Other versions
EP3532933A1 (en
EP3532933B1 (en
Inventor
Frederick A. Ware
John Eric Linstadt
Kenneth L. WRIGHT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of EP3532933A1 publication Critical patent/EP3532933A1/en
Publication of EP3532933A4 publication Critical patent/EP3532933A4/en
Application granted granted Critical
Publication of EP3532933B1 publication Critical patent/EP3532933B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/305—Providing cache or TLB in specific location of a processing system being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
EP17865589.0A 2016-10-31 2017-10-10 Hybrid memory module Active EP3532933B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662415143P 2016-10-31 2016-10-31
PCT/US2017/055908 WO2018080783A1 (en) 2016-10-31 2017-10-10 Hybrid memory module

Publications (3)

Publication Number Publication Date
EP3532933A1 EP3532933A1 (en) 2019-09-04
EP3532933A4 true EP3532933A4 (en) 2020-10-07
EP3532933B1 EP3532933B1 (en) 2022-03-02

Family

ID=62025388

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17865589.0A Active EP3532933B1 (en) 2016-10-31 2017-10-10 Hybrid memory module

Country Status (4)

Country Link
US (2) US10847196B2 (en)
EP (1) EP3532933B1 (en)
CN (1) CN109416656B (en)
WO (1) WO2018080783A1 (en)

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US10909012B2 (en) * 2018-11-12 2021-02-02 H3 Platform, Inc. System having persistent memory
US11579925B2 (en) 2019-09-05 2023-02-14 Nvidia Corporation Techniques for reconfiguring partitions in a parallel processing system
US11249905B2 (en) * 2019-09-05 2022-02-15 Nvidia Corporation Techniques for configuring a processor to function as multiple, separate processors
US11893423B2 (en) 2019-09-05 2024-02-06 Nvidia Corporation Techniques for configuring a processor to function as multiple, separate processors
US11663036B2 (en) 2019-09-05 2023-05-30 Nvidia Corporation Techniques for configuring a processor to function as multiple, separate processors
CN111782146B (en) * 2020-06-30 2023-10-13 深圳忆联信息系统有限公司 Method, device, computer equipment and storage medium for realizing write cache

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US20100293420A1 (en) * 2009-05-15 2010-11-18 Sanjiv Kapil Cache coherent support for flash in a memory hierarchy
US20160267027A1 (en) * 2015-03-10 2016-09-15 Kabushiki Kaisha Toshiba Memory device for computer

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US6000006A (en) 1997-08-25 1999-12-07 Bit Microsystems, Inc. Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage
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US7050351B2 (en) * 2003-12-30 2006-05-23 Intel Corporation Method and apparatus for multiple row caches per bank
US7269708B2 (en) 2004-04-20 2007-09-11 Rambus Inc. Memory controller for non-homogenous memory system
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EP1712985A1 (en) * 2005-04-15 2006-10-18 Deutsche Thomson-Brandt Gmbh Method and system for storing logical data blocks into flash-blocks in multiple non-volatile memories which are connected to at least one common data I/O bus
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8055833B2 (en) * 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
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Also Published As

Publication number Publication date
CN109416656B (en) 2023-08-11
US20210118480A1 (en) 2021-04-22
CN109416656A (en) 2019-03-01
US10847196B2 (en) 2020-11-24
US11456025B2 (en) 2022-09-27
EP3532933A1 (en) 2019-09-04
EP3532933B1 (en) 2022-03-02
US20190259435A1 (en) 2019-08-22
WO2018080783A1 (en) 2018-05-03

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