EP3369117A1 - Procédé de fabrication d'un substrat composite - Google Patents
Procédé de fabrication d'un substrat compositeInfo
- Publication number
- EP3369117A1 EP3369117A1 EP16806229.7A EP16806229A EP3369117A1 EP 3369117 A1 EP3369117 A1 EP 3369117A1 EP 16806229 A EP16806229 A EP 16806229A EP 3369117 A1 EP3369117 A1 EP 3369117A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- assembly
- bricks
- layers
- layer
- electrical insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000011449 brick Substances 0.000 claims abstract description 81
- 238000010292 electrical insulation Methods 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 229910052782 aluminium Inorganic materials 0.000 claims description 22
- 239000000843 powder Substances 0.000 claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 19
- 238000000429 assembly Methods 0.000 claims description 19
- 230000000712 assembly Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 230000005496 eutectics Effects 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 238000005304 joining Methods 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 238000007650 screen-printing Methods 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 6
- 229910052788 barium Inorganic materials 0.000 claims description 6
- 239000011230 binding agent Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 230000005693 optoelectronics Effects 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- -1 SiO x or SiO 2 Chemical compound 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims description 3
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 239000002178 crystalline material Substances 0.000 claims 1
- 238000005520 cutting process Methods 0.000 abstract description 12
- 239000010410 layer Substances 0.000 description 145
- 238000009792 diffusion process Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 5
- 238000005245 sintering Methods 0.000 description 5
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000007669 thermal treatment Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910021471 metal-silicon alloy Inorganic materials 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 239000003637 basic solution Substances 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005779 cell damage Effects 0.000 description 1
- 208000037887 cell injury Diseases 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/047—PV cell arrays including PV cells having multiple vertical junctions or multiple V-groove junctions formed in a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0475—PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Definitions
- the present invention relates to the field of composite substrates, in particular for the manufacture of photovoltaic cells and modules for solar panels, as well as for the manufacture of LED arrays.
- the invention particularly relates to a method of manufacturing a composite substrate and said composite substrate obtained by this method.
- the cells are interconnected in series by welding or gluing metal strips arranged alternately above and below successive cells. Mechanical stresses are thus generated on the edges of the latter and promote damage or even breakage of the cells.
- this interconnection involves respecting a minimum distance between two successive cells so that the ribbon can be correctly placed from the front of one cell to the back of the next. This results in active surface losses and thus power losses.
- the second disadvantage mentioned above takes even more weight because it is necessary to connect a larger number of cells for the same surface so that the risk of breakage increases.
- the spacing between the larger cells in total covers a larger area in the final module compared to a conventional module.
- the present invention thus aims to overcome at least these two disadvantages.
- the invention proposes a method for manufacturing a composite substrate intended for applications in the photovoltaic or optoelectronic field, the method comprising the following steps: a) providing bricks for assembly to form at least one assembly, bricks having joining surfaces,
- this process leads in few steps to obtaining a composite substrate suitable for the manufacture of series-connected electronic components, the composite substrate being constituted by the result of the cutting of a plurality of bricks (commonly called Slab in the English terminology), assembled by an electrical conduction layer so as to form at least one assembly, the bricks being electrically isolated from each other by two layers of electrical insulation between which the conduction layer is disposed.
- a composite substrate suitable for the manufacture of series-connected electronic components
- the composite substrate being constituted by the result of the cutting of a plurality of bricks (commonly called Slab in the English terminology), assembled by an electrical conduction layer so as to form at least one assembly, the bricks being electrically isolated from each other by two layers of electrical insulation between which the conduction layer is disposed.
- step e After cutting according to step e), the bricks form cobblestones assembled through the electric conduction layer and the cut brick assembly becomes a pavement, formed of assembled blocks.
- the assembly plan of the bricks is a plane parallel to the planes defined by the assembly surfaces of said bricks.
- the composite substrate can thus be used as a precursor in the manufacture of cells and assemblies of photovoltaic cells, capable of delivering high voltage from the serial connection of the blocks via the layer electrical conduction.
- Part of the interconnection is advantageously obtained by the method of manufacturing the composite substrate itself, using the conduction layer which also plays the role of an assembly layer between the blocks for forming the PV cells.
- the conventional welding step between the cells is avoided so that the risks of breakage and cell damage are reduced.
- the lost space for the connection between the cells is limited only by the thickness of the electrical conduction layer and the insulation layers and not by the space required to deposit a conductive ribbon between neighboring cells.
- this method allows the manufacture of photovoltaic modules (PV) of the desired size by varying the number of blocks or cells put in series and their size (standard 156x156mm 2 or other).
- the bricks, from which the cells are derived are obtained by cutting, to the desired dimensions, blocks or ingots available commercially.
- a tiling, of the desired PV module size is obtained.
- step a) comprises providing bricks made of generally p-doped and / or doped type n-type semiconductor material, the semiconductor material being selected from GaN-based alloys and elements or alloys of elements of column IV, and preferably the semiconductor material is silicon and generally crystalline silicon.
- the composite substrate is thus formed of materials that are particularly suitable for applications in the photovoltaic field, microelectronics and optoelectronics.
- the bricks are for example obtained by cutting ingots or from blocks of material, commonly called 'bulk'.
- the cutting is performed so as to obtain a sufficient thickness of bricks to obtain the optimum yields according to the intended applications. It is generally between 100 and 800 micrometers.
- the electrical insulating layers are formed in step b) from silicon oxide, such as SiO or Si0 2, or from a Ti0 2 oxide powder, Al 2 0 3 , ZnO, SiO 2, a mixture of these oxide powders, or a mixture of these oxide powders with at least one organic and / or inorganic binder.
- the layers of electrical insulation between two bricks may be of different natures, especially if it is necessary to passivate surface conditions of one of the bricks.
- the formation of the SiO 2 silicon oxide electrical insulation layer is conventionally deposited by PECVD (acronym for Plasma Enhanced Chemical Vapor Deposition) over a thickness that makes it possible to provide electrical insulation for the conduction layer, once the composite substrate formed.
- PECVD plasma Enhanced Chemical Vapor Deposition
- the thickness is thus from a few tens of nanometers to a few micrometers and preferably the thickness is in a range from 10 nm to 5 micrometers.
- the SiOx electrical insulation layer is obtained by thermal oxidation of the silicon brick by annealing in an oven to a thickness of a few microns and preferably a thickness in the range of 10 nm to 500 nm.
- a sintering step is necessary in order to melt the envelope external beads (forming the powder) and ensure the bonding and cohesion of the balls together.
- This sintering step typically comprises an annealing of 30 to 300 minutes carried out over a temperature range from 700 to 1200 ° C, associated with the application of a pressure exerted in a direction perpendicular to the assembly plane.
- the use of an organic and / or inorganic binder mixed with these powders advantageously makes it possible to reduce the annealing temperature of the sintering step and a very good mechanical adhesion between the silicon bricks.
- the final thickness of an electrical insulation layer formed by this method varies between about 20 nm and 200 micrometers.
- the thickness of the electrical insulation layers varies according to the materials used so as always to have the insulation properties necessary to isolate the two bricks together and isolate them from the conduction layer.
- Stage d) of the process advantageously makes it possible to anneal the oxide powders mixed or not with binders.
- the sintering step is obtained.
- step c) of the method according to the invention comprises:
- step b) forming a silicon layer directly on the silicon oxide electrical insulation layers formed in step b) and covering the assembly surfaces of the bricks
- metal layer directly on each of the silicon layers the metal being chosen in particular to form a eutectic with silicon, such as aluminum, silver, gold, platinum, barium, copper or an alloy of these metals, and
- the advantage of using a metal and especially a low-melting point metal, such as aluminum, to form the electrical conduction layer is that the heat treatment applied in step d) allows to liquefy at least partly the metal layers in contact so as to homogenize the electric conduction layer and to ensure a good bond between the bricks. Furthermore, the heat treatment guarantees the diffusion of the adjacent silicon in the liquid aluminum phase, which, after cooling, allows the formation of an Al-Si alloy whose composition is close to that of the eutectic when the heat treatment applied reaches 650 ° C. In addition, the electrical insulation layers deposited upstream on the silicon bricks form an effective barrier to the diffusion of the metal to the bricks so that the electrical insulation between the bricks is well maintained.
- electrical insulation layers act as barrier layers for the diffusion of impurities from the metal to the bricks, which could have adverse effects on the performance of the cells.
- the material of the electrical insulation layers may be of any of the aforementioned types, namely a deposited silicon oxide, thermal, in the form of powder and oxide powders.
- the metal layer is advantageously formed by sputtering or by evaporation or by full plate screen printing of a conductive paste whose conductive element forms a eutectic with silicon.
- the nature of the metal of said metal layers is chosen so that the bonding resulting from the contacting and the annealing is resistant to the temperatures applied in the rest of the process, in particular in the case of the manufacture of homojunction or heterojunction photovoltaic cells. .
- the nature of the metal present in the metal layer is also chosen so that the metal layer has an electrical resistivity of less than or equal to 10 -4 ohm cm.
- the heat treatment of step d) is carried out at a temperature between the eutectic formation temperature between the silicon and said metal and 900 ° C.
- step c) comprises the disposition of at least one metal element, such as an Al, Ar, Au, Zn, Cu, Pt or Ba insert, so as to form the electrical conduction between the layers of electrical insulation.
- at least one metal element such as an Al, Ar, Au, Zn, Cu, Pt or Ba insert
- the metallic element can take a multitude of forms, such as a perforated metal plate, in which at least one through hole has been formed, a plurality of wires or metal blades, patterns formed by screen printing through a mechanical mask, insofar as regions of the electrical insulation layer on which the metal element is disposed are not covered. The contacting of these regions with the second layer of electrical insulation makes it possible to assemble the bricks in step c) of the process.
- discontinuous electrical conduction layer must still provide continuity in at least one direction so that current can be collected.
- the electrical conduction layer is continuous or discontinuous depending on the embodiments considered and for the needs of future applications.
- the arrangement of at least one metal element is chosen especially in the case where the electrical insulation layers are formed by at least one oxide powder which will be sintered, so as to obtain good electrical conduction.
- the use of the metallic elements can be combined with layers of electrical insulation formed by thermal Si0 2 or Si0 2 deposited. This configuration makes it possible to combine the advantages of good electrical conduction and good mechanical adhesion of the electrical insulating material.
- step c) of forming the electrical conduction layer comprises a screen-printing deposit of a layer of conductive paste on at least one of the electrical insulation layers formed in step b).
- the screen printed conductive paste layer has a thickness of between 20 and 500 microns and preferably about 100 microns.
- This layer is deposited in the form of patterns, especially if the conducting element of the conductive paste does not form eutectic with silicon.
- the conductive paste consists, for example, of a fairly viscous mixture of a matrix, such as glass frit, and metal billets, such as aluminum billets.
- step d) is carried out at a temperature ranging from 300 to 900 ° C and preferably about 500 ° C so as to anneal or activate the screen-printed conductive paste, which increases the conductive character of the conductive paste and increases the bonding efficiency between the layers of electrical insulation forming the assembly between the bricks.
- step d) of applying a heat treatment is generally involved in reinforcing the bonding energy between the bricks.
- This bonding is particularly adapted to withstand the temperatures applied for the manufacture of electronic components, such as homojunction or heterojunction cells.
- the method comprises, after step e), a step f) for forming protection elements of the exposed surfaces of the electrical conduction layer and of the electrical insulation layers of the composite substrate.
- These protective elements of insulating material are indeed intended to limit the risk of short circuit between two neighboring bricks assembled.
- the exposed surfaces on which the protective elements are formed may be considered as exposed wafers of said layers of the composite substrate from the cut-out of the assembly.
- protection elements also serve to protect the layers of insulation and electrical conduction during the chemical treatments performed in the following process for the manufacture of microelectronic components.
- These protection elements are formed from insulating materials such as silicon oxide, Al 2 O 3 alumina, AlN, SiN, resin, etc.
- These protective elements are mainly obtained by deposition by PECVD, ALD (Atomic Layer Deposition), by printing a screen-printing resin, such as an epoxy-based polymer, or by spraying through the openings of a mechanical mask.
- the resin is mainly used in the case where it is intended to remove the protective elements later, or if the subsequent heat treatments are performed at low temperatures.
- These protection elements have a width of about several tens of micrometers and a thickness of between 1 nm and 10 microns and on average a thickness of a few hundred nanometers according to the deposition technique used. These protection elements make it possible to insulate the insulation layers and the electrical conduction layers of the assembly interface between the blocks and to protect these layers against the attacks of acidic and basic reagents used during the manufacture of the components. such as photovoltaic cells.
- the method comprises, after step f), a step h) of screen printing of metal contacts configured to ensure the conduction of an electric current, via the electric conduction layer, between two bricks assembled and then cut to size. step e), said cut bricks forming two bonded blocks.
- a step g) is carried out between step f) and step h) comprising removing a portion of the protection elements so as to discover the surface of the underlying electrical conduction layer.
- the metal contacts are then easily formed on the exposed surface of the electrical conduction layer.
- step g) The removal of a portion of the protection elements according to step g) is advantageously carried out by laser ablation.
- the nature of the dough deposited by screen printing and the deposition temperature used are configured for a targeted consumption of a portion of the protection elements, so that the contacts are formed without requiring a separate step of removing the portions of the protective elements.
- the method may comprise, before step h), the formation of a layer of n-doped semiconductor material and a layer of p-doped semiconductor material. respectively on both sides of the composite substrate and an antireflection layer on the face intended to receive the light radiation.
- the process comprises, before step d) a step i) of bonding at least two assemblies.
- the composite substrate is formed from least two bonded assemblies, suitable for forming modules for photovoltaic applications.
- step d) The heat treatment of step d) is then useful for reinforcing the bonding energy of the assembly of the bricks and also the bonding of the assemblies together.
- step i) comprises:
- step k for forming layers of electrical insulation, so as to cover the assembly faces
- the electrical insulation layers covering the assembly faces intersect with the electrical conduction layers assembling two neighboring bricks.
- the electrical conduction layers between two assemblies are isolated from the electrical conduction layers between the bricks by the presence of the electrical insulation layers connecting two assemblies.
- the present invention proposes a composite substrate, intended for applications in the photovoltaic field, comprising:
- pavers each comprising joining surfaces, the blocks being assembled via the joining surfaces so as to form at least one paving
- the electric conduction layer between the electrical insulation layers of the assembled blocks, the electric conduction layer having an electrical resistivity of less than or equal to 10 -4 ohm cm and being electrically insulated by the insulation layers.
- the at least one paving is the result of the cutting of an assembly of assembled bricks, in a plane perpendicular to the brick assembly plane, each brick becoming a paving unit after having been cut out, in other words a pavement.
- the blocks are in p-type doped silicon and / or doped n-type.
- the paving can consist of successive blocks of p-type or n-type silicon, or alternating n-type and p-type blocks.
- the electrical insulation layers are made of silicon oxide and the electrical conduction layers comprise aluminum. A very good vertical electrical conduction is thus obtained between the blocks.
- the composite substrate comprises at least two pavements bonded laterally to one another by means of an electrical conduction layer, electrically insulated between two layers of electrical insulation covering the bonded lateral sides of the at least two tilings.
- the electric conduction layer serves two functions, that of ensuring the assembly / bonding between the paving stones and the tilings respectively, resistant to temperature, and that of ensuring electrical interconnection between the pavers and between the tessellations.
- the nature of the materials and the thicknesses of the electrical insulation layers are chosen according to the material of the blocks, the nature of the conduction layer and the temperatures that will be applied thereafter, so as to form a barrier to the diffusion of the elements constituting the conduction layer to the cobblestones. Thus, the properties of these are not altered.
- the composite substrate comprises metal contacts configured to ensure the conduction of the electric current between the blocks and between the at least two tilings bonded via the electric conduction layers.
- Each of the blocks can thus be used as an active element in an electronic component, such as a photovoltaic cell.
- these pavings are judiciously used to form LED arrays.
- the invention relates to a photovoltaic module comprising at least one composite substrate as previously described.
- FIG. 16 and 17 schematically illustrate a top view of two examples of a photovoltaic cell.
- Figure 1 illustrates a front view of two bricks 1 (or slab) of silicon having a thickness of 78 mm and side dimensions of 156 mm x 156 mm, provided according to step a) of the method.
- These silicon bricks 1 are initially obtained by prior steps of cutting silicon ingots (conventionally generated), doped p-type with a boron doping rate of 10 15 atoms. cm "3. Once the ingot cut to the desired dimensions to form bricks 1 Gross, they are etched with a basic solution to remove the silicon regions work-hardened to the cutting step.
- joining surfaces 2 of bricks 1 then have the flatness and roughness necessary for their subsequent assembly, for example a roughness of less than 10 ⁇ and preferably of 2 ⁇
- the bricks 1 are then placed in an oxidation furnace thermal treatment for the application of a thermal treatment at 850 ° C. for a period of 30 minutes These conditions allow the formation of a layer of SiOx silicon oxide, a few nanometers thick, on the bricks 1, forming the electrical insulation layers 3 covering the joining surfaces 2.
- the electrical insulating layers 3 may be formed of other insulating materials such as silicon oxide Si0 2 deposited, an oxide powder based on Ti0 2, AI 2 0 3, from ZnO, SiO 2 powder, a mixture of these oxide powders, or a mixture of these oxide powders with at least one organic binder and / or inorganic.
- the presence of the binders makes it possible to lower the temperature necessary for sintering the powders.
- a silicon layer 6 of a few micrometers thick is formed on each electrical insulation layer 3 by evaporation followed by a metal layer 7 of aluminum formed with the same technique to a similar thickness.
- the metal of the metal layer 7 is chosen among aluminum, silver, gold, platinum, barium, copper or an alloy of these metals to achieve a eutectic with silicon.
- step d) the joining surfaces 2 of the two bricks 1 are placed facing for a contacting according to step c) of the method and obtaining an assembly 5 of the two bricks 1 ( Figure 2).
- the assembly 5 is then subjected to a heat treatment commonly called “bonding annealing” according to step d).
- This treatment is carried out at 650 ° C. for 30 minutes in an oven under atmospheric pressure so as to liquefy the aluminum layer 7, to promote the diffusion of the silicon in the aluminum so as to obtain a layer of Al-Si alloy of the composition of the eutectic after cooling (eutectic: 12.6% weight of silicon at 577 ° C.).
- the conditions of the heat treatment varies between the temperature of the silicon eutectic with the corresponding metal and 700 ° C.
- an electric conduction layer 4 comprising an aluminum layer resulting from the assembly of the two aluminum layers 7 initially formed by evaporation.
- the electrical conduction layer (4) has an electrical resistivity of less than or equal to 10 -4 ohm cm
- This aluminum layer is framed on either side of a layer of an Al-Si alloy. all aluminum layers 7 and the layers of an Al-Si alloy as the electrically conductive layer 4 also framed by an electrically insulating layer 3 of SiO x.
- This electrical insulator layer 3 is elsewhere configured to form a barrier to the diffusion of aluminum to the bricks 1 and to ensure good electrical insulation between the two bricks 1.
- This electrical insulation layer 3 is also configured to electrically isolate the conduction layer 4 and the two bricks one to the other.
- the necessary thickness of the electric insulating layer 3 is about 15 nm. in case of oxide powder, the thickness of the electrical insulation layer 3 after fri is between about 20 nm and 200 micrometers.
- the assembly 5 of the two bricks 1 is then cut in a plane perpendicular to the assembly plane of the bricks 1, that is to say in a vertical plane with respect to FIGS. according to step e) of the method.
- the cut illustrated in FIG. 3 by dashed lines, is carried out by any conventional method known to those skilled in the art such as cutting by band saw, wire with diamond inserts or using grains of SiC as abrasive, of thus form a paving 8, with a thickness chosen according to the desired cell and which may be between 100 to 800 microns, typically about 200 microns, formed by the assembly of two pavers 9 from the two cut bricks 1.
- the composite substrate 100 thus formed of bricks 1 assembled and then cut is assimilated to a paving 8 consisting of two blocks 9 interconnected by means of an electrical conduction layer 4, insulated between two layers of electrical insulation 3.
- the FIG. 5 illustrates a perspective view of the composite substrate 100 rotated at an angle of 90 ° with respect to the view of FIG. 4. According to this view, the assembly plane of the bricks 1 is a horizontal plane.
- more than two bricks 1 can be assembled using the method mentioned above for obtaining a paving 8 consisting of 3, 4 or more blocks 9 assembled (FIGS. 16 and 17).
- the present invention also proposes the bonding between several assemblies each comprising several bricks, followed by cutting to form a PV module (FIG. 17).
- the method comprises providing three brick assemblies 1 formed in step c of the method, each of the three assemblies having assembly faces 11 (step j).
- An electrical insulation layer 3 of the same type as that formed on the assembly surfaces 2 of the bricks 1 is formed on the assembly faces 11 according to step k.
- an electric conduction layer 4 (step I) of the same type as previously described for the assembly 5 of the bricks 1 is formed between two layers of electrical insulation 3 so as to stick the three assemblies 5 in pairs. Thanks to this method, the electric conduction layers 3 between the three assemblies 5 are electrically isolated from the electrical conduction layers 4 connecting the bricks 1 of the same assembly 5.
- the bonded assemblies 5 are cut according to step e) of the process so as to obtain the composite substrate 100 comprising the result of the cutting of three assemblies 5 bonded together in pairs comprising each three bricks 1 of silicon, ie a composite substrate 100 comprising three tilings 8 glued in pairs, each of the tessellations 8 comprising three assembled blocks 9 of silicon, as illustrated in FIG. 17.
- FIGS. 6 to 9 illustrate steps of functionalization of the composite substrate 100, in particular for the manufacture of high voltage photovoltaic modules from a paving 8 comprising two assembled silicon blocks 9 measuring 78 mm wide and 156 mm thick. long, as shown in Figure 5.
- Protection elements 12 of the exposed surfaces of the assembly interface between the two blocks 9 are formed on either side of the electrical conduction layer 4. These elements 12 are formed by CVD deposition of an electrical insulating material through the openings of a mechanical mask (step f, Figure 6). According to an alternative, the protective elements 12 are deposited by screen printing of a resin or an insulating paste.
- An n-doped silicon layer is formed by doping the blocks about 500 nm deep from one of the paving surfaces 8 to receive the light, followed by a p-doped silicon layer 10 'formed on the opposite face then an antireflection layer 16 (ARC for Anti Reflective Coat) on the n-doped layer 10 and / or on the p-doped layer 10 '. Then, as illustrated in FIG. 7, a portion of each of the protection elements 12 is removed, for example by laser ablation, so as to discover the underlying electrical conduction layer 4 (step g). Metal contacts 13 (Al and Ag) are then screen-printed at the location of the removed portions, so as to ensure electrical conduction, schematically illustrated by the arrow in FIG. 9, between two blocks 9 via the coating layer. electrical conduction 4 (step h). Of course, other methods of forming conventional contacts and known to those skilled in the art can be used.
- PV photovoltaic cell
- the assembly between the bricks 1 and the bonding between the assemblies 5 are configured to withstand the heat treatments used in the manufacture of homo-junction PV cells (850 ° C.) as heterojunction (230 ° C.) thanks to the nature of the materials used. to form the electrical insulation layers 3 and the formation of the electrical conduction layer 4 of bonding and / or assembly, their deposition mode, and the heat treatment applied in step d).
- the Tiling configuration 8 is adaptable depending on the number of cells desired for example 1x4 (illustrated in Figure 16), 2x2, 3x3 (illustrated in Figure 17), etc.
- the number of cells formed in a single composite substrate 100 is not limited and may vary depending on the desired applications.
- the open-circuit voltage is between 30 and 50V. If each of the conventional cells is replaced by a composite substrate 100 comprising 4 cells in series according to the present invention, for a similar PV panel surface, the open-circuit voltage obtained is between 120 and 200V. It is then possible to remove a high voltage conversion stage from the inverter and reduce system costs.
- FIGS. 10 and 11 illustrate a second embodiment of the invention which differs from the previous one in that step c) is performed by depositing a layer of conductive paste 14 based on aluminum and a matrix of glass frit on an electrical insulation layer 3 of silicon oxide to form the electric conduction layer 4 having finally a thickness of about 100 microns.
- the metal contained in the conductive paste 14 may be silver or copper.
- the thickness of the electric conduction layer 4 can vary between 5 and 500 ⁇ and preferably between 10 and 100 micrometers.
- step d serving to stiffen the conductive paste 14 ensuring the mechanical adhesion of the assembly 5, is applied for 200 minutes at a temperature of about 700 ° C.
- the duration of the heat treatment may vary between 1 and 300 minutes and the temperature may be between 200 and 900 ° C.
- FIGS. 12 to 15 illustrate a third embodiment which differs from the first embodiment by the formation of the electric conduction layer 4.
- the conduction layer formation step c) is carried out by the insertion of several blades. 15 of aluminum (FIG. 12) between the electrical insulation layers 3. As represented in FIGS. 13 and 14, all of these blades 15 thus form a discontinuous conduction layer 4 in the paving 8, and passing vertically at the join between two pavers 9, (also visible on the Figure 15 which is a cross-sectional view of the paving 8 along the plane A of Figure 14, at the level of the electrical contacts 13). Electrical contacts 13, illustrated by a block diagram (FIGS. 14 and 15), are formed from these blades 15 for current conduction in subsequent applications.
- the inserted metal element 15 can take any form (wire, perforated plate, etc.) insofar as it ultimately allows the electrical conduction and the putting into series of the PV cells.
- the nature of the metal of the inserted element used may be chosen from Ar, Au, Zn, Cu, Pt or Ba or other insofar as this metal makes it possible to obtain good electrical conduction between the blocks 9 and the tilings 8, resistant to the thermal treatments used later in the manufacture of the desired electronic components.
- the method of the present invention makes it possible to manufacture composite substrates 100 adapted to the formation of PV cells of desired size, delivering high voltage, a part of the interconnection being made in the manufacturing process of the composite substrate 100
- This process makes it possible to produce mono or bifacial cells. Since the step of placing the cells in modules represents approximately 40% of the total cost of a PV installation (excluding cabling), this innovation guarantees a significant improvement in the cost / performance ratio of the cells while allowing high-voltage work to be performed directly exit.
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- General Physics & Mathematics (AREA)
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Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1560285A FR3043252B1 (fr) | 2015-10-28 | 2015-10-28 | Procede de fabrication d’un substrat composite |
PCT/FR2016/052784 WO2017072446A1 (fr) | 2015-10-28 | 2016-10-26 | Procédé de fabrication d'un substrat composite |
Publications (1)
Publication Number | Publication Date |
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EP3369117A1 true EP3369117A1 (fr) | 2018-09-05 |
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ID=55862849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP16806229.7A Withdrawn EP3369117A1 (fr) | 2015-10-28 | 2016-10-26 | Procédé de fabrication d'un substrat composite |
Country Status (3)
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EP (1) | EP3369117A1 (fr) |
FR (1) | FR3043252B1 (fr) |
WO (1) | WO2017072446A1 (fr) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US8334451B2 (en) * | 2003-10-03 | 2012-12-18 | Ixys Corporation | Discrete and integrated photo voltaic solar cells |
FR3003087B1 (fr) * | 2013-03-05 | 2015-04-10 | Commissariat Energie Atomique | Procede de realisation d’un collage direct metallique conducteur |
FR3012674B1 (fr) * | 2013-10-29 | 2015-12-11 | Commissariat Energie Atomique | Substrat composite a base de silicium presentant des zones actives separees par des zones d'isolation electrique comportant un feuillard en carbure de silicium |
-
2015
- 2015-10-28 FR FR1560285A patent/FR3043252B1/fr not_active Expired - Fee Related
-
2016
- 2016-10-26 WO PCT/FR2016/052784 patent/WO2017072446A1/fr unknown
- 2016-10-26 EP EP16806229.7A patent/EP3369117A1/fr not_active Withdrawn
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Publication number | Publication date |
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WO2017072446A1 (fr) | 2017-05-04 |
FR3043252A1 (fr) | 2017-05-05 |
FR3043252B1 (fr) | 2019-07-19 |
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