EP3304284A4 - Packed data alignment plus compute instructions, processors, methods, and systems - Google Patents

Packed data alignment plus compute instructions, processors, methods, and systems Download PDF

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Publication number
EP3304284A4
EP3304284A4 EP16803946.9A EP16803946A EP3304284A4 EP 3304284 A4 EP3304284 A4 EP 3304284A4 EP 16803946 A EP16803946 A EP 16803946A EP 3304284 A4 EP3304284 A4 EP 3304284A4
Authority
EP
European Patent Office
Prior art keywords
processors
systems
methods
packed data
data alignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP16803946.9A
Other languages
German (de)
French (fr)
Other versions
EP3304284B1 (en
EP3304284A1 (en
Inventor
Edwin Jan Van Dalen
Alexander Augusteijn
Martinus C. WEZELENBURG
Steven Roos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP3304284A1 publication Critical patent/EP3304284A1/en
Publication of EP3304284A4 publication Critical patent/EP3304284A4/en
Application granted granted Critical
Publication of EP3304284B1 publication Critical patent/EP3304284B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
EP16803946.9A 2015-06-02 2016-05-09 Packed data alignment plus compute instructions, processors, methods, and systems Active EP3304284B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/728,693 US10001995B2 (en) 2015-06-02 2015-06-02 Packed data alignment plus compute instructions, processors, methods, and systems
PCT/US2016/031422 WO2016195921A1 (en) 2015-06-02 2016-05-09 Packed data alignment plus compute instructions, processors, methods, and systems

Publications (3)

Publication Number Publication Date
EP3304284A1 EP3304284A1 (en) 2018-04-11
EP3304284A4 true EP3304284A4 (en) 2019-03-20
EP3304284B1 EP3304284B1 (en) 2020-12-09

Family

ID=57441550

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16803946.9A Active EP3304284B1 (en) 2015-06-02 2016-05-09 Packed data alignment plus compute instructions, processors, methods, and systems

Country Status (7)

Country Link
US (2) US10001995B2 (en)
EP (1) EP3304284B1 (en)
JP (1) JP6814369B2 (en)
KR (2) KR102592056B1 (en)
CN (2) CN114816523A (en)
TW (1) TWI697835B (en)
WO (1) WO2016195921A1 (en)

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US10001995B2 (en) 2015-06-02 2018-06-19 Intel Corporation Packed data alignment plus compute instructions, processors, methods, and systems
US11169802B2 (en) * 2016-10-20 2021-11-09 Intel Corporation Systems, apparatuses, and methods for fused multiply add
EP3586228B1 (en) * 2017-02-23 2023-03-29 ARM Limited Element by vector operations in a data processing apparatus
EP3428792B1 (en) * 2017-07-10 2022-05-04 Arm Ltd Testing bit values inside vector elements
GB2564853B (en) * 2017-07-20 2021-09-08 Advanced Risc Mach Ltd Vector interleaving in a data processing apparatus
US10795677B2 (en) * 2017-09-29 2020-10-06 Intel Corporation Systems, apparatuses, and methods for multiplication, negation, and accumulation of vector packed signed values
US10691621B2 (en) 2018-04-12 2020-06-23 Sony Interactive Entertainment Inc. Data cache segregation for spectre mitigation
US10678540B2 (en) * 2018-05-08 2020-06-09 Arm Limited Arithmetic operation with shift
US11048509B2 (en) * 2018-06-05 2021-06-29 Qualcomm Incorporated Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
GB2589334B (en) * 2019-11-26 2022-01-05 Advanced Risc Mach Ltd Register-provided-opcode instruction

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US20140297994A1 (en) * 2013-03-30 2014-10-02 Edward T. Grochowski Processors, methods, and systems to implement partial register accesses with masked full register accesses

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US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US6446195B1 (en) * 2000-01-31 2002-09-03 Intel Corporation Dyadic operations instruction processor with configurable functional blocks
JP3779540B2 (en) * 2000-11-08 2006-05-31 株式会社ルネサステクノロジ SIMD operation method that can specify multiple registers
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US7818356B2 (en) 2001-10-29 2010-10-19 Intel Corporation Bitstream buffer manipulation with a SIMD merge instruction
US7373369B2 (en) 2003-06-05 2008-05-13 International Business Machines Corporation Advanced execution of extended floating-point add operations in a narrow dataflow
GB2409064B (en) * 2003-12-09 2006-09-13 Advanced Risc Mach Ltd A data processing apparatus and method for performing in parallel a data processing operation on data elements
US7328230B2 (en) * 2004-03-26 2008-02-05 Intel Corporation SIMD four-data element average instruction
US7257695B2 (en) * 2004-12-28 2007-08-14 Intel Corporation Register file regions for a processing system
GB2464292A (en) * 2008-10-08 2010-04-14 Advanced Risc Mach Ltd SIMD processor circuit for performing iterative SIMD multiply-accumulate operations
US9747105B2 (en) * 2009-12-17 2017-08-29 Intel Corporation Method and apparatus for performing a shift and exclusive or operation in a single instruction
US8667042B2 (en) * 2010-09-24 2014-03-04 Intel Corporation Functional unit for vector integer multiply add instruction
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US9489196B2 (en) * 2011-12-23 2016-11-08 Intel Corporation Multi-element instruction with different read and write masks
WO2013101124A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Packed data operation mask comparison processors, methods, systems, and instructions
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WO2013101232A1 (en) * 2011-12-30 2013-07-04 Intel Corporation Packed rotate processors, methods, systems, and instructions
US9213523B2 (en) * 2012-06-29 2015-12-15 Intel Corporation Double rounded combined floating-point multiply and add
US9152382B2 (en) * 2012-10-31 2015-10-06 Intel Corporation Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values
US9513906B2 (en) * 2013-01-23 2016-12-06 International Business Machines Corporation Vector checksum instruction
US9632781B2 (en) 2013-02-26 2017-04-25 Qualcomm Incorporated Vector register addressing and functions based on a scalar register data value
US20140281418A1 (en) * 2013-03-14 2014-09-18 Shihjong J. Kuo Multiple Data Element-To-Multiple Data Element Comparison Processors, Methods, Systems, and Instructions
US9329865B2 (en) * 2013-06-11 2016-05-03 Intel Corporation Context control and parameter passing within microcode based instruction routines
US9990202B2 (en) * 2013-06-28 2018-06-05 Intel Corporation Packed data element predication processors, methods, systems, and instructions
US9552205B2 (en) 2013-09-27 2017-01-24 Intel Corporation Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and instructions
US10001995B2 (en) 2015-06-02 2018-06-19 Intel Corporation Packed data alignment plus compute instructions, processors, methods, and systems

Patent Citations (2)

* Cited by examiner, † Cited by third party
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US6047372A (en) * 1996-12-02 2000-04-04 Compaq Computer Corp. Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot
US20140297994A1 (en) * 2013-03-30 2014-10-02 Edward T. Grochowski Processors, methods, and systems to implement partial register accesses with masked full register accesses

Also Published As

Publication number Publication date
CN114816523A (en) 2022-07-29
TWI697835B (en) 2020-07-01
US20190012172A1 (en) 2019-01-10
CN107667345A (en) 2018-02-06
JP2018516400A (en) 2018-06-21
US10001995B2 (en) 2018-06-19
KR102556033B1 (en) 2023-07-17
EP3304284B1 (en) 2020-12-09
WO2016195921A1 (en) 2016-12-08
CN107667345B (en) 2022-03-04
KR20180014690A (en) 2018-02-09
US20160357563A1 (en) 2016-12-08
KR102592056B1 (en) 2023-10-23
EP3304284A1 (en) 2018-04-11
KR20230109791A (en) 2023-07-20
JP6814369B2 (en) 2021-01-20
TW201710886A (en) 2017-03-16
US10936312B2 (en) 2021-03-02

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