EP3295569A1

EP3295569A1 - Multi-rate ldpc encoding and decoding with different code lengths using one multi-rate exponent table and one expansion factor

Info

Publication number: EP3295569A1
Application number: EP15722234.0A
Authority: EP
Inventors: Giacomo Cannalire; Christian Mazzucco
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2015-05-18
Filing date: 2015-05-18
Publication date: 2018-03-21
Also published as: WO2016184493A1; CN107592958B; CN107592958A

Abstract

Encoder and decoder devices for performing multi-rate and multi-length LDPC coding and decoding and methods thereof using only one stored expansion table with one corresponding expansion factor. An encoder device (200) for performing LDPC coding includes: an input (210) for receiving an information sequence (B1); an output (220) for providing an encoded sequence (B2); a memory (201) for storing exponent matrices (H_exp), wherein the exponent matrices (H_exp) are stored in a plurality of groups (203a, 203b, 203c), such that each group (203a, 203b, 203c) corresponds to one code rate, and wherein each group (203a, 203b, 203c) comprises a plurality of nested exponent matrices (H_exp), each nested exponent matrix (H_exp) within a particular group corresponding to one code word length for the code rate of the particular group, wherein common elements in different groups (203a, 203b, 203c) are stored once in the memory (201); and further comprising a processing unit (205) configured to extract an exponent matrix (H_exp) for a specific code rate (R) from a corresponding group (203a, 203b, 203c) and; an encoding unit (207) for encoding the information sequence (B1) based on the extracted parity-check exponent matrix (H_exp) to provide the encoded sequence (B2).

Description

MULTI-RATE LDPC ENCODING AND DECODING WITH DIFFERENT CODE LENGTHS USING ONE MULTI-RATE EXPONENT TABLE AND ONE EXPANSION FACTOR

TECHNICAL FI ELD

The present disclosure relates to digital communications using a communication channel and encoding/decoding devices, wherein the encoding device encodes an information sequence to be transmitted over the communication channel and the decoding device decodes a received sequence transmitted over the communication channel. In particular, the present invention relates to LDPC (Low Density Parity Check) block coding.

BACKGROUND

Fig. 1 shows a block diagram illustrating a digital communications system 100 including an encoder device 200 and a decoder device 300 according to an implementation form.

The input of channel encoder CH_ENC 200 is an information sequence B1 of k bits to which a redundancy sequence of r bits is added thereby producing an encoded sequence B2 of n bits. The channel code rate R is defined as the ratio between the information bits number k and the encoded bits number n, Vnus R = k/ n . The modulator MOD 103 transforms the encoded vector B2 into a modulated signal vector CHJ N which is in turn transmitted through a channel CH 101 . Since the channel CH 101 is usually subject to noisy disturbance NS, the channel output CH OUT may differ from the channel input CH IN. At the receiving end, the channel output CH_OUT is processed by the demodulator DEM 105 which performs the MOD inverse operation and produces some likelihood ratio. The channel decoder CH_DEC 300 uses the redundancy in the received sequence B3 to correct the error in the information sequence of the received sequence B3 and produces a decoded signal B4 which is an information signal estimate.

Encoder/decoder structures CH_ENC 200, CH_DEC 300 use Low Density Parity Check (LDPC) block codes. In the general formulation of the channel coding the block codes use a generator matrix G for the encoding operation. A binary parity-check matrix H is used for the decoding operation. For a block code with information sequence of k bits, a code word of n bits and redundancy (parity) sequence of r=(n-k) bits, the generator matrix G has kxn dimensions, and the binary parity-check matrix H has rxn=(n-k)xn dimensions. These two matrixes enjoy the orthogonal property, which states that for any matrix Gkxn with k linearly independent rows there exists a matrix -«_n with r=(n-k) linearly independent rows such that any row of Gkxn is orthogonal to the rows of - _rxnsuch that the following equation is satisfied:

^Gto» -^HL ^{= 0} (1 )

The encoding operation is performed by means of the multiplication between the information sequence Bl_lxk and the code generator matrix G^ . The result, of such multiplication, is the encoded output sequence B2_lxn as follows:

^B2lxn = ⁵¹ \xk ^{- G}kxn (2)

At the receiving side, due to the orthogonal property between matrixes and H_rxn , the following equation should be satisfied:

where B_n ^T _xl is the decoded received sequence which comprises the information signal estimate B4_lxk ; if the above equation is verified the information signal estimate B4_lxlc is correct.

Once the code generator matrix is built, it is possible to obtain the binary parity-check matrix H_rxn and vice versa.

There are several design techniques for generating a binary parity-check matrix H_rxn , shortly parity-check matrix, of an LDPC code. The most used generating technique in LDPC code design is the semi-random technique. The binary parity-check matrix H_rxn is built combining in a certain manner three matrixes: the parity-check exponent matrix H^exp , which is a non-binary matrix, for a specific rate R, the seed matrix for the rate R and the spreading matrix. The non-binary parity-check exponent matrix H^exp , also shortly called parity-check exponent matrix or exponent matrix, is multiplied, element by element, by the binary seed matrix and the result is in turn expanded, via the spreading matrix, to the parity- check matrix H_rxn, hereby also called expanded matrix H™. The spreading matrix is a square binary matrix of weight one and dimension Z₀xZ₀ , where Z₀ is the spreading factor.

An exponent matrix is a conventional matrix representing a block structured matrix. The elements of the exponent matrix are expanded in square matrixes of dimension Z₀xZ₀ by applying the rules known from the art. The same "expansion" rules can be applied using for obtaining the exponent matrix H^exp . The elements in the parity-check exponent matrix H^exp are permutation matrixes of the identity matrix (with weight equal to "1 " for each row and for each column) with dimensions Z₀xZ₀. The value of the exponent matrix element indicates the cyclic shift to the right of the identity matrix.

According to some known implementations of LDPC codes, a parity-check exponent matrix dedicated for each code rate, is defined (see I EEE Standard 802.16e: "Air Interface for Fixed and Mobile Broadband Wireless Access Systems" of February 28, 2006). The parity- check exponent matrix H^exp is built for the largest code length and shorter LDPC code words are obtained from the from the parity-check exponent matrix using a conversion formula; in these implementations H^exp is also known as base model parity-check exponent matrix. The exponent values are comprised between 0 and (Z₀ -1) .

To illustrate coding techniques mentioned above, the following three LDPC codes are considered: A first one with rate ?_j = 1/2 , the largest information sequence k_x = 6480 and highest spreading factor Z₀ = 108 ; a second one with rate R₂ = 5/6 , the largest information sequence k₂ = 10800 and highest spreading factor Z₀ = 108 ; and a third one with rate ?₃ = 9/10 , the largest information sequence k = 11664 and highest spreading factor Z₀ = 108.

The largest LDPC code word length is computed from the largest information sequence and from the code rate as follows: η_χ = k l R = 6480 - (2/ 1) = 12960

n₂ = k₂ /R₂ = 10800- (6/5) = 12960 «. = k₃IR₃ =11664- (10/9) = 12960

The column number n_b of the block structured base model exponent matrix H^exp is computed from the largest code word length n₀ = n_x - n₂ - n₃ and the highest spreading factor Z_n as follows: n_b =n₀/Z₀ =12960/108 = 120.

The block structured information sequences k_bl,k_b2,k_b3 are computed from the largest information sequences k₁,k₂,k₃ and the highest spreading factor Z₀ as follows: k_hl = k Z₀ =6480/108 = 60

k_b2 =k₂/Z_a =10800/108 = 100

k_b3 = k₃/Z₀ =11664/108 = 108

The block structured parity sequences (base model exponent matrix rows) r_bl,r_b2,r_b3 are computed from the column number n_b and block info sequences k_bl,k_b2,k_b3 as follows: r_A1 =w, -h, =120-60 = 60

r_b2 =n_b -^ =120-100 = 20

M =n_h -k_M =120-108 = 12.

Tables 1 , 2 and 3 illustrate the base model LDPC code and shorter LDPC codes according to the IEEE standard 802.16e. Table 1 applies the rate Ri = 1/2, Table 2 applies the rate R₂=5/6 and Table 3 applies the rate R₃=9/10.

Table 1 : Base model LDPC code and shorter LDPC codes according to IEEE Standard 802.16e with rate = 1/2 Z _j spread n_codeword k_info rjparity

108 12960 10800 2160

81 9720 8100 1620

54 6480 5400 1080

Table 2: Base model LDPC code and shorter LDPC codes according to IEEE Standard 802.16e with rate ?₀ = 5/ 6

Table 3: Base model LDPC code and shorter LDPC codes according to IEEE Standard 802.16e with rate = 9/10

Using one dedicated parity-check exponent matrix for each code rate has the drawback of high hardware requirements for storage of all exponent matrixes. In addition, the conversion from base model exponent matrix to shorter LDPC code words has the drawbacks of high digital signal processing requirements and high program memory requirements.

The LDPC codes suggested by the document EP 2 148 445 A1 : "Generating exponent matrices for LDPC codes" use an exponent table built so as to include parity-check exponent matrices dedicated for all coderates and for the largest spreading factor. For each code rate the parity-check exponent matrix in the exponent table corresponds to the longest codeword.

This model uses a variable spreading factor, wherein each spreading factor is linked to a respective codeword length. Shorter codewords for a given code rate are obtained from the parity-check exponent matrix for that code rate and the spreading factor for the respective codeword. As for the method described with reference to the IEEE Standard 802.16e, a conversion formula is used for obtaining from the parity-check exponent matrix shorter LDPC codewords. Table 4 illustrates the base model LDPC code and shorter LDPC codes according to EP 2 148 445 A1. The table 4 corresponds to a multi-rate exponent table which has three different rates 1/2, 5/6 and 9/10 and uses three spreading factors 108, 81 and 54. H^exp _base R _ rate Z spread n_codeword k_info rjparity

(60,120) 1/2 108 12960 6480 6480

81 9720 4860 4860

54 6480 3240 3240

(20,120) 5/6 108 12960 10800 2160

81 9720 8100 1620

54 6480 5400 1080

(12,120) 9/10 108 12960 11664 1296

81 9720 8748 972

54 6480 5832 648

Table 4: Base model LDPC code and shorter LDPC codes according to EP 2 148 445 A1

This method has the drawbacks of high digital signal processing requirements and high program memory requirements.

The LDPC coding method suggested by the document EP 2 21 1 470 A1 "Generating an exponent table for coding and decoding LDPC codewords of different lengths" uses a exponent matrix dedicated for each code rate. Parity-check matrixes for a specific codelength are extracted from a multi-length exponent table. In particular, shorter codewords are not achieved starting from parity-check exponent matrix built for the largest code length using a conversion formula, but are achieved by means of an opportune reduction of rows and columns of the base model exponent matrix.

Tables 5, 6 and 7 describe the base model LDPC code and shorter LDPC codes according to EP 2 21 1 470 A1 . In table 5 the rate is used, In table 6 the rate Ri=5/6 is used, In table 7 the rate is used,

Table 5: Base model LDPC code and shorter LDPC codes according to EP 2 21 1 470 A1 with rate R_j = 1 /2 H^exp _base Z spread n_codeword k_in†o rjparity

(20,120) 108 12960 10800 2160

(15, 90) 108 9720 8100 1620

(10, 60) 108 6480 5400 1080

Table 6: Base model LDPC code and shorter LDPC codes according to EP 2 21 1 470 A1 with rate R, = 5/6

Table 7: Base model LDPC code and shorter LDPC codes according to EP 2 211 470 A1 with rate R_i = 9/10 .

The aforementioned method has the drawback that exponent matrixes for each code rate have to be stored in the memory, thereby demanding high hardware requirements.

There is a need to improve LDPC coding techniques in digital communications with respect to computational complexity and memory requirements.

SUMMARY

It is the object of the invention to provide a concept for improving the LDPC coding efficiency in digital communications systems.

This object is achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures. In order to describe the invention in detail, the following terms, abbreviations and notations will be used:

LDPC: Low Density Parity Check

exponent matrix

R: code rate H: binary parity check matrix

Z₀ : spreading factor

According to a first aspect, the invention relates to an encoder device comprising: an input for receiving an information sequence; an output for providing an encoded sequence; a memory for storing exponent matrices, wherein the exponent matrices are stored in a plurality of groups, such that each group corresponds to one code rate, and wherein each group comprises a plurality of nested exponent matrices, each nested exponent matrix within a particular group corresponding to one code word length for the code rate of the particular group, wherein common elements of different groups are stored once in the memory; and further comprising a processing unit configured to extract an exponent matrix for a specific code rate from a corresponding group; and

an encoding unit for encoding the information sequence based on the parity-check matrix to provide the encoded sequence.

Such an encoder device allows reducing the data memory requirements because the encoder device uses an efficient storing of the exponent matrices in a plurality of groups, in particular due to the nested manner of storing the exponent matrices. In a first possible implementation form of the encoder device according to the first aspect, the exponent matrices are stored in an exponent table, wherein the exponent table is step- shaped, such that each step of the exponent table includes exponent matrices corresponding to one code rate, and the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices for each step, each nested exponent matrix of the plurality of nested exponent matrices within a particular step corresponding to one code word length for the code rate of the particular step.

By using such an exponent table having a "step shape", a multi-rate exponent table may be realized. By using such an exponent table having a "nested shape", a multi-length exponent table may be realized. Each step may correspond to one code rate and each nested matrix may correspond to one code word length to that code rate. As an example, using an exponent table is an easily way of implementing the data arrangement described above with reference to the first aspect, which allows to reduce data memory requirements. In a second possible implementation form of the encoder device according to the first implementation form of the first aspect the exponent table comprises block codes implementing a plurality of code rates, such as 1 /2, 5/6, 9/10 and a plurality of code word lengths, such as 120, 90, 60.

Such code rate and code word lengths are parameters that can be used for implementing LDPC codes. Such encoders may use a constant spreading factor. An advantage of the data structure implemented in the encoder device is that the program memory may be reduced. The working word length may remain unchanged and allows operating both a digital signal processing reduction (arithmetic operation reduction) and a program memory requirement reduction.

In a third possible implementation form of the encoder device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect, the extracting unit is configured to extract the exponent matrix (H_eXp) based on a specific code rate . and a specific codeword length n_bj , the number of columns and the number of rows of the exponent matrix (H_ex_P) to be extracted being respectively given by the formulas j + ¹ = ^R, ·"¾, +! and ¾ = n_bJ ^■ (1 - R, ) . This provides the advantage that such encoders do not have to apply any conversion formula to obtain shorter LDPC codewords from the exponent matrix. Hence, these encoders allow reducing the data memory requirements because they use only one base model exponent table with variable code rates (for all code rates) and variable code words (for all code words). Since it is not necessary anymore to calculate conversion formulas, the proposed scheme has lower digital signal processing requirements and lower hardware requirements for storing the exponent matrices.

In a fourth possible implementation form of the encoder device according to the first aspect as such or according to any of the preceding implementation forms of the first aspect each exponent matrix in each group comprises a random part and a deterministic part, the deterministic part of an exponent matrix for a particular code length being at least partially comprised in at least one random matrix corresponding to a different code length.

In this manner, the deterministic part of each exponent matrix can be at least partially comprised in at least some of the remaining exponent matrices. Therefore, memory use can be optimized. I n a fifth possible implementation form of the encoder device according to the fourth implementation form of the first aspect, the random part is a random matrix and the deterministic part is the first column of a deterministic matrix, and the processing unit is adapted to build a complete exponent matrix by using the random part and the deterministic matrix, the deterministic matrix being obtained by combining the deterministic part with a matrix with a dual diagonal structure, wherein block codes for a particular code word length and a particular code rate are built based on the complete exponent matrix. According to the implementation above, the deterministic matrix is built when block codes for a particular code word length and a particular code rate are built. In this manner, the exponent table does not need to store the complete deterministic matrix but only part of it, such as the first column of the deterministic matrix. Storing only the first column of the deterministic matrix in the exponent table allows reducing the computational complexity for LDPC block encoder.

I n a sixth possible implementation form of the encoder device according to the fifth implementation form of the first aspect the extracting unit is further adapted to build a block code of a higher code rate by a reduction of a row number of the exponent table for the complete exponent matrices.

In comparison to the prior art, encoders and decoders according to the disclosure allow to reduce the data memory requirements because they use only one base model exponent table with variable code rates (for all code rates) and variable code words (for all code words). The exponent table only stores the random matrix and part (the 1 ^st column) of the deterministic matrix forming the exponent matrix.

I n a seventh possible implementation form of the encoder device according to the fifth or the sixth implementation form of the first aspect for a given code rate, the extracting unit is further adapted to build a block code of a shorter code word for the complete exponent matrices by a reduction of a column number, and proportional reduction of a row number of the exponent table.

Such an encoder device allows reducing the data memory requirements because the encoder device uses only one base model exponent table with variable code rates (for all code rates) and variable code words (for all code words). I n an eighth possible implementation form of the encoder device according to any of the preceding implementation forms of the first aspect a constant spreading factor is used for all code words and all code rates. This provides the advantage that a program memory requirement may be reduced because the working word length remains unchanged and a digital signal processing may be reduced, i.e. a number of arithmetic operations may be reduced, because a constant value is used for the spreading factor. According to a second aspect, the invention relates to a decoder device for performing LDPC coding, comprising: an input for receiving an encoded sequence; an output for providing an information sequence estimate; a memory for storing exponent matrices; wherein the exponent matrices are stored in a plurality of groups, such that each group corresponds to one code rate, and wherein each group comprises a plurality of nested exponent matrices, each nested exponent matrix within a particular group corresponding to one code word length for the code rate of the particular group, and common elements of different groups being stored once in the memory, and further comprising: a processing unit configured to extract an exponent matrix for a specific code rate from a corresponding group and configured to generate a binary parity-check matrix starting from the extracted exponent matrix for the specific code rate; and a decoding unit for decoding the encoded sequence based on the binary parity-check matrix to provide the information sequence estimate.

Such a decoder device allows reducing the data memory requirements because the decoder device uses an efficient storing of nested exponent matrices in a plurality of groups.

I n a first possible implementation form of the decoder device according to the second aspect, the exponent matrices are stored in an exponent table, wherein the exponent table is step-shaped, such that each step of the exponent table includes exponent matrices corresponding to one code rate, and the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices for each step, each nested exponent matrix of the plurality of nested exponent matrices within a particular step corresponding to one code word length for the code rate of the particular step. By using such an exponent table having a "step shape", a multi-rate exponent table may be realized. By using such an exponent table having a "nested shape", a multi-length exponent table may be realized . Each step may correspond to one code rate and each nested matrix may correspond to one code word length to that code rate. As an example, using an exponent table is an easy way of implementing the data arrangement described above with reference to the second aspect, which allows to reduce data memory requirements. In a second possible implementation form of the decoder device according to the first implementation form of the second aspect the exponent table comprises block codes implementing a plurality of code rates, such as 1 /2, 5/6, 9/10 and a plurality of code word lengths, such as 120, 90, 60. Such code rate and code word lengths are parameters that can be used for implementing LDPC codes. Such encoders may use a constant spreading factor. An advantage of the data structure implemented in the encoder device is that the program memory may be reduced. The working word length may remain unchanged and allows operating both a digital signal processing reduction (arithmetic operation reduction) and a program memory requirement reduction.

In a third possible implementation form of the decoder device according to the second aspect as such or according to any of the preceding implementation forms of the second aspect, the extracting unit is configured to extract the exponent matrix (H_ex ) based on a specific code rate R_i and a specific code word length n_bj , the number of columns and the number of rows of the exponent matrix (H_ex_P) to be extracted being respectively given by the formulas k_bi] + 1 = R_t -n_b] + \ and r_Uj = n_bJ · (1 - R, ) .

This provides the advantage that such decoders do not have to apply any conversion formula to obtain shorter LDPC code words from the exponent matrix. Hence, these decoders allow to reduce the data memory requirements because they use only one base model exponent table with variable code rates (for all code rates) and variable code words (for all code words). Since it is not necessary anymore to calculate conversion formulas, the proposed scheme has lower digital signal processing requirements and lower hardware requirements for storing the exponent matrices.

In a fourth possible implementation form of the decoder device according to the second aspect as such or according to any of the preceding implementation forms of the second aspect each exponent matrix in each group comprises a random part and a deterministic part, the deterministic part of an exponent matrix for a particular code length being at least partially comprised in at least one random matrix corresponding to a different code length. I n this manner, the deterministic part of each exponent matrix can be at least partially comprised in at least some of the remaining exponent matrices. Therefore, memory use can be optimized.

I n a fifth possible implementation form of the decoder device according to the fourth implementation form of the second aspect, the random part is a random matrix and the deterministic part is the first column of a deterministic matrix, and the processing unit is adapted to build a complete exponent matrix by using the random part and the deterministic matrix, the deterministic matrix being obtained by combining the deterministic part with a matrix with a dual diagonal structure, wherein block codes for a particular code word length and a particular code word rate are built based on the complete exponent matrix.

According to the implementation above, the deterministic matrix is build when block codes for a particular code word length and a particular code rate are built. In this manner, the exponent table does not need to store the complete deterministic matrix but only part of it, such as the first column of the deterministic matrix. Storing only the first column of the deterministic matrix in the exponent table allows reducing the computational complexity for LDPC block encoder.

I n a sixth possible implementation form of the encoder device according to the fifth implementation form of the second aspect the extracting unit is further adapted to build a block code of a higher code rate by a reduction of a row number of the exponent table for the complete exponent matrices.

I n a seventh possible implementation form of the decoder device according to the fifth or sixth implementation form of the second aspect for a given code rate, the extracting unit is further adapted to build a block code of a shorter code word for the complete exponent matrices by a reduction of a column number, and proportional reduction of a row number of the exponent table. Such a decoder device allows reducing the data memory requirements because the decoder device uses only one base model exponent table with variable code rates (for all code rates) and variable code words (for all code words). I n an eighth possible implementation form of the decoder device according to any of the preceding implementation forms of the second aspect a constant spreading factor is used for all code words and all code rates.

This provides the advantage that a program memory requirement may be reduced because the working word length remains unchanged and a digital signal processing may be reduced, i.e. a number of arithmetic operations may be reduced, because a constant value is used for the spreading factor.

According to a third aspect, the invention relates to a method for LDPC encoding, comprising: receiving an information sequence; extracting from one of a plurality of groups an exponent matrix for a specific code rate among a plurality of exponent matrices, wherein the plurality of exponent matrices is stored in the plurality of groups, such that each group corresponds to one code rate, and the exponent matrices in each group are nested, each nested exponent matrix within a particular group corresponding to one code word length for the code rate of the particular group, wherein common elements of different groups are stored once; and providing an encoded sequence based on the extracted exponent matrix.

Such an LDPC encoding method allows reducing the data memory requirements because the encoding uses an efficient storing of the exponent matrices in a plurality of groups, in particular due to the nested manner of storing the exponent matrices.

I n a first possible implementation form of the method according to the third aspect, the method comprises: using a constant spreading factor for all code words and all code rates. This provides the advantage that a program memory requirement may be reduced because the working word length remains unchanged and a digital signal processing may be reduced, i.e. a number of arithmetic operations may be reduced, because a constant is used for the spreading factor. I n a second possible implementation form of the method according to the third aspect as such or according to the first implementation form of the third aspect, the method comprises: storing the exponent matrices in an exponent table, wherein the exponent table is step- shaped, such that each step of the exponent table includes exponent matrices corresponding to one code rate, and the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices for each step, each nested exponent matrix of the plurality of nested exponent matrices within a particular step corresponding to one code word length for the code rate of the particular step.

By using such an exponent table having a "step shape", a multi-rate exponent table may be realized. By using such an exponent table having a "nested shape", a multi-length exponent table may be realized . Each step may correspond to one code rate and each nested matrix may correspond to one code word length to that code rate.

According to a fourth aspect, the invention relates to a method for LDPC decoding, comprising: receiving an encoded sequence; extracting from one of a plurality of groups an exponent matrix for a specific code rate among a plurality of exponent matrices, wherein the plurality of exponent matrices is stored in a plurality of groups, such that each group corresponds to one code rate, and the exponent matrices in each group are nested, each nested exponent matrix within a particular group corresponding to one code word length for the code rate of the particular group, and wherein common elements of different groups are stored once; generating a binary parity-check matrix starting from the extracted exponent matrix for the specific code rate, and decoding the encoded sequence based on the extracted exponent matrix to provide an information sequence estimate.

Such LDPC decoding method allows reducing the data memory requirements because the decoding uses an efficient storing of nested exponent matrices in a plurality of groups.

I n a first possible implementation form of the method according to the fourth aspect, the method comprises: using a constant spreading factor for all code words and all code rates. This provides the advantage that a program memory requirement may be reduced because the working word length remains unchanged and a digital signal processing may be reduced, i.e. a number of arithmetic operations may be reduced, because a constant is used for the spreading factor. I n a second possible implementation form of the method according to the fourth aspect as such or according to the first implementation form of the third aspect, the method comprises: storing the exponent matrices in an exponent table, wherein the exponent table is step- shaped, such that each step of the exponent table includes exponent matrices corresponding to one code rate, and the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices for each step, each nested exponent matrix of the plurality of nested exponent matrices within a particular step corresponding to one code word length for the code rate of the particular step.

By using such an exponent table having a "step shape", a multi-rate exponent table may be realized. By using such an exponent table having a "nested shape", a multi-length exponent table may be realized. Each step may correspond to one code rate and each nested matrix may correspond to one code word length to that code rate. The exponent table according to the disclosure has both a "step shape", which corresponds to a "multi-rate exponent table", and a "nested shape", which corresponds to a "multi-length exponent table". The exponent table according to the disclosure has a "step shape" and inside each step has more nested exponent matrixes; each step corresponds to one code rate and each nested matrix corresponds to one code word length to that code rate.

The data structure used for storing the exponent matrices according to the disclosure allows to design encoders and decoders and respective encoding and decoding methods, which do not apply conversion formulas for obtaining different code word lengths. Besides in comparison to the prior art, encoders and decoders using the data structure according to the disclosure, such as one base model exponent table with variable code rates (for all code rates) and variable code words (for all code words), allow to reduce the data memory requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the invention will be described with respect to the following figures, in which:

Fig. 1 shows a block diagram illustrating a digital communications system 100 including an encoder device 200 and a decoder device 300 according to an implementation form;

Fig. 2 shows a block diagram illustrating an encoder device 200 for performing LDPC encoding according to an implementation form; Fig. 3 shows a block diagram illustrating a decoder device 300 for performing LDPC decoding according to an implementation form;

Fig. 4 shows a schematic diagram illustrating a method 400 for LDPC encoding according to an implementation form;

Fig. 5 shows a schematic diagram illustrating a method 500 for LDPC decoding according to an implementation form; Fig. 6a, b, c show an exemplary exponent parity-check table for construction of 9 LDPC block codes with 3 code rates R1 =1/2, R2=5/6, R3=9/10 and 3 block code word lengths nb1 =120, nb2=90, nb3=60 with spreading factor Zf=108 according to an implementation form; Fig. 7 shows an exemplary exponent parity-check matrix for LDPC block codes with code rate R=9/10 and code word length nb3=60 with spreading factor Zf=108 extracted from the exponent parity-check table of Fig. 6a, b, c according to a first example;

Fig. 8 shows an exemplary exponent parity-check matrix for LDPC block codes with code rate R=5/6 and code word length nb3=60 with spreading factor Zf=108 extracted from the exponent parity-check table of Fig. 6a, b, c according to a second example; and

Fig. 9 shows an exemplary exponent parity-check matrix for LDPC block codes with code rate R=1/2 and code word length nb3=60 with spreading factor Zf=108 extracted from the exponent parity-check table of Fig. 6a, b, c according to a third example.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Fig. 2 shows a block diagram illustrating an encoder device 200 for performing LDPC encoding according to an implementation form. The encoder device 200 includes an input 210, an output 220, a memory 201 , a processing unit 205 and an encoding unit 207. The input 210 is used for receiving an information sequence B1 , e.g. as described above with respect to Fig. 1. The output 220 is used for providing an encoded sequence B2. The memory 201 is used for storing exponent matrices Hexp. The exponent matrices are arranged in a data structure, according to which the exponent matrices H_ex are stored in a plurality of groups 203a, 203b, 203c, such that each group 203a, 203b, 203c corresponds to one code rate, and wherein each group 203a, 203b, 203c comprises a plurality of nested exponent matrices H_exp. Each nested exponent matrix Hexp within a particular group corresponds to one code word length for the code rate of the particular group, wherein common elements of different groups 203a, 203b, 203c are stored once in the memory (201 ) , e.g. as illustrated below with respect to Figs. 6a, b, c. In the figs. 6a,b,c is shown an exponent parity-check table. In this table are stored 9 exponent parity- check matrices, which correspond to 9 LDPC block codes.

Each exponent matrix is a set composed by a random matrix and a deterministic part, wherein the latter may be the first column of the deterministic matrix. Each extracted exponent matrix includes all the deterministic parts of the nested subset of exponent matrices as random parts. Further, the plurality of groups have a non-empty intersection and elements belonging to the intersection of at least two of the plurality of groups 203a, 203b, 203c are consequently written only once in the memory 201 . In other words, the device and method according to figures 2 and 4 are based on the observation that exponent matrices corresponding to different code word length and different code rates may have common elements. The encoder device 200 and the decoder device 400, as well as the corresponding encoding and decoding methods, are thus configured to store the exponent matrices using a data structure, which allow writing the elements common to at least two different groups only once in the memory. This allows a reduction of the data memory requirements for the encoder device 200. An exponent matrix corresponding to a predefined code rate and code word length may be extracted from the data structure defined above according to the rules described in the following.

A possible practical implementation of the above descried data structure can be realized by storing nested exponent matrices in an exponent table having a step-like structure, wherein each step corresponds to a group for a particular code rate, as discussed in the following.

The processing unit 205 is configured to extract an exponent matrix H_ex_P for a specific code rate R from a corresponding group 203a, 203b, 203c. The encoding unit 207 is used for encoding the information sequence B1 based on the extracted parity-check matrix exponent matrix H_ex_P to provide the encoded sequence B2. The encoded sequence B2 may then be transformed into a modulated signal vector, which is in turn transmitted through a channel to a decoding device. The exponent matrices Η_βχ stored in the memory 201 may be organized in an exponent table. Accordingly, the exponent table will be stored in the memory 201. The exponent table may be step-shaped, such that each step of the exponent table includes exponent matrices Hexp corresponding to one code rate. In this realization a group 203a, 203b, 203c as defined before corresponds to a step in the in the exponent table. The exponent table may be nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices H_ex for each step, each nested exponent matrix H_exp of the plurality of nested exponent matrices H_ex_P within a particular step corresponding to one code word length for the code rate of the particular step. In this particular implementation, each of the plurality of groups for a given code rate R, is realized by one step in the exponent table. The exponent matrices nested in a particular group for a code rate R correspond to the nested exponent matrices in the steps of the exponent table. Each of the steps on the exponent table, corresponding to a particular code rate R, will also include elements of at least one step corresponding to a different code rate R'. These elements will appear only once in the exponent table and thus will be written only once in the memory.

A reduction of a row number of the exponent table may provide a block code of a higher code rate for the complete exponent matrices including both the random part and the deterministic part. It has to be noted here, that a reduction of the row number of the exponent table as given, for instance in figures 6a, 6b, 6c, causes a reduction of the deterministic matrix built using by the deterministic part of the exponent matrix and a dual- diagonal matrix. The reduction of the deterministic matrix has to be considered and compensated for when building the complete exponent matrix. The examples described with reference to figures 6 ff. are designed for implementing 3 code rates and 3 code lengths. However, the present invention can be extended to systems implementing a different number of code rates and code lengths, for example more or less than 3 code rates and more or less than 3 code lengths. In this case the elements of the exponent table, including the deterministic part have to be designed so as to support the chosen number of code rates and the chosen number of code lengths. In particular implementations, the number of code rates may not be equal to the number of code words. In the case of 15 codes, for example, the exponent table will have 15 columns and 15 rows, which will generate 3 different groups and 5 different code word lengths, or 5 different groups and 3 different code word lengths.

A reduction of a column number of the exponent table may provide a block code of a shorter code word for the complete exponent matrices including both the random part and the deterministic part as described in the following example. Upon reducing the number of columns, a proportional reduction of the number of rows may also be performed in order to keep the code rate unchanged. Once the extracted exponent matrix is completed by the bi-diagonal matrix added to the first column of the deterministic part, a reduction of the rows number leads to an increase of the code rate. In this case the bi-diagonal matrix has to be re-dimensioned accordingly, for example according to the following relationships: (60,120)-»R=1/2; (20,120)^R=5/6; (12,120)-»R=9/10, where the numbers in parenthesis indicate the number of rows and the number of columns of the complete exponent matrix, respectively. Also, for a fixed code rate, a reduction of columns with a proportional code rate reduction of rows gives LDPC codes with shorter code words. This means that, for a given code rate corresponding to a group, a different nested matrix is used. For example starting from matrix dimensions (20,120) with R = 5/6, if X are the removed columns Y = (1 - R)^■ X will be the removed rows then for X = 30 follows the matrix dimensions (15, 90). The exponent table may include block codes with at least one of the code rates: 1/2, 5/6, 9/10 and/or at least one of the code word lengths: 120, 90, 60, e.g. as illustrated below with respect to Figures 6a, b, c. A size of the extracted exponent matrix H_ex may be determined based on the formulas k_biJ + 1 = R_; -n_bj +\ and r_bij = n_bj · (1 - R_; ) , where R_t is a code rate and n_bJ is a code word length. The formulas above allow to obtain, based on the code rate R_t and the code word length n_bj , the number of columns and rows of the exponent matrix H_exp. The number of columns (k_blJ. + 1) and the number of rows (r_blJ ) obtained starting from the particular code rate and code word length allows identifying the element set of the exponent table which must be extracted.

The LDPC block codes, built with semi-random technique, have an exponent parity check matrix composed by two sub-matrices: the first one is a random matrix and the second one is a deterministic matrix. In the present disclosure, reference is made to exponent matrixes Hexp stored in the memory of an encoder/decoder. The stored exponent matrices according to an implementation include a random matrix and at least part of the deterministic matrix, for instance the first column of a deterministic matrix. For example, each exponent matrix Hexp in each group may include a random part and a deterministic part. The random part may be a random matrix and the deterministic part may be the first column of a deterministic matrix, wherein the deterministic part of each exponent matrix in a particular group may be at least partially included in at least some of the exponent matrices in one or more different groups. The exponent matrices stored in the memory can also be indicated as incomplete exponent matrices. The complete exponent matrices can be built by adding a bi-diagonal matrix to the incomplete exponent matrix as described in detail below.

The block codes for a particular code word length and a particular code rate may be built by using the random part and the deterministic matrix. Specifically, the processing unit 205, 305 may be adapted to build a complete exponent matrix by using the random part and the deterministic matrix, wherein the deterministic matrix may be obtained by combining the deterministic part with a matrix with a dual diagonal structure. Block codes for a particular code word length and a particular code rate are built based on the so obtained complete exponent matrix. The LDPC code design is determined by both the exponent table and the spreading factor. In this disclosure the exponent table is designed so as to allow the use of a constant spreading factor for all the code words (variable code words) for all the code rates (variable code rates). Since the spreading factor is constant, the working word length remains unchanged and allows to operate a digital signal processing reduction (arithmetic operation reduction), a program memory requirement reduction and a data memory requirements.

Using a constant spreading factor the encoders and decoders according to the disclosure as described hereinafter and the corresponding methods provide advantages over solutions using a plurality of spreading factors, such as digital signal processing reduction and program memory requirement reduction.

Besides, encoders and decoders according to the disclosure allow to reduce the data memory requirements because they use only one base model exponent table for all code rates (variable code rates) and for all code words (variable code words). The exponent table according to the disclosure has both a "step shape", which corresponds to a "multi-rate exponent table", and a "nested shape", which corresponds to a "multi-length exponent table". The exponent table according to the disclosure has a "step shape" and inside each step it has more nested exponent matrices; each step corresponds to one code rate and each nested matrix corresponds to one code word length for that code rate.

Such a "nested and a step-wise table" cannot be implemented in the base model of the exponent matrix described for instance in IEEE 802.16e. Indeed, the exponent matrix of said LDPC code base model is for each code rate and uses shorter spreading factors to realize LDPC Codes with shorter code words.

According to some prior art methods, such as those described in EP 2 148 445 A1 a "step- shape" exponent table is used for realizing several code rates. Such method, however, uses a plurality of spreading factors for realizing LDPC codes with shorter code words.

Other methods instead, such as the method described in EP 2 21 1 470 A1 uses a "nested- shape" exponent table for realizing LDPC codes with shorter code words. Such methods, however, rely on the use of a constant spreading factor. Further, according to this methods each exponent table is dedicated only to one code rate.

In the following, methods and devices using block codes are described. Examples of such block codes are given in Figures 6a, 6b and 6c described below. Further, methods and devices using a constant spreading factor are further described. This allows reducing program memory requirements. Since such methods and devices allow to carry-out the LDPC block codes with shorter code word, there is no need for implementing conversion formulas for converting high spreading factors (long LDPC code word) to low spreading factors (short LDPC code word).

An opportune pre-processing (off-line), such as the above described pre-processing, may be performed on the exponent table according to the disclosure to satisfy the conditions on the deterministic matrix (only two elements of the first column are involved) to minimize the hardware complexity, for instance, of the LDPC block encoder. The exponent parity-check table obtained starting from an exemplary exponent table according to the disclosure is shown in the following table:

Table 8: Base model LDPC code and shorter LDPC codes according to the disclosure

The exponent parity-check matrices in table 8 are block structured matrices; the exemplary table 8 summarizes 9 LDPC block codes with 3 code rates {R₁ = \I2,R₂ = 5/ 6, ?₃ = 9/ 10

) and 3 block code word lengths {n_bl = \20,n_b2 = 90,«_ω = 60). The binary code word lengths are computed as follows:

"l = ¾ ^' = 120 ^•108 = : 12960

n₂ = ⁿb2 ^{■ Z}f = 90 · 108 = 9720

n = ⁿb3 ^Zf = 60 · 108 = 6480 The construction of the exponent parity-check table will be shown in the following with reference to figures 6a, b, c for 9 LDPC block codes with 3 code rates and 3 code words according to table 8.

Fig. 3 shows a block diagram illustrating a decoder device 300 for performing LDPC decoding according to an implementation form.

The decoder device 300 includes an input 310, an output 320, a memory 301 , a processing unit 305 and a decoding unit 307. The input 310 is used for receiving an encoded sequence B3. The encoded sequence may be obtained by demodulating a modulated encoded sequence received from a decoder over a transmission channel. The output 320 is used for providing an information sequence estimate B4. The memory 301 is used for storing exponent matrices H_ex . The exponent matrices H_ex_P are stored in a plurality of groups 303a, 303b, 303c, such that each group (303a, 303b, 303c) corresponds to one code rate, and wherein each group 303a, 303b, 303c comprises a plurality of exponent matrices H_exp, each nested exponent matrix H_ex_P within a particular group 303a, 303b, 303c corresponding to one code word length for the code rate of the particular group, and common elements in different groups 303a, 303b, 303c are stored once in the memory (301 ). The above described group structure can be realized by building an exponent table with a step structure, e.g. as illustrated below with respect to Figures 6a, b, c. The processing unit 305 is configured to extract an exponent matrix H_exp for a specific code rate R from a corresponding group 303a, 303b, 303c and configured to generate a binary parity-check matrix H starting from the extracted exponent matrix H_exp for the specific code rate R, e.g. as illustrated below with respect to Figures 6a, b, c. The decoding unit 307 is used for decoding the encoded sequence B3 based on the binary parity-check matrix H to provide the information sequence estimate B4.

The exponent matrices H_ex_P may be stored in an exponent table. The exponent table may be step-shaped, such that each step of the exponent table includes exponent matrices (H_exp) corresponding to one code rate. The exponent table may be nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices H_ex_P for each step, each nested exponent matrix H_ex of the plurality of nested exponent matrices Hex_P within a particular step corresponding to one code word length for the code rate of the particular step, e.g. as described above with respect to Fig. 2. A reduction of a row number of the exponent table may provide a block code of a higher code rate for the complete exponent matrices including both the random part and the deterministic part, e.g. as described above with respect to Fig. 2. A reduction of a column number of the exponent table may provide a block code of a shorter code word for the complete exponent matrices including both the random part and the deterministic part, e.g. as described above with respect to Fig. 2. With the reduction of the number of columns of the exponent table, a proportional reduction of the number of rows may also be performed in order to keep the code rate unchanged. Figures 6a, b, c are an example of how the data structure described above, realized for example using an exponent table with a step structure, may be used for implementing a plurality of the code rates, such as 1/2, 5/6, 9/10 and a plurality of code word lengths, such as 120, 90, 60, e.g. as illustrated below with respect to Figures 6a, b, c.

A size of the extracted exponent matrix H_ex may be determined based on the formulas k_bi] + 1 = R_; -n_bJ +l and r_bi] = n_b] · (1 - R_t ) , where R_t is a code rate and n_b] is a code word, e.g. as described above with respect to Fig. 2. The formulas above allow to obtain, based on the code rate R_t and the code word length n_bj , the number of columns and rows of the exponent matrix H_ex_P . Each exponent matrix H_exp in each group may include a random part and a deterministic part. The random part may be a random matrix and the deterministic part may be the first column of a deterministic matrix. The block codes for a particular code word length and a particular code rate may be built by using the random part and the deterministic matrix, the deterministic matrix may be obtained by combining the deterministic part with a matrix with a dual diagonal structure, e.g. as described above with respect to Fig. 2.

Fig. 4 shows a schematic diagram illustrating a method 400 for LDPC encoding according to an implementation form.

The method 400 includes receiving 401 an information sequence B1 , e.g. as described above with respect to Fig 2. The method 400 includes extracting 402 from one of a plurality of groups an exponent matrix H_ex for a specific code rate R among a plurality of exponent matrices, wherein the plurality of exponent matrices H_exp is stored in the plurality of groups, such that each group corresponds to one code rate. The exponent matrices H_ex in each group are nested and each nested exponent matrix H_eXp within a particular group corresponds to one code word length for the code rate of the particular group, wherein common elements in different groups are stored once, e.g. as described above with respect to Fig. 2 and illustrated below with respect to Figure 6a, b, c. The method 400 includes providing 404 an encoded sequence B2 starting directly from the extracted exponent matrix Hexp, e.g. as described above with respect to Figure 2. The sequence B2 may then be modulated and transmitted to the decoder through a channel.

The extraction of the exponent matrix in step 402 may be performed during the configuration of the system. Specifically, a particular code rate and a particular code length are set on the basis of the LDPC code used for the encoding/coding procedure. Based on the set code rate and on the set code length, the corresponding exponent matrix is extracted as described above with reference to the previous figures. In this way the encoder acquires the information sequence B1 and processes it in real time with the parity-check exponent matrix extracted during configuration of the system.

The method 400 may include using a constant spreading factor for all code words and all code rates, e.g. as described above with respect to Figure 2. The method 400 may include storing the exponent matrices H_exp in an exponent table, wherein the exponent table is step- shaped, such that each step of the exponent table includes exponent matrices H_exp corresponding to one code rate, and the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices H_ex_P for each step, each nested exponent matrix H_ex_P of the plurality of nested exponent matrices H_exp within a particular step corresponding to one code word length for the code rate of the particular step, e.g. as described above with respect to Figure 2 and illustrated below with respect to Figures 6a, b, c. Fig. 5 shows a schematic diagram illustrating a method 500 for LDPC decoding according to an implementation form.

The method 500 includes receiving 501 an encoded sequence B3, e.g. as described above with respect to Figs. 2 and 3. The method 500 includes extracting 502 from one of a plurality of groups an exponent matrix H_ex_P for a specific code rate R among a plurality of exponent matrices, wherein the plurality of exponent matrices H_exp is stored in a plurality of groups, such that each group corresponds to one code rate, and the exponent matrices H_exp in each group are nested, each nested exponent matrix H_ex_P within a particular group corresponding to one code word length for the code rate of the particular group, and wherein common elements in different groups are stored once, e.g. as described above with respect to Fig. 3 and illustrated below with respect to Figures 6a, b, c. The method 500 includes generating, a binary parity-check matrix based on the extracted exponent matrix. The method 500 includes decoding 504 the encoded sequence B3 based on the generated binary parity- check matrix to provide an information sequence estimate B4, e.g. as described above with respect to Figure 3. Unlike in the LDPC encoding process, where the encoded sequence to be transmitted is obtained based on the exponent parity-check matrix, in the decoding process as the one described above, the information sequence estimate B4 may be obtained from the binary parity-check matrix. In fig.5 the extracting circuit 502 produces during the configuration system, the binary parity-check matrix and the decoding circuit 504 uses the encoded sequence B3 and the binary parity-check matrix H to provide the information sequence estimate B4.

The method 500 may include using a constant spreading factor for all code words and all code rates, e.g. as described above with respect to Figure 3. The method 500 may include storing the exponent matrices H_ex in an exponent table, wherein the exponent table is step- shaped, such that each step of the exponent table includes exponent matrices H_exp corresponding to one code rate, and the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices H_ex_P for each step, each nested exponent matrix H_ex_P of the plurality of nested exponent matrices H_exp within a particular step or more generally within a particular group, corresponding to one code word length for the code rate of the particular step, e.g. as described above with respect to Figure 3 and illustrated below with respect to Figures 6a, b, c.

In the following extraction of the exponent matrix and the generation of block codes starting from an exponent table as performed by the devices and methods of the invention will be described with reference di figures 6 ff.

According to the invention, one exponent parity-check table may be used for building a plurality of LDPC block codes corresponding to different code rates R . and block code word lengths n_bj . These LDPC block codes may be built for a given spreading factorZ .

The code word lengths are obtained by multiplying the block code word lengths by the spreading factorZ _f . The number of LDPC block codes that can be built starting from the exponent parity-check table according to the invention can vary based on the hardware capabilities and the particular system being implemented. Fig. 6a, b, c show an exemplary exponent parity-check table for construction of 9 LDPC block codes with 3 code rates R_j = 1/2 , R₂= 5/6 , R₃ = 9/10 and 3 block code word lengths n_bl = 120 , n_b2 = 90 , n_b3 = 60 with spreading factor Z _f= 108 according to an implementation form. As explained above, for a spreading factorZ = 108 , the block code word lengths n_bl= 120 , n_b2= 9 , n_b3 = 60 correspond respectively to the code word lengths n_x= 12960 , n₂ = 9720 , n₃ = 6480 .

Clearly, the above is only an example and it has to be understood that the invention is not limited to the described choice of code rates, the block code length and of the spreading factor and that an exponent parity-check table can be designed for any code rates, block code lengths and spreading factor according to the system to be implemented.

In the figs. 6a, b, c is shown an exponent parity-check table. In this table are stored 9 exponent parity-check matrixes which correspond to 9 LDPC block codes. Each exponent matrix is a set composed by the random matrix and the deterministic part (first column of the deterministic matrix). The extracted exponent matrix considers all the deterministic parts of the contained subset as random parts. The described methods and devices may apply an opportune pre-processing on the exponent table so that it can include all 9 exponent parity-check matrixes corresponding to 9 LDPC block codes and maintain the properties of low computational complexity for the LDPC encoding process. The "opportune preprocessing" comprises including the first column of the deterministic matrix in the data structure used for storing the exponent matrices as deterministic part of the stored exponent matrix. The first column of the deterministic matrix may be the only column of the deterministic matrix stored in the data structure according to the device and methods described in this disclosure. Further, the first and the last elements of the first column of the deterministic matrix may be chosen to have the same value. Of the remaining elements, at least one element has exponent 0 (which corresponds to the identity matrix). The advantage thereof is a low computational complexity to implement the LDPC encoding process. In figure 6a, b, c the exponent parity-check table construction for 9 LDPC block codes with 3 code rates and 3 code words according to table 8 is shown. To obtain the wished LDPC block code from the table of figure 6a, b, c an exponent parity-check matrix may be built according to a semi-random technique. The configuration of the complete exponent matrix and its relationship with the incomplete exponent matrix stored according to the data structure described in figures 6 ff. will be explained using the example below. The complete exponent parity-check matrix includes two sub-matrices: the first one is a random matrix, while the second one is a deterministic matrix (an example of semi-randomly built complete exponent matrix is given in Annex H - H.3 Method 2 - of IEEE Standard 802.16e: "Air Interface for Fixed and Mobile Broadband Wireless Access Systems", February 28, 2006). The complete exponent matrix can be expressed by using the following block structure:

A B T

H C D E

The matrices A and C are random with sizes, respectively, (r_b - Y)xk_b and lxk_b while the matrices B, D, T and E are deterministic with sizes, respectively, (r_b - l)xl , lxl , (r_b - \)x(r_b - 1) and \x(r_b - 1) .

To minimize the hardware complexity of the LDPC block encoder only the first column of the deterministic matrix constituted by the vector B and the scalar D may be stored in an appropriate data structure, such as the groups and/or the step-shaped exponent table described above with reference to figures 2 to 6. As explained above with reference to the opportune pre-processing, the scalar D may be chosen so as to be equal to the first element of the vector B and at least one of the remaining elements of the vector B may be chosen to be equal to 0 (exponent of the identity matrix). In Fig. 6a, b, c there are 9 LDPC block codes (3 code rates and 3 code words) where the exponent parity-check matrix has the following configuration:

A B

C D

Then the LDPC block code exponent matrix, in figure 6a, b, c, is constituted by the random matrix (-4, C) and the first column (B, D) of the deterministic matrix.

Specifically, the table of figure 6a, b, c has 60 rows and 109 columns and comprises the exponent matrices for the parity check of 9 LDPC block codes, the code rates are 3 (

R_x— 1/2 , R₂— 5/6 , R₃— 9/10 ) and the block code words lengths/ code word lengths are 3 ( w_M= 120 , n_h2= 90 , n_b3 = 60 or n_x= 12960 , «₂= 9720 , n₃ = 6480 respectively with spreading factor Z ,= 108 ). In order to show the step and nested nature of the table some rows and columns (in this example 9) have bold frames. Within each bold framed column there are 2 framed elements, one of which indicates the intersection of a column with bold frame with a corresponding row with bold frame. Each row with bold frame is linked to one and only one column with bold frame and vice versa. As a result, in the universal table of Fi. 6a, b, c there are memorized 9 parity exponent matrices.

In this universal exponent table, the LDPC codes are constructed using a "semi-random" technique. Thus, each parity matrix includes all the columns of the random part and only the first column of the deterministic part (the remaining columns of the deterministic part are obtained by combining the deterministic part with a dual diagonal matrix as explained above).

The deterministic matrix design is performed in an opportune way, wherein only two elements of the first column are involved (framed elements), to reduce the hardware complexity of the LDPC block encoder.

Known R₍ (code rate) and n_b] (code word) it is necessary to calculate (k_biJ + 1) and (r_bij ) to extract the opportune exponent parity-check matrix as shown in the following: R_t = (4)

=> r_bt] = n_bJ - {\ - R_t) (5)

Now, using the equations (4) and (5), it is shown below with respect to Figures 7 to 9 how to extract from figure 6a, b, c the corresponding exponent parity-check matrix.

Fig. 7 shows an exemplary exponent parity-check matrix for LDPC block codes with code rate R=9/10 and code word length n3=6480 (corresponding to nb3=60) with spreading factor Zf=108 according to a first example. By using the equations (4) and (5) above, it is shown how to extract from figure 6a, b, c the corresponding exponent parity-check matrix.

By applying equation (4) the following expression is achieved: 9

k_{b J} + 1 = R₃ ^■ n_b + 1 =— · 60 + 1 = 55 and by applying equation (5) the following expression is achieved: r_i33 = «_M . (l - R₃ ) = 60 - (l - ^) = 6

With reference to figure 6a, b, c the exponent parity-check matrix with 6 rows and 55 columns H_exp (6,55) can be extracted from the exponent table, see borders in bold in Fig. 7 and reference "Exp1 " in Fig. 6b. The complete exponent matrix of figure 7 for the LDPC block code can be obtained by adding a bi-diagonal matrix to the extracted exponent matrix H_exp (6,55) . The obtained complete exponent matrix H(6,60) , with code rate R₃ = 9/10 and n_bi— 60 will have 6 rows and 60 columns. The matrix in figure 7 can be masked with the seed matrix to give the wished column weight which determines the LDPC block code performances and finally the resulting matrix can be expanded with the spreading matrix to achieve the binary parity-check matrix which is used in the decoding process. In figure 7 the permutation matrices, denoted in a conventional way as "-Γ, are matrices with all the elements being equal to zero.

Fig. 8 shows an exemplary exponent parity-check matrix for LDPC block codes with code rate R=5/6 and code word length n3=6480 (corresponding to nb3=60) with spreading factor Zf=108 according to a second example. By using the equations (4) and (5) above, it is shown how to extract from figure 6a, b, c the corresponding exponent parity-check matrix.

R₂ =— and n_bi = 60

6

By applying the equations (4) and (5) the following expression is achieved: k_b23 + 1 = R₂ ^■ n_b3 + 1 =— · 60 + 1 = 1

6 r₆₂₃ = «_Μ . (1 - Λ₂ ) = 60 · (1 - -¾ = 10

6

From figure 6a, b, c the exponent parity-check matrix is extracted with size H_exp (10,51) that is 10 rows and 51 columns, see borders in bold in Fig. 8 and reference "Exp2" in Fig. 6a. To achieve the complete exponent matrix for LDPC block code it is necessary to add the deterministic matrixes T and E and then the exponent matrix of figure 8, H(10,60) is obtained with code rate R₂ = 5/ 6 and n_bi— 60. Fig. 9 shows an exemplary exponent parity-check matrix for LDPC block codes with code rate R=1/2 and code word length n3=6480 (corresponding to nb3=60) with spreading factor Zf=108 according to a third example.

By using the equations (4) and (5) above, it is shown how to extract from figure 6a, b, c the corresponding exponent parity-check matrix. ?_! = and n_b3 = 60

By applying the equations (4) and (5) the following expressions are achieved:

k_bU + l = R_l - n_b + 1 = - 60 + 1 = 31 r_bl3 = _¾ · (1 - ^) = 60 · (1-1) = 30

From figure 6a, b, c the exponent parity-check matrix is extracted with size H_exp (30,31) , that is, 30 rows and 31 columns, see borders in bold in Fig. 9 and reference Έχρ3" in Fig. 6a. To achieve the complete exponent matrix for LDPC block code it is necessary to add the deterministic matrixes l and E to have the exponent matrix of figure 9, H(30,60) , with code rate R₁ = 1 /2 and n_b3 = 60.

The remaining six LDPC block code exponent matrices can be achieved as described in the following.

A block code according to a fourth example can be achieved by the expressions:

9

R₃ =— and n_b2 = 90 , see reference„Exp4" in Fig. 6c k_bi2 and r_bi2 A block code according to a fifth example can be achieved by the expressions:

R₂ =— and n_b2 = 90 , see reference„Exp5" in Fig. 6b

6

k_b22 and r_b22

A block code according to a sixth example can be achieved by the expressions:

R_\ =— and n_b2 = 90 , see reference„Exp6" in Fig. 6a k_bn and

A block code according to a seventh example can be achieved by the expressions:

9

i?₃ =— and n_bl = 120 , see reference„Exp7" in Fig. 6c k_bil and r_bil

A block code according to an eighth example can be achieved by the expressions:

R₂ =— and n_bl = 120 , see reference„Exp8" in Fig. 6c

6

k_b21 and r_bTi

A block code according to a ninth example can be achieved by the expressions:

R_x = ^ and n_bl = 120 , see reference„Exp9" in Fig. 6b k_bu and r_bu The present disclosure also supports a computer program product including computer executable code or computer executable instructions that, when executed, causes at least one computer to execute the performing and computing steps described herein, in particular the methods 400 and 500 as described above with respect to Figs. 4 and 5 and the techniques described above with respect to Figs. 1 to 9. Such a computer program product may include a readable storage medium storing program code thereon for use by a computer. The program code may perform the method 400 or 500 as described above with respect to Figs. 4 and 5.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms "coupled" and "connected", along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein. Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:

1. An encoder device (200) for performing LDPC coding, comprising:

an input (210) for receiving an information sequence (B1 );

an output (220) for providing an encoded sequence (B2);

a memory (201 ) for storing exponent matrices (H_ex_P), wherein the exponent matrices (Hexp) are stored in a plurality of groups (203a, 203b, 203c), such that each group (203a, 203b, 203c) corresponds to one code rate, and

wherein each group (203a, 203b, 203c) comprises a plurality of nested exponent matrices (H_eXp), each nested exponent matrix (H_exp) within a particular group corresponding to one code word length for the code rate of the particular group, wherein common elements of different groups (203a, 203b, 203c) are stored once in the memory (201 ); and

further comprising a processing unit (205) configured to extract an exponent matrix (Hexp) for a specific code rate (R) from a corresponding group (203a, 203b, 203c); and an encoding unit (207) for encoding the information sequence (B1 ) based on the extracted exponent matrix (H_exp) to provide the encoded sequence (B2).

2. A decoder device (300) for performing LDPC coding, comprising:

an input (310) for receiving an encoded sequence (B3);

an output (320) for providing an information sequence estimate (B4);

a memory (301 ) for storing exponent matrices (H_eXp);

wherein the exponent matrices (H_exp) are stored in a plurality of groups (303a, 303b, 303c), such that each group (303a, 303b, 303c) corresponds to one code rate, and

wherein each group (303a, 303b, 303c) comprises a plurality of exponent matrices (Hexp), each nested exponent matrix (H_exp) within a particular group (303a, 303b, 303c) corresponding to one code word length for the code rate of the particular group, and common elements of different groups (303a, 303b, 303c) being stored once in the memory (301 ),

and further comprising:

a processing unit (305) configured to extract an exponent matrix (H_eXp) for a specific code rate (R) from a corresponding group (303a, 303b, 303c) and configured to generate a binary parity-check matrix (H) starting from the extracted exponent matrix (H_ex_P) for the specific code rate (R); and

a decoding unit (307) for decoding the encoded sequence (B3) based on the binary parity-check matrix (H) to provide the information sequence estimate (B4).

3. The device (200, 300) of claim 1 or 2, wherein the exponent matrices (H_exp) are stored in an exponent table, wherein

the exponent table is step-shaped, such that each step of the exponent table includes exponent matrices (H_ex ) corresponding to one code rate, and

the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices (Hexp) for each step, each nested exponent matrix (H_ex_P) of the plurality of nested exponent matrices (H_ex_P) within a particular step corresponding to one code word length for the code rate of the particular step.

4. The device (200, 300) of claim 3,

wherein the exponent table comprises block codes implementing a plurality of code rates, such as 1 /2, 5/6, 9/10 and a plurality of code word lengths, such as 120, 90, 60.

5. The device (200, 300) of any one of the preceding claims,

wherein the extracting unit is configured to extract the exponent matrix (H_exp) based on the specific code rate R_t and a specific code word length n_bj , the number of columns and the number of rows of the exponent matrix (H_ex_P) to be extracted being respectively given by the formulas k_bjj + 1 = R_t -n_bj + \ and r_Uj = n_bj ^■ (1 - R_t) .

6. The device (200, 300) of any one of the preceding claims,

wherein each exponent matrix (H_ex_P) in each group comprises a random part and a deterministic part, the deterministic part of an exponent matrix for a particular code length being at least partially comprised in at least one random matrix corresponding to a different code length.

7. The device (200, 300) of claim 6,

wherein the random part is a random matrix and the deterministic part is the first column of a deterministic matrix, and

the processing unit (205, 305) is adapted to build a complete exponent matrix by using the random part and the deterministic matrix, the deterministic matrix being obtained by combining the deterministic part with a matrix with a dual diagonal structure,

wherein block codes for a particular code word length and a particular code rate are built based on the complete exponent matrix.

The device (200, 300) of claim 7, wherein the extracting unit is further adapted to build a block code of a higher code rate by a reduction of a row number of the exponent table for the complete exponent matrices.

9. The device (200, 300) of claim 7 or 8,

wherein, for a given code rate, the extracting unit is further adapted to build a block code of a shorter code word for the complete exponent matrices by a reduction of a column number, and proportional reduction of a row number of the exponent table.

10. The device (200, 300) of any one of the preceding claims,

wherein a constant spreading factor is used for all code words and all code rates.

1 1. A method (400) for LDPC encoding, comprising:

receiving (401 ) an information sequence (B1 );

extracting (402) from one of a plurality of groups an exponent matrix (H_ex_P) for a specific code rate (R) among a plurality of exponent matrices, wherein the plurality of exponent matrices (H_exp) is stored in the plurality of groups, such that each group corresponds to one code rate, and the exponent matrices (H_exp) in each group are nested, each nested exponent matrix (H_exp) within a particular group corresponding to one code word length for the code rate of the particular group, wherein common elements in different groups are stored once; and

providing (404) an encoded sequence (B2) based on the extracted exponent matrix

12. A method (500) for LDPC decoding, the method comprising:

receiving (501 ) an encoded sequence (B3);

extracting (502) from one of a plurality of groups an exponent matrix (H_exp) for a specific code rate (R) among a plurality of exponent matrices, wherein the plurality of exponent matrices (H_exp) is stored in a plurality of groups, such that each group corresponds to one code rate, and the exponent matrices (H_exp) in each group are nested, each nested exponent matrix (H_exp) within a particular group corresponding to one code word length for the code rate of the particular group, and wherein common elements in different groups are stored once;

generating a binary parity-check matrix (H) starting from the extracted exponent matrix (H_exp) for the specific code rate (R); and decoding (504) the encoded sequence (B3) based on the generated parity-check matrix (H) to provide an information sequence estimate (B4).

13. The method (400, 500) of claim 1 1 or claim 12, comprising:

using a constant spreading factor for all code words and all code rates.

14. The method (400, 500) of one of claims 1 1 to 13, comprising:

storing the exponent matrices (H_ex ) in an exponent table, wherein

the exponent table is step-shaped, such that each step of the exponent table includes exponent matrices (H_eXp) corresponding to one code rate, and

the exponent table is nested-shaped within each step, such that the exponent table comprises a plurality of nested exponent matrices (H_exp) for each step, each nested exponent matrix (H_ex ) of the plurality of nested exponent matrices (H_ex ) within a particular step corresponding to one code word length for the code rate of the particular step.