EP3270409A1 - Compound semiconductor substrate - Google Patents

Compound semiconductor substrate Download PDF

Info

Publication number
EP3270409A1
EP3270409A1 EP16761353.8A EP16761353A EP3270409A1 EP 3270409 A1 EP3270409 A1 EP 3270409A1 EP 16761353 A EP16761353 A EP 16761353A EP 3270409 A1 EP3270409 A1 EP 3270409A1
Authority
EP
European Patent Office
Prior art keywords
layer
composite
gan
semiconductor substrate
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP16761353.8A
Other languages
German (de)
French (fr)
Other versions
EP3270409A4 (en
Inventor
Akira FUKAZAWA
Mitsuhisa Narukawa
Keisuke Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Air Water Inc
Original Assignee
Air Water Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Air Water Inc filed Critical Air Water Inc
Publication of EP3270409A1 publication Critical patent/EP3270409A1/en
Publication of EP3270409A4 publication Critical patent/EP3270409A4/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02387Group 13/15 materials
    • H01L21/02389Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/02447Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • H01L21/02507Alternating layers, e.g. superlattice
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02581Transition metal or rare earth elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes
    • H01L29/475Schottky barrier electrodes on AIII-BV compounds

Definitions

  • This invention relates to a composite semiconductor substrate. More specifically, this invention relates to a composite semiconductor substrate including a SiC (silicon carbide) layer.
  • SiC has a wide band gap when compared to Si (silicon), and has high insulated breakdown field strength. Therefore, SiC is expected to serve as material of high-voltage semiconductor devices. Since the lattice constant of 3C-SiC (SiC which has a 3C type crystal structure) is similar to the lattice constant of GaN (gallium nitride), 3C-SiC can be used as a buffer layer for growing GaN. When 3C-SiC is used as a buffer layer for growing GaN, higher-voltage semiconductor devices of GaN can be obtained, since GaN and 3C-SiC have high insulated breakdown field strength.
  • Si substrates or bulk SiC substrates are widely used. Since there are only about 4 inch SiC substrates at present, it is difficult to increase the diameter. To obtain an inexpensive and large diameter SiC layer, it is preferable that an Si substrate is used as the foundation substrate.
  • the below Document 1 discloses a method for manufacturing a semiconductor substrate having a first step and a second step, wherein a film of Al x In y Ga 1-x-y N layer (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1) is formed on a film of a SiC layer formed on a Si substrate at a temperature higher than a GaN film forming temperature, and a film of GaN is formed at the GaN film forming temperature in the first step, and a film of an Al x In y Ga 1-x-y N layer (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1) is formed at a temperature lower than the GaN film forming temperature, and a film of GaN is formed at the GaN film forming temperature in the second step.
  • the below Documents 2 to 4 disclose methods for doping a nitride semiconductor layer with C (carbon) or the like, to improve tolerance of a semiconductor device including a nitride semiconductor layer. More specifically, the below Document 2 discloses a composite semiconductor substrate in which a multilayer buffer layer and nitride active layer are deposited in series on a Si single-crystal substrate, wherein Al x Ga 1-x N single-crystal layers (0.6 ⁇ x ⁇ 1.0) including C at 1*10 18 to 1*10 21 atoms / cm 3 and Al y Ga 1-y N single-crystal layers (0.1 ⁇ y ⁇ 0.5) including C at 1*10 17 to 1*10 21 atoms / cm 3 are alternately and repeatedly deposited in this order in the multilayer buffer layer, and the nitride active layer consists of an electron transition layer in which the C containing density is equal to or less than 5*10 17 atoms / cm 3 and an electron supply layer.
  • the below Document 3 discloses a nitride semiconductor wafer including a substrate and a buffer layer on the substrate, wherein the buffer layer includes an alternating layer of Al x Ga 1-x N layer (0 ⁇ x ⁇ 0.05) and Al y Ga 1-y N layer (0 ⁇ y ⁇ 1, and x ⁇ y). In the alternating layer, only the Al y Ga 1-y N layer includes acceptors.
  • a nitride semiconductor element which includes a base substrate, a buffer layer formed above the base substrate, an active layer formed on the buffer layer, and at least 2 electrodes formed above the active layer.
  • the buffer layer has one or more composite layers which include a plurality of nitride semiconductor layers having different lattice constants.
  • a carrier area of the nitride semiconductor layer having the largest lattice constant among the plurality of nitride semiconductor layers is intentionally doped with carbon atoms at a density beforehand determined and oxygen atoms at a density beforehand determined.
  • This invention is to solve the above problems.
  • the object is to provide composite semiconductor substrates which can improve the voltage withstanding and the crystalline quality.
  • a composite semiconductor substrate comprises: an Si substrate or an SOI (Silicon On Insulator) substrate, an SiC layer formed on a surface of the substrate, an Al a In b Ga 1-a-b N layer (0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ 1-a-b ⁇ 1, a>b, a>1-a-b) formed on a surface of the SiC layer, a composite layer formed on a surface of the Al a In b Ga1 -a-b N layer, and an Al c In d G a1-c-d N layer (0 ⁇ c ⁇ 0.3, 0 ⁇ d ⁇ 0.4, c ⁇ a, 1-a-b ⁇ 1-c-d) formed on a surface of the composite layer, wherein the composite layer includes an Al v In w Ga 1-v-w N layer (0 ⁇ v ⁇ 0.3, 0 ⁇ w ⁇ 0.4, v ⁇ a, 1-a-b ⁇ 1-v
  • number of the composite layers is more than or equal to 1 and equal to or less than 9.
  • the number of the composite layers is plural, and the Al v In w Ga 1-v-w N layer in at least one of the plurality of the composite layers includes C.
  • average densities of C and Fe in the Al v In w Ga 1-v-w N layers in the plurality of composite layers decrease from the Al v ln w Ga 1-v-w N layer nearest the SiC layer toward the Al v In w Ga 1-v-w N layer farthest from the SiC layer.
  • the number of the composite layers is more than or equal to 3 and equal to or less than 6.
  • a compositional ratio of each of Al, In, and Ga of one Al v In w Ga 1-v-w N layer in the plurality of composite layers and a compositional ratio of each of Al, In, and Ga of another Al v In w Ga 1-v-w N layer in the plurality of composite layers are different from each other, and a compositional ratio of each of Al, In, and Ga of one Al x In y Ga 1-x-y N layer in the plurality of composite layers and a compositional ratio of each of Al, In, and Ga of another Al x In y Ga 1-x-y N layer in the plurality of composite layers are different from each other.
  • an average density of C and Fe in the Al v In w Ga 1-v-w N layer of at least one of the composite layers is more than or equal to 1*10 18 atoms / cm 3 and equal to or less than 1*10 20 atoms / cm 3 .
  • the average density of C and Fe in the Al v In w Ga 1-v-w N layer of at least one of the composite layers is more than or equal to 3*10 18 atoms / cm 3 and equal to or less than 1*10 19 atoms / cm 3 .
  • a density of C and Fe in an inner part of the Al v In w Ga 1-v-w N layer in at least one of the composite layers changes from a side close to the SiC layer toward a side away from the SiC layer.
  • the Al v In w Ga 1-v-w N layer in at least one of the composite layers includes a first layer, a second layer formed on a surface of the first layer, and a third layer formed on a surface of the second layer, and an average density of C and Fe in the second layer is higher than an average density of C and Fe in the first layer and an average density of C and Fe in the third layer.
  • the Al v In w Ga 1-v-w N layer is an Al v Ga 1-v N layer (0 ⁇ v ⁇ 0.3, v ⁇ a, 1-a-b ⁇ 1-v)
  • the Al x In y Ga 1-x-y N layer is an Al x Ga 1-x N layer (v ⁇ x ⁇ 1, 0 ⁇ x ⁇ 1, 1-x ⁇ 1-v, c ⁇ x, 1-x ⁇ 1-c-d, x>1-x).
  • the Al v In w Ga 1-v-w N layer is a GaN layer
  • the Al x In y Ga 1-x-y N layer is an AlN layer.
  • the composite semiconductor substrate further comprises a first and a second electrodes formed at the surface side of the Al c In d Ga 1-c-d N layer, wherein magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.
  • composite semiconductor substrates being able to improve the voltage withstanding and the crystalline quality can be provided.
  • a "surface" of each of layers which constitute a composite semiconductor substrate is a term to represent an upper side face in Figures
  • a "reverse face” is a term to represent a lower side face in Figures.
  • the term of a "surface side” encompasses a location making contact with the "surface” and an upper location in Figures being separated from the "surface”.
  • the term of a "reverse face side” encompasses a location making contact with the "reverse face” and a lower location in Figures being separated from the "reverse face”.
  • Figure 1 shows a cross section view of a structure of a composite semiconductor substrate, according to the first embodiment of this invention.
  • a composite semiconductor substrate includes a HEMT (High Electron Mobility Transistor).
  • the composite semiconductor substrate is equipped with Si substrate 1, SiC layer 2, AlN layer 3, composite layers 6a, 6b and 6c, GaN layer 7, AlGaN layer 8, source electrode 11 and drain electrode 12 (examples of the first and the second electrodes), and gate electrode 13.
  • Si substrate 1 SiC layer 2, AlN layer 3, composite layers 6a, 6b and 6c, GaN layer 7, AlGaN layer 8, source electrode 11 and drain electrode 12 (examples of the first and the second electrodes), and gate electrode 13.
  • Si substrate 1 comprises of undoped Si.
  • the (111) plane is exposed on the surface of Si substrate 1.
  • Si substrate 1 may have p-type or n-type conductivity.
  • the (100) plane or the (110) plane may be exposed on the surface of Si substrate 1.
  • SiC layer 2 is formed on the surface of Si substrate 1.
  • SiC layer 2 comprises of 3C-SiC, 4H-SiC, 6H-SiC, or the like.
  • SiC layer 2 typically comprises of 3C-SiC.
  • SiC layer 2 may be formed by homoepitaxial growth of SiC, by using the MBE (Molecular Beam Epitaxy) method, the CVD (Chemical Vapor Deposition) method, the LPE (Liquid Phase Epitaxy) method, or the like, on the foundation layer which comprises of SiC obtained by carbonizing of the surface of Si substrate 1.
  • SiC layer 2 may be formed only by carbonizing of the surface of Si substrate 1. Further, SiC layer 2 may be formed by heteroepitaxial growth on the surface of Si substrate 1 (a buffer layer may be interposed).
  • SiC layer 2 may be changed to an n-type or a p-type.
  • impurity (dopant) for making SiC layer 2 the p-type at least one of B (boron), Al (aluminium), Ga (gallium), and In (indium) can be used, for example.
  • impurity for making SiC layer 2 the n-type at least one of N (nitrogen), P (phosphorus), and As (arsenic) can be used, for example.
  • transition elements such as V (vanadium) may be used for doping.
  • AlN layer 3 is formed on the surface of SiC layer 2.
  • AlN layer 3 acts as a buffer layer to alleviate difference between the lattice constant of SiC layer 2 and the lattice constant of GaN layer 4.
  • AlN layer 3 is formed by using the MOCVD (Metal Organic Chemical Vapor Deposition) method, for example.
  • the growth temperature of AlN layer 3 is more than or equal to 1100 degree Celsius and equal to or less than 1300 degree Celsius, for example.
  • As Al source gas TMA (Tri Methyl Aluminium), TEA (Tri Ethyl Aluminium), or the like is used, for example.
  • N source gas NH 3 (ammonia) is used, for example.
  • the thickness of AlN layer 3 is preferably more than or equal to 10nm and equal to or less than 500nm.
  • AlN layer 3 may be an Al a In b Ga 1-a-b N layer (0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ 1-a-b ⁇ 1, a>b, a>1-a-b) by replacing part of Al atoms with at least one of In atoms and Ga atoms (However, the compositional ratio of In should not exceed the compositional ratio of Al).
  • AlN layer 3 may be an Al a Ga 1-a N layer (0 ⁇ a ⁇ 1, a>1-a), by replacing part of Al atoms with Ga atoms.
  • the Al a In b G a1-a-b N layer is preferably an AlN layer (It is better not to replace Al atoms with In atoms and Ga atoms).
  • Composite layers 6a, 6b and 6c are formed on the surface of SiC layer 2, in this order.
  • Each of composite layers 6a, 6b and 6c includes a GaN layer and an AlN layer.
  • GaN layer 4a of composite layer 6a is formed on the surface of AlN layer 3.
  • AlN layer 5a of composite layer 6a is formed on the surface of GaN layer 4a.
  • GaN layer 4b of composite layer 6b is formed on the surface of AlN layer 5a.
  • AlN layer 5b of composite layer 6b is formed on the surface of GaN layer 4b.
  • GaN layer 4c of composite layer 6c is formed on the surface of AlN layer 5b.
  • AlN layer 5c of composite layer 6c is formed on the surface of GaN layer 4c.
  • any one of GaN layers 4a, 4b and 4c may be referred to as GaN layer 4.
  • Any one of AlN layers 5a, 5b and 5c may be referred to as AlN layer 5.
  • Any of composite layers 6a, 6b and 6c may be referred to as composite layer 6.
  • the composite semiconductor substrate should have at least one composite layer 6.
  • the composite semiconductor substrate preferably has more than or equal to 1 and equal to or less than 9 composite layers.
  • the composite semiconductor substrate more preferably has a plurality of composite layers (more than or equal to 2 and equal to or less than 9 layers).
  • the composite semiconductor substrate furthermore preferably has more than or equal to 3 and equal to or less than 6 composite layers.
  • the thickness of GaN layer 4 is preferably more than or equal to 50nm and equal to or less than 5 ⁇ m. Herewith, inhibiting warpage of the substrate, a high quality GaN layer can be obtained.
  • GaN layer 4a is formed by using the MOCVD method, for example, in the following manner. Firstly, three-dimensional nuclei of GaN crystal are formed at predetermined density. Next, the three-dimensional nuclei of GaN crystal are grown in the horizontal direction at a temperature lower than the growth temperature of AlN layer 5 to form a continuous GaN single-crystal film. At this time, as Ga source gas, TMG (Tri Methyl Gallium), TEG (Tri Ethyl Gallium), or the like is used, for example. As N source gas, NH3 is used, for example.
  • each of GaN layers 4b and 4c (the GaN layer other than GaN layer 4a) is formed by using the MOCVD method, for example, in the following manner.
  • a continuous GaN single-crystal film is formed by two dimensions nucleus growth (coherent growth), at a temperature lower than the growth temperature of AlN layer 5.
  • Ga source gas TMG, TEG, or the like is used, for example.
  • N source gas NH 3 is used, for example.
  • the process temperature in the step for forming the three-dimensional nucleus, the step for growing three-dimensional nucleus of GaN crystals in the horizontal direction, and the step for the two dimensions nucleus growth is higher than the growth temperature of AlN layer 5.
  • the growth temperature of GaN layer 4 is more than or equal to 900 degree Celsius and equal to or less than 1200 degree Celsius, for example.
  • GaN layer 4 may be an Al v In w Ga 1-v-w N layer (0 ⁇ v ⁇ 0.3, 0 ⁇ w ⁇ 0.4, v ⁇ a, 1-a-b ⁇ 1-v-w), by replacing part of Ga atoms with at least one of Al atoms and In atoms.
  • GaN layer 4 may be Al v Ga 1-v N layer (0 ⁇ v ⁇ 0.3, v ⁇ a, 1-a-b ⁇ 1-v) by replacing part of Ga atoms with Al atoms.
  • an Al v In w Ga 1-v-w N layer is preferably a GaN layer (It is better not to replace Ga atoms with Al atoms and In atoms).
  • AlN layer 5 fulfills the function for suppressing the occurrence of warpage.
  • AlN layer 5 When AlN layer 5 is sandwiched by two GaN layers 4, AlN layer 5 fulfills the function for alleviating stress between the two GaN layers 4.
  • AlN layer 5 is formed by using the MOCVD method, for example.
  • the growth temperature of AlN layer 5 is lower than the growth temperature of AlN layer 3, and is more than or equal to 800 degree Celsius and equal to or less than 1200 degree Celsius, for example.
  • Al source gas TMA, TEA, or the like is used, for example.
  • N source gas NH 3 is used, for example.
  • the thickness of AlN layer 5 is preferably more than or equal to 10nm and equal to or less than 500nm.
  • dislocation formed in AlN layer 5 is reduced, and the crystalline quality of GaN layer 4 can be improved.
  • the time required for forming AlN layer 5 can be shorten.
  • AlN layer 5 may be an Al x In y Ga 1-x-y N layer (v ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ 1-x-y ⁇ 1, 1-x-y ⁇ 1-v-w, c ⁇ x, 1-x-y ⁇ 1-c-d, x>y, x>1-x-y), by replacing part of Al atoms with at least one of In atoms and Ga atoms (However, the compositional ratio of In should not exceed the compositional ratio of Al).
  • AlN layer 5 may be an Al x Ga 1-x N layer (v ⁇ x ⁇ 1, 0 ⁇ x ⁇ 1, 1-x ⁇ 1-v, c ⁇ x, 1-x ⁇ 1-c-d), by replacing part of Al atoms with Ga atoms.
  • an Al x In y Ga 1-x-y N layer is preferably an AlN layer (It is better not to replace Al atoms with In atoms and Ga atoms).
  • GaN layer 4 is an Al v In w Ga 1-v-w N layer
  • AlN layer 5 is an Al x In y Ga 1-x-y N layer
  • the compositional ratio of Al in the Al x In y Ga 1-x-y N layer is higher than the compositional ratio of Al in the Al v In w Ga 1-v-w N layer (namely, v ⁇ x)
  • the compositional ratio of Ga in the Al x In y Ga 1-x-y N layer is lower than the compositional ratio of Ga in the Al v In w Ga 1-v-w N layer (namely, 1-x-y ⁇ 1-v-w).
  • the lattice constant of AlN and the lattice constant of GaN are very close, and the lattice constant of AlN is smaller than the lattice constant of GaN.
  • the AlN layer did not take over the crystal structure of the foundation GaN layer. Slip occurs at the interface between the AlN layer and the GaN layer.
  • the GaN layer grows coherently with respect to the foundation AlN layer, and compression stress occurs in the GaN layer, being subject to the influence of the lattice constant of the AlN layer. In consequence, the occurrence of cracks in the GaN layer and warpage are suppressed.
  • the quality of the crystals of GaN layer 4 and AlN layer 5 can be improved, by forming AlN layer 3, GaN layer 4, and AlN layer 5 on the surface of SiC layer 2, under the above mentioned growth condition.
  • the average density of C and Fe in GaN layer 4 is higher than the average density of C and Fe in AlN layer 5.
  • the average density of C and Fe in GaN layer 4 is preferably more than or equal to 1*10 18 atoms / cm 3 , is more preferably more than or equal to 3*10 18 atoms / cm 3 , and is furthermore preferably more than or equal to 5*10 18 atoms / cm 3 .
  • the resistor of GaN layer 4 can be increased greatly, so that the voltage withstanding can be improved.
  • the average density of C and Fe in GaN layer 4 is preferably equal to or less than 1*10 20 atoms / cm 3 , is more preferably equal to or less than 1*10 19 atoms / cm 3 .
  • crystalline quality degradation of GaN layer 4 can be suppressed.
  • GaN layer 4 in at least one of composite layers 6 preferably includes C.
  • the average density of C and Fe means the average value of the density distribution of the sum total of C and Fe in the normal direction (the depth direction) of the surface of Si substrate 1 in the layers.
  • the density distribution of C and Fe in the normal direction of the surface of Si substrate 1 in the layers can be measured by using SIMS (Secondary Ion Mass Spectrometry).
  • GaN layer 4 is doped with C in the following manner, for example.
  • the film forming temperature and the formed film pressure different from the case in which a film of a GaN layer not being doped with C in a positive manner are adopted.
  • GaN layer 4 is doped with C included in Ga organic metal.
  • GaN layer 4 may be doped with C, by introducing organic gas into the chamber in which the MOCVD is performed. C ions may be injected into GaN layer 4.
  • GaN layer 4 is doped with Fe, in the following manner, for example.
  • GaN layer 4 is formed by using the MOCVD method
  • GaN layer 4 is doped with Fe, by introducing Fe organic metal into the chamber in which the MOCVD is performed. Fe ions may be injected into GaN layer 4.
  • GaN layer 4 does not include O.
  • GaN layer 7 is formed on the surface of composite layer 6c. Impurity was not introduced to GaN layer 7, and GaN layer 7 acts as an electron transition layer of the HEMT. GaN layer 7 is formed in a manner similar to GaN layer 5.
  • AlGaN layer 8 is formed on the surface of GaN layer 7.
  • AlGaN layer 8 has n-type conductivity, and is a barrier layer of the HEMT.
  • AlGaN layer 8 is formed by the MOCVD method or the like, for example.
  • Source electrode 11, drain electrode 12, and gate electrode 13 are formed on the surface of AlGaN layer 8, being spaced apart from each other. Source electrode 11 and drain electrode 12 are placed in ohmic contact with AlGaN layer 8. Gate electrode 13 is placed in schottky contact with Al GaN layer 8. Source electrode 11 and drain electrode 12 have a structure in which a Ti (titanium) layer and an Al (aluminium) layer are laminated in the order from the side of AlGaN layer 8, for example. The gate electrode 13 has a structure in which an Ni (nickel) layer and an Au (gold) layer are laminated in the order from the side of AlGaN layer 8, for example. Source electrode 11, drain electrode 12, and gate electrode 13 are formed by a deposition method, a MOCVD method, a sputtering method, or the like, for example.
  • the HEMT according to the embodiment works, as follows. Due to the band gap difference between GaN layer 7 and AlGaN layer 8, electrons occurred in AlGaN layer 8 gather at the heterojunction interface of GaN layer 7 and Al GaN layer 8, and form the two dimensions electron gas. In line with the forming the two dimensions electron gas, AlGaN layer 8 completely becomes a depletion layer by the depletion layer extending upwardly from the heterojunction interface with GaN layer 7 in Figure 1 and the depletion layer extending downwardly from the joint interface with gate electrode 13 in Figure 1 .
  • the quality of the GaN layer 4 crystal can be improved. Since the average density of C and Fe in GaN layer 4 is high, in at least one of composite layers 6, the electrical resistance of the GaN layer 4 increases, and the voltage withstanding of the composite semiconductor substrate can be improved. Further, since the average density of C and Fe in AlN layer 5 is low, in at least one of composite layers 6, the quality of the GaN layer 4 crystal formed on the surface can be improved.
  • Figure 2 shows a graph indicating the first example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • the average density of C and Fe in each of GaN layers 4a, 4b and 4c is higher than the average density of C and Fe in each of AlN layers 5a, 5b and 5c.
  • the density of C and Fe in the inner part of each of GaN layers 4a, 4b and 4c is a constant value (density C1), regardless of the distance from the surface of Si substrate 1.
  • the average densities of C and Fe in GaN layers 4a, 4b and 4c are all density C1.
  • the density of C and Fe in each of AlN layers 5a, 5b and 5c is a constant value (density C11), regardless of the distance from the surface of Si substrate 1.
  • the average densities of C and Fe in AlN layers 5a, 5b and 5c are all density C11 ( ⁇ C1).
  • a composite layer in which the density distribution of C and Fe is uniform, can be formed.
  • Figure 3 shows a graph indicating the second example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • the average density of C and Fe in each of GaN layers 4a and 4b is higher than the average density of C and Fe in each of AlN layers 5a and 5b.
  • the average density of C and Fe in GaN layer 4c is lower than the average density of C and Fe in AlN layer 5c.
  • the density of C and Fe in the inner part of each of GaN layers 4a, 4b and 4c is a constant value, regardless of the distance from the surface of Si substrate 1.
  • the density of C and Fe in each of AlN layers 5a, 5b and 5c is a constant value (density C11), regardless of the distance from the surface of Si substrate 1.
  • the average densities of C and Fe in AlN layers 5a, 5b and 5c are all density C11 (C3 ⁇ C11 ⁇ C2).
  • the average density of C and Fe in each of GaN layers 4a, 4b and 4c decreases from GaN layer 4a nearest from SiC layer 2 toward GaN layer 4c farthest from SiC layer 2. More specifically, the average density of C and Fe in GaN layer 4a is density C1. The average density of C and Fe in GaN layer 4b is density C2 ( ⁇ C1). The average density of C and Fe in GaN layer 4c is density C3 ( ⁇ C2).
  • GaN layer 4 (mainly, GaN layer 4a) close to SiC layer 2 plays a role of improving the voltage withstanding, and GaN layer 4 (mainly, GaN layer 4c) away from SiC layer 2 play a role of improving the crystalline quality of GaN layer 4.
  • both the voltage withstanding and the crystalline quality can be improved in an effective manner.
  • the average densities of C and Fe in AlN layers 5a, 5b and 5c may decrease from AlN layer 5a nearest from SiC layer 2 toward AlN layer 5c farthest from SiC layer 2.
  • Figure 4 shows a graph indicating the third example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • the density of C and Fe in the inner part of each of GaN layers 4a, 4b and 4c changes from the reverse side (the side close to Si substrate 1) toward the surface side (the side away from Si substrate 1). More specifically, the density of C and Fe in GaN layer 4a decreases from the reverse side to the surface side, from density C1A to density C1B ( ⁇ C1 ⁇ C1A). The density of C and Fe in GaN layer 4b decreases from the reverse side to the surface side, from density C2A to density C2B ( ⁇ C2 ⁇ C2A). The density of C and Fe in GaN layer 4c decreases from the reverse side to the surface side, from density C3A to density C3B ( ⁇ C3 ⁇ C3A).
  • the average densities of C and Fe of GaN layers 4a, 4b and 4c decrease from GaN layer 4a nearest from SiC layer 2 toward GaN layer 4d farthest from SiC layer 2. More specifically, the average density of C and Fe in GaN layer 4a is density C1. The average density of C and Fe in GaN layer 4b is density C2 ( ⁇ C1). The average density of C and Fe in GaN layer 4c is density C3 ( ⁇ C2). The densities of C and Fe of AlN layers 5a, 5b and 5c are a constant value (density C11), regardless of the distance from the surface of Si substrate 1. The average densities of C and Fe in AlN layers 5a, 5b and 5c are all density C11 (C3 ⁇ C11 ⁇ C2).
  • the effect similar to the second example can be obtained, and the density distribution of C and Fe in the inner part of GaN layer 4 can fluctuate.
  • the density of C and Fe in the inner part of each of AlN layers 5a, 5b and 5c may be changed from the reverse side (the side closed to Si substrate 1) to the surface side (the side away from Si substrate 1).
  • Figure 5 shows a graph indicating the fourth example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • Figure 5 only the density distribution of C and Fe in GaN layer 4a is selectively indicated.
  • GaN layer 4a consists of a plurality of layers of which the densities of C and Fe are different from each other.
  • GaN layer 4a includes the first layer 31, the second layer 32, and the third layer 33.
  • the second layer 32 is formed on the surface of the first layer 31.
  • the third layer 33 is formed on the surface of the second layer 32.
  • the density of C and Fe in the inner part of each of the first layer 31, the second layer 32, and the third layer 33 is a constant value, regardless of the distance from the surface of Si substrate 1.
  • the average density of C and Fe in the second layer 32 is density C4.
  • the average density of C and Fe in each of the first layer 31 and the third layer 33 is density C5 ( ⁇ C4).
  • the average density of C and Fe in GaN layer 4a is C1 (C5 ⁇ C1 ⁇ C4, C11 ⁇ C1).
  • the second layer 32 plays a role of improving the voltage withstanding
  • each of the first layer 31 and the third layer plays a role of smoothing the boundary face with AlN layers 3 and 5a.
  • both the voltage withstanding and the crystalline quality can be improved in an effective manner, and the occurrence of warpage and cracks can be suppressed in an effective manner.
  • each of GaN layer 4b and 4c may have the density distribution of C and Fe similar to the density distribution of C and Fe of the inner part of GaN layer 4a, and may have the density distribution of C and Fe different from the density distribution of C and Fe of the inner part of GaN layer 4a.
  • AlN layer 5 may be formed by a plurality of layers of which the densities of C and Fe are different from each other, as similar to GaN layer 4a.
  • Figure 6 shows a cross section view of a structure of a composite semiconductor substrate, according to the second embodiment of this invention.
  • the composite semiconductor substrate according to the embodiment is different from the composite semiconductor substrate of the first embodiment, in the sense that it is equipped with SOI substrate 1 as substitute for a Si substrate.
  • An SOI substrate is a substrate of a single-crystal Si, formed on an insulating film.
  • SOI substrate 1 includes Si substrate 21, SiO 2 (silicon dioxide) layer 22, and SOI layer 23. On the surface of Si substrate 21, SiO 2 layer 22 is formed. On the surface of SiO 2 layer 22, SOI layer 23 consist of Si is formed.
  • SOI substrate 1 is made by an arbitrary method.
  • the junction capacitance of the composite semiconductor substrate can be smaller, and the voltage withstanding can be improved.
  • a composite semiconductor substrate has a plurality of composite layers 6, and a layer corresponds to GaN layer 4 in each of the plurality of composite layers 6 consists of an Al v In w Ga 1-v-w N layer (0 ⁇ v ⁇ 0.3, 0 ⁇ w ⁇ 0.4, v ⁇ a, 1-a-b ⁇ 1-v-w)
  • the compositional ratio of each of Al, In, and Ga in one Al v In w Ga 1-v-w N layer in the plurality of composite layer 6 and the compositional ratio of each of Al, In, and Ga in another Al v In w Ga 1-v-w N layer in the plurality of composite layer 6 may be different with each other.
  • each of a plurality of composite layer 6 consists of an Al x In y Ga 1-x-y N layer (v ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1, 1-x-y ⁇ 1-v-w, c ⁇ x, 1-x-y ⁇ 1-c-d)
  • the compositional ratio of each of Al, In, and Ga in one Al x In y Ga 1-x-y N layer in the plurality of composite layer 6 and the compositional ratio of each of Al, In, and Ga in another Al x In y Ga 1-x-y N layer in the plurality of composite layer 6 may be different with each other.
  • a device formed on the composite semiconductor substrate is an arbitrary device, and it may be a transistor, an LED (Light Emitting Diode), a thyristor, a semiconductor laser, or the like, other than the above mentioned device.
  • the composite semiconductor substrate may be a substrate in which the magnitude of the electrical current flows between the first electrode and the second electrode formed at the surface side of the Al x In y Ga 1-x-y N layer depends on the electrical voltage between the first electrode and the second electrode.

Abstract

A composite semiconductor substrate being able to improve voltage withstanding and crystalline quality is provided.
A composite semiconductor substrate is equipped with an Si (silicon) substrate, an SiC (silicon carbide) layer formed on the surface of the Si substrate, an AlN (aluminum nitride) layer formed on the surface of the SiC layer, a composite layer formed on the surface of the AlN layer, and a GaN (gallium nitride) layer formed on the surface of the composite layer. The composite layer includes an AlN (aluminum nitride) layer and a GaN layer formed on the surface of the AlN layer. In at least one composite layer, the average density of C and Fe in the GaN layer is higher than the average density of C and Fe in the AlN layer.

Description

    FIELD OF THE INVENTION
  • This invention relates to a composite semiconductor substrate. More specifically, this invention relates to a composite semiconductor substrate including a SiC (silicon carbide) layer.
  • BACKGROUND OF THE INVENTION
  • SiC has a wide band gap when compared to Si (silicon), and has high insulated breakdown field strength. Therefore, SiC is expected to serve as material of high-voltage semiconductor devices. Since the lattice constant of 3C-SiC (SiC which has a 3C type crystal structure) is similar to the lattice constant of GaN (gallium nitride), 3C-SiC can be used as a buffer layer for growing GaN. When 3C-SiC is used as a buffer layer for growing GaN, higher-voltage semiconductor devices of GaN can be obtained, since GaN and 3C-SiC have high insulated breakdown field strength.
  • As foundation substrates for growing SiC layers, Si substrates or bulk SiC substrates are widely used. Since there are only about 4 inch SiC substrates at present, it is difficult to increase the diameter. To obtain an inexpensive and large diameter SiC layer, it is preferable that an Si substrate is used as the foundation substrate.
  • The below Document 1 discloses a method for manufacturing a semiconductor substrate having a first step and a second step, wherein a film of AlxInyGa1-x-yN layer (0<x ≦ 1, 0 ≦ y ≦ 1, x+y ≦ 1) is formed on a film of a SiC layer formed on a Si substrate at a temperature higher than a GaN film forming temperature, and a film of GaN is formed at the GaN film forming temperature in the first step, and a film of an AlxInyGa1-x-yN layer (0<x ≦ 1, 0 ≦ y ≦ 1, x+y ≦ 1) is formed at a temperature lower than the GaN film forming temperature, and a film of GaN is formed at the GaN film forming temperature in the second step.
  • The below Documents 2 to 4 disclose methods for doping a nitride semiconductor layer with C (carbon) or the like, to improve tolerance of a semiconductor device including a nitride semiconductor layer. More specifically, the below Document 2 discloses a composite semiconductor substrate in which a multilayer buffer layer and nitride active layer are deposited in series on a Si single-crystal substrate, wherein AlxGa1-xN single-crystal layers (0.6 ≦ x ≦ 1.0) including C at 1*1018 to 1*1021 atoms / cm3 and AlyGa1-yN single-crystal layers (0.1 ≦ y ≦ 0.5) including C at 1*1017 to 1*1021 atoms / cm3 are alternately and repeatedly deposited in this order in the multilayer buffer layer, and the nitride active layer consists of an electron transition layer in which the C containing density is equal to or less than 5*1017 atoms / cm3 and an electron supply layer. The C containing densities in the AlxGa1-xN single-crystal layer and the AlyGa1-yN single-crystal layer decrease from the substrate side toward the active layer side.
  • The below Document 3 discloses a nitride semiconductor wafer including a substrate and a buffer layer on the substrate, wherein the buffer layer includes an alternating layer of AlxGa1-xN layer (0 ≦ x ≦ 0.05) and AlyGa1-yN layer (0<y ≦ 1, and x<y). In the alternating layer, only the AlyGa1-yN layer includes acceptors.
  • Further, the below Document 4 discloses a nitride semiconductor element which includes a base substrate, a buffer layer formed above the base substrate, an active layer formed on the buffer layer, and at least 2 electrodes formed above the active layer. The buffer layer has one or more composite layers which include a plurality of nitride semiconductor layers having different lattice constants. In at least one of the composite layers, a carrier area of the nitride semiconductor layer having the largest lattice constant among the plurality of nitride semiconductor layers is intentionally doped with carbon atoms at a density beforehand determined and oxygen atoms at a density beforehand determined.
  • PRIOR ART DOCUMENT(S) DOCUMENT(S) RELATED TO PATENT(S)
    • [Document 1] Japan Patent Publication No. 2013-179121
    • [Document 2] Japan Patent Publication No. 2011-82494
    • [Document 3] Japan Patent Publication No. 2014-49674
    • [Document 4] Japan Patent Publication No. 2013-69714
    OVERVIEW OF THE INVENTION PROBLEM(S) TO BE RESOLVED BY THE INVENTION
  • When producing a semiconductor device using GaN, and an Si substrate is used as a start substrate (foundation substrate), warpage of the substrate and cracks in the GaN layer are likely to occur, since differences of the lattice constants and the thermal expansion coefficients between GaN and Si are large. The lattice constants and thermal expansion coefficients of GaN and Si are relaxed, by using an SiC layer and an AlxInyGa1-x-yN layer as buffer layers such as a technique disclosed in the Document 1, so that warpage of the substrate and cracks in the GaN layer are suppressed. On the other hand, the technique of the Document 1 has a problem in which the voltage withstanding is poor.
  • When the nitride semiconductor layer is doped with C or the like to improve tolerance, according to the techniques of Documents 2 to 4, there arises a problem in which the crystalline quality of the nitride semiconductor layer is degraded by the C used for the doping.
  • This invention is to solve the above problems. The object is to provide composite semiconductor substrates which can improve the voltage withstanding and the crystalline quality.
  • THE WAY TO SOLVE THE PROBLEM(S)
  • According to one aspect of this invention, a composite semiconductor substrate comprises: an Si substrate or an SOI (Silicon On Insulator) substrate, an SiC layer formed on a surface of the substrate, an AlaInbGa1-a-bN layer (0<a ≦ 1, 0 ≦ b<1, 0 ≦ 1-a-b<1, a>b, a>1-a-b) formed on a surface of the SiC layer, a composite layer formed on a surface of the AlaInbGa1-a-bN layer, and an AlcIndGa1-c-dN layer (0 ≦ c ≦ 0.3, 0 ≦ d ≦ 0.4, c<a, 1-a-b<1-c-d) formed on a surface of the composite layer, wherein the composite layer includes an AlvInwGa1-v-wN layer (0 ≦ v ≦ 0.3, 0 ≦ w ≦ 0.4, v<a, 1-a-b<1-v-w) and AlxInyGa1-x-yN layer (v<x ≦ 1, 0 ≦ y<1, 0 ≦ 1-x-y<1, 1-x-y<1-v-w, c<x, 1-x-y<1-c-d, x>y, x>1-x-y) formed on a surface of the AlvInwGa1-v-wN layer, and an average density of C and Fe in the AlvInwGa1-v-wN layer is higher than an average density of C and Fe in the AlxInyGa1-x-yN layer in at least one the composite layer.
  • Preferably, as for the composite semiconductor substrate, number of the composite layers is more than or equal to 1 and equal to or less than 9.
  • Preferably, as for the composite semiconductor substrate, the number of the composite layers is plural, and the AlvInwGa1-v-wN layer in at least one of the plurality of the composite layers includes C.
  • Preferably, as for the composite semiconductor substrate, average densities of C and Fe in the AlvInwGa1-v-wN layers in the plurality of composite layers decrease from the AlvlnwGa1-v-wN layer nearest the SiC layer toward the AlvInwGa1-v-wN layer farthest from the SiC layer.
  • Preferably, as for the composite semiconductor substrate, the number of the composite layers is more than or equal to 3 and equal to or less than 6.
  • Preferably, as for the composite semiconductor substrate, a compositional ratio of each of Al, In, and Ga of one AlvInwGa1-v-wN layer in the plurality of composite layers and a compositional ratio of each of Al, In, and Ga of another AlvInwGa1-v-wN layer in the plurality of composite layers are different from each other, and a compositional ratio of each of Al, In, and Ga of one AlxInyGa1-x-yN layer in the plurality of composite layers and a compositional ratio of each of Al, In, and Ga of another AlxInyGa1-x-yN layer in the plurality of composite layers are different from each other.
  • Preferably, as for the composite semiconductor substrate, an average density of C and Fe in the AlvInwGa1-v-wN layer of at least one of the composite layers is more than or equal to 1*1018 atoms / cm3 and equal to or less than 1*1020 atoms / cm3.
  • Preferably, as for the composite semiconductor substrate, the average density of C and Fe in the AlvInwGa1-v-wN layer of at least one of the composite layers is more than or equal to 3*1018 atoms / cm3 and equal to or less than 1*1019 atoms / cm3.
  • Preferably, as for the composite semiconductor substrate, a density of C and Fe in an inner part of the AlvInwGa1-v-wN layer in at least one of the composite layers changes from a side close to the SiC layer toward a side away from the SiC layer.
  • Preferably, as for the composite semiconductor substrate, the AlvInwGa1-v-wN layer in at least one of the composite layers includes a first layer, a second layer formed on a surface of the first layer, and a third layer formed on a surface of the second layer, and an average density of C and Fe in the second layer is higher than an average density of C and Fe in the first layer and an average density of C and Fe in the third layer.
  • Preferably, as for the composite semiconductor substrate, the AlvInwGa1-v-wN layer is an AlvGa1-vN layer (0 ≦ v ≦ 0.3, v<a, 1-a-b<1-v), and the AlxInyGa1-x-yN layer is an AlxGa1-xN layer (v<x ≦ 1, 0<x ≦ 1, 1-x<1-v, c<x, 1-x<1-c-d, x>1-x).
  • Preferably, as for the composite semiconductor substrate, the AlvInwGa1-v-wN layer is a GaN layer, the AlxInyGa1-x-yN layer is an AlN layer.
  • Preferably, the composite semiconductor substrate further comprises a first and a second electrodes formed at the surface side of the AlcIndGa1-c-dN layer, wherein magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.
  • THE EFFECT OF THE INVENTION
  • According to this invention, composite semiconductor substrates being able to improve the voltage withstanding and the crystalline quality can be provided.
  • BRIEF DESCRIPTION OF THE DRAWINGS
    • [Figure 1] shows a cross section view of a structure of a composite semiconductor substrate, according to the first embodiment of this invention.
    • [Figure 2] shows a graph indicating the first example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
    • [Figure 3] shows a graph indicating the second example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
    • [Figure 4] shows a graph indicating the third example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
    • [Figure 5] shows a graph indicating the fourth example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
    • [Figure 6] shows a cross section view of a structure of a composite semiconductor substrate, according to the second embodiment of this invention.
    DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The embodiments of this invention will be explained in the followings based on the Figures. In the following explanations, a "surface" of each of layers which constitute a composite semiconductor substrate is a term to represent an upper side face in Figures, and a "reverse face" is a term to represent a lower side face in Figures. The term of a "surface side" encompasses a location making contact with the "surface" and an upper location in Figures being separated from the "surface". The term of a "reverse face side" encompasses a location making contact with the "reverse face" and a lower location in Figures being separated from the "reverse face".
  • [The first embodiment]
  • Figure 1 shows a cross section view of a structure of a composite semiconductor substrate, according to the first embodiment of this invention.
  • Referring to Figure 1, a composite semiconductor substrate according to this embodiment includes a HEMT (High Electron Mobility Transistor). The composite semiconductor substrate is equipped with Si substrate 1, SiC layer 2, AlN layer 3, composite layers 6a, 6b and 6c, GaN layer 7, AlGaN layer 8, source electrode 11 and drain electrode 12 (examples of the first and the second electrodes), and gate electrode 13.
  • Si substrate 1 comprises of undoped Si. The (111) plane is exposed on the surface of Si substrate 1. Si substrate 1 may have p-type or n-type conductivity. The (100) plane or the (110) plane may be exposed on the surface of Si substrate 1.
  • SiC layer 2 is formed on the surface of Si substrate 1. SiC layer 2 comprises of 3C-SiC, 4H-SiC, 6H-SiC, or the like. In particular, when SiC layer 2 was made by epitaxial growth on the surface of Si substrate 1, SiC layer 2 typically comprises of 3C-SiC.
  • SiC layer 2 may be formed by homoepitaxial growth of SiC, by using the MBE (Molecular Beam Epitaxy) method, the CVD (Chemical Vapor Deposition) method, the LPE (Liquid Phase Epitaxy) method, or the like, on the foundation layer which comprises of SiC obtained by carbonizing of the surface of Si substrate 1. SiC layer 2 may be formed only by carbonizing of the surface of Si substrate 1. Further, SiC layer 2 may be formed by heteroepitaxial growth on the surface of Si substrate 1 (a buffer layer may be interposed).
  • SiC layer 2 may be changed to an n-type or a p-type. As impurity (dopant) for making SiC layer 2 the p-type, at least one of B (boron), Al (aluminium), Ga (gallium), and In (indium) can be used, for example. As impurity for making SiC layer 2 the n-type, at least one of N (nitrogen), P (phosphorus), and As (arsenic) can be used, for example. To control carrier density of the p-type and the n-type, transition elements such as V (vanadium) may be used for doping.
  • AlN layer 3 is formed on the surface of SiC layer 2. AlN layer 3 acts as a buffer layer to alleviate difference between the lattice constant of SiC layer 2 and the lattice constant of GaN layer 4. AlN layer 3 is formed by using the MOCVD (Metal Organic Chemical Vapor Deposition) method, for example. The growth temperature of AlN layer 3 is more than or equal to 1100 degree Celsius and equal to or less than 1300 degree Celsius, for example. At this time, as Al source gas, TMA (Tri Methyl Aluminium), TEA (Tri Ethyl Aluminium), or the like is used, for example. As N source gas, NH3 (ammonia) is used, for example. The thickness of AlN layer 3 is preferably more than or equal to 10nm and equal to or less than 500nm.
  • AlN layer 3 may be an AlaInbGa1-a-bN layer (0<a ≦ 1, 0 ≦ b<1, 0 ≦ 1-a-b<1, a>b, a>1-a-b) by replacing part of Al atoms with at least one of In atoms and Ga atoms (However, the compositional ratio of In should not exceed the compositional ratio of Al). AlN layer 3 may be an AlaGa1-aN layer (0<a ≦ 1, a>1-a), by replacing part of Al atoms with Ga atoms. To maintain the crystalline quality of GaN layer 4, the AlaInbGa1-a-bN layer is preferably an AlN layer (It is better not to replace Al atoms with In atoms and Ga atoms).
  • Composite layers 6a, 6b and 6c are formed on the surface of SiC layer 2, in this order. Each of composite layers 6a, 6b and 6c includes a GaN layer and an AlN layer. GaN layer 4a of composite layer 6a is formed on the surface of AlN layer 3. AlN layer 5a of composite layer 6a is formed on the surface of GaN layer 4a. GaN layer 4b of composite layer 6b is formed on the surface of AlN layer 5a. AlN layer 5b of composite layer 6b is formed on the surface of GaN layer 4b. GaN layer 4c of composite layer 6c is formed on the surface of AlN layer 5b. AlN layer 5c of composite layer 6c is formed on the surface of GaN layer 4c.
  • In the following explanations, any one of GaN layers 4a, 4b and 4c may be referred to as GaN layer 4. Any one of AlN layers 5a, 5b and 5c may be referred to as AlN layer 5. Any of composite layers 6a, 6b and 6c may be referred to as composite layer 6. The composite semiconductor substrate should have at least one composite layer 6. The composite semiconductor substrate preferably has more than or equal to 1 and equal to or less than 9 composite layers. The composite semiconductor substrate more preferably has a plurality of composite layers (more than or equal to 2 and equal to or less than 9 layers). The composite semiconductor substrate furthermore preferably has more than or equal to 3 and equal to or less than 6 composite layers.
  • The thickness of GaN layer 4 is preferably more than or equal to 50nm and equal to or less than 5µm. Herewith, inhibiting warpage of the substrate, a high quality GaN layer can be obtained.
  • GaN layer 4a is formed by using the MOCVD method, for example, in the following manner. Firstly, three-dimensional nuclei of GaN crystal are formed at predetermined density. Next, the three-dimensional nuclei of GaN crystal are grown in the horizontal direction at a temperature lower than the growth temperature of AlN layer 5 to form a continuous GaN single-crystal film. At this time, as Ga source gas, TMG (Tri Methyl Gallium), TEG (Tri Ethyl Gallium), or the like is used, for example. As N source gas, NH3 is used, for example.
  • Further, each of GaN layers 4b and 4c (the GaN layer other than GaN layer 4a) is formed by using the MOCVD method, for example, in the following manner. A continuous GaN single-crystal film is formed by two dimensions nucleus growth (coherent growth), at a temperature lower than the growth temperature of AlN layer 5. At this time, as Ga source gas, TMG, TEG, or the like is used, for example. As N source gas, NH3 is used, for example.
  • The process temperature in the step for forming the three-dimensional nucleus, the step for growing three-dimensional nucleus of GaN crystals in the horizontal direction, and the step for the two dimensions nucleus growth (the growth temperature of GaN layer 4) is higher than the growth temperature of AlN layer 5. The growth temperature of GaN layer 4 is more than or equal to 900 degree Celsius and equal to or less than 1200 degree Celsius, for example.
  • GaN layer 4 may be an AlvInwGa1-v-wN layer (0 ≦ v ≦ 0.3, 0 ≦ w ≦ 0.4, v<a, 1-a-b<1-v-w), by replacing part of Ga atoms with at least one of Al atoms and In atoms. GaN layer 4 may be AlvGa1-vN layer (0 ≦ v ≦ 0.3, v<a, 1-a-b<1-v) by replacing part of Ga atoms with Al atoms. However, to maintain crystalline quality of GaN layer 4, an AlvInwGa1-v-wN layer is preferably a GaN layer (It is better not to replace Ga atoms with Al atoms and In atoms).
  • AlN layer 5 fulfills the function for suppressing the occurrence of warpage. When AlN layer 5 is sandwiched by two GaN layers 4, AlN layer 5 fulfills the function for alleviating stress between the two GaN layers 4. AlN layer 5 is formed by using the MOCVD method, for example. The growth temperature of AlN layer 5 is lower than the growth temperature of AlN layer 3, and is more than or equal to 800 degree Celsius and equal to or less than 1200 degree Celsius, for example. At this time, as Al source gas, TMA, TEA, or the like is used, for example. As N source gas, NH3 is used, for example. The thickness of AlN layer 5 is preferably more than or equal to 10nm and equal to or less than 500nm. Herewith, dislocation formed in AlN layer 5 is reduced, and the crystalline quality of GaN layer 4 can be improved. In addition, the time required for forming AlN layer 5 can be shorten.
  • AlN layer 5 may be an AlxInyGa1-x-yN layer (v<x ≦ 1, 0 ≦ y<1, 0 ≦ 1-x-y<1, 1-x-y<1-v-w, c<x, 1-x-y<1-c-d, x>y, x>1-x-y), by replacing part of Al atoms with at least one of In atoms and Ga atoms (However, the compositional ratio of In should not exceed the compositional ratio of Al). AlN layer 5 may be an AlxGa1-xN layer (v<x ≦ 1, 0<x ≦ 1, 1-x<1-v, c<x, 1-x<1-c-d), by replacing part of Al atoms with Ga atoms. However, to maintain the crystalline quality of GaN layer 4, an AlxInyGa1-x-yN layer is preferably an AlN layer (It is better not to replace Al atoms with In atoms and Ga atoms).
  • When GaN layer 4 is an AlvInwGa1-v-wN layer, and AlN layer 5 is an AlxInyGa1-x-yN layer, the compositional ratio of Al in the AlxInyGa1-x-yN layer is higher than the compositional ratio of Al in the AlvInwGa1-v-wN layer (namely, v<x), and the compositional ratio of Ga in the AlxInyGa1-x-yN layer is lower than the compositional ratio of Ga in the AlvInwGa1-v-wN layer (namely, 1-x-y<1-v-w).
  • The lattice constant of AlN and the lattice constant of GaN are very close, and the lattice constant of AlN is smaller than the lattice constant of GaN. When the AlN layer was formed on the GaN layer as a foundation, the AlN layer does not take over the crystal structure of the foundation GaN layer. Slip occurs at the interface between the AlN layer and the GaN layer. On the other hand, when a GaN layer is formed on an AlN layer as a foundation, the GaN layer grows coherently with respect to the foundation AlN layer, and compression stress occurs in the GaN layer, being subject to the influence of the lattice constant of the AlN layer. In consequence, the occurrence of cracks in the GaN layer and warpage are suppressed. In addition, the quality of the crystals of GaN layer 4 and AlN layer 5 can be improved, by forming AlN layer 3, GaN layer 4, and AlN layer 5 on the surface of SiC layer 2, under the above mentioned growth condition.
  • In at least one of composite layers 6, the average density of C and Fe in GaN layer 4 is higher than the average density of C and Fe in AlN layer 5.
  • In at least one of composite layers 6, the average density of C and Fe in GaN layer 4 is preferably more than or equal to 1*1018 atoms / cm3, is more preferably more than or equal to 3*1018 atoms / cm3, and is furthermore preferably more than or equal to 5*1018 atoms / cm3. Herewith, the resistor of GaN layer 4 can be increased greatly, so that the voltage withstanding can be improved. On the other hand, in at least one of composite layers 6, the average density of C and Fe in GaN layer 4 is preferably equal to or less than 1*1020 atoms / cm3, is more preferably equal to or less than 1*1019 atoms / cm3. Herewith, crystalline quality degradation of GaN layer 4 can be suppressed. GaN layer 4 in at least one of composite layers 6 preferably includes C.
  • The average density of C and Fe means the average value of the density distribution of the sum total of C and Fe in the normal direction (the depth direction) of the surface of Si substrate 1 in the layers. The density distribution of C and Fe in the normal direction of the surface of Si substrate 1 in the layers can be measured by using SIMS (Secondary Ion Mass Spectrometry).
  • GaN layer 4 is doped with C in the following manner, for example. When forming GaN layer 4 doped with C in a positive manner by using the MOCVD method, the film forming temperature and the formed film pressure different from the case in which a film of a GaN layer not being doped with C in a positive manner are adopted. Then, GaN layer 4 is doped with C included in Ga organic metal. GaN layer 4 may be doped with C, by introducing organic gas into the chamber in which the MOCVD is performed. C ions may be injected into GaN layer 4.
  • GaN layer 4 is doped with Fe, in the following manner, for example. When GaN layer 4 is formed by using the MOCVD method, GaN layer 4 is doped with Fe, by introducing Fe organic metal into the chamber in which the MOCVD is performed. Fe ions may be injected into GaN layer 4.
  • Since O (oxygen) has a harmful effect on the crystalline quality of the GaN layer, it is preferable that GaN layer 4 does not include O.
  • GaN layer 7 is formed on the surface of composite layer 6c. Impurity was not introduced to GaN layer 7, and GaN layer 7 acts as an electron transition layer of the HEMT. GaN layer 7 is formed in a manner similar to GaN layer 5.
  • AlGaN layer 8 is formed on the surface of GaN layer 7. AlGaN layer 8 has n-type conductivity, and is a barrier layer of the HEMT. AlGaN layer 8 is formed by the MOCVD method or the like, for example.
  • Source electrode 11, drain electrode 12, and gate electrode 13 are formed on the surface of AlGaN layer 8, being spaced apart from each other. Source electrode 11 and drain electrode 12 are placed in ohmic contact with AlGaN layer 8. Gate electrode 13 is placed in schottky contact with Al GaN layer 8. Source electrode 11 and drain electrode 12 have a structure in which a Ti (titanium) layer and an Al (aluminium) layer are laminated in the order from the side of AlGaN layer 8, for example. The gate electrode 13 has a structure in which an Ni (nickel) layer and an Au (gold) layer are laminated in the order from the side of AlGaN layer 8, for example. Source electrode 11, drain electrode 12, and gate electrode 13 are formed by a deposition method, a MOCVD method, a sputtering method, or the like, for example.
  • The HEMT according to the embodiment works, as follows. Due to the band gap difference between GaN layer 7 and AlGaN layer 8, electrons occurred in AlGaN layer 8 gather at the heterojunction interface of GaN layer 7 and Al GaN layer 8, and form the two dimensions electron gas. In line with the forming the two dimensions electron gas, AlGaN layer 8 completely becomes a depletion layer by the depletion layer extending upwardly from the heterojunction interface with GaN layer 7 in Figure 1 and the depletion layer extending downwardly from the joint interface with gate electrode 13 in Figure 1.
  • When positive electrical voltage is applied to gate electrode 13 and drain electrode 12, in a state in which source electrode 11 is kept at the ground potential, the two dimensions electron gas density increases by the electrical field effect, so that electrical current flows from drain electrode 12 to source electrode 11.
  • According to the composite semiconductor substrate of this embodiment, since AlN layer 3 is formed on the surface of SiC layer 2, and GaN layer 4 is formed on the surface of AlN layer 3, the quality of the GaN layer 4 crystal can be improved. Since the average density of C and Fe in GaN layer 4 is high, in at least one of composite layers 6, the electrical resistance of the GaN layer 4 increases, and the voltage withstanding of the composite semiconductor substrate can be improved. Further, since the average density of C and Fe in AlN layer 5 is low, in at least one of composite layers 6, the quality of the GaN layer 4 crystal formed on the surface can be improved. More specifically, if the average density of C and Fe in AlN layer 5 is high, smoothness of the surface of AlN layer 5 degrades, and compression force does not act on GaN layer 4 formed on the surface of AlN layer 5. In consequence, cracks and warpage are likely to occur in GaN layer 4 formed on the surface of AlN layer 5. The occurrence of cracks and warpage in GaN layer 4 results in deterioration of quality in layers formed at the surface side of the GaN layer 4. To maintain smoothness on the surface of AlN layer 5, it is necessary to decrease the average density of C and Fe in AlN layer 5, if at all possible.
  • Since electrical resistance of an AlN layer is high when compared to a GaN layer, even though an AlN layer is doped with C or Fe in a positive manner, the effect of improving voltage withstanding is small. Therefore, it is better not to dope AlN layer 3 with C or Fe in a positive manner.
  • Next, examples of the density distribution of C and Fe in the composite layer will be explained.
  • Figure 2 shows a graph indicating the first example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • Referring to Figure 2, according to this example, in all the composite layers 6a, 6b and 6c, the average density of C and Fe in each of GaN layers 4a, 4b and 4c is higher than the average density of C and Fe in each of AlN layers 5a, 5b and 5c. The density of C and Fe in the inner part of each of GaN layers 4a, 4b and 4c is a constant value (density C1), regardless of the distance from the surface of Si substrate 1. The average densities of C and Fe in GaN layers 4a, 4b and 4c are all density C1. The density of C and Fe in each of AlN layers 5a, 5b and 5c is a constant value (density C11), regardless of the distance from the surface of Si substrate 1. The average densities of C and Fe in AlN layers 5a, 5b and 5c are all density C11 (<C1).
  • According to this example, a composite layer in which the density distribution of C and Fe is uniform, can be formed.
  • Figure 3 shows a graph indicating the second example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • Referring to Figure 3, according to this example, in each of composite layers 6a and 6b, the average density of C and Fe in each of GaN layers 4a and 4b is higher than the average density of C and Fe in each of AlN layers 5a and 5b. On the other hand, in composite layer 6c, the average density of C and Fe in GaN layer 4c is lower than the average density of C and Fe in AlN layer 5c. The density of C and Fe in the inner part of each of GaN layers 4a, 4b and 4c is a constant value, regardless of the distance from the surface of Si substrate 1. The density of C and Fe in each of AlN layers 5a, 5b and 5c is a constant value (density C11), regardless of the distance from the surface of Si substrate 1. The average densities of C and Fe in AlN layers 5a, 5b and 5c are all density C11 (C3<C11<C2).
  • The average density of C and Fe in each of GaN layers 4a, 4b and 4c decreases from GaN layer 4a nearest from SiC layer 2 toward GaN layer 4c farthest from SiC layer 2. More specifically, the average density of C and Fe in GaN layer 4a is density C1. The average density of C and Fe in GaN layer 4b is density C2 (<C1). The average density of C and Fe in GaN layer 4c is density C3 (<C2).
  • According to this example, GaN layer 4 (mainly, GaN layer 4a) close to SiC layer 2 plays a role of improving the voltage withstanding, and GaN layer 4 (mainly, GaN layer 4c) away from SiC layer 2 play a role of improving the crystalline quality of GaN layer 4. In consequence, both the voltage withstanding and the crystalline quality can be improved in an effective manner.
  • The average densities of C and Fe in AlN layers 5a, 5b and 5c may decrease from AlN layer 5a nearest from SiC layer 2 toward AlN layer 5c farthest from SiC layer 2.
  • Figure 4 shows a graph indicating the third example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention.
  • Referring to Figure 4, according to this example, the density of C and Fe in the inner part of each of GaN layers 4a, 4b and 4c changes from the reverse side (the side close to Si substrate 1) toward the surface side (the side away from Si substrate 1). More specifically, the density of C and Fe in GaN layer 4a decreases from the reverse side to the surface side, from density C1A to density C1B (<C1<C1A). The density of C and Fe in GaN layer 4b decreases from the reverse side to the surface side, from density C2A to density C2B (<C2<C2A). The density of C and Fe in GaN layer 4c decreases from the reverse side to the surface side, from density C3A to density C3B (<C3<C3A).
  • The average densities of C and Fe of GaN layers 4a, 4b and 4c decrease from GaN layer 4a nearest from SiC layer 2 toward GaN layer 4d farthest from SiC layer 2. More specifically, the average density of C and Fe in GaN layer 4a is density C1. The average density of C and Fe in GaN layer 4b is density C2 (<C1). The average density of C and Fe in GaN layer 4c is density C3 (<C2). The densities of C and Fe of AlN layers 5a, 5b and 5c are a constant value (density C11), regardless of the distance from the surface of Si substrate 1. The average densities of C and Fe in AlN layers 5a, 5b and 5c are all density C11 (C3<C11<C2).
  • According to this example, the effect similar to the second example can be obtained, and the density distribution of C and Fe in the inner part of GaN layer 4 can fluctuate.
  • The density of C and Fe in the inner part of each of AlN layers 5a, 5b and 5c may be changed from the reverse side (the side closed to Si substrate 1) to the surface side (the side away from Si substrate 1).
  • Figure 5 shows a graph indicating the fourth example of relationship between the distance from the Si substrate surface and the density of C and Fe in the composite layer, according to the composite semiconductor substrate of the first embodiment of this invention. In Figure 5, only the density distribution of C and Fe in GaN layer 4a is selectively indicated.
  • Referring to Figure 5, according to this example, GaN layer 4a consists of a plurality of layers of which the densities of C and Fe are different from each other. GaN layer 4a includes the first layer 31, the second layer 32, and the third layer 33. The second layer 32 is formed on the surface of the first layer 31. The third layer 33 is formed on the surface of the second layer 32. The density of C and Fe in the inner part of each of the first layer 31, the second layer 32, and the third layer 33 is a constant value, regardless of the distance from the surface of Si substrate 1. The average density of C and Fe in the second layer 32 is density C4. The average density of C and Fe in each of the first layer 31 and the third layer 33 is density C5 (<C4). The average density of C and Fe in GaN layer 4a is C1 (C5<C1<C4, C11<C1).
  • According to this example, the second layer 32 plays a role of improving the voltage withstanding, and each of the first layer 31 and the third layer plays a role of smoothing the boundary face with AlN layers 3 and 5a. In consequence, both the voltage withstanding and the crystalline quality can be improved in an effective manner, and the occurrence of warpage and cracks can be suppressed in an effective manner.
  • In this example, each of GaN layer 4b and 4c may have the density distribution of C and Fe similar to the density distribution of C and Fe of the inner part of GaN layer 4a, and may have the density distribution of C and Fe different from the density distribution of C and Fe of the inner part of GaN layer 4a. AlN layer 5 may be formed by a plurality of layers of which the densities of C and Fe are different from each other, as similar to GaN layer 4a.
  • [The second embodiment]
  • Figure 6 shows a cross section view of a structure of a composite semiconductor substrate, according to the second embodiment of this invention.
  • Referring to Figure 6, the composite semiconductor substrate according to the embodiment is different from the composite semiconductor substrate of the first embodiment, in the sense that it is equipped with SOI substrate 1 as substitute for a Si substrate. An SOI substrate is a substrate of a single-crystal Si, formed on an insulating film. SOI substrate 1 includes Si substrate 21, SiO2 (silicon dioxide) layer 22, and SOI layer 23. On the surface of Si substrate 21, SiO2 layer 22 is formed. On the surface of SiO2 layer 22, SOI layer 23 consist of Si is formed. SOI substrate 1 is made by an arbitrary method.
  • Since the structures of the composite semiconductor substrate according to the embodiment other than the above mentioned and the density distribution of C and Fe in the composite layers and so on are similar to the composite semiconductor substrate according to the first embodiment, the same numerals are provided for same components, and the explanations are not repeated.
  • According to this embodiment, by adopting SOI substrate 1 as a foundation of SiC layer 2, the junction capacitance of the composite semiconductor substrate can be smaller, and the voltage withstanding can be improved.
  • [Others]
  • When a composite semiconductor substrate has a plurality of composite layers 6, and a layer corresponds to GaN layer 4 in each of the plurality of composite layers 6 consists of an AlvInwGa1-v-wN layer (0 ≦ v ≦ 0.3, 0 ≦ w ≦ 0.4, v<a, 1-a-b<1-v-w), the compositional ratio of each of Al, In, and Ga in one AlvInwGa1-v-wN layer in the plurality of composite layer 6 and the compositional ratio of each of Al, In, and Ga in another AlvInwGa1-v-wN layer in the plurality of composite layer 6 may be different with each other. When a layer corresponds to AlN layer 5 in each of a plurality of composite layer 6 consists of an AlxInyGa1-x-yN layer (v<x ≦ 1, 0 ≦ y <1, 0<x+y ≦ 1, 1-x-y<1-v-w, c<x, 1-x-y<1-c-d), the compositional ratio of each of Al, In, and Ga in one AlxInyGa1-x-yN layer in the plurality of composite layer 6 and the compositional ratio of each of Al, In, and Ga in another AlxInyGa1-x-yN layer in the plurality of composite layer 6 may be different with each other.
  • A device formed on the composite semiconductor substrate is an arbitrary device, and it may be a transistor, an LED (Light Emitting Diode), a thyristor, a semiconductor laser, or the like, other than the above mentioned device. The composite semiconductor substrate may be a substrate in which the magnitude of the electrical current flows between the first electrode and the second electrode formed at the surface side of the AlxInyGa1-x-yN layer depends on the electrical voltage between the first electrode and the second electrode.
  • Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustrated and example only and is not to be taken by way limitation, the scope of the present invention being interpreted by terms of the appended claims.
  • [Explanation of referential numerals]
  • 1
    Si (silicon) substrate or SOI (Silicon On Insulator) substrate
    2
    SiC layer
    3, 5, 5a, 5b, 5c
    AlN (aluminum nitride) layer
    4, 4a, 4b, 4c, 7
    GaN (gallium nitride) layer
    6, 6a, 6b, 6c
    composite layer
    8
    AlGaN (aluminum nitride gallium) layer
    11
    source electrode
    12
    drain electrode
    13
    gate electrode
    21
    Si substrate
    22
    SiO2 (oxidized silicon) layer
    23
    Si layer
    31
    the first layer
    32
    the second layer
    33
    the third layer

Claims (13)

  1. A composite semiconductor substrate comprising:
    an Si substrate or an SOI (Silicon On Insulator) substrate,
    an SiC layer formed on a surface of the substrate,
    an AlaInbGa1-a-bN layer (0<a ≦ 1, 0 ≦ b<1, 0 ≦ 1-a-b<1, a>b, a>1-a-b) formed on a surface of the SiC layer,
    a composite layer formed on a surface of the AlaInbGa1-a-bN layer, and
    an AlcIndGa1-c-dN layer (0 ≦ c ≦ 0.3, 0 ≦ d ≦ 0.4, c<a, 1-a-b<1-c-d) formed on a surface of the composite layer, wherein
    the composite layer includes an AlvInwGa1-v-wN layer (0 ≦ v ≦ 0.3, 0 ≦ w ≦ 0.4, v<a, 1-a-b<1-v-w) and an AlxInyGa1-x-yN layer (v<x ≦ 1, 0 ≦ y<1, 0 ≦ 1-x-y<1, 1-x-y<1-v-w, c<x, 1-x-y<1-c-d, x>y, x>1-x-y) formed on a surface of the AlvInwGa1-v-wN layer, and
    an average density of C and Fe in the AlvlnwGa1-v-wN layer is higher than an average density of C and Fe in the AlxInyGa1-x-yN layer in at least one the composite layer.
  2. The composite semiconductor substrate according to claim 1, wherein
    number of the composite layers is more than or equal to 1 and equal to or less than 9.
  3. The composite semiconductor substrate according to claim 2, wherein
    the number of the composite layers is plural, and
    the AlvInwGa1-v-wN layer in at least one of the plurality of the composite layers includes C.
  4. The composite semiconductor substrate according to claim 3, wherein
    average densities of C and Fe in the AlvInwGa1-v-wN layers in the plurality of composite layers decrease from the AlvInwGa1-v-wN layer nearest the SiC layer toward the AlvInwGa1-v-wN layer farthest from the SiC layer.
  5. The composite semiconductor substrate according to claim 3, wherein
    the number of the composite layers is more than or equal to 3 and equal to or less than 6.
  6. The composite semiconductor substrate according to claim 3, wherein
    a compositional ratio of each of Al, In, and Ga of one AlvInwGa1-v-wN layer in the plurality of composite layers and a compositional ratio of each of Al, In, and Ga of another AlvInwGa1-v-wN layer in the plurality of composite layers are different from each other, and
    a compositional ratio of each of Al, In, and Ga of one AlxInyGa1-x-yN layer in the plurality of composite layers and a compositional ratio of each of Al, In, and Ga of another AlxInyGa1-x-yN layer in the plurality of composite layers are different from each other.
  7. The composite semiconductor substrate according to claim 1, wherein
    an average density of C and Fe in the AlvInwGa1-v-wN layer of at least one of the composite layers is more than or equal to 1*1018 atoms / cm3 and equal to or less than 1*1020 atoms / cm3.
  8. The composite semiconductor substrate according to claim 7, wherein
    the average density of C and Fe in the AlvInwGa1-v-wN layer of at least one of the composite layers is more than or equal to 3*1018 atoms / cm3 and equal to or less than 1*1019 atoms / cm3.
  9. The composite semiconductor substrate according to claim 1, wherein
    a density of C and Fe in an inner part of the AlvInwGa1-v-wN layer in at least one of the composite layers changes from a side close to the SiC layer toward a side away from the SiC layer.
  10. The composite semiconductor substrate according to claim 1, wherein
    the AlvInwGa1-v-wN layer in at least one of the composite layers includes a first layer, a second layer formed on a surface of the first layer, and a third layer formed on a surface of the second layer, and
    an average density of C and Fe in the second layer is higher than an average density of C and Fe in the first layer and an average density of C and Fe in the third layer.
  11. The composite semiconductor substrate according to claim 1, wherein
    the AlvInwGa1-v-wN layer is an AlvGa1-vN layer (0 ≦ v ≦ 0.3, v<a, 1-a-b<1-v), and the AlxInyGa1-x-yN layer is an AlxGa1-xN layer (v<x ≦ 1, 0<x ≦ 1, 1-x<1-v, c<x, 1-x<1-c-d, x>1-x).
  12. The composite semiconductor substrate according to claim 11, wherein
    the AlvInwGa1-v-wN layer is a GaN layer,
    the AlxInyGa1-x-yN layer is an AlN layer.
  13. The composite semiconductor substrate according to claim 1, further comprising:
    a first and a second electrodes formed at the surface side of the AlcIndGa1-c-dN layer, wherein
    magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.
EP16761353.8A 2015-03-09 2016-01-14 Compound semiconductor substrate Pending EP3270409A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015046375A JP6473017B2 (en) 2015-03-09 2015-03-09 Compound semiconductor substrate
PCT/JP2016/050987 WO2016143381A1 (en) 2015-03-09 2016-01-14 Compound semiconductor substrate

Publications (2)

Publication Number Publication Date
EP3270409A1 true EP3270409A1 (en) 2018-01-17
EP3270409A4 EP3270409A4 (en) 2018-11-21

Family

ID=56880187

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16761353.8A Pending EP3270409A4 (en) 2015-03-09 2016-01-14 Compound semiconductor substrate

Country Status (7)

Country Link
US (1) US10186421B2 (en)
EP (1) EP3270409A4 (en)
JP (1) JP6473017B2 (en)
KR (1) KR102573938B1 (en)
CN (1) CN107408511B (en)
TW (1) TWI712075B (en)
WO (1) WO2016143381A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3544045A4 (en) * 2016-11-18 2019-09-25 Air Water Inc. Compound semiconductor substrate manufacturing method and compound semiconductor substrate
CN113227467A (en) * 2018-12-25 2021-08-06 爱沃特株式会社 Compound semiconductor substrate
EP3913116A4 (en) * 2019-01-16 2022-03-09 Air Water Inc. Compound semiconductor substrate

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6781095B2 (en) 2017-03-31 2020-11-04 エア・ウォーター株式会社 Compound semiconductor substrate
JP6692334B2 (en) 2017-09-20 2020-05-13 株式会社東芝 Semiconductor substrate and semiconductor device
JP6812333B2 (en) * 2017-12-08 2021-01-13 エア・ウォーター株式会社 Compound semiconductor substrate
EP3503163A1 (en) * 2017-12-21 2019-06-26 EpiGan NV A method for forming a silicon carbide film onto a silicon substrate
JP6898222B2 (en) * 2017-12-27 2021-07-07 エア・ウォーター株式会社 Compound semiconductor substrate
CN113439342A (en) * 2019-02-01 2021-09-24 苏州晶湛半导体有限公司 Semiconductor structure and manufacturing method thereof
US20220020870A1 (en) * 2019-02-05 2022-01-20 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing semiconductor device
KR102518610B1 (en) * 2019-10-23 2023-04-05 미쓰비시덴키 가부시키가이샤 Semiconductor wafer and its manufacturing method
US20220328678A1 (en) * 2021-04-12 2022-10-13 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
JPWO2022219861A1 (en) * 2021-04-15 2022-10-20

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3752810B2 (en) * 1997-11-26 2006-03-08 昭和電工株式会社 Epitaxial wafer, manufacturing method thereof, and semiconductor device
JP4542912B2 (en) * 2005-02-02 2010-09-15 株式会社東芝 Nitrogen compound semiconductor device
JP5224311B2 (en) * 2007-01-05 2013-07-03 古河電気工業株式会社 Semiconductor electronic device
JP2010123725A (en) * 2008-11-19 2010-06-03 Sanken Electric Co Ltd Compound semiconductor substrate and semiconductor device using the same
JP2010232297A (en) * 2009-03-26 2010-10-14 Sumitomo Electric Device Innovations Inc Semiconductor device
JP5188545B2 (en) 2009-09-14 2013-04-24 コバレントマテリアル株式会社 Compound semiconductor substrate
JP5624940B2 (en) * 2011-05-17 2014-11-12 古河電気工業株式会社 Semiconductor device and manufacturing method thereof
JP5546514B2 (en) 2011-09-20 2014-07-09 古河電気工業株式会社 Nitride semiconductor device and manufacturing method
US8796738B2 (en) * 2011-09-21 2014-08-05 International Rectifier Corporation Group III-V device structure having a selectively reduced impurity concentration
JP6052570B2 (en) * 2012-02-28 2016-12-27 エア・ウォーター株式会社 Manufacturing method of semiconductor substrate
JP6002508B2 (en) 2012-09-03 2016-10-05 住友化学株式会社 Nitride semiconductor wafer
US9276066B2 (en) * 2012-09-25 2016-03-01 Fuji Electric Co., Ltd. Semiconductor multi-layer substrate and semiconductor element
JP2014072429A (en) * 2012-09-28 2014-04-21 Fujitsu Ltd Semiconductor device
US9245736B2 (en) * 2013-03-15 2016-01-26 Semiconductor Components Industries, Llc Process of forming a semiconductor wafer
US9748344B2 (en) * 2015-07-08 2017-08-29 Coorstek Kk Nitride semiconductor substrate having recesses at interface between base substrate and initial nitride
FR3041470B1 (en) * 2015-09-17 2017-11-17 Commissariat Energie Atomique SEMICONDUCTOR STRUCTURE HAVING IMPROVED TENSION
JP6465785B2 (en) * 2015-10-14 2019-02-06 クアーズテック株式会社 Compound semiconductor substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3544045A4 (en) * 2016-11-18 2019-09-25 Air Water Inc. Compound semiconductor substrate manufacturing method and compound semiconductor substrate
US11476115B2 (en) 2016-11-18 2022-10-18 Air Water Inc. Compound semiconductor substrate comprising a SiC layer
CN113227467A (en) * 2018-12-25 2021-08-06 爱沃特株式会社 Compound semiconductor substrate
EP3913116A4 (en) * 2019-01-16 2022-03-09 Air Water Inc. Compound semiconductor substrate

Also Published As

Publication number Publication date
JP6473017B2 (en) 2019-02-20
CN107408511B (en) 2021-01-08
US10186421B2 (en) 2019-01-22
TWI712075B (en) 2020-12-01
CN107408511A (en) 2017-11-28
KR20170122267A (en) 2017-11-03
KR102573938B1 (en) 2023-09-05
JP2016167517A (en) 2016-09-15
TW201707063A (en) 2017-02-16
EP3270409A4 (en) 2018-11-21
WO2016143381A1 (en) 2016-09-15
US20180053647A1 (en) 2018-02-22

Similar Documents

Publication Publication Date Title
US10186421B2 (en) Composite semiconductor substrate
US10211296B2 (en) P-doping of group-III-nitride buffer layer structure on a heterosubstrate
EP2498293B1 (en) Epitaxial substrate for semiconductor element and method for producing epitaxial substrate for semiconductor element
EP3366807B1 (en) Compound semiconductor substrate provided with sic layer
US10263094B2 (en) Nitride semiconductor device and process of forming the same
CN109564855B (en) Semiconductor material growth using ion implanted high resistivity nitride buffer layer
US20200402922A1 (en) Compound semiconductor substrate
US9401402B2 (en) Nitride semiconductor device and nitride semiconductor substrate
TWI791495B (en) Compound semiconductor substrate
US10186585B2 (en) Semiconductor device and method for manufacturing the same
US11476115B2 (en) Compound semiconductor substrate comprising a SiC layer
CN105957881A (en) AlGaN/GaN polarization doped field effect transistor with back barrier and manufacturing method of AlGaN/GaN polarization doped field effect transistor

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20170906

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20181018

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/02 20060101ALI20181012BHEP

Ipc: H01L 21/20 20060101ALI20181012BHEP

Ipc: H01L 21/205 20060101ALI20181012BHEP

Ipc: H01L 29/812 20060101ALI20181012BHEP

Ipc: H01L 29/778 20060101ALI20181012BHEP

Ipc: H01L 21/338 20060101AFI20181012BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20200812

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: AIR WATER INC.