EP3248291A1 - Multi-path, series-switched, passively-summed digital-to-analog converter - Google Patents
Multi-path, series-switched, passively-summed digital-to-analog converterInfo
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- EP3248291A1 EP3248291A1 EP16740716.2A EP16740716A EP3248291A1 EP 3248291 A1 EP3248291 A1 EP 3248291A1 EP 16740716 A EP16740716 A EP 16740716A EP 3248291 A1 EP3248291 A1 EP 3248291A1
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- Prior art keywords
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- signal
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- low
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/70—Automatic control for modifying converter range
Definitions
- the present invention relates to electronic devices, more particularly to digital-to- analog converters, and still more particularly to D-A conversion systems and methods which utilize multiple D-A converters and/or provide low noise and/or high dynamic range.
- Audio DAC digital-to-analog conversion
- the present invention seeks to greatly improve both dynamic range and self-noise of digital-to- analog conversion.
- the present invention improves today's DAC best dynamic range performance by roughly 4 bits while reducing broadband self-noise by roughly 15dB.
- a number of novel design techniques are combined and optimized, including DSP-controlled multi-path parallel conversion, ADC multi-path monitor and DSP compensation, DSP- managed passive summing and high-range series switching.
- ADC analog-to-digital conversion
- DSP- managed passive summing and high-range series switching.
- ADC analog-to-digital conversion
- multiple pre-adapted digital input signals may be processed according to alternative embodiments of the present invention.
- the present invention is directed to an apparatus for conversion of an input digital signal to an output analog signal having a maximum output level.
- the input digital signal is nominally a signal of K bits.
- the apparatus includes a bit grouping providing system which takes the input digital signal and produces a low-path digital signal of L bits and a high-path digital signal of H bits, where L + H is greater than or equal to J, and J is a number of bits of said input digital signal utilized by said bit divider where J is less than or equal to K.
- the apparatus includes a low-path digital-to-analog converter for digital inputs of R L bits or less, the low-path digital signal being bit shift mapped to an input of the low-path digital-to-analog converter where L is less than or equal to R L , and where the L bits of the low-path digital signal are level shift mapped upwards by L s bits where L + L s ⁇ R L .
- the low-path digital-to- analog converter produces a low-path digital-to-analog converter output signal.
- the apparatus includes a high-path digital-to-analog converter for digital inputs of R H bits, the high-path digital signal being digitally level shifted to an input of said high-path digital-to- analog converter by a bit shift of H s bits such that (K - H s ) ⁇ R H and (K - H - H s ) > 0.
- the high-path digital-to-analog converter produces a high-path digital-to-analog converter output signal.
- the apparatus further includes a low-path attenuator which attenuates the low-path digital-to-analog converter output signal to produce an attenuated low-path analog signal, and a high-path amplifier which amplifies the high-path digital-to-analog converter output signal to produce an amplified high-path signal having a maximum level equal to the maximum output level of the apparatus.
- the apparatus further includes a passive summing node which, if a signal level characteristic of the input digital signal exceeds a threshold level, sums a penultimate low-path signal derived from the attenuated low-path analog signal and a penultimate high-path signal derived from the amplified high-path signal to produce the output analog signal and, if the signal level characteristic of the input digital signal does not exceed said threshold level, utilizes a means to reduce access of noise from the high-path amplifier to the passive summing node.
- the present invention is also directed to an apparatus for conversion of an input digital signal to an output analog signal having a maximum output level, where the input digital signal is nominally a signal of K bits.
- the apparatus includes a bit grouping providing system which takes the input digital signal and produces a low-path digital signal of L bits, a middle-path digital signal of M bits, and a high-path digital signal of H bits, where L + M + H is greater than or equal to J, and J is a number of bits of said input digital signal utilized by said bit divider, where J is less than or equal to K.
- the apparatus includes a low-path digital- to-analog converter for digital inputs of R L bits or less.
- the low-path digital signal is digitally level shifted by the bit grouping providing system to an input of the low-path digital-to-analog converter, where L is less than or equal to R L , such that the L bits of the low-path digital signal are level shift mapped by L s bits, where L + L s ⁇ R L .
- the low-path digital-to-analog converter produces a low-path digital-to-analog converter output signal.
- the apparatus includes a middle-path digital-to-analog converter for digital inputs of R M bits or less.
- the middle-path digital signal is digitally level shifted by the bit grouping providing system to an input of the middle-path digital-to-analog converter, where M is less than or equal to R M .
- the middle-path digital-to-analog converter produces a middle-path digital-to- analog converter output signal.
- the apparatus also includes a high-path digital-to-analog converter for digital inputs of R H bits or less.
- the high-path digital signal is digitally level shifted by the bit grouping providing system to an input of the high-path digital-to-analog converter, where H is less than or equal to R H , such that the H bits of the high-path digital signal are level shift mapped downwards by L s bits, where (J - H s ) ⁇ R H .
- the high-path digital-to-analog converter produces a high-path digital-to-analog converter output signal.
- the apparatus further includes a low-path attenuator which attenuates the low-path digital-to- analog converter output signal to produce an attenuated low-path analog signal, and a high- path amplifier which amplifies the high-path digital-to-analog converter output signal to produce an amplified high-path signal having a maximum level equal to the maximum output level.
- the apparatus further includes a passive summing node which, if a signal level characteristic of the input digital signal exceeds a first threshold level, sums a penultimate low-path signal derived from the attenuated low-path analog signal, a penultimate middle- path signal derived from the middle-path digital-to-analog converter output signal, and a penultimate high-path signal derived from the amplified high-path signal to produce the output analog signal.
- a passive summing node which, if a signal level characteristic of the input digital signal exceeds a first threshold level, sums a penultimate low-path signal derived from the attenuated low-path analog signal, a penultimate middle- path signal derived from the middle-path digital-to-analog converter output signal, and a penultimate high-path signal derived from the amplified high-path signal to produce the output analog signal.
- the apparatus If the signal level characteristic of the input digital signal exceeds a second threshold level but not the first threshold level, the apparatus sums the penultimate low-path signal derived from said attenuated low-path analog signal and the penultimate middle-path signal derived from the middle-path digital-to-analog converter output signal to produce the output analog signal, and utilizes a means to reduce access of noise from the high-path amplifier to the passive summing node. And if the signal level characteristic of said input digital signal does not exceed the second threshold level, the apparatus utilizes a means to reduce access of noise from the middle-path digital-to-analog converter output signal and the high-path amplifier to the passive summing node.
- the present invention is also directed to an apparatus for conversion of an input digital signal to an output analog signal having a maximum output level, where the input digital signal is nominally a signal of K bits.
- the apparatus includes a bit grouping providing system which takes the input digital signal and produces a low-path digital signal of L bits, a number n of middle-path digital signals of M 1 , ... , M n bits, and a high-path digital signal of H bits, where h + M 1 + ... + M n + H is greater than or equal to J, and J is a number of bits of the input digital signal utilized by said bit divider, where J is less than or equal to K.
- the apparatus has a low-path digital-to-analog converter for digital inputs of R L bits or less, the low-path digital signal being digitally level shifted to an input of the low-path digital-to- analog converter, where L is less than or equal to R L , such that the L bits of the low-path digital signal are level shift mapped upwards by L s bits where L + L s ⁇ R L .
- the low-path digital-to-analog converter producing a low-path digital-to-analog converter output signal.
- the apparatus has n middle-path digital-to-analog converters for digital inputs of R M1 , . . . , R MJ!
- the middle-path digital signals being digitally level shifted to inputs of the middle-path digital-to-analog converter where M 1 ... M n are less than or equal to R M1 , . . . , R ⁇ , respectively.
- the middle-path digital-to-analog converters produce middle-path digital-to-analog converter output signals.
- the apparatus has a high-path digital-to-analog converter for digital inputs of R H bits, the high-path digital signal being digitally level shifted downwards to an input of the high-path digital-to-analog converter by a bit shift of H s bits such that (J - H s ) ⁇ R H .
- the high-path digital-to-analog converter produces a high-path digital-to-analog converter output signal.
- the apparatus includes a low-path attenuator which attenuates the low-path digital-to-analog converter output signal to produce an attenuated low-path analog signal, and a high-path amplifier which amplifies the high-path digital-to-analog converter output signal to produce an amplified high-path signal having a maximum level equal to the maximum output level.
- the apparatus has a passive summing node which, if a signal level characteristic of the input digital signal exceeds a highest threshold level, sums a penultimate low-path signal derived from the attenuated low-path analog signal, penultimate middle-path signals derived from the middle-path digital-to-analog converter output signals, and a penultimate high-path signal derived from the amplified high- path signal to produce the output analog signal. If the signal level characteristic of the input digital signal does not exceed a lowest threshold level, the apparatus utilizes a means to reduce access of noise from the middle-path digital-to-analog converter output signals and the high-path amplifier to the passive summing node.
- FIG 1A shows a schematic of a digital-to-analog converter which separates the processing of the most significant bits (MSB) and the least significant bits (LSB).
- Figure IB shows the separation of the bits of a 24-bit signal into a group of 13 least significant bits (LSB) and 13 most significant bits (MSB).
- Figure 2A shows a schematic of a digital-to-analog converter which separates the processing of the low-range signal, mid-range signal and high-range signal.
- Figure 2B shows the separation of the bits of a 32-bit signal into a group of 12 low- range bits, 13 mid-range bits, and 11 high-range bits by a digital signal processor.
- Figure 3A shows a two-path digital-to-analog conversion circuit according to the present invention.
- Figure 3B shows signal and noise levels at various points in the circuit of Figure 3A where the entire 32-bit digital input signal is utilized.
- Figure 3C shows signal and noise levels at various points in the circuit of Figure 3A where 30 bits of the 32-bit digital input signal is utilized.
- Figure 4 shows the separation of the bits of a 32-bit signal into a group of 12 low- range bits, 13 mid-range bits, and 11 high-range bits prior to input to a digital signal processor.
- Figure 5 shows a schematic of system which utilizes the present invention in the processing of sound captured by a low sound-pressure level microphone and a high sound- pressure level microphone.
- Figure 6A shows a three-path digital-to-analog conversion circuit according to the present invention.
- Figure 6B shows signal and noise levels at various points in the circuit of Figure 6A.
- Figure 6C shows an exemplary division of a 32 bit digital input signal into five digital portions.
- Figure 6D shows an instance where maximal numbers of bits are directed to the mid- path and high-path digital-to-analog converters.
- Figure 7 shows a calibration process for the circuit of Figure 3A.
- Figure 8 shows a calibration process for the circuit of Figure 6A.
- Figure 9 shows signal levels at various points in the circuit of Figure 6A when there is a -6dB shift in levels relative to those shown in Figure 6B.
- Figure 10 shows the interrelationship of key operational parameters.
- DACs digital-to-analog converters
- present invention improves certain performance characteristics, the primary objectives being the reduction of systemic noise and an increase in dynamic range.
- the circuit (100) shown in FIG. 1A shows the fundamental process and system on which the current invention is built upon.
- the circuit (100) of FIG. 1A performs a multi- range D-A conversion of a signal (101) (typically a PCM-encoded signal) which is sent (110) to a digital signal processor (DSP) (120) or any digital processing circuit capable of the necessary digital functions described herein.
- DSP digital signal processor
- the DSP (120) is designed or programmed to separate the inputted digital signal (110) into multiple sections. For instance, as shown in FIG. IB, the DSP (120) separates a 24-bit digital word (110) into two smaller contiguous data packets (111) and (112).
- the number of bits shown in the lowest significant bits (LSB) packet (111) and the most significant bits (MSB) packet (112) packets is an arbitrary example, and may vary depending upon specific design criteria.
- Each data packet (111) and (112) is sent to a digital-to-analog converter (DAC) (102) and (103), respectively, which is an integrated circuit or other manner or style of digital-to-analog converter.
- the lower DAC (102) is dedicated to the least significant bits (LSB) packet (111)
- the upper DAC (103) is dedicated to the most significant bits (MSB) packet (112).
- some bit overlap (which is facilitated by cross-fading, level-shifting or other adjustments, as described in detail below) may be used.
- each DAC (102) and (103) can be differential or single- ended, but is typically differential in integrated circuit DACs.
- the analog output of each DAC (102) and (103) is sent to an analog summing node (104) which recombines the outputs of the LSB DAC (102) and the MSB DAC (103) into a single analog signal.
- the method and system of the present invention is not limited to a two stage topology, but can be realized with any number of stages as is suggested by the dotted-line mid-level DAC (220) unit shown in FIG. 2A.
- a 32-bit PCM input signal (210) is separated into a three-stage topology.
- the DSP (202) separates the 32-bit digital word (210) in the incoming data stream into three smaller packets: a low-range packet (203), a mid-range packet (204), and high- range packet (205).
- the number of bits shown in the low-, mid-, and high-range packets (203), (204) and (205) is an arbitrary example, and may vary depending upon specific design criteria.
- Each data packet (203), (204) and (205) is sent to a DAC (206), (207) and (208), respectively, which is an integrated circuit or other manner or style of DAC irrespective of topology, whether signed, unsigned, twos-complement, or otherwise.
- DAC DAC
- FIG. 2B some bit overlap (which is facilitated by dynamic optimization, cross-fading, level- shifting or other adjustments, as described in detail below) may be used.
- the 11 th and 12 th bits of the input signal (210) are allocated to both the low-range packet (203) and the mid-range packet (204), and the 22 nd and 23rd bits of the input signal (210) are allocated to both the mid-range packet (204) and the high-range packet (205).
- each DAC (206), (207) and (208) can be differential or single- ended, but is typically differential in integrated circuit DACs.
- the analog output (236), (237) and (238) of each DAC (206), (207) and (208), respectively, is sent to an analog summing node (209) which combines the low-, mid-, and high-range analog signals into a single analog output signal (240).
- FIG. 3A provides a schematic of a two-path circuit (300) for a 32-bit signal according to a preferred embodiment of the present invention which provides increased systemic dynamic range and decreased baseline (i.e., no input signal) self-noise.
- the present invention employs a digital signal processing circuit (DSP) to partition pulse code modulated (PCM) data into multiple smaller "bit packets" of contiguous or slightly overlapping data which are processed along separate data "paths" to increase dynamic range relative to what is possible with single-path DACs.
- DSP digital signal processing circuit
- PCM pulse code modulated
- Each-path (referred to as low, mid, high, etc.) is optimized for a partial dynamic range of the original digital signal, and then, according to the present invention, the signals from the multiple paths are passively summed to provide the analog output.
- the input to the circuit (300) of FIG. 3A may be a single digital signal source (301), or multiple digital signal sources (301) and (340), (341), etc.
- DSP digital signal processor
- the analog output (343) and (344) of each DAC (303) and (304) is sent to an active analog amplifier (305) and (306), respectively.
- integrated circuit DAC outputs are differential, but the present invention is not limited to differential signal paths and can employ differential or single-ended signal paths.
- the amplifiers (305) and (306) can provide a number of critical functions, including but not limited to current-to- voltage conversion (IV conversion), high and/or low frequency filtering, DC servo, current buffering/current sourcing, voltage gain, and impedance buffering.
- critical requirements of these amplifiers (305) and (306) include sufficiently low noise, sufficiently low output impedance, sufficiently high output current, and sufficiently high output voltage to properly interface with a passive analog summing node (360) which combines the low-path and high-path signals into a single analog signal capable of driving real-world external devices (309) to a sufficiently high level and wide bandwidth, while maintaining sufficiently low noise and distortion.
- the passive analog summing could be implemented using an audio signal transformed s).
- the high-path output signal (335), the low-path output signal (336), and the summing node output signal (365) are assigned distinct reference numerals
- the high-path output signal (335) is the portion of the output signal (365) that is generated by the high-path circuitry (303), (305), and (307)
- the low-path output signal (336) is the portion of the output signal (365) that is generated by the low-path circuitry (304), (306), and (308).
- DAC unweighted audio spectrum noise floor
- any unmapped (i.e., not processed for instance according to the present invention) digital input level (361) below -112dBu cannot be effectively resolved at the DAC output (343) and (344) because such level is below the DACs' (303) and (304) residual broadband noise floors (
- each DAC (303) and (304) is effectively limited to 20-bit operation, specifically input bits 5-24 which corresponds to the range of -112dBu to +8dBu.
- amplifier output (354) exhibits a residual unity-gain audio spectrum broadband unweighted noise floor of -106dBu
- amplifier output (353) exhibits a maximum analog level of +32dBu with an audio spectrum broadband unweighted noise floor of -88dBu when configured at +30dB of gain.
- Level shift mapping of bits is defined in the present specification as where a contiguous group of bits is mapped such that all bits are shifted by the same mapping formula, i.e., the input bit is mapped to the ( ⁇ + ⁇ ) ⁇ output bit, where i is the amount of level shift applied. Equivalently, a level shift mapping can be thought of as a multiplication by X of the signal level where i is the amount of bit level shift applied. More generally, level shift mapping is not limited to integer-wide or bit-alignment shifts within a digital register, but may result from arithmetic multiplications wherein the coefficient of multiplication may be any value within the operational range of the digital signal processing.
- the mapping process requires that the DSP (302) performs a level shift on the high-path signal (333) and the low-path signal (334).
- the input (334) to the low-path DAC (304) is shifted up by +54dB by the DSP (302), such that an input level (361) of - 160dBu for the 32-bit DSP (302) is mapped to a level of -106dBu in terms of the 24-bit low-path DAC input (334), i.e., according to this preferred embodiment of the present invention the lowest bit of the input
- the low- path DAC (304) receives an 18-bit signal (334) representing signal levels at the input (361) to the DSP (302) from -160dBu to -52dBu, i.e., a signal (334) having 108dB of dynamic range.
- the 14 bits comprising the input (333) to the high-path DAC (303) represents signal levels from -52dBu to +32dbu, i.e., 84dB of dynamic range.
- the output (344) of low DAC (304) bit 23 has an analog level of +2dBu and has a broadband, unweighted noise floor ⁇ 1 1 ⁇ (346) of -112dBu.
- the output (343) of high DAC (303) bit 23 has an analog level of +2dBu and a broadband, unweighted noise floor ⁇ ⁇ (345) of -112dBu.
- the +2dBu signal level at the output (343) of the high-path DAC (303) represents a level of +32dBu at the input (361) to the DSP (302)
- a +2dBu signal level at the output (344) of the low-path DAC (304) represents a level (361) of -52dBu at the input (361) to the DSP (302).
- low-path amplifier (306) is configured to provide unity gain and therefore produces an output signal (354) having a maximum level equal to that of the input (344).
- high-path amplifier (305) is configured to provide +30dB of gain.
- the unity gain amplifier (306) has a broadband, unweighted self-noise (
- the high-path amplifier (305) produces a gain of 30dB and has -88dBu of broadband, unweighted self-noise (355).
- the high-path amplifier (305) amplifies an input signal (343) having a maximum level of +2dBu by +30dB to produce a maximum level of +32dBu at the output (353) of the high-path amplifier (305), and the amplifier's noise floor (355) of -88dBu is the noise floor (355) of the output signal (353).
- the output (353) of the high-path amplifier (305) is fed, via series switching element
- the series switching element (315) may follow the resistive element (307), so that the switching element (315) is connected between (307) and (335)).
- the series switching element (315) is controlled by a control signal (316) provided by the DSP (302).
- the output (354) of the low-path amplifier (306) is fed directly to a low-path passive resistive element RE1 (308).
- the resistive elements (307) and (308) may perform a number of functions, including signal attenuation, noise management, impedance
- resistive elements (307) and (308) have low series resistance and provide sufficiently low output impedance at (335) and (336) for proper summing of signals (335) and (336) at node (360).
- the resistive elements RE2 (307) and RE1 (308) both exhibit 200 ohm series resistance. Additional frequency filtering (such as high- pass and/or low-pass filtering) can be added to the high-path resistive elements (307) and (308) as may be required based on the particulars of the circuit (300) and the requirements of the external device (309).
- the low-path resistive element RE1 (308) produces -54dB of attenuation, provides 200 ohms series resistance, and provides for frequency filtering as may be required by the DAC (304).
- the high-path resistive element RE2 (307) exhibits no attenuation, provides 200 ohms series resistance, and provides for frequency filtering as may be required by the DAC (303).
- Other series resistance values can be employed in the resistive elements (307) and (308).
- a lower resistance will provide lower overall thermal noise but with a higher potential level loss, dependent upon the destination (309) impedance.
- a higher resistance will cause higher overall thermal noise but with a lower potential level loss, dependent upon the destination (309) impedance.
- V n (4 k B TfR) 112 (1.1)
- k B Boltzmann's Constant of 1.3806504x10 23 (joule/Kelvin)
- Tis absolute temperature in Kelvin /is the frequency bandwidth in Hz
- R is the value of the resistance in ohms.
- V ref unweighted noise
- the summation node (360) is a simple physical electrical connection of the output signals (335) and (336) from the resistive elements (307) and (308), respectively. With sufficiently high source currents at (353) and (354), and sufficiently low series resistances of the resistive elements (307) and (308), the summation of the high-path output (335) and the low-path output (336) will properly interface with real world devices (309) while maintaining low noise and high dynamic range, as will be further described below.
- the high-path switching element (315) under control of DSP (302) via control line (316) is held open (as is depicted in FIG. 3A).
- this switch (315) When this switch (315) is open, it creates an open-circuit at the input to high- path resistive element RE2 (307) resulting in effectively no thermal noise (337) from the resistive element RE2 (307) reaching the summing node (360).
- the only noise which is input to the summing node (360) is the thermal noise (338) generated by the low-path resistive element RE1 (308), plus any residual noise (356) generated by prior circuit elements, such as the low-path DAC (304) and low-path amplifier (306).
- the combined noise from the low-path DAC (304) and low-path amplifier (306) is attenuated down to -160dBu and can be neglected relative to the noise (338) of -130dBu (roughly the thermal noise of 200 ohms series resistance) from the low-path resistive element RE1 (308).
- the high-path amplifier (305) produces a gain of +30dB, and the self-noise (355) of the high-path amplifier (305) at +30dB gain is -88dBu.
- High-path resistive element RE2
- non-attenuated passive path which exhibits 200 ohms total series resistance (non-attenuated means, for example, that a +4dBu signal at the input will remain a +4dBu signal at the output when measured under no load).
- the DSP (302) sends a control signal (316) which causes high-path series switching element (315) to close (i.e., to switch to the position opposite that depicted in FIG. 3A).
- this switch closure occurs immediately before the DSP (302) begins to send high-path program signal to high-path DAC (303).
- a delay and look- ahead function could be used in the DSP (302), i.e., the input signal (361) could be slightly delayed in the DSP (302), for example on the order of a few milliseconds, while the DSP (302) determines in advance the optimal point of switch (315) closure, and activates such closure at a pre-determined optimum point.
- the high-path amplifier (305) produces +30dB of gain (which is apparent in FIG. 3B by the +30dB increase in the height of amplifier output signal (353) relative to the DAC output signal (343)) and has -88 dBu of unweighted broadband self-noise (355).
- the high- path amplifier (305) is followed by resistive element RE2 (307) which has 200 ohms total series resistance and -130 dBu of unweighted broadband self-noise.
- the total broadband unweighted audio path noise ⁇ ⁇ (337) at the output (335) of the resistive element RE2 (307) is also roughly -88dBu.
- the high- path amplifier (305) output signal (353) is switched by high-path switching element (315) into electrical connection with the summing node (360) when the low-path (336) program level at summing node (360) approaches or exceeds -52dBu, there exists at least a 30dB level difference (the level difference between -88dBu and -52dBu) between low-path-program level (336) and high-path noise level (337) when the high-path circuitry (303) and (305) is switched into electrical connection with the output node (360).
- the 30dB signal-to-noise difference provides a high degree of psychoacoustic masking to the -88 dBu broadband unweighted high-path noise level (360b) added by the closure of switch (315), making the noise (337) generated by the high-path components (303), (305), (307), and (315) generally making it psychoacoustically undetectable.
- This is an important aspect of the present invention. (It should be noted that because of the inherent difficulty, extracting objective baseline noise measurements from active audio program is generally not attempted. Broadband noise measurements are typically taken with no program present.)
- the total series resistance into the summing node (360) is 200 ohms, i.e., the inherent series resistance of low-path resistive element RE1 (308).
- the parallel resistances of low-path resistive element RE1 (308) and high-path resistive element RE2 (307) produce a total resistance at output node (360) of 100 ohms, i.e., the total resistance of RE1 (308) and RE2 (307) when connected in parallel.
- the DSP (302) adjusts its digital output levels (333) and (334) to compensate for any level shift of the summed output signal (365) produced by the ratio of the change in the total source resistance against the fixed destination impedance (309) as described below.
- the DSP calculates the amount of compensation required based on measurements it receives via ADCs (320), (325), and (330).
- the high-path switching element (315) is to be understood to represent any method or technique under DSP (302) control for removing the high-path output signal (335) from the summing node (360) in such a manner as to eliminate or significantly reduce the self-noise generated by the high-path components (303), (305), (307) .
- the high-path switching element (315) could be two discrete switching elements, with one switching element per each leg of the differential signal.
- high-path amplifier (305) may employ a selectable shut-down, mute or disable (etc.) function in which a design feature of the amplifier (305) itself allows selective (i.e., DSP (302) controlled) removal of signal and noise from the output (353) of the amplifier (305).
- the signal levels at the summing node (360), high-level amplifier output (353), and low-level amplifier output (344) are monitored by analog-to- digital converters (ADCs) (320), (325) and (330) when switched into monitoring via associated series-path switching elements (321), (326) and (331), respectively.
- ADCs analog-to- digital converters
- Each ADC device (320), (325) and (330) reports its analog input level to the DSP (302).
- the ADC level reporting is used by the DSP (302) to control the level of the output signals (333) and (334) to compensate for normal passive level losses and other losses or changes in output level.
- the DSP (302) will send (710) a steady-state AC signal, or a sequence of steady-state signals, of precisely known amplitude through both the high-path DAC (303) and the low-path DAC (304), while holding switching element (315) open (which is the position in which it is depicted in FIG 3).
- the DSP (302) will then send (715) a control signal via control line (322) to close switching element (321), and the DSP (302) will measure (717) the amplitude of the output signal (365) using ADC (320).
- the DSP (302) will then send (720) a control signal via control line (316) to close switching element (315), thereby changing the source impedance seen at summing node (360).
- the DSP (302) will again measure (722) the amplitude of the output signal (365) using ADC (320).
- the amplitude difference (if any) between the first and second measurements will be stored (725) in DSP (302) memory and used as a calibration factor to maintain linear performance in the course of impedance and resistance shifts due to the opening and closing of high-level switching element (315). If the external device (309) is changed, and especially if the destination (input) impedance of (309) is changed, this routine should be repeated to determine new calibration factors.
- the internal impedances of the ADCs (320), (325) and (330) are preferably at least ten times greater, more preferably at least twenty times greater, and still more preferably at least forty times greater than the internal impedances of the components (303)/(305)/(307), and (304) /(306) /(308) in the signal paths the ADCs (320), (325) and (330) are monitoring.
- ADC (325) and ADC (330) are used to compare measured amplitudes with expected amplitudes.
- the DSP (302) can send control signals via control lines (327) and (328) to close high-level and low-level monitoring switches (326) and (331) thereby connecting ADCs (325) and (330) to the outputs of the high-level and low-level amplifiers (305) and (306).
- the difference between the measured amplitude values provided by ADCs (325) and (330) and the expected values are used by the DSP (302) to gather correction/calibration factors.
- the measurements will typically be taken immediately at power-on with zero input program, but can also be taken during any sufficiently long period of zero input program.
- Switching elements (326) and (331) are used to completely remove the ADC inputs from the low-level and high-level circuit paths when not in use, thereby fully removing any potentially detrimental electrical issues.
- FIG. 6A provides a schematic of a three-path circuit (600) for a 32-bit signal according to a preferred embodiment of the present invention which-provides increased systemic dynamic range and decreased baseline (i.e., no input signal) self-noise.
- the circuit of FIG. 6A divides a 32-bit input signal (661) (corresponding to a signal range of 192 dB, which for the audio circuitry according to the preferred embodiment will be assigned the range of -160dBu to +32dBu) into three smaller words or bit packets, a low-path packet (605), and mid-path packet (606) and a high-path packet (608).
- the input to the circuit (600) of FIG. 6A may be a single digital signal source (601), or multiple digital signal sources (601) and (690), (691), etc.
- the digital signal source (601) or sources (601) and (690), (691), etc. are fed to a digital signal processor (DSP) (602) which divides the input signal into a high-path output (608), a mid-path output (606) and a low-path output (605), and directs them (608), (606) and (605) to a high-path DAC (613), a mid-path DAC (611), and a low-path DAC (610), respectively.
- DSP digital signal processor
- each DAC (613), (611) and (610) is sent to an active analog amplifier (623), (621) and (620), respectively.
- active analog amplifier (623), (621) and (620) can provide a number of critical functions, including but not limited to current-to-voltage conversion (IV conversion), high and/or low frequency filtering, DC servo, current buffering/current sourcing, voltage gain, and impedance buffering.
- critical requirements of these amplifiers (623), (621) and (620) include sufficiently low noise, sufficiently low output impedance, sufficiently high output current, and sufficiently high output voltage to properly interface with a passive analog summing node (651) which combines the low-path, mid-path and high-path signals into a single analog signal capable of driving typical external devices (660) to a sufficiently high level and wide bandwidth, while maintaining sufficiently low noise and distortion.
- a passive analog summing node 651 which combines the low-path, mid-path and high-path signals into a single analog signal capable of driving typical external devices (660) to a sufficiently high level and wide bandwidth, while maintaining sufficiently low noise and distortion.
- Such sufficient audio specifications will be generally understood by those skilled in the art of professional audio circuit design.
- circuit (600) of FIG. 6A which has three DACs (610), (611) and (613) which, as shown in the signal levels chart of FIG. 6B, can each accept a 24- bit input (605), (606) and (608), and can each produce a maximum analog level of +8dBu with a residual broadband, unweighted audio spectrum noise floor (615a), (616a) and (618a) of -112dBu, giving each DAC device (610), (611) and (613) a total potentially usable broadband, unweighted dynamic range of 120dB, i.e., 20 bits.
- any unmapped digital input level (661) below -112dBu cannot be effectively resolved at the DAC output (615), (616) or (618) because such level is below the DACs' (610), (611) and (613) residual broadband noise floor (615a), (616a) and (618a), respectively, of -112dBu.
- each DAC (610), (611) and (613) is effectively limited to 20-bit operation, specifically input bits 5-24 which corresponds to the range of -112dBu to +8dBu.
- amplifiers (620) and (621) provide a maximum analog output level (685) and (686) of +32dBu with a residual unity-gain audio spectrum broadband unweighted noise floor of -106dBu (685a) and (686a), and amplifier (623) provides a maximum analog output level (688) of +32dBu with a residual +24dB gain audio spectrum broadband unweighted noise floor of -98dBu (688a).
- any analog level (615) and (616) below -106dBu cannot be effectively resolved by amplifier devices (620) and (621), and any analog level (618) below roughly -98dBu cannot be effectively resolved by amplifier device (623) because such levels are below the amplifiers' (620), (621) and (623) respective residual broadband, unweighted, noise floors.
- the DSP divides a 32-bit PCM input (661) into a low-path DAC input signal (605), a mid-path DAC input signal (606) and a high-path DAC input signal (608).
- Source (601) input bits (661) 1 through 17 are mapped by the DSP (602) to input bits 6 through 22 of the input (605) to the low-path DAC (610), source (601) input bits (661) 18 through 24 are mapped by the DSP (602) to input bits 18 through 24 of the input (606) to the mid-path DAC (611), while source (601) input bits (661) 25 through 32 are mapped to input bits 17 through 24 of the input (608) to the high-path DAC (613).
- the mapping process requires that the DSP (602) performs a digital level shift on the high-path signal (608), the mid-path signal (606) and the low-path signal (605).
- the input (605) to the low-path DAC (610) is digitally level shifted by +54dB by the DSP (602), such that an equivalent input level (661) of -160dBu is mapped to a level of -106dBu at the low- path DAC input (334), i.e., the lowest bit of the input (605) to the low-path DAC (610) is mapped to just above the noise floor (615a) of the DAC (610).
- the input (606) to the mid-path DAC (611) is digitally level shifted by +24dB so that an input level (661) to the DSP (602) of -16dBu is mapped to a DAC signal level of +8dBu at the input (606) to the mid-path DAC (611).
- the input (608) to the high-path DAC (613) is digitally level shifted by -24dB so that an input level (661) to the DSP (602) of +32dBu is mapped to a DAC signal level of +8dBu at the input (608) to the high-path DAC (613).
- the low-path DAC (610) receives a 17-bit signal (605) representing signal levels at the input (661) to the DSP (602) from -160dBu to -58dBu, i.e., a signal (605) having 102dB of dynamic range.
- the 7-bit signal comprising the input (606) to the mid-path DAC (611) represents signal levels at the input (661) to the DSP (602) from -58dBu to -16dBu, i.e., 42dB of dynamic range.
- the 8-bit signal comprising the input (608) to the high-path DAC (613) represents signal levels at the input (661) to the DSP (602) from -16dBu to +32dBu, i.e., 48dB of dynamic range.
- the output (615) of low-path DAC (610) bit 22 exhibits a maximum level of -4dBu and a broadband, unweighted noise floor (615a) of -112dBu.
- the output (616) of mid-path DAC (611) bit 24 exhibits a maximum level of +8dBu and a broadband, unweighted noise floor (616a) of -112dBu.
- the output (618) of high-path DAC (613) bit 24 exhibits a maximum level of +8dBu and a broadband, unweighted noise floor (618a) of -112dBu.
- FIG. 6D is a particular example which illustrates the general fact that any number of bits up to the maximum input capacity of the DACs (610), (611) and (613) (which in the current preferred embodiment is 24 bits) can be transferred from the DSP (602) to low- path DAC (610), mid-path DAC (611), and high-path DAC (613).
- low-path amplifier (620) is configured to provide unity gain and therefore produces an output signal (685) having a maximum level (in dBu) equal to that of the input (615).
- the unity gain amplifier (620) has a broadband, unweighted self-noise (685a) of -106dBu.
- mid-path amplifier output (686) is configured to provide unity gain and therefore produces an output signal (686) having a maximum level (in dBu) equal to that of the input (616).
- the unity gain amplifier (621) has a broadband, unweighted self-noise of -106 dBu.
- high-path amplifier (623) is configured to provide +24dB of gain and therefore produces an output signal (688) having an amplitude 24dB higher than the input (618).
- the high-path amplifier (623) configured with a gain of +24dB, exhibits a broadband, unweighted self-noise (688a) of -98dBu. Therefore, as shown in FIG.
- the high-path amplifier (623) amplifies an input signal (618) having a maximum level of +8dBu by 24dB to produce a maximum level of +32dBu at the output (688) of the high-path amplifier (623), and the amplifier's noise floor of -98dBu is the noise floor (688a) of the output signal (688).
- the output (688) of the high-path amplifier (623) is fed, via series switching element (681), to a high-path-passive resistive element RES (633) (in an alternative embodiment of the invention, not shown in FIG. 6A, the series switching element (681) may follow the resistive element (633), so that the switching element (681) is connected between (633) and (643)).
- the series switching element (681) is controlled by a control signal (682) provided by the DSP (602).
- the output (686) of the mid-path amplifier (621) is fed directly to the mid- path passive resistive element RE2 (631).
- the output (685) of the low-path amplifier (620) is fed directly to the low-path passive resistive element RE1 (630).
- the resistive elements can perform a number of functions, including signal attenuation, noise management, impedance management, and frequency filtering.
- high-path resistive element (633) provides a low series resistance, provides sufficiently low output impedance at (643) for proper summing of signals (643), (641) and (640) at node (651), and provides for frequency filtering as may be required by DAC (613).
- the mid-path resistive element (631) provides a low series resistance, provides sufficiently low output impedance at (641) for proper summing of signals (643), (641) and (640) at node (651), and provides for frequency filtering as may be required by DAC (611).
- FIG. 6A high-path resistive element (633) provides a low series resistance, provides sufficiently low output impedance at (643) for proper summing of signals (643), (641) and (640) at node (651), and provides for frequency filtering as may be required by DAC (611).
- the low-path resistive element (630) provides a low series resistance, provides sufficiently low output impedance at (640) for proper summing of signals (643), (641) and (640) at node (651), and provides for frequency filtering as may be required by DAC (610).
- the high-path resistive element RE3 (633) is a 200 ohm resistor exhibiting no series attenuation.
- This non- attenuated signal path is represented on FIG. 6B as a dashed horizontal line beginning at the top of the bar of the high-path amplifier output (688) and ending at the top of the bar of the high-path resistive element RE3 output (643).
- the mid-path resistive element RE2 (631) exhibits 200 ohms series resistance and provides -24dB of series attenuation. This series attenuation is represented on FIG.
- the low-path resistive element REl (630) exhibits 200 ohms series resistance and provides -54dB of series attenuation.
- This series attenuation is represented on FIG. 6B as a dashed downward sloping diagonal line beginning at the top of the bar of the low-path amplifier output (685) and ending at the top of the bar of the low-path resistive element REl output (640).
- the summation node (651) is a simple physical electrical connection of the output signals (640), (641) and (643) from the resistive elements (630), (631) and (633),
- summing node (651) will suitably interface with typical real world external devices (660), meaning that the summed signal at (650) will maintain high level, high current, high bandwidth, low noise, and low distortion when coupled with typical external devices (660).
- the high-path switching element (681) under control of DSP (602) via control line (682) is held open (as is depicted in FIG. 6A).
- this switch (681) When this switch (681) is open, it creates an open-circuit at the input to high- path resistive element RE3 (633) resulting in effectively zero thermal noise from the resistive element RE3 (633) reaching the summing node (651).
- the only noise which is input to the summing node (651) is the thermal noise generated by the low-path resistive elements RE1 (630) and RE2 (631), plus any residual noise generated by prior circuit elements, such as the low-path DAC (610), low-path amplifier (620), mid-path DAC (611), and mid-path amplifier (621).
- the noise from the low-level DAC (610) and amplifier (620) is attenuated by RE1 (630) down to -160dBu and can be neglected relative to the thermal noise of -130dBu (640a) generated from the low-path resistive element RE1 (630).
- the sum of all broadband noise from the mid-level DAC (611), mid-level amplifier (621), and mid-path resistive element RE2 (631) is roughly -130dBu (641a).
- the 200 ohms series resistance of the low-path resistive element RE1 (630) combines in parallel with the 200 ohms series resistance of the mid-path resistive element RE2 (631), creating a total series resistance of 100 ohms, which can further reduce the total thermal noise (650b) as measured at the summing node (651).
- the high-path amplifier (623) produces a gain of +24dB, and the self-noise (688a) of the high-path amplifier (623) at +24 dB gain is -98dBu.
- High-path resistive element RE3 (633) is a non-attenuated passive path which exhibits 200 ohms series resistance.
- the DSP (602) sends a control signal (682) which causes high-path series switching element (681) to close (i.e., to switch to the position opposite that depicted in FIG. 6A). According to the preferred embodiment of the present invention, this switch closure occurs immediately before the DSP (602) begins to send high- path-program signal (608) to high-path DAC (613).
- the high-path amplifier (623) produces +24dB of gain (which is apparent in FIG. 6B by the 24dB increase in the height of amplifier output signal (688) relative to the DAC output signal (618)) and has -98dBu of unweighted broadband self-noise (688a).
- the high-path amplifier (623) is followed by resistive element RE3 (633) which has 200 ohms total series resistance and -130dBu of unweighted broadband self-noise.
- the self-noise of the resistive element RE3 (633) is so much less than the noise generated by the high-path amplifier (623) and high-path DAC (613), the total broadband unweighted audio path noise (643a) at the output (643) of the resistive element RE3 (633) is roughly -98dBu.
- the high-path amplifier (623) output signal (688) is switched by high-path switching element (681) into electrical connection with the summing node (651) when the mid-path program level (641) at summing node (651) is at or near -16dBu, there exists a roughly 80dB level difference (the level difference between -98dBu and -16dBu) between mid-path-program level (641) and high-path noise level (650c) when the high-path (643) is switched into electrical connection with the output summing node (651).
- the roughly 80dB signal-to-noise difference provides a very high degree of psychoacoustic masking to the -98dBu broadband unweighted high-path noise level added by the closure of switch (681), making the total noise (650c) generated by the high-path components (613), (623), (681) and (633) generally psychoacoustically undetectable.
- 650c total noise generated by the high-path components (613), (623), (681) and (633) generally psychoacoustically undetectable.
- the total series resistance into the summing node (651) is 100 ohms, i.e., the total series resistance of low-path and mid-path resistive element RE1 (630) and RE2 (631) in parallel.
- high-path switching element (681) is closed (i.e., the state opposite to that depicted in FIG.
- the parallel resistances of low-path resistive element RE1 (630), mid-path resistive element RE2 (631) and high-path resistive element RE3 (633) produce a total series resistance at output node (651) of 66.67 ohms, i.e., the total resistance of RE1 (630), RE2 (631) and RES (633) when connected in parallel.
- the DSP (602) adjusts its high-path digital output levels (605), (606) and (608) as required to compensate for any level shift of the output signal (650) produced by the change in the total circuit resistance.
- the DSP (602) calculates the amount of compensation required based on prior measurements it receives via ADCs (670), (672), (674) and (675), as described elsewhere.
- the high-path switching element (681) is to be understood to represent any method or technique under DSP (602) control for removing the high-path output signal (643) from the summing node (651) in such a manner as to eliminate or significantly reduce the self-noise generated by the high-path components (613), (623) and (633).
- the high-path switching element (681) could be two discrete switching elements, with one switching element per each leg of the differential signal.
- more than one DAC path may employ a series-switching element used for the purpose of removing path noise from the summing node.
- high-path amplifier (623) may employ a selectable shut-down, mute or disable (etc.) function in which a design feature of the amplifier (623) itself allows selective (i.e., DSP (602) controlled) removal of signal and noise from the output (643) of the amplifier (623).
- a reed relay is used for switching element (681) due to its fast switching speed, electrically and physically quiet operation, and complete removal of the high-path noise generation devices (613), (623) and (633) from the output summing node (651).
- the signal levels, at the output of the summing node (651), high-path amplifier (688), mid-path amplifier (686), and low-path amplifier (685) are monitored by analog-to-digital converters (ADCs) (674), (675), (672) and (670), respectively, when switched into monitoring via associated series-path switching elements (677), (676), (673) and (671), respectively.
- ADCs analog-to-digital converters
- Each ADC device (674), (675), (672) and (670) reports its analog input level to the DSP (602).
- ADC level reporting is used by the DSP (602) to adapt to circuit variations by calibrating the level of the output signals (688), (686), (685) and (650). If the external device (660) is changed, and especially if the destination (input) impedance of (660) is changed, the calibration routine described below and shown in FIG. 8 should be repeated to determine new calibration factors.
- the internal impedance of the ADCs (674), (675), (672) and (670) is great enough that switching them (674), (675), (672) and (670) into the circuit via switching elements (677), (676), (673) and (671) causes minimal amplitude shifts of the signal they (674), (675), (672) and (670) are measuring.
- the internal impedances of the ADCs (674), (675), (672) and (670) are preferably at least ten times greater, more preferably at least twenty times greater, and still more preferably at least forty times greater than the impedance of the circuit point the ADCs (674), (675), (672) and (670) are monitoring.
- ADC (674), (675), (672) and (670) are used to compare measured amplitudes with expected amplitudes.
- the DSP (602) can close any desired combination of switching elements (677), (676), (673) and (671), thereby connecting ADCs (674), (675), (672) and/or (670) to the outputs (688), (686) and (685) of the high-, mid- and low-level amplifiers (623), (621) and (620), and the summed output node (651).
- the difference between the measured amplitude values provided by ADCs (674), (675), (672) and/or (670) and the expected values in DSP (602) memory are used by the DSP (602) for correction/calibration factors.
- the calibration measurements will typically be taken at power-on with zero input program (661), but can also be taken during any sufficiently long period of zero input program (661).
- Switching elements (677), (676), (673) and (671) are used to completely remove the ADC inputs from their respective circuit paths when not in use, thereby fully removing any potentially detrimental electrical issues.
- the circuit (600) of the present invention is not limited to a single digital signal source (601), i.e., the circuit (600) may be utilized for the D-A conversion of a plurality of previously conditioned multi-path signals (i.e., any contiguous signal that has been pre-conditioned (split) into two or more discrete paths for the purpose of improved dynamic range, such as given by the example of patent LIS20140328501.)
- a plurality of previously conditioned multi-path signals i.e., any contiguous signal that has been pre-conditioned (split) into two or more discrete paths for the purpose of improved dynamic range, such as given by the example of patent LIS20140328501.
- Additional digital signal input sources (690), (691) ... (699) are represented here in a multi- input parallel topology for clarity, but such multi-path sources can also be configured in a single input serial topology, or hybrid series-parallel topology, or any other appropriate method or topology of digital data transfer, transmission, and/or input.
- a method of level control will now be described which takes advantage of the novel architecture of the present invention, wherein the levels of the analog outputs (685), (686), and (688) of the DAC devices (620), (621) and (623) are shifted by dynamically altering the DSP multi-path bit shift mapping characteristics.
- a digital signal (661) is mapped into multiple DAC devices (610), (611) and (613) by DSP (602).
- the mapping is done in a manner which achieves a fixed (non-adjustable) analog level range at the output (650) with respect to the input (661).
- the level of the analog output (650) can be varied, either higher or lower, by adjusting the mapped location of input bits (661) via a level adjustment control (655) connected to DSP (602) via signal path (656), as is shown in FIG. 6A.
- the level adjustment control (655) can be any manner of input control or control device to the DSP which provides a signal (656) to the DSP (602) which instructs the DSP (602) to carry out a resultant level adjustment.
- Some examples of such a level control (655) or control device (655) include, but are not limited to, gray-coded rotary encoder control, quadrature rotary encoder control, up-down control via switches, or any other means well-known to those skilled in the art of digital control.
- the 32 bit digital input signal (661) corresponds to an analog level range of -160dBu to +32dBu resulting in a usable output (650) level range of -130dBu to +32dBu.
- the cross-hatching below -130dBu indicates that range is not usable because of noise.
- FIG. 9 shows an example where the maximum level of the output (650') is reduced by -6dB relative to the digital input signal (661). (Shifted levels relative to those of FIG. 6B are noted by primed reference numerals. For clarity of depiction, the noise levels shown in FIG. 6B are not depicted in FIG. 9 since their characteristics are adequately described in FIG.
- This -6dB reduction in output range is achieved by a downward level shift by the DSP (602) by 1 bit at each input (605'), (606'), and (608') to the DACs (610), (611) and (613). More specifically, as shown in FIG. 9, to achieve a level reduction of -6dB at the output (650') relative to the output level (650) achieved in FIG.
- the source (601) input bits (661) 1 through 17 are mapped by the DSP (602) to input bits 5 through 21 of the input (605') to the low-path DAC (610), source (601) input bits (661) 18 through 24 are mapped by the DSP (602) to input bits 17 through 23 of the input (606') to the mid-path DAC (611), and source (601) input bits (661) 25 through 32 are mapped by the DSP (602') to input bits 16 through 23 of the input (608') to the high-path DAC (613).
- the DSP (602) performs a digital level shift such that the input (605') to the low-path DAC (610) is shifted up by 4 bits by the DSP (602) so that bit 1 of input signal (661), which corresponds to an analog level of -160dBu in the 32-bit DSP (602), is mapped to bit 5 of the low-path DAC (610), which corresponds to a level of -112dBu of the 24-bit low-path DAC output (615').
- the input (606') to the mid-path DAC (611) is shifted down by 1 bit by the DSP (602') so that bit 18 of input signal (661), which corresponds to an analog level of -58dBu in the 32-bit DSP (602), is mapped to bit 17 of the mid-path DAC (611), which corresponds to an analog level of -40dBu at the output (616') of the 24-bit mid-path DAC (611).
- the input (608') to the high-path DAC (613) is shifted down by 9 bits by the DSP (602') so that bit 32 of input signal (661), which corresponds to an analog level of +32dBu in the 32-bit DSP (602), is mapped to bit 23 of the high-path DAC (613), which corresponds to an analog level of +2dBu at the output (618') of the high-path DAC (613).
- the output levels (640'), (641 '), and (643') of resistive elements (630), (631), and (633) are is -6dB lower than the resistive element output levels (640), (641), and (643) described above in reference to FIG. 6B.
- the low-path, mid-path, and high-path output signals (640'), (641 '), and (643') shown in FIG. 9 are at all times -6dB lower than the low-path, mid-path, and high-path output signals (640), (641), and (643) shown in FIG. 6B
- FIG. 9 describes an embodiment of the invention where a -6dB level shift at output (650') is achieved relative to the output level (650) described above in reference to FIG. 6B. Therefore, a downward level shift at the analog output (650) can be realized via appropriate digital level shifting implemented by the DSP (602). Similarly, an upward relative level shift at analog output (650) can also be realized via appropriate digital level shifting implemented by the DSP (602).
- Level shift mapping is not limited to integer-wide or bit-alignment shifts within a digital register, but may result from arithmetic multiplications wherein the coefficient of multiplication may be any value within the operational range of the digital signal processing. For a change in level to be psychoacoustically perceived as linear (i.e., non-stepped) audio level changes of no greater than roughly O.
- ldB per increment are required, i.e., increments at or below the "just noticeable difference” in level shifts (see Introduction to the Physics and Psychophysics of Music, Juan Roederer, Springer Verlag, 1978, p81, which is incorporated herein by reference).
- each level control may be implemented as an analog potentiometer, adjustable resistor, or a digitally-controlled analog leveling device, or a digital gain function in the DSP (602), or a gain control in the DAC devices (610), (611) and (613) themselves.
- H s 8 bits.
- the digital signal processor (DSP) (410) may have multiple digital inputs (412), (413) and (414) which receive digital signals (402), (403), and (404), respectively, which represent portions of an original digital signal (401).
- a 32-bit digital input signal (401) is shown in FIG. 4, it should be noted that the input signal (401) may be comprised of any number of bits.
- the original input signal (401) is divided into three smaller partial input signals (402), (403) and (404) that each feed separate DSP (410) inputs (412), (413) and (414).
- the partial signals (402), (403) and (404) may have some overlap of data between paths, such as is shown FIG. 4 where bits 11-12 (420) are shared by low-level and mid-level signals (402) and (403), and bits 22-23 (421) are shared by mid-level and high-level signals (403) and (404).
- the partial-path signals (402), (403) and (404) may be contiguous with no bit overlap.
- any number of partial-path sources could be packaged into a single serial data stream, or any other manner of digital transmission or input.
- the processing would then be as shown in FIG. 3A, where the DSP (in this case (401) rather than (302)) would then align the multi-path input data (402), (403) and (404) into two output paths feeding high-level
- the invention provides for any multiple of multi-path input signals to feed any number of multi-path DACs, divided into any number of bits, or sub-bit coefficient multiplier, per path.
- two audio microphones (510) and (511) are utilized.
- the two microphones (510) and (511) are exposed to a wide dynamic range acoustic source (501).
- Microphone (510) is optimized for performance with relatively low sound-pressure level (SPL) acoustic signals.
- Microphone (511) is optimized for performance with relatively high SPL acoustic signals.
- Each microphone (510) and (511) feeds a conditioning amplifier (520) and (521), respectively, with each conditioning amplifier (520) and (521) providing suitable gain, input and output impedance, and other preferred- performance characteristics as familiar to one skilled in the art of microphone termination, for instance according to the means and methods described in
- conditioning amplifiers (521) and (520), being suitably conditioned, are then fed to analog- to-digital converters (ADCs) (531) and (530), respectively.
- ADCs analog- to-digital converters
- the output of each ADC (536) and (535) then feeds the inputs of a suitable DSP (540).
- the system (500) of FIG. 5 may be applied to the system (300) of FIG. 3A, in which case the outputs (536) and (535) of the ADCs (531) and (530) would be the digital signal sources (301) and (340), and the digital outputs (551) and (550) would be the inputs (333) and (334) to the high-path DAC (303) and the low-path DAC (304), respectively.
- FIG. 4 and FIG. 5 show just two examples (400) and (500) among myriad possible applications of the present invention for feeding multiple DACs a plurality of digital signals that represent a single program (as opposed to feeding a single original signal to DSP that then feeds multiple multi-path DACs). Any number of microphones, or any other plurality of multi-path-program signals, could for instance be used. As per equations (1.1) and (1.2), thermal noise VN rises with circuit source resistance
- each resistive element has a resistance of between 10 and 1,000 ohms, and more preferably a resistance between 30 and 300 ohms.
- the invention is not limited to 32-bit input signal— an input signal of any bit length signal may be used; the allocation of bits between paths may or may not include overlapping bits or fractional bit levels (i.e., less than one full bit) thereof ; the switching in and out of mid- and high-path circuitry may be rapid or involve fade-ins and fade-outs, or dithering; the digital signal processor may be any manner of digital processor (such as FPGA, etc.) that has adequate speed, bandwidth, input/output capabilities, and programmable features to perform the necessary processing; although 200 ohm resistive elements are taught, the invention can be designed with any resistances appropriate and suitable to low noise, high performance passive summing; the resistive elements may generate values of attenuation (or no attenuation) other than the particular values taught above— the invention can function successfully over a wide range of attenuation values when suitably designed in consort with other parameters of the circuitry; the invention is not limited to 2-path and 3-path topologies, and any number of paths can be
Abstract
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US201514935363A | 2015-11-06 | 2015-11-06 | |
PCT/US2016/014199 WO2016118674A1 (en) | 2015-01-22 | 2016-01-21 | Multi-path, series-switched, passively-summed digital-to-analog converter |
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US10834632B2 (en) | 2018-09-21 | 2020-11-10 | At&T Intellectual Property I, L.P. | Energy-efficient wireless communications for advanced networks with low-resolution digital-to-analog converters |
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US9871530B1 (en) | 2016-12-11 | 2018-01-16 | John Howard La Grou | Multi-path analog-to-digital and digital-to-analog conversion of PDM signals |
US10256782B2 (en) | 2017-04-25 | 2019-04-09 | John Howard La Grou | Multi-path power amplifier |
TWI707587B (en) * | 2019-05-16 | 2020-10-11 | 瑞昱半導體股份有限公司 | Audio playback device and method |
CN110492925B (en) * | 2019-08-02 | 2021-09-07 | 三维通信股份有限公司 | Uplink combining and summing method and device and distributed antenna system |
CN116719266B (en) * | 2023-08-09 | 2023-11-03 | 浙江国利信安科技有限公司 | Control apparatus |
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EP0790709A1 (en) * | 1996-02-15 | 1997-08-20 | STUDER Professional Audio AG | Method and apparatus for converting a digital audiosignal |
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JP2008153928A (en) * | 2006-12-18 | 2008-07-03 | Toshiba Corp | D/a converter and magnetic resonance imaging apparatus by the converter |
FR2941339B1 (en) * | 2009-01-19 | 2011-02-18 | Spidcom Technologies | METHOD AND DEVICE FOR REDUCING QUANTIZATION NOISE FOR TRANSMISSION OF A MULTI-CARRIER SIGNAL |
JP5373680B2 (en) * | 2010-03-26 | 2013-12-18 | ルネサスエレクトロニクス株式会社 | DIGITAL / ANALOG CONVERSION CIRCUIT, DATA DRIVER AND DISPLAY DEVICE |
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CN103795415A (en) * | 2014-01-24 | 2014-05-14 | 中国人民解放军国防科学技术大学 | High-precision analog to digital conversion method and device based on double-path combination analog to digital converter |
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2016
- 2016-01-21 EP EP16740716.2A patent/EP3248291A4/en not_active Withdrawn
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US10834632B2 (en) | 2018-09-21 | 2020-11-10 | At&T Intellectual Property I, L.P. | Energy-efficient wireless communications for advanced networks with low-resolution digital-to-analog converters |
US11140577B2 (en) | 2018-09-21 | 2021-10-05 | At&T Intellectual Property I, L.P. | Energy-efficient wireless communications for advanced networks with low-resolution digital-to-analog converters |
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CN107210752A (en) | 2017-09-26 |
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WO2016118674A1 (en) | 2016-07-28 |
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