EP3238044A4 - Method and apparatus for performing reduction operations on a set of vector elements - Google Patents

Method and apparatus for performing reduction operations on a set of vector elements Download PDF

Info

Publication number
EP3238044A4
EP3238044A4 EP15873971.4A EP15873971A EP3238044A4 EP 3238044 A4 EP3238044 A4 EP 3238044A4 EP 15873971 A EP15873971 A EP 15873971A EP 3238044 A4 EP3238044 A4 EP 3238044A4
Authority
EP
European Patent Office
Prior art keywords
apparatus
set
method
vector elements
reduction operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP15873971.4A
Other languages
German (de)
French (fr)
Other versions
EP3238044A1 (en
Inventor
David M. Kunzman
Christopher J. Hughes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US14/581,478 priority Critical patent/US9851970B2/en
Application filed by Intel Corp filed Critical Intel Corp
Priority to PCT/US2015/062074 priority patent/WO2016105764A1/en
Publication of EP3238044A1 publication Critical patent/EP3238044A1/en
Publication of EP3238044A4 publication Critical patent/EP3238044A4/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036Instructions to perform operations on packed data, e.g. vector operations
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001Arithmetic instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018Bit or string instructions; instructions using a mask
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/30101Special purpose registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • G06F9/3834Maintaining memory consistency
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction, e.g. SIMD
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053Vector processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029Logical and Boolean instructions, e.g. XOR, NOT
EP15873971.4A 2014-12-23 2015-11-23 Method and apparatus for performing reduction operations on a set of vector elements Pending EP3238044A4 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/581,478 US9851970B2 (en) 2014-12-23 2014-12-23 Method and apparatus for performing reduction operations on a set of vector elements
PCT/US2015/062074 WO2016105764A1 (en) 2014-12-23 2015-11-23 Method and apparatus for performing reduction operations on a set of vector elements

Publications (2)

Publication Number Publication Date
EP3238044A1 EP3238044A1 (en) 2017-11-01
EP3238044A4 true EP3238044A4 (en) 2018-08-22

Family

ID=56129476

Family Applications (1)

Application Number Title Priority Date Filing Date
EP15873971.4A Pending EP3238044A4 (en) 2014-12-23 2015-11-23 Method and apparatus for performing reduction operations on a set of vector elements

Country Status (7)

Country Link
US (1) US9851970B2 (en)
EP (1) EP3238044A4 (en)
JP (1) JP6699845B2 (en)
KR (1) KR20170097008A (en)
CN (1) CN107003843A (en)
TW (2) TWI575454B (en)
WO (1) WO2016105764A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160224465A1 (en) * 2015-01-08 2016-08-04 Technion Research And Development Foundation Ltd. Hybrid processor
US10162603B2 (en) * 2016-09-10 2018-12-25 Sap Se Loading data for iterative evaluation through SIMD registers
US20180189061A1 (en) * 2016-12-30 2018-07-05 Mikhail Plotnikov Systems, apparatuses, and methods for broadcast arithmetic operations
US10268479B2 (en) * 2016-12-30 2019-04-23 Intel Corporation Systems, apparatuses, and methods for broadcast compare addition
US10108581B1 (en) * 2017-04-03 2018-10-23 Google Llc Vector reduction processor
WO2019005165A1 (en) * 2017-06-30 2019-01-03 Intel Corporation Method and apparatus for vectorizing indirect update loops
CN107833176A (en) * 2017-10-30 2018-03-23 上海寒武纪信息科技有限公司 A kind of information processing method and Related product
US20190042261A1 (en) * 2018-09-14 2019-02-07 Intel Corporation Systems and methods for performing horizontal tile operations

Citations (8)

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US5845112A (en) * 1997-03-06 1998-12-01 Samsung Electronics Co., Ltd. Method for performing dead-zone quantization in a single processor instruction
US20050125631A1 (en) * 2003-12-09 2005-06-09 Arm Limited Data element size control within parallel lanes of processing
WO2013095631A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction
WO2013095634A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction
US20130311530A1 (en) * 2012-03-30 2013-11-21 Victor W. Lee Apparatus and method for selecting elements of a vector computation
US20140013075A1 (en) * 2011-12-23 2014-01-09 Mostafa Hagog Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction
US20140095842A1 (en) * 2012-09-28 2014-04-03 Paul Caprioli Accelerated interlane vector reduction instructions
US20140189307A1 (en) * 2012-12-29 2014-07-03 Robert Valentine Methods, apparatus, instructions, and logic to provide vector address conflict resolution with vector population count functionality

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
US7506135B1 (en) 2002-06-03 2009-03-17 Mimar Tibet Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements
US7330964B2 (en) * 2005-11-14 2008-02-12 Texas Instruments Incorporated Microprocessor with independent SIMD loop buffer
US7991987B2 (en) * 2007-05-10 2011-08-02 Intel Corporation Comparing text strings
US8447962B2 (en) * 2009-12-22 2013-05-21 Intel Corporation Gathering and scattering multiple data elements
US20110302394A1 (en) 2010-06-08 2011-12-08 International Business Machines Corporation System and method for processing regular expressions using simd and parallel streams
WO2013081588A1 (en) * 2011-11-30 2013-06-06 Intel Corporation Instruction and logic to provide vector horizontal compare functionality
US9268626B2 (en) * 2011-12-23 2016-02-23 Intel Corporation Apparatus and method for vectorization with speculation support
US9378182B2 (en) * 2012-09-28 2016-06-28 Intel Corporation Vector move instruction controlled by read and write masks
KR101772299B1 (en) 2012-12-28 2017-08-28 인텔 코포레이션 Instruction to reduce elements in a vector register with strided access pattern
US9372692B2 (en) 2012-12-29 2016-06-21 Intel Corporation Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
US9411584B2 (en) 2012-12-29 2016-08-09 Intel Corporation Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5845112A (en) * 1997-03-06 1998-12-01 Samsung Electronics Co., Ltd. Method for performing dead-zone quantization in a single processor instruction
US20050125631A1 (en) * 2003-12-09 2005-06-09 Arm Limited Data element size control within parallel lanes of processing
WO2013095631A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction
WO2013095634A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction
US20140013075A1 (en) * 2011-12-23 2014-01-09 Mostafa Hagog Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction
US20130311530A1 (en) * 2012-03-30 2013-11-21 Victor W. Lee Apparatus and method for selecting elements of a vector computation
US20140095842A1 (en) * 2012-09-28 2014-04-03 Paul Caprioli Accelerated interlane vector reduction instructions
US20140189307A1 (en) * 2012-12-29 2014-07-03 Robert Valentine Methods, apparatus, instructions, and logic to provide vector address conflict resolution with vector population count functionality

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2016105764A1 *

Also Published As

Publication number Publication date
TW201737062A (en) 2017-10-16
US20160179537A1 (en) 2016-06-23
TWI575454B (en) 2017-03-21
TWI616817B (en) 2018-03-01
TW201643705A (en) 2016-12-16
JP6699845B2 (en) 2020-05-27
EP3238044A1 (en) 2017-11-01
CN107003843A (en) 2017-08-01
JP2018500656A (en) 2018-01-11
US9851970B2 (en) 2017-12-26
KR20170097008A (en) 2017-08-25
WO2016105764A1 (en) 2016-06-30

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