EP3238044A4 - Method and apparatus for performing reduction operations on a set of vector elements - Google Patents
Method and apparatus for performing reduction operations on a set of vector elements Download PDFInfo
- Publication number
- EP3238044A4 EP3238044A4 EP15873971.4A EP15873971A EP3238044A4 EP 3238044 A4 EP3238044 A4 EP 3238044A4 EP 15873971 A EP15873971 A EP 15873971A EP 3238044 A4 EP3238044 A4 EP 3238044A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- vector elements
- reduction operations
- performing reduction
- operations
- vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
- G06F9/38873—Iterative single instructions for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/581,478 US9851970B2 (en) | 2014-12-23 | 2014-12-23 | Method and apparatus for performing reduction operations on a set of vector elements |
PCT/US2015/062074 WO2016105764A1 (en) | 2014-12-23 | 2015-11-23 | Method and apparatus for performing reduction operations on a set of vector elements |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3238044A1 EP3238044A1 (en) | 2017-11-01 |
EP3238044A4 true EP3238044A4 (en) | 2018-08-22 |
Family
ID=56129476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP15873971.4A Withdrawn EP3238044A4 (en) | 2014-12-23 | 2015-11-23 | Method and apparatus for performing reduction operations on a set of vector elements |
Country Status (7)
Country | Link |
---|---|
US (1) | US9851970B2 (en) |
EP (1) | EP3238044A4 (en) |
JP (1) | JP6699845B2 (en) |
KR (1) | KR102449616B1 (en) |
CN (1) | CN107003843B (en) |
TW (2) | TWI575454B (en) |
WO (1) | WO2016105764A1 (en) |
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US10996959B2 (en) * | 2015-01-08 | 2021-05-04 | Technion Research And Development Foundation Ltd. | Hybrid processor |
US10162603B2 (en) * | 2016-09-10 | 2018-12-25 | Sap Se | Loading data for iterative evaluation through SIMD registers |
EP3336692B1 (en) * | 2016-12-13 | 2020-04-29 | Arm Ltd | Replicate partition instruction |
US10846087B2 (en) * | 2016-12-30 | 2020-11-24 | Intel Corporation | Systems, apparatuses, and methods for broadcast arithmetic operations |
US10268479B2 (en) * | 2016-12-30 | 2019-04-23 | Intel Corporation | Systems, apparatuses, and methods for broadcast compare addition |
US10275217B2 (en) * | 2017-03-14 | 2019-04-30 | Samsung Electronics Co., Ltd. | Memory load and arithmetic load unit (ALU) fusing |
US10108581B1 (en) * | 2017-04-03 | 2018-10-23 | Google Llc | Vector reduction processor |
WO2019005165A1 (en) * | 2017-06-30 | 2019-01-03 | Intel Corporation | Method and apparatus for vectorizing indirect update loops |
CN109117184A (en) | 2017-10-30 | 2019-01-01 | 上海寒武纪信息科技有限公司 | Artificial intelligence process device and the method for executing Plane Rotation instruction using processor |
US11277455B2 (en) | 2018-06-07 | 2022-03-15 | Mellanox Technologies, Ltd. | Streaming system |
GB2574817B (en) * | 2018-06-18 | 2021-01-06 | Advanced Risc Mach Ltd | Data processing systems |
US11990137B2 (en) | 2018-09-13 | 2024-05-21 | Shanghai Cambricon Information Technology Co., Ltd. | Image retouching method and terminal device |
US11579883B2 (en) | 2018-09-14 | 2023-02-14 | Intel Corporation | Systems and methods for performing horizontal tile operations |
US20200106828A1 (en) * | 2018-10-02 | 2020-04-02 | Mellanox Technologies, Ltd. | Parallel Computation Network Device |
US11625393B2 (en) * | 2019-02-19 | 2023-04-11 | Mellanox Technologies, Ltd. | High performance computing system |
EP3699770A1 (en) | 2019-02-25 | 2020-08-26 | Mellanox Technologies TLV Ltd. | Collective communication system and methods |
US11294670B2 (en) * | 2019-03-27 | 2022-04-05 | Intel Corporation | Method and apparatus for performing reduction operations on a plurality of associated data element values |
US11327862B2 (en) | 2019-05-20 | 2022-05-10 | Micron Technology, Inc. | Multi-lane solutions for addressing vector elements using vector index registers |
US11507374B2 (en) | 2019-05-20 | 2022-11-22 | Micron Technology, Inc. | True/false vector index registers and methods of populating thereof |
US11340904B2 (en) | 2019-05-20 | 2022-05-24 | Micron Technology, Inc. | Vector index registers |
US11403256B2 (en) | 2019-05-20 | 2022-08-02 | Micron Technology, Inc. | Conditional operations in a vector processor having true and false vector index registers |
US11061741B2 (en) * | 2019-07-16 | 2021-07-13 | Nvidia Corporation | Techniques for efficiently performing data reductions in parallel processing units |
US11750699B2 (en) | 2020-01-15 | 2023-09-05 | Mellanox Technologies, Ltd. | Small message aggregation |
US11252027B2 (en) | 2020-01-23 | 2022-02-15 | Mellanox Technologies, Ltd. | Network element supporting flexible data reduction operations |
US11876885B2 (en) | 2020-07-02 | 2024-01-16 | Mellanox Technologies, Ltd. | Clock queue with arming and/or self-arming features |
US11556378B2 (en) | 2020-12-14 | 2023-01-17 | Mellanox Technologies, Ltd. | Offloading execution of a multi-task parameter-dependent operation to a network device |
CN114629501B (en) * | 2022-03-16 | 2024-06-14 | 重庆邮电大学 | Edge data classification compression method for state information in machining process |
CN115220789B (en) * | 2022-06-24 | 2023-02-07 | 北京联盛德微电子有限责任公司 | Operation command trigger scheduling method and unit for multiple registers |
US20240004647A1 (en) * | 2022-07-01 | 2024-01-04 | Andes Technology Corporation | Vector processor with vector and element reduction method |
US11922237B1 (en) | 2022-09-12 | 2024-03-05 | Mellanox Technologies, Ltd. | Single-step collective operations |
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WO2013095631A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction |
US20130311530A1 (en) * | 2012-03-30 | 2013-11-21 | Victor W. Lee | Apparatus and method for selecting elements of a vector computation |
US20140013075A1 (en) * | 2011-12-23 | 2014-01-09 | Mostafa Hagog | Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction |
US20140095842A1 (en) * | 2012-09-28 | 2014-04-03 | Paul Caprioli | Accelerated interlane vector reduction instructions |
US20140189307A1 (en) * | 2012-12-29 | 2014-07-03 | Robert Valentine | Methods, apparatus, instructions, and logic to provide vector address conflict resolution with vector population count functionality |
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-
2014
- 2014-12-23 US US14/581,478 patent/US9851970B2/en active Active
-
2015
- 2015-11-23 KR KR1020177013503A patent/KR102449616B1/en active IP Right Grant
- 2015-11-23 TW TW104138807A patent/TWI575454B/en active
- 2015-11-23 TW TW105142765A patent/TWI616817B/en not_active IP Right Cessation
- 2015-11-23 JP JP2017527586A patent/JP6699845B2/en active Active
- 2015-11-23 EP EP15873971.4A patent/EP3238044A4/en not_active Withdrawn
- 2015-11-23 WO PCT/US2015/062074 patent/WO2016105764A1/en active Application Filing
- 2015-11-23 CN CN201580063820.8A patent/CN107003843B/en active Active
Patent Citations (8)
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US5845112A (en) * | 1997-03-06 | 1998-12-01 | Samsung Electronics Co., Ltd. | Method for performing dead-zone quantization in a single processor instruction |
US20050125631A1 (en) * | 2003-12-09 | 2005-06-09 | Arm Limited | Data element size control within parallel lanes of processing |
WO2013095634A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction |
WO2013095631A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction |
US20140013075A1 (en) * | 2011-12-23 | 2014-01-09 | Mostafa Hagog | Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction |
US20130311530A1 (en) * | 2012-03-30 | 2013-11-21 | Victor W. Lee | Apparatus and method for selecting elements of a vector computation |
US20140095842A1 (en) * | 2012-09-28 | 2014-04-03 | Paul Caprioli | Accelerated interlane vector reduction instructions |
US20140189307A1 (en) * | 2012-12-29 | 2014-07-03 | Robert Valentine | Methods, apparatus, instructions, and logic to provide vector address conflict resolution with vector population count functionality |
Non-Patent Citations (1)
Title |
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See also references of WO2016105764A1 * |
Also Published As
Publication number | Publication date |
---|---|
US20160179537A1 (en) | 2016-06-23 |
TW201737062A (en) | 2017-10-16 |
EP3238044A1 (en) | 2017-11-01 |
JP2018500656A (en) | 2018-01-11 |
US9851970B2 (en) | 2017-12-26 |
KR102449616B1 (en) | 2022-10-04 |
CN107003843B (en) | 2021-03-30 |
KR20170097008A (en) | 2017-08-25 |
JP6699845B2 (en) | 2020-05-27 |
TW201643705A (en) | 2016-12-16 |
CN107003843A (en) | 2017-08-01 |
WO2016105764A1 (en) | 2016-06-30 |
TWI575454B (en) | 2017-03-21 |
TWI616817B (en) | 2018-03-01 |
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