EP3101650A1 - Procédé et appareil pour effectuer entrelacement - Google Patents

Procédé et appareil pour effectuer entrelacement Download PDF

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Publication number
EP3101650A1
EP3101650A1 EP16172382.0A EP16172382A EP3101650A1 EP 3101650 A1 EP3101650 A1 EP 3101650A1 EP 16172382 A EP16172382 A EP 16172382A EP 3101650 A1 EP3101650 A1 EP 3101650A1
Authority
EP
European Patent Office
Prior art keywords
tiled
operations
interleaving
graphics
compute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP16172382.0A
Other languages
German (de)
English (en)
Inventor
John Brothers
Abhinav GOLAS
Joohoon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/981,395 external-priority patent/US10089775B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of EP3101650A1 publication Critical patent/EP3101650A1/fr
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2350/00—Solving problems of bandwidth in display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/08—Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving

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  • Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
EP16172382.0A 2015-06-04 2016-06-01 Procédé et appareil pour effectuer entrelacement Pending EP3101650A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562171071P 2015-06-04 2015-06-04
US14/981,395 US10089775B2 (en) 2015-06-04 2015-12-28 Automated graphics and compute tile interleave
KR1020160014084A KR20160143489A (ko) 2015-06-04 2016-02-04 인터리빙을 수행하는 방법 및 장치.

Publications (1)

Publication Number Publication Date
EP3101650A1 true EP3101650A1 (fr) 2016-12-07

Family

ID=56409460

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16172382.0A Pending EP3101650A1 (fr) 2015-06-04 2016-06-01 Procédé et appareil pour effectuer entrelacement

Country Status (1)

Country Link
EP (1) EP3101650A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222870A1 (en) * 1997-07-02 2003-12-04 Mental Images G.M.B.H. & Co, Kg System and method for generating and using systems of cooperating and encapsulated shaders and shader DAGs for use in a computer graphics system
US20110050716A1 (en) * 2009-09-03 2011-03-03 Advanced Micro Devices, Inc. Processing Unit with a Plurality of Shader Engines
US20110148919A1 (en) * 2009-12-17 2011-06-23 Frode Heggelund Graphics processing systems
US20130069943A1 (en) * 2011-09-19 2013-03-21 Qualcomm Incorporated Optimizing resolve performance with tiling graphics architectures
US20130235057A1 (en) * 2012-03-12 2013-09-12 Ati Technologies, Ulc Area-based dependency chain analysis of shaders and command stream
US20140327671A1 (en) * 2013-05-02 2014-11-06 Arm Limited Graphics processing systems

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222870A1 (en) * 1997-07-02 2003-12-04 Mental Images G.M.B.H. & Co, Kg System and method for generating and using systems of cooperating and encapsulated shaders and shader DAGs for use in a computer graphics system
US20110050716A1 (en) * 2009-09-03 2011-03-03 Advanced Micro Devices, Inc. Processing Unit with a Plurality of Shader Engines
US20110148919A1 (en) * 2009-12-17 2011-06-23 Frode Heggelund Graphics processing systems
US20130069943A1 (en) * 2011-09-19 2013-03-21 Qualcomm Incorporated Optimizing resolve performance with tiling graphics architectures
US20130235057A1 (en) * 2012-03-12 2013-09-12 Ati Technologies, Ulc Area-based dependency chain analysis of shaders and command stream
US20140327671A1 (en) * 2013-05-02 2014-11-06 Arm Limited Graphics processing systems

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