EP3095136A1 - Sic trench transistor and method for producing same - Google Patents

Sic trench transistor and method for producing same

Info

Publication number
EP3095136A1
EP3095136A1 EP14802057.1A EP14802057A EP3095136A1 EP 3095136 A1 EP3095136 A1 EP 3095136A1 EP 14802057 A EP14802057 A EP 14802057A EP 3095136 A1 EP3095136 A1 EP 3095136A1
Authority
EP
European Patent Office
Prior art keywords
compensation layer
terminal
layer
doping
sic trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP14802057.1A
Other languages
German (de)
French (fr)
Inventor
Ning Qu
Thomas Jacke
Michael Grieb
Martin Rambach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3095136A1 publication Critical patent/EP3095136A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • the present invention relates to a SiC trench transistor and a method of manufacturing the same.
  • the gate oxide In the case of SiC-based components, the gate oxide generally has a lower band offset in the conduction band than comparable components made of silicon, so that degradation due to tunnel currents already occurs at lower
  • Gate field strengths occurs.
  • SiC transistors in particular MOSFETs (metal oxide semiconductor field effect transistor)
  • MOSFETs metal oxide semiconductor field effect transistor
  • a meaningful field strength in the gate oxide will be 3 MV / cm. Compliance with this limit is particularly critical in lock-up and makes design measures required, especially in
  • the field strength at the gate oxide can be reduced, for example, by introducing a double trench with a low p implantation.
  • the lower-lying p regions constitute a JFET (junction field effect transistor), which shields the actual trench MOSFET structure.
  • the field strengths at the gate oxide can also be reduced to about 4 MV / cm by introducing p-type p-type regions (p-bubbles) below the gate oxide (J. Tan et al., High Voltage Accumulation Layer, UMOSFETs in 4H-SiC, IEEE ELECTRON DEVICE LETTERS, VOL 19, NO 12, DECEMBER 1998).
  • Double trenches also significantly increased the resistance in the current path.
  • a SiC trench transistor having a first terminal, an epitaxial layer arranged vertically between a gate trench and a second terminal is provided, wherein a horizontally extending compensation layer is provided in the epitaxial layer, which provides an effective doping of opposite type having the doping of the epitaxial layer.
  • the compensation layer allows a reduction of the electric gate field strength without increased space requirement.
  • the core of the invention is a semiconductor structure which reduces the gate field strength and is inserted vertically into the SiC trench structure. Due to the vertical integration, the trench structures can be packed significantly denser and the surface resistivity between drain and source
  • the field strength in the gate region can be adjusted by appropriate choice of doping and spacing. By decoupling the gate-near field region from the epitaxial layer or the drift region, higher n-type dopants can be used in the channel near the drift region without significant disadvantages for the
  • the arithmetic mean of the doping of the compensation layer may correspond to the doping of opposite type. This allows manifold
  • Embodiments of the doping of the compensation layer since only the means must correspond to a certain doping value. Thus, irregular doping is possible.
  • the transistor it is provided that the transistor
  • the first terminal is a source terminal
  • the second terminal is a drain structure
  • the epitaxial layer is a drift zone.
  • the adaptation or adjustment of the gate field strength according to the invention is important.
  • the compensation layer can have passages with a doping of the type of drift zone. These passages allow current to pass through the MOSFET so that the functionality or functionality of the MOSFET is not restricted.
  • the passages may have round or angular outlines and may be arranged at regular or irregular intervals or patterns.
  • the compensation layer has an alternating sequence of p-doped and n-doped regions in a planar direction of the compensation layer.
  • This variant is easy to manufacture and allows a good passage of electricity as well as a simple calculation and Production of the doping of the compensation layer, in particular the
  • the compensation layer comprises an alternating pattern of p-doped and n-doped regions in two
  • the transistor is a SiC trench IGBT (insulated-gate bipolar transistor), the first terminal is a cathode terminal, the second terminal is an anode terminal and the epitaxial layer is a base zone.
  • the compensation layer allows a reduction of the field strength in the gate oxide, which opens up new fields of application for IGBTs.
  • the compensation layer may have a low homogeneous dopant of the opposite type to the doping of the base region. This doping can be easily produced.
  • the compensation layer has a maximum distance of 25% of the drift zone thickness to the gate channel. It has been shown that this
  • Distance range allows an optimal field strength in the gate oxide.
  • the inventive method for producing a SiC trench transistor basically comprises the following steps:
  • the introduction of the compensation layer according to the invention advantageously permits control of the electric field characteristic in the gate trench and / or in the gate Epitaxial layer, so that the transistor can be adjusted exactly to its use.
  • Figure 1 is a schematic sectional view of a SiC trench MOSFETs with compensation layer and associated electric field characteristic
  • Figure 2 shows an embodiment of the compensation layer in one
  • FIG. 3 shows a further embodiment of the compensation layer in a surface direction
  • FIG. 4 shows a further embodiment of the compensation layer in another surface direction
  • FIG. 5 shows a further embodiment of the compensation layer in two surface directions
  • Figure 6 is a schematic sectional view of a SiC trench IGBT with compensation layer and associated electric field profile.
  • Figure 1 shows in cross-section an SIC trench transistor 1 with a
  • an epitaxial layer in the form of a drift zone 4 is arranged below the source terminal 2 and the gate trench 3.
  • a drain connection or a drain structure 5 is arranged below the drift zone 4 .
  • a compensation layer 6 is provided which extends horizontally. The directions given here, such as below or horizontally, refer to the pictorial representation in the figures. Should the transistor 1 be oriented differently than in FIG. 1, these are relative terms
  • the directional references may be more specifically referred to with reference to the gate trench 3
  • Main extension which runs here from top to bottom, to be defined.
  • the compensation layer 6 is perpendicular to the gate trench. 3
  • the drift zone 4 is n-doped and the compensation layer 6 is effectively p-doped, ie with the opposite type or charge type to the drift zone 4.
  • the dopants can also be selected in reverse.
  • the effective doping may be exemplified as the arithmetic mean of the
  • Extension of the compensation layer 6 in a plane, for example the x and y direction, is then usually limited to the cell or the region of the transistor 1.
  • the second curve 8 shows the field intensity profile of the illustrated SIC trench transistor 1 according to the invention.
  • the compensation layer 6 effects a step in the vertical field profile, with the lower level of the field profile lying between the gate 3 and the compensation layer 6 the high field level below the compensation layer 6 more precisely lies in the region of the pn junction between the compensation layer 6 and the drift zone 4.
  • the vertical arrangement of the compensation layer 6, that is in particular the Distance between the compensation layer 6 and the gate trench 3 and / or the thickness of the compensation layer 6 in the vertical direction, the
  • Field strength profile of the transistor 1 can be adjusted or adjusted individually to the respective purposes.
  • FIG. 2 shows a first realization of the compensation layer 6.
  • the compensation layer consists of an alternating sequence of n-doped regions 6a and p-doped regions 6b.
  • the n-doped regions 6a form passages for the current of the transistor 1.
  • the distances of the individual regions or their width or length are greater than that
  • Drift zone length that is the distance between the gate 3 and the
  • Drain structure 5 This results in a typical structure size of 0.1 ... 5 ⁇ .
  • the doped regions 6a and 6b extend in the form of a strip in the direction of the strip-shaped gate trench 3, in this case into the plane of the page.
  • the highest possible doping level is to be striven for under the boundary condition that the effective doping or average doping or, in other words, the volume-weighted difference between the n and the p-
  • Dopant concentration is maintained according to the vertical field strength target profile including the manufacturing tolerances.
  • the design of the pn junctions of the compensation layer 6 can be largely free, that is to pass properties or
  • the periodicity of the compensation layer 6, that is to say the alternating sequence of the n-doped regions 6a and the p-doped regions 6b, is to be selected smaller or in the order of magnitude of the drift zone (typically 1... 10 ⁇ m).
  • FIG. 3 shows a SiC trench transistor 1 with a compensation layer 6 which has a greater periodicity, that is to say that the layer 6 has more pn junctions per cell in comparison to FIG.
  • the compensation layer 6 also has a stripe design parallel to the gate orientation, ie, a surface direction of the stripe design Compensation layer 6 on.
  • the n-regions 6a of the compensation layer 6 are advantageously aligned below the channel region.
  • FIG. 4 shows another example of a SiC trench transistor 1 with a compensation layer 6. Again, there is the compensation layer
  • the doped regions 6a and 6b extend transversely or perpendicularly to the extent of the strip-shaped gate 3
  • the doped regions 6a and 6b may also be arranged at a different angle.
  • FIG. 5 shows a SiC trench transistor with a compensation layer 6, in which an alternating pattern of p-doped regions 6b and n-doped regions 6a is provided in two surface directions of the compensation layer 6.
  • the pattern here is a two-dimensional periodic lattice that is particularly suitable for two-dimensional MOS designs, such as hexagonal cell structures.
  • a checkerboard design is also possible.
  • the n-regions 6a of the compensation layer 6 are advantageously aligned below the channel region, at least as regards the
  • FIG. 6 shows a SiC trench IGBT 10 with a cathode terminal 12 and a gate trench 13. Beneath the gate trench 13 and the cathode terminal 12, a base zone 14 is arranged in the form of an epitaxial layer. Again below the base zone 14, an anode terminal 15 is provided. In the base zone 14 is a horizontally extending
  • Compensating layer 16 is provided to reduce the field strength in the gate oxide. As before, the compensation layer 16 has an effective doping of an opposite type to the doping of the base region 14. In this case,
  • the base region 14 is n-doped while the compensation layer 16 is p-doped. Since no unipolar through-current is required in an IGBT, the compensation layer 16 may be formed as a low-doped homogeneous layer.
  • the field strength curve shown on the right in FIG. 6 corresponds to the profile shown in FIG.
  • the curve 17 shows the course of the field strength for a known IGBT without compensation layer 16. Clearly For example, the amount of field strength in the region of the gate oxide is highest.
  • the curve 18 shows the field strength profile optimized by the compensation layer 16 with significantly lower field strength in the region of the gate oxide.
  • the transistor 10 includes below the base region 14 an optional heavily n-doped layer 19 for limiting or stopping the electric field. Between the layer 19 and the anode 15, a p-doped layer 20 is arranged. Also in this area, the compensation layer 16 changes the course of the field strength. Thus, the field strength course extends through the
  • the compensation layer 6 or 16 is implanted or structured implanted.
  • the gate region body, source or cathode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to an SiC trench transistor (1) with a first terminal (2) and an epitaxial layer (4) arranged vertically between a gate trench (3) and a second terminal (5), a compensation layer (6) which extends horizontally and has an effective doping type opposite the doping type of the epitaxial layer (4) being provided in the epitaxial layer (4). The invention further relates to a method for producing an SiC trench transistor (1), wherein an epitaxial layer (4) is provided on a second terminal (5) of the SiC trench transistor (1); a compensation layer (6) which extends horizontally and has an effective doping type opposite the doping type of the epitaxial layer (4) is implanted into the epitaxial layer (4); and a first terminal (2) and a gate trench (3) are provided above the compensation layer (6).

Description

Beschreibung  description
Titel title
SiC-Trench-Transistor und Verfahren zu dessen Herstellung Die vorliegende Erfindung betrifft einen SiC-Trench-Transistor und ein Verfahren zu dessen Herstellung.  SiC Trench Transistor and Method for Producing the same The present invention relates to a SiC trench transistor and a method of manufacturing the same.
Stand der Technik Leistungshalbleiter auf Basis von Silizium (Si) sind mittlerweile bei einigenBackground Art Power semiconductors based on silicon (Si) have become common in some cases
Anwendungen am Bereich ihrer physikalischen Grenzen. Abhilfe schaffen Verbundhalbleiterwerkstoffe wie etwa Siliziumkarbid (SiC). Applications in the range of their physical limits. To remedy this, compound semiconductor materials such as silicon carbide (SiC).
Bei SiC basierten Bauelementen weist das Gateoxid grundsätzlich ein geringeres Bandoffset im Leitungsband auf als vergleichbare Bauelemente aus Silizium, so dass Degradation infolge von Tunnelströmen schon bei niedrigeren In the case of SiC-based components, the gate oxide generally has a lower band offset in the conduction band than comparable components made of silicon, so that degradation due to tunnel currents already occurs at lower
Gatefeldstärken auftritt. Für SiC-Transistoren insbesondere MOSFETs (Metall- Oxid-Halbleiter-Feldeffekttransistor) wird eine sinnvolle Feldstärke im Gateoxid bei 3 MV / cm liegen. Die Einhaltung dieses Grenzwerts ist insbesondere im Sperrbetrieb kritisch und macht Designmaßnahmen erforderlich, speziell beiGate field strengths occurs. For SiC transistors, in particular MOSFETs (metal oxide semiconductor field effect transistor), a meaningful field strength in the gate oxide will be 3 MV / cm. Compliance with this limit is particularly critical in lock-up and makes design measures required, especially in
Trench-Devices. Trench devices.
Der derzeitige Stand der Wissenschaft beziehungsweise Technik ist das double-trench SiC-Device Konzept von Rohm aus dem Jahr 201 1 , das mit 0,79 mOhm*cm2 einen Bestwert für den spezifischen Durchlasswiderstand Ron in derThe current state of science and technology is the double-trench SiC device concept of Rohm from the year 201 1, which with 0.79 mOhm * cm 2 a best value for the specific on-resistance Ron in the
Spannungsklasse von 600V erreicht. Voltage class of 600V achieved.
Die Feldstärke am Gate-Oxid lässt sich zum Beispiel durch Einführung eines Doppeltrenches mit tiefer p-lmplantation reduzieren. Dabei stellen die tiefer liegenden p-Gebiete einen JFET (Sperrschicht-Feldeffekttransistor) dar, der die eigentliche Trench-MOSFET-Struktur abschirmt. Die Feldstärken am Gateoxid können ebenfalls durch Einführung von p-dotierten Bereichen (p-Bubbles) unterhalb des Gateoxids auf etwa 4 MV / cm reduziert werden (J. Tan et al, High-Voltage Accumulation-Layer, UMOSFETs in 4H-SiC, IEEE ELECTRON DEVICE LETTERS, VOL. 19, NO. 12, DECEMBER 1998). The field strength at the gate oxide can be reduced, for example, by introducing a double trench with a low p implantation. In this case, the lower-lying p regions constitute a JFET (junction field effect transistor), which shields the actual trench MOSFET structure. The field strengths at the gate oxide can also be reduced to about 4 MV / cm by introducing p-type p-type regions (p-bubbles) below the gate oxide (J. Tan et al., High Voltage Accumulation Layer, UMOSFETs in 4H-SiC, IEEE ELECTRON DEVICE LETTERS, VOL 19, NO 12, DECEMBER 1998).
Alternativ können die beiden oben genannten Maßnahmen (double trench , p- Bubbles) kombiniert werden (Quelle 4: Shinsuke Harada et al. , "Determination of optimum structure of 4H-SiC Trench MOSFET" .Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, pp. 253ff). Alternatively, the two above measures (double trench, p-bubbles) can be combined (Source 4: Shinsuke Harada et al., "Determination of optimum structure of 4H-SiC trench MOSFET". Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, pp. 253ff).
Die bisher bekannten Maßnahmen zur Reduktion der Gateoxid-Feldstärke sind teilweise nur bedingt wirksam oder weisen erhebliche Nachteile auf, wie zum Beispiel erhöhten Flächenbedarf, elektrischen Widerstand und/oder Prozess- Komplexität. Insbesondere die "double trench" Struktur benötigt erheblichenThe previously known measures for the reduction of the gate oxide field strength are partially only partially effective or have significant disadvantages, such as increased space requirements, electrical resistance and / or process complexity. In particular, the "double trench" structure requires significant
Platzbedarf, da die erforderliche Trenchstruktur neben dem Trench-Gate angeordnet ist. Damit steigt der spezifische Flächenwiderstand Ron*A und beschränkt den Technologiefortschritt durch höhere Integrationsdichte. Required space, since the required trench structure is arranged next to the trench gate. This increases the specific sheet resistance Ron * A and limits the advancement of technology by higher integration density.
Neben dem erhöhten Flächenbedarf wird durch den JFET Effekt des In addition to the increased space requirement is due to the JFET effect of
Doppeltrenches auch der Widerstand im Strompfad zum Teil deutlich erhöht. Double trenches also significantly increased the resistance in the current path.
Offenbarung der Erfindung Disclosure of the invention
Erfindungsgemäß wird ein SiC-Trench-Transistor mit einem ersten Anschluss, einer vertikal zwischen einem Gate-Trench und einem zweiten Anschluss angeordneten Epitaxieschicht zur Verfügung gestellt, wobei eine sich horizontal erstreckende Kompensationsschicht in der Epitaxieschicht vorgesehen ist, die eine effektive Dotierung mit entgegengesetztem Typ zu der Dotierung der Epitaxieschicht aufweist. Die Kompensationsschicht erlaubt eine Reduktion der elektrischen Gate-Feldstärke ohne erhöhten Flächenbedarf. Diese zusätzlicheAccording to the invention, a SiC trench transistor having a first terminal, an epitaxial layer arranged vertically between a gate trench and a second terminal is provided, wherein a horizontally extending compensation layer is provided in the epitaxial layer, which provides an effective doping of opposite type having the doping of the epitaxial layer. The compensation layer allows a reduction of the electric gate field strength without increased space requirement. This additional
Schicht bewirkt eine Stufe im vertikalen Feldprofil, wobei das niedrigere Niveau zwischen Body und Kompensationsschicht liegt (Gate-naher Bereich) und das hohe Feldniveau unterhalb der Kompensationsschicht liegt (Epitaxieschicht beziehungsweise Driftregion). So kann das insbesondere bei Siliziumkarbid (SiC) basierten Bauelementen geringere Bandoffset im Leitungsband des Gateoxids kompensiert werden. Kern der Erfindung ist eine Halbleiterstruktur, welche die Gate-Feldstärke herabsetzt und vertikal in die SiC-Trench Struktur eingefügt ist. Durch die vertikale Integration können die Trench Strukturen erheblich dichter gepackt werden und der spezifische Flächenwiderstand zwischen Drain und SourceLayer causes a step in the vertical field profile, with the lower level between the body and the compensation layer (gate near area) and the high field level below the compensation layer (epitaxial layer or drift region). Thus, the lower band offset in the conduction band of the gate oxide can be compensated in particular for silicon carbide (SiC) based components. The core of the invention is a semiconductor structure which reduces the gate field strength and is inserted vertically into the SiC trench structure. Due to the vertical integration, the trench structures can be packed significantly denser and the surface resistivity between drain and source
Rdson*A sinkt entsprechend. Zweitens kann die Feldstärke im Gate-Bereich durch entsprechende Wahl der Dotierungen und Abstände eingestellt werden. Durch die Entkopplung des Gate-nahen Feldbereichs von der Epitaxieschicht beziehungsweise vom Driftbereich können im Kanal nahen Driftbereich höhere n-Dotierungen verwendet werden ohne signifikante Nachteile für die Rdson * A drops accordingly. Second, the field strength in the gate region can be adjusted by appropriate choice of doping and spacing. By decoupling the gate-near field region from the epitaxial layer or the drift region, higher n-type dopants can be used in the channel near the drift region without significant disadvantages for the
Spannungsaufnahmefähigkeit der Driftzone. Vorteil ist hier die Reduktion von ohmschen Verlusten im Kanal-nahen Bereich („current spreading").  Voltage absorbing capacity of the drift zone. The advantage here is the reduction of ohmic losses in the channel-near range ("current spreading").
Das arithmetische Mittel der Dotierung der Kompensationsschicht kann der Dotierung mit entgegengesetztem Typ entsprechen. Dies erlaubt vielfältigeThe arithmetic mean of the doping of the compensation layer may correspond to the doping of opposite type. This allows manifold
Gestaltungen der Dotierung der Kompensationsschicht, da lediglich das Mittel einem bestimmten Dotierungswert entsprechen muss. Somit sind unregelmäßige Dotierungen möglich. In einer besonderen Ausführungsform ist vorgesehen, dass der Transistor einEmbodiments of the doping of the compensation layer, since only the means must correspond to a certain doping value. Thus, irregular doping is possible. In a particular embodiment, it is provided that the transistor
SiC-Trench-MOSFET ist, der erste Anschluss ein Source-Anschluss, der zweite Anschluss eine Drainstruktur und die Epitaxieschicht eine Driftzone ist. SiC trench MOSFET, the first terminal is a source terminal, the second terminal is a drain structure, and the epitaxial layer is a drift zone.
Insbesondere bei MOSFETs ist die erfindungsgemäße Anpassung oder Einstellung der Gate-Feldstärke wichtig. Especially with MOSFETs, the adaptation or adjustment of the gate field strength according to the invention is important.
Die Kompensationsschicht kann Durchgänge mit einer Dotierung vom Typ der Driftzone aufweisen. Diese Durchgänge erlauben einen Stromdurchgang für den MOSFET, sodass die Funktionsweise beziehungsweise Funktionsfähigkeit des MOSFETs nicht eingeschränkt ist. Die Durchgänge können runde oder eckige Umrisse aufweisen und in regelmäßigen oder unregelmäßigen Abständen beziehungsweise Mustern angeordnet sein. The compensation layer can have passages with a doping of the type of drift zone. These passages allow current to pass through the MOSFET so that the functionality or functionality of the MOSFET is not restricted. The passages may have round or angular outlines and may be arranged at regular or irregular intervals or patterns.
Es ist mit Vorteil vorgesehen, dass die Kompensationsschicht eine alternierende Folge von p-dotierten und n-dotierten Gebieten in einer Flächenrichtung der Kompensationsschicht aufweist. Diese Variante ist einfach herzustellen und erlaubt einen guten Stromdurchgang sowie eine einfache Berechnung und Herstellung der Dotierung der Kompensationsschicht, insbesondere die It is advantageously provided that the compensation layer has an alternating sequence of p-doped and n-doped regions in a planar direction of the compensation layer. This variant is easy to manufacture and allows a good passage of electricity as well as a simple calculation and Production of the doping of the compensation layer, in particular the
Berechnung und Umsetzung des arithmetischen Mittels der Dotierung. Calculation and implementation of the arithmetic mean of the doping.
Alternativ ist mit Vorteil vorgesehen, dass die Kompensationsschicht ein alternierendes Muster von p-dotierten und n-dotierten Gebieten in zwei Alternatively, it is advantageously provided that the compensation layer comprises an alternating pattern of p-doped and n-doped regions in two
Flächenrichtungen der Kompensationsschicht aufweist. Diese zweidimensionale Anordnung der Gebiete erlaubt im Vergleich zu der zuvor genannten Surface directions of the compensation layer has. This two-dimensional arrangement of the areas allows in comparison to the aforementioned
eindimensionalen Anordnung eine noch feinere Einstellung von Dotierung und Stromdurchgang und damit der Gate-Feldstärke. one-dimensional arrangement an even finer adjustment of doping and current passage and thus the gate field strength.
Auch ist es möglich, dass der Transistor ein SiC-Trench-IGBT (insulated-gate bipolar transistor) ist, der erste Anschluss ein Kathoden-Anschluss, der zweite Anschluss ein Anoden-Anschluss und die Epitaxieschicht eine Basiszone ist. Hier erlaubt die Kompensationsschicht eine Absenkung der Feldstärke im Gateoxid, was neue Einsatzgebiete für IGBTs eröffnet. It is also possible that the transistor is a SiC trench IGBT (insulated-gate bipolar transistor), the first terminal is a cathode terminal, the second terminal is an anode terminal and the epitaxial layer is a base zone. Here, the compensation layer allows a reduction of the field strength in the gate oxide, which opens up new fields of application for IGBTs.
Die Kompensationsschicht kann eine niedrige homogene Dotierung vom entgegengesetzten Typ zu der Dotierung der Basiszone aufweisen. Diese Dotierung kann einfach hergestellt werden. The compensation layer may have a low homogeneous dopant of the opposite type to the doping of the base region. This doping can be easily produced.
Vorzugsweise hat die Kompensationsschicht einen Abstand von maximal 25% der Driftzonendicke zum Gatekanal. Es hat sich gezeigt, dass dieser Preferably, the compensation layer has a maximum distance of 25% of the drift zone thickness to the gate channel. It has been shown that this
Abstandsbereich eine optimale Feldstärke im Gateoxid erlaubt. Distance range allows an optimal field strength in the gate oxide.
Das erfindungsgemäße Verfahren zur Herstellung eines SiC-Trench-Transistors umfasst grundsätzlich folgende Schritte: The inventive method for producing a SiC trench transistor basically comprises the following steps:
- Vorsehen einer Epitaxieschicht auf einen zweiten Anschluss des  Providing an epitaxial layer on a second terminal of the
SiC-Trench-Transistors;  SiC trench transistor;
- Implantieren einer sich horizontal erstreckenden Kompensationsschicht in die Epitaxieschichtm, die eine effektive Dotierung mit entgegengesetztem Typ zu der Dotierung der Epitaxieschicht aufweist;  - implanting a horizontally extending compensation layer in the epitaxial layer, which has an effective doping of opposite type to the doping of the epitaxial layer;
und and
- Vorsehen eines ersten Anschlusses und eines Gate-Trenchs oberhalb der Kompensationsschicht.  Providing a first terminal and a gate trench above the compensation layer.
Die erfindungsgemäße Einbringung der Kompensationsschicht erlaubt vorteilhaft eine Steuerung des elektrischen Feldverlaufs im Gate-Trench und/oder in der Epitaxieschicht, sodass der Transistor genau auf seine Verwendung eingestellt werden kann. The introduction of the compensation layer according to the invention advantageously permits control of the electric field characteristic in the gate trench and / or in the gate Epitaxial layer, so that the transistor can be adjusted exactly to its use.
Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben und in der Beschreibung beschrieben. Advantageous developments of the invention are specified in the subclaims and described in the description.
Zeichnungen drawings
Ausführungsbeispiele der Erfindung werden anhand der Zeichnungen und der nachfolgenden Beschreibung näher erläutert. Es zeigen: Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:
Figur 1 eine schematische Schnittdarstellung eines SiC-Trench-MOSFETs mit Kompensationsschicht und dazugehörigem elektrischem Feldverlauf; Figure 1 is a schematic sectional view of a SiC trench MOSFETs with compensation layer and associated electric field characteristic;
Figur 2 ein Ausführungsbeispiel der Kompensationsschicht in einer Figure 2 shows an embodiment of the compensation layer in one
Flächenrichtung; Surface direction;
Figur 3 ein weiteres Ausführungsbeispiel der Kompensationsschicht in einer Flächenrichtung; FIG. 3 shows a further embodiment of the compensation layer in a surface direction;
Figur 4 ein weiteres Ausführungsbeispiel der Kompensationsschicht in einer anderen Flächenrichtung; FIG. 4 shows a further embodiment of the compensation layer in another surface direction;
Figur 5 ein weiteres Ausführungsbeispiel der Kompensationsschicht in zwei Flächenrichtungen; und FIG. 5 shows a further embodiment of the compensation layer in two surface directions; and
Figur 6 eine schematische Schnittdarstellung eines SiC-Trench-IGBTs mit Kompensationsschicht und dazugehörigem elektrischem Feldverlauf. Figure 6 is a schematic sectional view of a SiC trench IGBT with compensation layer and associated electric field profile.
Ausführungsformen der Erfindung Embodiments of the invention
Figur 1 zeigt im Querschnitt einen SIC-Trench-Transistor 1 mit einem Figure 1 shows in cross-section an SIC trench transistor 1 with a
Sourceanschluss 2 und einem Gate-Trench 3. Unterhalb des Sourceanschlusses 2 und des Gate-Trenches 3 ist eine Epitaxieschicht in Form einer Driftzone 4 angeordnet. Unterhalb der Driftzone 4 befindet sich ein Drainanschluss oder eine Drainstruktur 5. In der zwischen dem Gate 3 und der Drainstruktur 5 angeordneten Driftzone 4 ist eine Kompensationsschicht 6 vorgesehen, die sich horizontal erstreckt. Die hier gemachten Richtungsangaben, wie zum Beispiel unterhalb oder horizontal, beziehen sich auf die bildliche Darstellung in den Figuren. Sollte der Transistor 1 anders als in Figur 1 ausgerichtet sein, sind diese relativen Begriffe Source terminal 2 and a gate trench 3. Below the source terminal 2 and the gate trench 3, an epitaxial layer in the form of a drift zone 4 is arranged. Below the drift zone 4 there is a drain connection or a drain structure 5. In the drift zone 4 arranged between the gate 3 and the drain structure 5, a compensation layer 6 is provided which extends horizontally. The directions given here, such as below or horizontally, refer to the pictorial representation in the figures. Should the transistor 1 be oriented differently than in FIG. 1, these are relative terms
entsprechend umzudefinieren. Die Richtungsbezüge können andererseits auch unter Bezugnahme auf den Gate-Trench 3 genauer gesagt auf dessen to redefine accordingly. The directional references, on the other hand, may be more specifically referred to with reference to the gate trench 3
Haupterstreckung, die hier von oben nach unten verläuft, definiert werden. Main extension, which runs here from top to bottom, to be defined.
Demnach verläuft die Kompensationsschicht 6 senkrecht zu dem Gate-Trench 3. Accordingly, the compensation layer 6 is perpendicular to the gate trench. 3
In dem in Figur 1 dargestellten Beispiel des SIC-Trench-Transistors 1 ist die Driftzone 4 n-dotiert und die Kompensationsschicht 6 ist effektiv p-dotiert, also mit dem entgegengesetzten Typ oder Ladungstyp zu der Driftzone 4. In the example of the SIC trench transistor 1 shown in FIG. 1, the drift zone 4 is n-doped and the compensation layer 6 is effectively p-doped, ie with the opposite type or charge type to the drift zone 4.
Selbstverständlich können die Dotierungen auch umgekehrt ausgewählt werden. Die effektive Dotierung kann beispielsweise als das arithmetische Mittel derOf course, the dopants can also be selected in reverse. The effective doping may be exemplified as the arithmetic mean of the
Dotierung in der Kompensationsschicht 6 definiert sein. Die räumliche Doping be defined in the compensation layer 6. The spatial
Erstreckung der Kompensationsschicht 6 in einer Ebene, beispielsweise der x- und y-Richtung, ist dann üblicherweise auf die Zelle beziehungsweise den Bereich des Transistors 1 begrenzt. Extension of the compensation layer 6 in a plane, for example the x and y direction, is then usually limited to the cell or the region of the transistor 1.
Rechts neben dem Transistor 1 ist in einem Diagramm der Betrag der elektrischen Feldstärke E über die vertikale Erstreckung des Transistors 1 aufgetragen. Eine erste gestrichelt dargestellte Kurve 7 zeigt den Right next to the transistor 1, the magnitude of the electric field strength E is plotted over the vertical extent of the transistor 1 in a diagram. A first dashed curve 7 shows the
Feldstärkenverlauf für einen bekannten SIC-Trench-Transistor ohne Field strength curve for a known SIC trench transistor without
Kompensationsschicht. Hier liegt das Maximum der elektrischen Feldstärke imCompensation layer. Here lies the maximum of the electric field strength in
Bereich des pn-Überganges zwischen dem Sourcebereich und der Driftzone 4, was zu einer hohen Gate-Feldstärke führt. Die zweite Kurve 8 hingegen zeigt den Feldstärkenverlauf des dargestellten erfindungsgemäßen SIC-Trench-Transistors 1. Wie zu sehen ist, bewirkt die Kompensationsschicht 6 eine Stufe im vertikalen Feldprofil, wobei das niedrigere Niveau des Feldverlaufs zwischen dem Gate 3 und der Kompensationsschicht 6 liegt, während das hohe Feldniveau unterhalb der Kompensationsschicht 6 genauer gesagt im Bereich des pn-Überganges zwischen der Kompensationsschicht 6 und der Driftzone 4 liegt. Area of the pn junction between the source region and the drift zone 4, resulting in a high gate field strength. The second curve 8, on the other hand, shows the field intensity profile of the illustrated SIC trench transistor 1 according to the invention. As can be seen, the compensation layer 6 effects a step in the vertical field profile, with the lower level of the field profile lying between the gate 3 and the compensation layer 6 the high field level below the compensation layer 6 more precisely lies in the region of the pn junction between the compensation layer 6 and the drift zone 4.
Über die Höhe der effektiven Dotierung der Kompensationsschicht 6, die vertikale Anordnung der Kompensationsschicht 6, das heißt insbesondere der Abstand zwischen der Kompensationsschicht 6 und dem Gate-Trench 3 und/oder die Dicke der Kompensationsschicht 6 in vertikaler Richtung kann das About the amount of the effective doping of the compensation layer 6, the vertical arrangement of the compensation layer 6, that is in particular the Distance between the compensation layer 6 and the gate trench 3 and / or the thickness of the compensation layer 6 in the vertical direction, the
Feldstärkeprofil des Transistors 1 individuell auf die jeweiligen Einsatzzwecke angepasst oder eingestellt werden. Field strength profile of the transistor 1 can be adjusted or adjusted individually to the respective purposes.
In Figur 2 ist eine erste Realisierung der Kompensationsschicht 6 dargestellt. Hier besteht die Kompensationsschicht aus einer alternierenden Folge von n- dotierten Gebieten 6a und p-dotierten Gebieten 6b. Die n-dotierten Gebiete 6a bilden dabei Durchgänge für den Strom des Transistors 1. Die Abstände der einzelnen Gebiete beziehungsweise deren Breite oder Länge sind grösser als dieFIG. 2 shows a first realization of the compensation layer 6. Here, the compensation layer consists of an alternating sequence of n-doped regions 6a and p-doped regions 6b. The n-doped regions 6a form passages for the current of the transistor 1. The distances of the individual regions or their width or length are greater than that
Raumladungszonen und klein (idealerweise kleiner 1/10) gegenüber der Space charge zones and small (ideally less than 1/10) over the
Driftzonenlänge, das heißt dem Abstand zwischen dem Gate 3 und der Drift zone length, that is the distance between the gate 3 and the
Drainstruktur 5. Damit ergibt sich eine typische Strukturgröße von 0.1 ... 5μηι. Die dotierten Gebiete 6a und 6b erstrecken sich streifenförmig in Richtung des streifenförmigen Gate-Trenches 3, hier also in die Blattebene hinein. Drain structure 5. This results in a typical structure size of 0.1 ... 5μηι. The doped regions 6a and 6b extend in the form of a strip in the direction of the strip-shaped gate trench 3, in this case into the plane of the page.
Für die Stromleitfähigkeit der Kompensationsschicht 6 im Durchlassfall des Transistors 1 ist ein möglichst hohes Dotierniveau anzustreben unter der Randbedingung, dass die effektive Dotierung oder mittlere Dotierung oder anders ausgedrückt die volumengewichtete Differenz zwischen der n- und der p-For the current conductivity of the compensation layer 6 in the case of the passage of the transistor 1, the highest possible doping level is to be striven for under the boundary condition that the effective doping or average doping or, in other words, the volume-weighted difference between the n and the p-
Dotierstoffkonzentration entsprechend dem vertikalen Feldstärkezielverlauf inklusive dem Fertigungstoleranzen eingehalten wird. Dopant concentration is maintained according to the vertical field strength target profile including the manufacturing tolerances.
Die Ausgestaltung der pn-Übergänge der Kompensationsschicht 6 kann weitgehend frei erfolgen, das heißt auf Durchlasseigenschaften beziehungsweiseThe design of the pn junctions of the compensation layer 6 can be largely free, that is to pass properties or
Fertigungsmöglichkeiten optimiert. Die Periodizität der Kompensationsschicht 6, das heißt die alternierende Abfolge der n-dotierten Gebiete 6a und der p- dotierten Gebiete 6b ist kleiner oder in der Größenordnung der Driftzone zu wählen (typischerweise 1... 10μηι). Optimized manufacturing capabilities. The periodicity of the compensation layer 6, that is to say the alternating sequence of the n-doped regions 6a and the p-doped regions 6b, is to be selected smaller or in the order of magnitude of the drift zone (typically 1... 10 μm).
In Figur 3 ist ein SiC-Trench-Transistor 1 mit einer Kompensationsschicht 6 gezeigt, die eine größere Periodizität aufweist, das heißt, dass die Schicht 6 pro Zelle mehr pn-Übergänge im Vergleich zu Figur 2 aufweist. Bei dem hier gezeigten Gate-Streifendesign weist auch die Kompensationsschicht 6 ein Streifendesign parallel zu der Gateorientierung also einer Flächenrichtung der Kompensationsschicht 6 auf. Hierbei sind vorteilhafterweise die n-Gebiete 6a der Kompensationsschicht 6 unter dem Kanalbereich ausgerichtet. FIG. 3 shows a SiC trench transistor 1 with a compensation layer 6 which has a greater periodicity, that is to say that the layer 6 has more pn junctions per cell in comparison to FIG. In the case of the gate stripe design shown here, the compensation layer 6 also has a stripe design parallel to the gate orientation, ie, a surface direction of the stripe design Compensation layer 6 on. In this case, the n-regions 6a of the compensation layer 6 are advantageously aligned below the channel region.
In Figur 4 ist ein weiteres Beispiel eines SiC-Trench-Transistors 1 mit einer Kompensationsschicht 6 dargestellt. Auch hier besteht die KompensationsschichtFIG. 4 shows another example of a SiC trench transistor 1 with a compensation layer 6. Again, there is the compensation layer
6 aus einer alternierenden Folge von p-dotierten Gebieten 6b und n-dotierten Gebieten 6a entlang einer Flächenrichtung der Kompensationsschicht 6. Im Unterschied zu den Figuren 2 und 3 verlaufen hier die dotierten Gebiete 6a und 6b quer oder senkrecht zu der Erstreckung des streifenförmigen Gates 3. Die dotierten Gebiete 6a und 6b können auch unter einem anderen Winkel angeordnet sein. 6 from an alternating sequence of p-doped regions 6b and n-doped regions 6a along a surface direction of the compensation layer 6. In contrast to FIGS. 2 and 3, the doped regions 6a and 6b extend transversely or perpendicularly to the extent of the strip-shaped gate 3 The doped regions 6a and 6b may also be arranged at a different angle.
In Figur 5 ist ein SiC-Trench-Transistor mit einer Kompensationsschicht 6 dargestellt, bei der ein alternierendes Muster von p-dotierten Gebieten 6b und n-dotierten Gebieten 6a in zwei Flächenrichtungen der Kompensationsschicht 6 vorgesehen ist. Das Muster ist hier ein zweidimensionales periodisches Gitter, das sich im Speziellen für zweidimensionale MOS-Designs wie zum Beispiel hexagonale Zellstrukturen eignet. Ein Schachbrettdesign ist ebenfalls möglich. Auch hier sind vorteilhafterweise die n-Gebiete 6a der Kompensationsschicht 6 unter dem Kanalbereich ausgerichtet, zumindest hinsichtlich der FIG. 5 shows a SiC trench transistor with a compensation layer 6, in which an alternating pattern of p-doped regions 6b and n-doped regions 6a is provided in two surface directions of the compensation layer 6. The pattern here is a two-dimensional periodic lattice that is particularly suitable for two-dimensional MOS designs, such as hexagonal cell structures. A checkerboard design is also possible. Again, the n-regions 6a of the compensation layer 6 are advantageously aligned below the channel region, at least as regards the
Längserstreckung des Gate-Trenchs 3.  Longitudinal extension of the gate trench 3.
In Figur 6 ist ein SiC-Trench-IGBT 10 dargestellt, mit einem Kathoden-Anschluss 12 und einem Gate-Trench 13. Unterhalb des Gate-Trenches 13 und des Kathodenanschlusses 12 ist in Form einer Epitaxieschicht eine Basiszone 14 angeordnet. Wiederum unterhalb der Basiszone 14 ist ein Anoden-Anschluss 15 vorgesehen. In der Basiszone 14 ist eine sich horizontal erstreckende FIG. 6 shows a SiC trench IGBT 10 with a cathode terminal 12 and a gate trench 13. Beneath the gate trench 13 and the cathode terminal 12, a base zone 14 is arranged in the form of an epitaxial layer. Again below the base zone 14, an anode terminal 15 is provided. In the base zone 14 is a horizontally extending
Kompensationsschicht 16 vorgesehen, um die Feldstärke im Gateoxid zu verringern. We zuvor hat die Kompensationsschicht 16 eine effektive Dotierung mit einem entgegengesetzten Typ zu der Dotierung der Basiszone 14. In diesemCompensating layer 16 is provided to reduce the field strength in the gate oxide. As before, the compensation layer 16 has an effective doping of an opposite type to the doping of the base region 14. In this
Fall ist die Basiszone 14 n-dotiert, während die Kompensationsschicht 16 p-dotiert ist. Da bei einem IGBT kein unipolarer Durchgangsstrom benötigt wird, kann die Kompensationsschicht 16 als eine niedrig dotierte homogene Schicht ausgebildet sein. Der in der Figur 6 rechts dargestellte Feldstärkenverlauf entspricht dem in Figur 1 dargestellten Verlauf. Die Kurve 17 zeigt den Verlauf der Feldstärke für einen bekannten IGBT ohne Kompensationsschicht 16. Dabei ist der Betrag der Feldstärke im Bereich des Gate-Oxids am höchsten. Die Kurve 18 zeigt den durch die Kompensationsschicht 16 optimierten Feldstärkeverlauf mit deutlich geringerer Feldstärke im Bereich des Gate-Oxids. Der Transistor 10 enthält unterhalb der Basiszone 14 eine optionale stark n-dotierte Schicht 19 zum Begrenzen beziehungsweise Stoppen des elektrischen Feldes. Zwischen der Schicht 19 und der Anode 15 ist eine p-dotierte Schicht 20 angeordnet. Auch in diesem Bereich verändert die Kompensationsschicht 16 den Verlauf der Feldstärke. So erstreckt sich der Feldstärkeverlauf durch die In this case, the base region 14 is n-doped while the compensation layer 16 is p-doped. Since no unipolar through-current is required in an IGBT, the compensation layer 16 may be formed as a low-doped homogeneous layer. The field strength curve shown on the right in FIG. 6 corresponds to the profile shown in FIG. The curve 17 shows the course of the field strength for a known IGBT without compensation layer 16. Dabei For example, the amount of field strength in the region of the gate oxide is highest. The curve 18 shows the field strength profile optimized by the compensation layer 16 with significantly lower field strength in the region of the gate oxide. The transistor 10 includes below the base region 14 an optional heavily n-doped layer 19 for limiting or stopping the electric field. Between the layer 19 and the anode 15, a p-doped layer 20 is arranged. Also in this area, the compensation layer 16 changes the course of the field strength. Thus, the field strength course extends through the
Kompensationsschicht 16 weiter in Richtung der Anode 15. Compensation layer 16 further in the direction of the anode 15th
Die technologische Umsetzung beziehungsweise Herstellung der oben gezeigten Bauelemente in Form von SiC-Trench-Transistoren 1 , 10 erfolgt in zwei The technological implementation or production of the components shown above in the form of SiC trench transistors 1, 10 takes place in two
Epitaxieschritten, wobei nach der ersten Epitaxie, bei der auf einem zweiten Anschluss (Drain 5, Anode 15) die Epitaxieschicht (Driftzone 4, Basiszone 14) aufgebracht wird, die Kompensationsschicht 6 beziehungsweise 16 implantiert beziehungsweise strukturiert implantiert wird. In einem zweiten Epitaxieschritt oder sonstigem Schritt wird anschließend der Gatebereich (Body, Source beziehungsweise Katode) hergestellt. Epitaxy steps, wherein after the first epitaxy, in which the epitaxial layer (drift zone 4, base zone 14) is applied to a second terminal (drain 5, anode 15), the compensation layer 6 or 16 is implanted or structured implanted. In a second Epitaxieschritt or other step then the gate region (body, source or cathode) is produced.

Claims

Ansprüche claims
SiC-Trench-Transistor mit einem ersten Anschluss (2; 12), einer vertikal zwischen einem Gate-Trench (3; 13) und einem zweiten Anschluss (5; 15) angeordneten Epitaxieschicht (4; 14), dadurch gekennzeichnet, dass eine sich horizontal erstreckende Kompensationsschicht (6; 16) in der SiC trench transistor having a first terminal (2; 12), an epitaxial layer (4; 14) arranged vertically between a gate trench (3; 13) and a second terminal (5; 15), characterized in that a horizontally extending compensation layer (6; 16) in the
Epitaxieschicht (4; 14) vorgesehen ist, die eine effektive Dotierung mit entgegengesetztem Typ zu der Dotierung der Epitaxieschicht (4; 14) aufweist.  Epitaxial layer (4; 14) is provided which has an effective doping of opposite type to the doping of the epitaxial layer (4; 14).
SiC-Trench-Transistor nach Anspruch 1 , wobei das arithmetische Mittel der Dotierung der Kompensationsschicht (6; 16) der Dotierung mit SiC trench transistor according to claim 1, wherein the arithmetic means of doping the compensation layer (6; 16) of the doping with
entgegengesetztem Typ entspricht.  opposite type corresponds.
SiC-Trench-Transistor nach Anspruch 1 oder 2, wobei der Transistor (1) ein SiC-Trench-MOSFET ist, der erste Anschluss ein Source-Anschluss (2), der zweite Anschluss eine Drainstruktur (5) und die Epitaxieschicht eine SiC trench transistor according to claim 1 or 2, wherein the transistor (1) is a SiC trench MOSFET, the first terminal a source terminal (2), the second terminal a drain structure (5) and the epitaxial layer a
Driftzone (4) ist.  Drift zone (4) is.
SiC-Trench-Transistor nach Anspruch 3, wobei die Kompensationsschicht (6) Durchgänge (6a) mit einer Dotierung vom Typ der Driftzone aufweist. SiC trench transistor according to claim 3, wherein the compensation layer (6) has passages (6a) with a doping of the type of drift zone.
SiC-Trench-Transistor nach Anspruch 3 oder 4, wobei die SiC trench transistor according to claim 3 or 4, wherein the
Kompensationsschicht (6) eine alternierende Folge von p-dotierten (6b) und n-dotierten (6a) Gebieten in einer Flächenrichtung der  Compensation layer (6) an alternating sequence of p-doped (6b) and n-doped (6a) areas in a plane direction of
Kompensationsschicht (6) aufweist.  Compensation layer (6).
SiC-Trench-Transistor nach einem der Ansprüche 3 bis 5, wobei die SiC trench transistor according to one of claims 3 to 5, wherein the
Kompensationsschicht (6) ein alternierendes Muster von p-dotierten (6b) und n-dotierten (6a) Gebieten in zwei Flächenrichtungen der  Compensation layer (6) an alternating pattern of p-doped (6b) and n-doped (6a) areas in two planar directions of
Kompensationsschicht (6) aufweist. Compensation layer (6).
7. SiC-Trench-Transistor nach Anspruch 1 oder 2, wobei der Transistor (10) ein SiC-Trench-IGBT ist, der erste Anschluss ein Kathoden-Anschluss (12), der zweite Anschluss ein Anoden-Anschluss (15) und die Epitaxieschicht eine Basiszone (14) ist. 7. SiC trench transistor according to claim 1 or 2, wherein the transistor (10) is a SiC trench IGBT, the first terminal a cathode terminal (12), the second terminal an anode terminal (15) and the Epitaxial layer is a base zone (14).
8. SiC-Trench-Transistor nach Anspruch 7, wobei die Kompensationsschicht (16) eine niedrige homogene Dotierung vom entgegengesetzten Typ aufweist. 8. SiC trench transistor according to claim 7, wherein the compensation layer (16) has a low homogeneous doping of the opposite type.
SiC-Trench-Transistor nach Anspruch 3 oder 7 oder 8, wobei die SiC trench transistor according to claim 3 or 7 or 8, wherein the
Kompensationsschicht (16) einen Abstand von maximal 25% der  Compensating layer (16) a distance of not more than 25% of
Driftzonendicke (4; 14) zum Gate-Trench (13) aufweist.  Drift zone thickness (4; 14) to the gate trench (13).
10. Verfahren zur Herstellung eines SiC-Trench-Transistors (1 ; 10), mit den 10. A method for producing a SiC trench transistor (1; 10), with the
folgenden Schritten:  following steps:
- Vorsehen einer Epitaxieschicht (4; 14) auf einen zweiten Anschluss (5;  - Providing an epitaxial layer (4; 14) on a second terminal (5;
15) des SiC-Trench-Transistors (1 ; 10);  15) of the SiC trench transistor (1; 10);
- Implantieren einer sich horizontal erstreckenden Kompensationsschicht (6; 16) in die Epitaxieschicht (4; 14), die eine effektive Dotierung mit entgegengesetztem Typ zu der Dotierung der Epitaxieschicht (4; 14) aufweist; und  - implanting a horizontally extending compensation layer (6; 16) into the epitaxial layer (4; 14) having an effective doping of opposite type to the doping of the epitaxial layer (4; 14); and
- Vorsehen eines ersten Anschlusses (2; 12) und eines Gate-Trenchs (3;  - Providing a first terminal (2, 12) and a gate trench (3;
13) oberhalb der Kompensationsschicht (6; 16).  13) above the compensation layer (6; 16).
EP14802057.1A 2014-01-15 2014-11-21 Sic trench transistor and method for producing same Ceased EP3095136A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014200613.9A DE102014200613A1 (en) 2014-01-15 2014-01-15 SiC trench transistor and method for its production
PCT/EP2014/075277 WO2015106863A1 (en) 2014-01-15 2014-11-21 Sic trench transistor and method for producing same

Publications (1)

Publication Number Publication Date
EP3095136A1 true EP3095136A1 (en) 2016-11-23

Family

ID=51945894

Family Applications (1)

Application Number Title Priority Date Filing Date
EP14802057.1A Ceased EP3095136A1 (en) 2014-01-15 2014-11-21 Sic trench transistor and method for producing same

Country Status (7)

Country Link
US (1) US9761706B2 (en)
EP (1) EP3095136A1 (en)
JP (1) JP6305547B2 (en)
CN (1) CN105917470A (en)
DE (1) DE102014200613A1 (en)
TW (1) TWI641053B (en)
WO (1) WO2015106863A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016205331A1 (en) 2016-03-31 2017-10-05 Robert Bosch Gmbh Vertical SiC-MOSFET
CN106876470A (en) * 2017-03-23 2017-06-20 深圳基本半导体有限公司 A kind of trench gate metal oxide field-effect transistor and its manufacture method
JP6870547B2 (en) * 2017-09-18 2021-05-12 株式会社デンソー Semiconductor devices and their manufacturing methods
JP6981890B2 (en) * 2018-01-29 2021-12-17 ルネサスエレクトロニクス株式会社 Semiconductor device
JP7277546B2 (en) * 2018-01-29 2023-05-19 ルネサスエレクトロニクス株式会社 semiconductor equipment
JP7140642B2 (en) * 2018-11-15 2022-09-21 トヨタ自動車株式会社 switching element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
US20060244056A1 (en) * 2005-04-28 2006-11-02 Nec Electronics Corporation Semiconductor device
DE102008044408A1 (en) * 2007-12-12 2009-06-25 Infineon Technologies Austria Ag Semiconductor device arrangement with low on-resistance

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2727481B2 (en) 1992-02-07 1998-03-11 キヤノン株式会社 Cleaning method for glass substrate for liquid crystal element
SE9704149D0 (en) 1997-11-13 1997-11-13 Abb Research Ltd A semiconductor device of SiC and a transistor of SiC having an insulated gate
JP4028333B2 (en) * 2002-09-02 2007-12-26 株式会社東芝 Semiconductor device
JP4564362B2 (en) * 2004-01-23 2010-10-20 株式会社東芝 Semiconductor device
JP2008177335A (en) 2007-01-18 2008-07-31 Fuji Electric Device Technology Co Ltd Silicon carbide insulated gate semiconductor device
JP4640439B2 (en) * 2008-04-17 2011-03-02 株式会社デンソー Silicon carbide semiconductor device
JP5728992B2 (en) * 2011-02-11 2015-06-03 株式会社デンソー Silicon carbide semiconductor device and manufacturing method thereof
JP2013155670A (en) 2012-01-30 2013-08-15 Daihatsu Motor Co Ltd Heat insulator
JP2013165197A (en) * 2012-02-13 2013-08-22 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device and silicon carbide semiconductor device manufacturing method
CN102842612A (en) * 2012-09-11 2012-12-26 电子科技大学 Insulated-gate bipolar transistor with embedded island structure
JP6171678B2 (en) * 2013-07-26 2017-08-02 住友電気工業株式会社 Silicon carbide semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
US20060244056A1 (en) * 2005-04-28 2006-11-02 Nec Electronics Corporation Semiconductor device
DE102008044408A1 (en) * 2007-12-12 2009-06-25 Infineon Technologies Austria Ag Semiconductor device arrangement with low on-resistance

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2015106863A1 *

Also Published As

Publication number Publication date
WO2015106863A1 (en) 2015-07-23
US20160329424A1 (en) 2016-11-10
JP6305547B2 (en) 2018-04-04
TW201539581A (en) 2015-10-16
JP2017504213A (en) 2017-02-02
DE102014200613A1 (en) 2015-07-16
TWI641053B (en) 2018-11-11
US9761706B2 (en) 2017-09-12
CN105917470A (en) 2016-08-31

Similar Documents

Publication Publication Date Title
DE102017108738B4 (en) SiC SEMICONDUCTOR DEVICE WITH AN OFFSET IN A TRENCH BOTTOM AND MANUFACTURING METHOD THEREOF
DE112016003510B4 (en) SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
DE112014000679B4 (en) Insulating layer silicon carbide semiconductor device and process for its production
DE102008039845B4 (en) IGBT with a semiconductor body
DE112012006039B4 (en) METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT
DE112013002125B4 (en) Silicon carbide semiconductor device and manufacturing method thereof
DE112012004043B4 (en) Semiconductor device
DE102013105060B4 (en) VERTICAL SEMICONDUCTOR DEVICE
DE102019111308A1 (en) SILICON CARBIDE SEMICONDUCTOR ELEMENT
DE102010016371B4 (en) Semiconductor device
DE102019121859B3 (en) SILICON CARBIDE DEVICE WITH TRENCH GATE
DE112015004374T5 (en) SEMICONDUCTOR DEVICE
WO2015106863A1 (en) Sic trench transistor and method for producing same
DE112019003790T5 (en) SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE
DE102012021534B4 (en) SCHOTTKY SEALING LAYER SEMICONDUCTOR ELEMENT FROM THE GRAY TYPE AND MANUFACTURING METHOD THEREFOR
DE102006055131A1 (en) Semiconductor component for power uses has super blocking arrangement having alternating first and second type dopant layers between substrate and channel
DE102018103550B4 (en) SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY MADE OF SILICON CARBIDE
DE112010005980T5 (en) Semiconductor element
DE112016002613T5 (en) Power semiconductor component
DE112017002113B4 (en) semiconductor unit
DE102015109545B4 (en) Transistor with field electrodes and improved avalanche breakdown behavior
DE102019112985B4 (en) Process for the production of semiconductor devices
DE102019108062B4 (en) SILICON CARBIDE DEVICE WITH TRENCH GATE STRUCTURE AND MANUFACTURING METHOD
DE112017003957T5 (en) Semiconductor element
DE102012108302A1 (en) Semiconductor device and method of manufacturing the semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20160816

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20191028

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ROBERT BOSCH GMBH

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

REG Reference to a national code

Ref country code: DE

Ref legal event code: R003

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20221210