EP3038070A1 - Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit - Google Patents

Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit Download PDF

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Publication number
EP3038070A1
EP3038070A1 EP15202102.8A EP15202102A EP3038070A1 EP 3038070 A1 EP3038070 A1 EP 3038070A1 EP 15202102 A EP15202102 A EP 15202102A EP 3038070 A1 EP3038070 A1 EP 3038070A1
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European Patent Office
Prior art keywords
bus
switching elements
master device
driver circuit
bus master
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EP15202102.8A
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German (de)
French (fr)
Inventor
Robin Janßen
Heiner Politze
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Novar GmbH
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Novar GmbH
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Publication of EP3038070A1 publication Critical patent/EP3038070A1/en
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    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B25/00Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems
    • G08B25/01Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium
    • G08B25/04Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium using a single signalling line, e.g. in a closed loop
    • G08B25/045Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium using a single signalling line, e.g. in a closed loop with sensing devices and central station in a closed loop, e.g. McCullough loop
    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B26/00Alarm systems in which substations are interrogated in succession by a central station
    • G08B26/001Alarm systems in which substations are interrogated in succession by a central station with individual interrogation of substations connected in parallel
    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/02Monitoring continuously signalling or alarm systems
    • G08B29/06Monitoring of the line circuits, e.g. signalling of line faults
    • GPHYSICS
    • G08SIGNALLING
    • G08BSIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/12Checking intermittently signalling or alarm systems
    • G08B29/123Checking intermittently signalling or alarm systems of line circuits

Definitions

  • the present invention is directed to a driver circuit, a bus master device, a fire detections system and a burglar alarming system using the driver circuit.
  • Alarming systems which have a control module or bus master device to which subscribers are connected by means of a two-wire line, said subscribers receiving from the control module, via the two-wire line operated as a field bus, both a power supply voltage and communication messages in the form of pulse trains impressed on the power supply voltage as voltage modulation.
  • the two-wire line to which the subscribers are connected in parallel may have a length of between 1000 and 2000 m, for example, and is frequently routed in a loop or ring shape, i.e. it starts and ends at the bus master device.
  • the two-wire line is also referred to simply as a field bus.
  • the subscribers may be sensors, e.g. fire or burglar alarms, and/or actuators, such as light-signal or sound-signal generators.
  • the power supply voltage for the subscribers may be in the range from 20 to 40 volts, for example, at the start of the two-wire line.
  • the communication between the bus master device and the subscribers is handled on the basis of a digital communication protocol.
  • the communication protocol defines time slots or time windows which are used to transmit pulses and pulse trains as data messages which represent addresses, commands and reports, in particular.
  • the pulses may comprise starting pulses with a length of 1 ms, for example, synchronization or separating pulses with a length of 0.5 ms, for example, and pulse trains representing bit-coded messages, with a single pulse length of between 100 and 200 ⁇ s, for example.
  • Each subscriber has a communication interface connected to the two-wire line, e.g. a UART interface for its microcontroller, which microcontroller detects and processes the pulses and pulse trains.
  • a communication interface connected to the two-wire line, e.g. a UART interface for its microcontroller, which microcontroller detects and processes the pulses and pulse trains.
  • Such a system is disclosed for example in DE 102011010922.6 A1 .
  • This document shows a bus master device having subscribers connected to it by a two-wire line.
  • the subscribers receive via the two-wire line both a power supply voltage and communication messages in the form of pulse trains impressed on the power supply voltage as voltage modulation.
  • the subscribers are provided with a transformer, which is provided to reduce power supply voltage of an internal value which is lower than the power supply voltage at least by the voltage swing of the pulses of the communication messages on the two-wire line.
  • a simple in-phase regulator is used as transformer.
  • bus master device are equipped with a class A, B or AB power amplifier with additional drive level/discharge circuitry, resulting in the following disadvantages.
  • the protocol/communication level cannot be generated universally (e.g. software defined), they are usually fixed and dependent on hardware. Rise and fall times and thus the transmission frequency are also hardware dependent.
  • the power dissipation of the output transistors is very high.
  • the efficiency is only about 50 % to 70 %.
  • the present invention has been made in order to overcome the above problems.
  • a driver circuit for a two wired loop bus comprising a first capacitance element connected between two input voltage supplies, a second capacitance element connected between two output voltage supplies, a first switching element connected between the two input voltage supplies, a second switching element connected between the two output voltage supplies, and an inductance connected between the first and second two switching elements.
  • the invention provides a driver circuit for a two wired loop bus comprising a first capacitance element connected between two input voltage supplies, a second capacitance element connected between two output voltage supplies, a first series connection of two switching elements connected between the two input voltage supplies, a second series connection of two switching elements connected between the two output voltage supplies, and an inductance, one end of which being connected between the two switching elements of the first series connection, and the other end thereof being connected between the two switching elements of the second series connection.
  • the driver circuit comprises a plurality of diodes, e.g. four diodes, each being connected in series with one of the switching elements and so as to bridge another switching element, if four switching elements are provided.
  • a bus master device for a two wired loop bus comprising a drive circuit as recited above, a current measuring element for measuring the current through the drive circuit, a controller for controlling the switching of the switching elements.
  • the bus master device might be configured so as to include two bus drivers connected with respective ends of the wired loop bus so as to drive the loop from any or both sides.
  • the bus master device can be configured so that the controller controls the switching of the switching elements with different pre-set timings, so as to provide different voltage levels on the two wired loop bus.
  • the bus master device is configured so as to switch two of the switching element synchronously.
  • a further aspect of the invention is directed to a fire detection system comprising a bus master device as recited above and a two wired loop bus comprising a plurality of fire detecting devices connected between the two wires of the bus.
  • the invention provides a burglar alarm system comprising a bus master device as recited above and a two wired loop bus comprising a plurality of burglar detecting devices and/or alarming devices connected between the two wires of the bus.
  • the alarm systems comprises a control center or bus master device 29 (possibly also subordinate control centers).
  • the bus master device 29 has both the start and the end of a two-wire line 11, 13 connected to it.
  • the two-wire line 11, 13 has numerous subscribers T01, T02, ... T10 electrically connected to it in parallel at intervals.
  • the two-wire line 11, 13 provides the power supply voltage for the subscribers T01, T02, ... T10 and is simultaneously used for bidirectional communication between the bus master device 29 and the subscribers T01, T02,... T10.
  • the two-wire line 11, 13 is therefore also referred to as a ring or loop bus for short.
  • the subscribers T01, T02, ... T10 can be e.g. fire detectors, burglar detectors, alarming devices and so on.
  • FIG 1 is a simplified figure showing the configuration of such an alarm system.
  • the loop bus can connect up to 123 subscribers T01, T02, ... T10 and supplies the corresponding operating voltage.
  • the loop bus is also configured to allow a digital communication between the subscribers T01, T02, ... T10 and the bus master device, e.g. by means of a pulse modulation technique or an amplitude modulation.
  • the subscribers can have the function of detectors or may have the function of alarming devices, like flash lights or acoustic alarms.
  • FIG. 2 shows the bus master device 29 in more detail.
  • the bus master device 29 mainly comprises a controller 25 for controlling the operation of the bus master device 29 and of the loop bus, a memory 17 for storing operation data and control data for the bus master device 29, a driver circuit 19for providing the operation voltage and the control signals for the loop bus and switching units 21, 23 for the connection of the output of the driver circuit 19 with the input side of the two wires 11, 13 of the loop bus. Additionally the bus master device might comprise a current detector 15 for detecting the current output by the driver circuit 19.
  • the bus master device 29 can be connected on a primary side, opposite to the loop bus side, with a communication bus, which in turn might be connected to a central control controlling a plurality of bus master devices. Additionally the bus master device is connected to a power supply and comprises a power converter to provide an internal operation voltage, e.g. 42 V, which is supplied to the input side of the driver circuit 19.
  • the bus master device 29 can comprise further elements dedicated to different control operations and to the internal operation of the bus master device 29. Which will not be explained in further detail in this application.
  • Figure 3 shows in more detail a possible configuration of the driver circuit 19 of Figure 2 .
  • the input side of the driver circuit 19 is connected between ground 3 and an internal voltage line 5 of the bus master device 29, which form input voltage supplies of the driver circuit.
  • the output side of the driver circuit is connected between ground 7 and an output voltage line 9 of the bus master device 29, which together form output voltage supplies.
  • the output voltage supplies 7, 9 are connected with respective wires of the loop bus 11, 13.
  • a first capacitance element C1 is connected between ground 3 and the internal voltage line 5.
  • the capacitor C1 is not specially limited to a particular capacitor type.
  • any type of switch like transistors, can be used.
  • the transistors are not limited to a particular transistor type. For example the use of FETs or of bi-polar n-channel or p-channel transistors is possible.
  • a respective diode D2 connected in series to the switching element S1. Further there is provided a diode D1 connected in series to the switching element S2.
  • the diodes are provided with the identical orientation and so as to block a current flowing from the internal voltage line 5 to ground 3, while allowing the flow of a current in the opposite direction.
  • an inductance L1 At an intermediate point between the two switching elements S1 and S2 of the first series connection of switching elements there is connected one end of an inductance L1.
  • the other end of the inductance L1 is connected with the output side of the driver circuit 19.
  • the size of the inductance L1 can be between 200 ⁇ H and 10 ⁇ H, without being limited to these values.
  • a second capacitance element C2 is connected between ground 7 and the output voltage line 9.
  • the capacitor C2 is not specially limited to a particular capacitor type.
  • any type of switch like transistors, can be used.
  • the transistors are not limited to a particular transistor type. For example the use of FETs or of bi-polar n-channel or p-channel transistors is possible.
  • a respective diode D3 connected in series to the switching element S4. Further there is provided a diode D4 connected in series to the switching element S3.
  • the diodes are provided with the identical orientation and so as to block a current flowing from the output voltage line 7 to ground 9, while allowing the flow of a current in the opposite direction.
  • the switching elements S1 to S4 are operated under the control of the control unit 25 of the master bus device 29.
  • the switching elements S1 and S4 are operated at the same timing.
  • the switching elements S1 and S4 are in the open state, while the switching elements S2 and S3 are closed, the internal voltage of the master bus device 29 will charge the capacitor C1.
  • the output voltage line 9 will be supplied with the energy stored in the inductance L1 and the capacitor C2.
  • T is the sum of t on (S1, S4) and t off (S1, S4), and where t on (S1, S4) is the time during which the switching elements S1 and S4 are closed while t on (S1, S4) / t off (S1, S4) is the time during which S1 and S4 are open.
  • the duty cycle dc will be t on (S1, S4) /T.
  • the driver circuit operates as a buck-boost converter.
  • the two operating states of a buck-boost converter are: a) when the switching elements S1, S4 are turned on, the input voltage source supplies current to the inductance L1, and the capacitor C2 supplies current to the loop bus (output load). When the switching elements S1, S4 are opened, the inductance supplies current to the bus loop.
  • the bus master device can be used for a plurality of different loop buses having different bus protocols regarding the voltage levels, slew rates and so on, without a modification of the hardware, simply by controlling the switching of the switching elements S1 to S4.
  • a switched mode driver circuitry is used instead of using the former described type of amplifier, i.e. A, B or AB power amplifier with additional drive level/discharge circuitry.
  • the basic principle is well known and used for example in switching voltage regulators. But is has never been used as driver for two wired loop systems.
  • the invention uses a cascaded buck-boost topology with four switches/transistors, four diodes (in case of FETs the bulk diodes can be used) and one inductor.
  • the communication levels can be easily set.
  • the output voltage is only dependent on the input voltage, which can be assumed as nearly constant in this application, and the turn on/off time of the switching element pair S1, S4.
  • the solution offers software defined protocol/communication levels and the reduction of the transmission frequency/slew rate if necessary.
  • a further advantage is a highly reduced power dissipation (efficiency > 90 %), a good energy recovery and an integrated current measurement with the current detector 15.
  • the switching elements S1 and S2 are omitted.
  • the operation is performed only by switching the remaining switches S3 and S4 with an appropriate timing.
  • the driver circuit will operate only as a boost converter.
  • the switching elements S3 and S4 are omitted. The operation is performed only by switching the remaining switches S1 and S2 with an appropriate timing. In this case, the driver circuit will operate only as a buck converter.
  • One advantage of using four switching elements, as discussed above, is that energy recovery can be achieved.
  • Fig. 4 shows a further embodiment of a bus master device 29.
  • the bus master device 29 is provided with a voltage supply 41 for supplying an operation voltage to the bus master device 29.
  • the bus master device of Fig. 4 comprises a first driver circuit 19a and a second driver circuit 19b.
  • the first driver circuit 19a is connected with one of the wires of the loop bus.
  • the second driver circuit 19b is connected with the other end of the same wire of the loop bus.
  • the bus master device of Fig. 4 comprises a controller 13 for controlling the operation of the switching elements in the first and second bus driver devices 19a, 19b.
  • the controller 13 is further connected with a current measurement device 15.
  • the current measurement device 15 is configured to measure the current flowing through the inductance in the first driver circuit 19a. Furthermore, the current measurement device 15 can be configured to measure the current flowing through the inductance in the second driver circuit 19b.
  • the current measurement device allows to scope with different loads at the bus.
  • the bus master device 29 of this embodiment comprises an input/output voltage measurement device 42.
  • the input/output voltage measurement device measures is the voltage the output of the voltage supply and the voltage at the output of the first and second driver circuits 19a and 19b.
  • the controller 13 can control the operation of the switching elements in the first and second driver circuit 19a, 19b in an appropriate manner.
  • the arrangement with the two driver circuits 19a and 19b has the advantage that in case of damage of one of the driver circuits, the system can still operate.
  • the circuit of Fig. 4 allows additionally an operation mode, in which both driver circuits 19a, 19b are operated at the same time, for example, in case that the loop is interrupted and the system is operated having two stubs.
  • a certain distortion of the edges of the pulses of the data transmission signal which might be used in a pulse modulation implementation, has to be considered.
  • a detecting device T01 - T10 arranged at a large distance from the bus master device 29, might receive a control signal having a distorted edge.
  • Using the present invention allows to provide the pulses with an adequate predistortion , so as to solve this problem.
  • the frequency used for data transmission through the bus is usually in the range of 10 kHz, i.e. with pulses of 0.1 ms.
  • the switching frequency of the switching elements is several times larger, for example 10 to 1000 times larger.
  • the edge of a pulse of the data transmission signal can be formed by changing the switching frequency of the switching elements in steps or by changing the duty cycle in steps. This allows to provide adequate formed pulses for different protocols and for different loops.
  • the current measurement device 15 can use either a small resistor provided in series with the respective inductance or can be configured as an inductive measuring element.
  • respective filter elements might be provided between the driver circuit 19a and/or 19b and the loop, in order to remove noise generated by the driver circuits.

Abstract

Invention concerning a driver circuit for a two wired loop bus comprising: a first capacitance element (C1) connected between two input voltage supplies (7,9); a second capacitance element (C2) connected between two output voltage supplies (7, 9); a first series connection of two switching elements (S1, S2) connected between the two input voltage supplies (3, 5); a second series connection of two switching elements (S3, S4) connected between the two output voltage supplies (3, 5); and an inductance (L1), one end of which being connected between the two switching elements (S1, S2) of the first series connection, and the other end thereof being connected between the two switching elements (S3, S4) of the second series connection.

Description

  • The present invention is directed to a driver circuit, a bus master device, a fire detections system and a burglar alarming system using the driver circuit.
  • Alarming systems are known which have a control module or bus master device to which subscribers are connected by means of a two-wire line, said subscribers receiving from the control module, via the two-wire line operated as a field bus, both a power supply voltage and communication messages in the form of pulse trains impressed on the power supply voltage as voltage modulation.
  • Alarm systems of the type cited above are prior art. The two-wire line to which the subscribers are connected in parallel may have a length of between 1000 and 2000 m, for example, and is frequently routed in a loop or ring shape, i.e. it starts and ends at the bus master device. The two-wire line is also referred to simply as a field bus.
  • The subscribers may be sensors, e.g. fire or burglar alarms, and/or actuators, such as light-signal or sound-signal generators. The power supply voltage for the subscribers may be in the range from 20 to 40 volts, for example, at the start of the two-wire line.
  • The communication between the bus master device and the subscribers is handled on the basis of a digital communication protocol. The communication protocol defines time slots or time windows which are used to transmit pulses and pulse trains as data messages which represent addresses, commands and reports, in particular. Depending on the meaning assigned to them, the pulses may comprise starting pulses with a length of 1 ms, for example, synchronization or separating pulses with a length of 0.5 ms, for example, and pulse trains representing bit-coded messages, with a single pulse length of between 100 and 200 µs, for example.
  • Each subscriber has a communication interface connected to the two-wire line, e.g. a UART interface for its microcontroller, which microcontroller detects and processes the pulses and pulse trains.
  • Such a system is disclosed for example in DE 102011010922.6 A1 . This document shows a bus master device having subscribers connected to it by a two-wire line. The subscribers receive via the two-wire line both a power supply voltage and communication messages in the form of pulse trains impressed on the power supply voltage as voltage modulation.
  • In order to reduce communication errors, the subscribers are provided with a transformer, which is provided to reduce power supply voltage of an internal value which is lower than the power supply voltage at least by the voltage swing of the pulses of the communication messages on the two-wire line.
  • According to this document preferably a simple in-phase regulator is used as transformer.
  • Usually the bus master device are equipped with a class A, B or AB power amplifier with additional drive level/discharge circuitry, resulting in the following disadvantages.
  • The protocol/communication level cannot be generated universally (e.g. software defined), they are usually fixed and dependent on hardware. Rise and fall times and thus the transmission frequency are also hardware dependent.
  • The power dissipation of the output transistors is very high. The efficiency is only about 50 % to 70 %.
  • The recovery of energy is not possible, e.g. during discharge of line and load capacitances.
  • The present invention has been made in order to overcome the above problems.
  • According to the invention this object is achieved by a combination of features of the independent claims.
  • Especially the invention provides a driver circuit for a two wired loop bus comprising a first capacitance element connected between two input voltage supplies, a second capacitance element connected between two output voltage supplies, a first switching element connected between the two input voltage supplies, a second switching element connected between the two output voltage supplies, and an inductance connected between the first and second two switching elements.
  • Preferably the invention provides a driver circuit for a two wired loop bus comprising a first capacitance element connected between two input voltage supplies, a second capacitance element connected between two output voltage supplies, a first series connection of two switching elements connected between the two input voltage supplies, a second series connection of two switching elements connected between the two output voltage supplies, and an inductance, one end of which being connected between the two switching elements of the first series connection, and the other end thereof being connected between the two switching elements of the second series connection.
  • According to a preferred embodiment the driver circuit comprises a plurality of diodes, e.g. four diodes, each being connected in series with one of the switching elements and so as to bridge another switching element, if four switching elements are provided.
  • According to a further aspect of the invention there is provided a bus master device for a two wired loop bus comprising a drive circuit as recited above, a current measuring element for measuring the current through the drive circuit, a controller for controlling the switching of the switching elements.
  • The bus master device might be configured so as to include two bus drivers connected with respective ends of the wired loop bus so as to drive the loop from any or both sides.
  • Furthermore, the bus master device can be configured so that the controller controls the switching of the switching elements with different pre-set timings, so as to provide different voltage levels on the two wired loop bus.
  • According to a further aspect of the invention the bus master device is configured so as to switch two of the switching element synchronously.
  • A further aspect of the invention is directed to a fire detection system comprising a bus master device as recited above and a two wired loop bus comprising a plurality of fire detecting devices connected between the two wires of the bus.
  • Finally the invention provides a burglar alarm system comprising a bus master device as recited above and a two wired loop bus comprising a plurality of burglar detecting devices and/or alarming devices connected between the two wires of the bus.
  • In the following preferred embodiments of the invention will be described with reference to the accompanying drawings, which show:
  • Figure 1
    a fire detection system according to the present invention;
    Figure 2
    a block diagram of the bus master device;
    Figure 3
    a circuit diagram of a driver circuit according to the invention;
    Figure 4
    a block diagram of second embodiment of a bus aster device according to the invention.
  • As explained at the outset, the alarm systems comprises a control center or bus master device 29 (possibly also subordinate control centers). The bus master device 29 has both the start and the end of a two- wire line 11, 13 connected to it. The two- wire line 11, 13 has numerous subscribers T01, T02, ... T10 electrically connected to it in parallel at intervals. The two- wire line 11, 13 provides the power supply voltage for the subscribers T01, T02, ... T10 and is simultaneously used for bidirectional communication between the bus master device 29 and the subscribers T01, T02,... T10. The two- wire line 11, 13 is therefore also referred to as a ring or loop bus for short.
  • The subscribers T01, T02, ... T10 can be e.g. fire detectors, burglar detectors, alarming devices and so on.
  • In Figure 1 is a simplified figure showing the configuration of such an alarm system. In a preferred embodiment the loop bus can connect up to 123 subscribers T01, T02, ... T10 and supplies the corresponding operating voltage. The loop bus is also configured to allow a digital communication between the subscribers T01, T02, ... T10 and the bus master device, e.g. by means of a pulse modulation technique or an amplitude modulation.
  • As mention above the subscribers can have the function of detectors or may have the function of alarming devices, like flash lights or acoustic alarms.
  • Figure 2 shows the bus master device 29 in more detail. The bus master device 29 mainly comprises a controller 25 for controlling the operation of the bus master device 29 and of the loop bus, a memory 17 for storing operation data and control data for the bus master device 29, a driver circuit 19for providing the operation voltage and the control signals for the loop bus and switching units 21, 23 for the connection of the output of the driver circuit 19 with the input side of the two wires 11, 13 of the loop bus. Additionally the bus master device might comprise a current detector 15 for detecting the current output by the driver circuit 19.
  • The bus master device 29 can be connected on a primary side, opposite to the loop bus side, with a communication bus, which in turn might be connected to a central control controlling a plurality of bus master devices. Additionally the bus master device is connected to a power supply and comprises a power converter to provide an internal operation voltage, e.g. 42 V, which is supplied to the input side of the driver circuit 19.
  • The bus master device 29 can comprise further elements dedicated to different control operations and to the internal operation of the bus master device 29. Which will not be explained in further detail in this application.
  • Figure 3 shows in more detail a possible configuration of the driver circuit 19 of Figure 2.
  • The input side of the driver circuit 19 is connected between ground 3 and an internal voltage line 5 of the bus master device 29, which form input voltage supplies of the driver circuit.
  • The output side of the driver circuit is connected between ground 7 and an output voltage line 9 of the bus master device 29, which together form output voltage supplies. The output voltage supplies 7, 9 are connected with respective wires of the loop bus 11, 13.
  • At the input side of the driver circuit 19 a first capacitance element C1, preferably a capacitor, is connected between ground 3 and the internal voltage line 5. The capacitor C1 is not specially limited to a particular capacitor type.
  • Parallel to the capacitor C1 there is connected a series connection of two switching elements S1, S2. Here any type of switch, like transistors, can be used. The transistors are not limited to a particular transistor type. For example the use of FETs or of bi-polar n-channel or p-channel transistors is possible.
  • In the preferred embodiment of Figure 3 there is provided a respective diode D2 connected in series to the switching element S1. Further there is provided a diode D1 connected in series to the switching element S2. The diodes are provided with the identical orientation and so as to block a current flowing from the internal voltage line 5 to ground 3, while allowing the flow of a current in the opposite direction.
  • At an intermediate point between the two switching elements S1 and S2 of the first series connection of switching elements there is connected one end of an inductance L1. The other end of the inductance L1 is connected with the output side of the driver circuit 19. The size of the inductance L1 can be between 200 µH and 10 µH, without being limited to these values.
  • At the output side of the driver circuit 19 a second capacitance element C2, preferably a capacitor, is connected between ground 7 and the output voltage line 9. The capacitor C2 is not specially limited to a particular capacitor type.
  • Parallel to the capacitor C2 there is connected a second series connection of two switching elements S3, S4. Here any type of switch, like transistors, can be used. The transistors are not limited to a particular transistor type. For example the use of FETs or of bi-polar n-channel or p-channel transistors is possible.
  • In the preferred embodiment of Figure 3 there is provided a respective diode D3 connected in series to the switching element S4. Further there is provided a diode D4 connected in series to the switching element S3. The diodes are provided with the identical orientation and so as to block a current flowing from the output voltage line 7 to ground 9, while allowing the flow of a current in the opposite direction.
  • The switching elements S1 to S4 are operated under the control of the control unit 25 of the master bus device 29.
  • In the preferred operation mode the switching elements S1 and S4 are operated at the same timing.
  • If the switching elements S1 and S4 are in the open state, while the switching elements S2 and S3 are closed, the internal voltage of the master bus device 29 will charge the capacitor C1. The output voltage line 9 will be supplied with the energy stored in the inductance L1 and the capacitor C2.
  • Upon closing the switching elements S1 and S4 and opening the switching elements S2 and S3, the energy accumulated in the capacitor will be transferred to the inductance L1.
  • When opening again the switching elements S1 and S4 and closing S2 and S3 the energy accumulated in the inductance L1 will be transferred to the output side and will recharge the capacitor C2.
  • Under the provision that the internal supply voltage of the master bus device is constant, e.g. 42 V, the voltage at the output line 9 will be determined only by the timing of the switching. U out / U in = t on S 1 , S 4 / t off S 1 , S 4 = t on S 1 , S 4 / T - t on 1 , S 4 = 1 / T / t on S 1 , S 4 - 1
    Figure imgb0001
  • Where T is the sum of ton (S1, S4) and toff (S1, S4), and where ton (S1, S4) is the time during which the switching elements S1 and S4 are closed while ton (S1, S4) / toff (S1, S4) is the time during which S1 and S4 are open. The duty cycle dc will be ton(S1, S4) /T.
  • Insofar the driver circuit operates as a buck-boost converter. As well-known the two operating states of a buck-boost converter are: a) when the switching elements S1, S4 are turned on, the input voltage source supplies current to the inductance L1, and the capacitor C2 supplies current to the loop bus (output load). When the switching elements S1, S4 are opened, the inductance supplies current to the bus loop.
  • From the above it is clear that a skilled person will be able to implement different output voltages, to be supplied to the two wired loop bus.
  • Due to this construction it is possible to implement a plurality of different voltage levels at the bus for an amplitude modulation of a digital signal.
  • Furthermore, while maintaining the duty cycle unchanged but varying the switching frequency it is possible to form the slew rate of the output voltage as desired.
  • Therefore, the bus master device can be used for a plurality of different loop buses having different bus protocols regarding the voltage levels, slew rates and so on, without a modification of the hardware, simply by controlling the switching of the switching elements S1 to S4.
  • Instead of using the former described type of amplifier, i.e. A, B or AB power amplifier with additional drive level/discharge circuitry, a switched mode driver circuitry is used. The basic principle is well known and used for example in switching voltage regulators. But is has never been used as driver for two wired loop systems. The invention uses a cascaded buck-boost topology with four switches/transistors, four diodes (in case of FETs the bulk diodes can be used) and one inductor.
  • As discussed above from the four switches two switches are operated simultaneously resulting in an open loop control mode. No closed loop control is necessary.
  • The communication levels can be easily set.
  • The output voltage is only dependent on the input voltage, which can be assumed as nearly constant in this application, and the turn on/off time of the switching element pair S1, S4.
  • For the simplest operation it is not necessary to measure the output voltage. In addition the four switches can be controlled individually to allow some special operating modes and to enhance efficiency.
  • The solution offers software defined protocol/communication levels and the reduction of the transmission frequency/slew rate if necessary.
  • The universal usage as driver or converter for any two wired loop system is enabled. Special and additional drive level/line discharge circuitries are obsolete.
  • A further advantage is a highly reduced power dissipation (efficiency > 90 %), a good energy recovery and an integrated current measurement with the current detector 15.
  • In an alternative embodiment, the switching elements S1 and S2 are omitted. The operation is performed only by switching the remaining switches S3 and S4 with an appropriate timing. In this case, the driver circuit will operate only as a boost converter.
  • In a further alternative embodiment, the switching elements S3 and S4 are omitted. The operation is performed only by switching the remaining switches S1 and S2 with an appropriate timing. In this case, the driver circuit will operate only as a buck converter.
  • One advantage of using four switching elements, as discussed above, is that energy recovery can be achieved.
  • Fig. 4 shows a further embodiment of a bus master device 29. The bus master device 29 is provided with a voltage supply 41 for supplying an operation voltage to the bus master device 29.
  • The bus master device of Fig. 4 comprises a first driver circuit 19a and a second driver circuit 19b. The first driver circuit 19a is connected with one of the wires of the loop bus. The second driver circuit 19b is connected with the other end of the same wire of the loop bus. Additionally, the bus master device of Fig. 4 comprises a controller 13 for controlling the operation of the switching elements in the first and second bus driver devices 19a, 19b.
  • The controller 13 is further connected with a current measurement device 15. The current measurement device 15 is configured to measure the current flowing through the inductance in the first driver circuit 19a. Furthermore, the current measurement device 15 can be configured to measure the current flowing through the inductance in the second driver circuit 19b. The current measurement device allows to scope with different loads at the bus.
  • Additionally, the bus master device 29 of this embodiment comprises an input/output voltage measurement device 42. The input/output voltage measurement device measures is the voltage the output of the voltage supply and the voltage at the output of the first and second driver circuits 19a and 19b.
  • Depending on the measurement results the controller 13 can control the operation of the switching elements in the first and second driver circuit 19a, 19b in an appropriate manner.
  • The arrangement with the two driver circuits 19a and 19b has the advantage that in case of damage of one of the driver circuits, the system can still operate.
  • The circuit of Fig. 4 allows additionally an operation mode, in which both driver circuits 19a, 19b are operated at the same time, for example, in case that the loop is interrupted and the system is operated having two stubs.
  • Due to the inherent capacitance and inductivity of the wires of the loop, a certain distortion of the edges of the pulses of the data transmission signal, which might be used in a pulse modulation implementation, has to be considered. In other words, in case of a large loop a detecting device (T01 - T10) arranged at a large distance from the bus master device 29, might receive a control signal having a distorted edge. Using the present invention allows to provide the pulses with an adequate predistortion, so as to solve this problem.
  • The frequency used for data transmission through the bus is usually in the range of 10 kHz, i.e. with pulses of 0.1 ms.
  • The switching frequency of the switching elements is several times larger, for example 10 to 1000 times larger.
  • Therefore, the edge of a pulse of the data transmission signal can be formed by changing the switching frequency of the switching elements in steps or by changing the duty cycle in steps. This allows to provide adequate formed pulses for different protocols and for different loops.
  • The current measurement device 15 can use either a small resistor provided in series with the respective inductance or can be configured as an inductive measuring element.
  • In the preferred embodiment always two switching elements are operated together. This however is not necessary. It is possible to control each switching element individually in order to improve the efficiency of the driver circuit.
  • Although not shown, respective filter elements might be provided between the driver circuit 19a and/or 19b and the loop, in order to remove noise generated by the driver circuits.
  • Although the invention has been described with regard to different advantageous embodiment, the invention is not limited to the specific features of these embodiments. For example, it might be possible to dispense with the input/output voltage measurement device in the bus master circuit 29 of Fig. 4.

Claims (11)

  1. Driver circuit for a two wired loop bus comprising:
    a first capacitance element (C1) connected between two input voltage supplies (3, 5);
    a second capacitance element (C2) connected between two output voltage supplies (7, 9);
    a first series connection of two switching elements (S1, S2) connected between the two input voltage supplies (3, 5); and
    an inductance (L1), one end of which being connected between the two switching elements (S1, S2) of the second series connection, the other end being connected with one of the output voltage supplies.
  2. Driver circuit according to claim 1 further comprising:
    a second series connection of two switching elements (S3, S4) connected between the two output voltage supplies (3, 5);
    the inductance (L1) being connected between the two switching elements (S1, S2) of the first series connection, and the other end thereof being connected between the two switching elements (S3, S4) of the second series connection.
  3. Driver circuit for a two wired loop bus comprising:
    a first capacitance element (C1) connected between two input voltage supplies (3, 5);
    a second capacitance element (C2) connected between two output voltage supplies (7, 9);
    a second series connection of two switching elements (S3, S4) connected between the two output voltage supplies (7, 9); and
    an inductance (L1), one end of which being connected between the two switching elements (S3, S4) of the second series connection, the other end being connected with one of the input voltage supplies.
  4. Driver circuit according to claim 1, 2 or 3, further comprising:
    a plurality of diodes (D1 to D4) each being connected in series with one of the switching elements (S1 to S4).
  5. A bus master device for a two wired loop bus, said bus master device comprising:
    a driver circuit (19) according to claim 1 to 4;
    a current measuring element (15) for measuring the current through the drive circuit;
    a controller (13) for controlling the switching of the switching elements (S1 to S4).
  6. The bus master device according to claim 5, comprising
    two driver circuits (19a, 19b) connected with respective ends of the two wired loop bus so as to allow to drive the bus from both sides.
  7. The bus master device according to claim 5 or 6, wherein wherein the current measuring element (15) is configured to measure the current flowing through the inductance (L1) of at least or both the driver circuits (19a, 19b).
  8. The bus master device according to claim 4, wherein
    the controller (13) is configured so as to control the switching of the switching elements (S1 to S4) of the at least one or both driver circuits (19a, 19b) with different pre-set timings, so as to provide different voltage levels on the two wired loop bus.
  9. The bus master device according to claim 8, wherein
    the controller (13) is configured so as to switch a first switching element (S1) and a second switching element (S4) synchronously.
  10. A fire detection system comprising:
    a bus master device (29) according to any of claims 5 to 9; and
    a two wired loop bus (11, 13) comprising a plurality of fire detecting devices (T01 - T10) connected between the two wires of the bus.
  11. A burglar alarm system comprising:
    a bus master device according to any of claims 5 to 9; and
    a two wired loop bus (11, 13) comprising a plurality of burglar detecting devices (15) and/or alarming devices connected between the two wires of the bus.
EP15202102.8A 2014-12-22 2015-12-22 Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit Pending EP3038070A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP15202102.8A EP3038070A1 (en) 2014-12-22 2015-12-22 Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP14199619.9A EP3038069B1 (en) 2014-12-22 2014-12-22 Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit
EP15202102.8A EP3038070A1 (en) 2014-12-22 2015-12-22 Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit

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EP3038070A1 true EP3038070A1 (en) 2016-06-29

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EP14199619.9A Active EP3038069B1 (en) 2014-12-22 2014-12-22 Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit
EP15202102.8A Pending EP3038070A1 (en) 2014-12-22 2015-12-22 Driver circuit, bus master device, fire detections system and burglar alarming system using the driver circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106130857A (en) * 2016-08-26 2016-11-16 深圳市嘉泰智能股份有限公司 Two-wire power supply and communication system and method
US11367339B2 (en) 2018-06-21 2022-06-21 Autronica Fire & Security As System and method for startup of a detector loop

Citations (4)

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Publication number Priority date Publication date Assignee Title
US5406254A (en) * 1992-11-25 1995-04-11 Borg-Warner Security Corporation Alarm system with remote module and associated alarm
DE102009004974A1 (en) * 2009-01-14 2010-07-15 Ic - Haus Gmbh Power and data transmission system for bus subscriber, has bus subscriber including integrated circuit with transceiver having controlled current source including connection associated with bus
EP2428942A1 (en) * 2010-09-09 2012-03-14 Novar GmbH Hazard notification assembly with two data transfer speeds
DE102011010922A1 (en) 2011-02-10 2012-08-16 Novar Gmbh Alarm system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5406254A (en) * 1992-11-25 1995-04-11 Borg-Warner Security Corporation Alarm system with remote module and associated alarm
DE102009004974A1 (en) * 2009-01-14 2010-07-15 Ic - Haus Gmbh Power and data transmission system for bus subscriber, has bus subscriber including integrated circuit with transceiver having controlled current source including connection associated with bus
EP2428942A1 (en) * 2010-09-09 2012-03-14 Novar GmbH Hazard notification assembly with two data transfer speeds
DE102011010922A1 (en) 2011-02-10 2012-08-16 Novar Gmbh Alarm system

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EP3038069A1 (en) 2016-06-29
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