Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
  • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
  • G06F16/22—Indexing; Data structures therefor; Storage structures
  • G06F16/2228—Indexing structures
  • G06F16/2246—Trees, e.g. B+trees
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
  • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
  • G06F12/0815—Cache consistency protocols
  • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
  • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
  • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
  • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
  • G06F16/24—Querying
  • G06F16/245—Query processing
  • G06F16/2455—Query execution
  • G06F16/24553—Query execution of query operations
  • G06F16/24562—Pointer or reference processing operations
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/44—Arrangements for executing specific programs
  • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
  • G06F9/45516—Runtime code conversion or optimisation

Definitions

• a hardware accelerator i.e., a dedicated digital circuit cooperating with or integrated with a processor for accelerating certain data processing operations - for manipulating data structures known as "Red and black trees".
• the invention also relates to a processor incorporating such a hardware accelerator and to a computer system comprising a processor, such a hardware accelerator and a memory.
• Red and black trees are well-known data structures for storing sorted data according to a reference key. These data structures are binary trees to which is added a coloring property of the nodes in which the manipulated data is contained. This property makes it possible to handle these trees with a complexity lower than that of conventional binary trees, in O (log n), n corresponding to the total number of nodes in the tree, for both insertion operations and deletion. This representation is particularly used in the context of the implementation of associative arrays. Associative arrays, implemented as red and black trees, are a collection of key and value pairs that allow a set of keys to be associated with a corresponding set of values. There are many programming libraries optimized for handling red and black trees, for example as part of the standard GNU C ++ library.
• the invention aims to accelerate the handling of red and black trees and, as a result, associative arrays implemented by means of such trees.
• such a goal is achieved through a hardware accelerator, used in conjunction with a slightly modified software representation of red and black trees.
• An object of the invention is therefore a hardware accelerator for handling red and black trees, each said tree comprising several nodes, each said node comprising data fields of predefined length representing:
• said hardware accelerator comprising:
• node registers which can store all the fields of two nodes of a said tree; and logic units configured to receive from a processor at least one input data selected from an address of a node of a said tree and a so-called reference key, and at least one instruction to be executed; to execute said instruction by performing a combination of the following operations:
• the hardware accelerator may also comprise a register, referred to as a reference register, which can store either a so-called reference key received from said processor, or a said reference key and a color indicator.
• Said logical units may comprise a processing unit and a control unit, said control unit being configured to: receive a said address of a node of a said tree as input data and transmit it to said memory ; receiving a said reference key as input data and storing it in said reference register; receiving a said instruction to be executed as input data, as well as one or more condition signals from said processing unit; in response to said instruction to be executed and said one or more condition signals, generating control signals from said processing unit; and providing, as output data, a node address received from said processing unit.
• Said control unit may be a finite state machine.
• the hardware accelerator may also include a register, called temporary register, which can store an address, called a temporary address, of a node of a said tree.
• Said processing unit may be configured to execute, in response to a said control signal, at least the following operations:
• Said processing unit may comprise: a selection and subtraction unit configured to receive at a first input, via a first multiplexer, the contents of said temporary register or said reference register, at a second input, by the intermediate of a second multiplexer, a key or key data field and color indicator from a said node register and a control input, a control signal from said control unit, and for providing at its output, as a function of said control signal, either one of said first and second inputs, or their difference; a reorganization unit configured to receive at a first input, the output of said comparison unit and subtractions, at a second input, a key or key data field and color indicator from a said node register at a third, a fourth and a fifth input, via said second multiplexer, three address data fields from a said node register and a control input, a control signal from said control unit; and to provide: at a first output, a key, key and color indicator or address data field present at one of its inputs, the value of said color indicator being
• Said processing unit may be configured to generate, in response to an instruction received as input data, a sequence of control signals for execution of a selected one of the following:
• Said logical units may also include an interface device with said memory configured to: receive from said control unit the address of a location of said memory; and transferring the contents of said memory lease into a said node register, or vice versa.
• Such an accelerator can comprise exactly three node registers.
• the color indicator and the key of each said node may be represented by different bits of the same data field, said color indicator being represented by a single bit of said field.
• each said node may be represented by: a data field of which one bit represents said color indicator and the remaining bits represent said key; and three other data fields representing the addresses of said parent nodes, left child and right child; said data fields all having the same number of bits.
• Another object of the invention is a processor comprising such a hardware accelerator as a functional unit having access to the first cache level.
• Yet another object of the invention is a computer system comprising a processor, a memory and such a hardware accelerator interconnected by a system bus, said processor being configured or programmed to communicate with said hardware accelerator through requests from system and to ensure cache coherency.
• FIGS. 1A and 1B respectively, a data structure used to represent a node of a red and black tree according to the prior art and according to the invention
• FIG. 1 the architecture of a hardware accelerator according to one embodiment of the invention.
• FIG. 3 a processor incorporating a hardware accelerator according to one embodiment of the invention
• a computer system comprising a processor, a hardware accelerator according to another embodiment of the invention and a memory;
• FIG. 5 a graph illustrating the performance gain obtained thanks to a hardware accelerator according to one embodiment of the invention compared with a purely software and "standard” treatment of red and black trees as well as with respect to software processing. optimized in the LLVM environment.
• a red and black tree is a binary tree in which each node has a property called "color", which can take two values - conventionally "red” and “black”.
• color can take two values - conventionally "red” and "black”.
• each node has a "parent” node (except the root node) and two "child” nodes (except the so-called “leaf” nodes, which terminate the branches of the tree), and more precisely a "left" child and a “right” child.
• Each node of a red and black tree (but this is also true for a "generic” binary tree) is also characterized by a "key”.
• the keys of the different nodes are ordered, and the following rule applies: the left child node of each node has a key of value lower than that of the key of its parent, the right child node of each node presents a key of greater value than the key of its parent.
• a red and black tree must further satisfy the following properties:
• the root node is black
• each simple path from a node to any one of its descendants contains the same number of black nodes.
• a red and black tree is, in the context of a preferred embodiment of the invention as in the context of other software implementations such as that of the standard GNU C ++ library, referenced from a node, said " head node "or simply" header "(" header "in English).
• This header node has the same structure as the nodes of the tree, but its parent node is the root node of the tree, its left child node is the leftmost leaf node of the tree, the presenting node. the smallest key of all nodes in the tree, its right child node is the rightmost leaf node of the tree, the node with the largest key of all nodes in the tree. Finally, the color field and the key field of the header node are unused.
• the header node is a point of entry of the tree used to quickly access the node of the red and black tree, during the manipulations of the latter. Another advantage of using a header node is related to the stability of this node during the entire life of the tree, while the root node may have to change during the handling of the tree.
• a node of a binary tree is represented by a data structure of the type illustrated in FIG. 1 A. This structure comprises:
• a color field COL for example of "long" type, encoded on 32 bits;
• a CLE field containing the key of the node, encoded on a variable number of bits.
• the overall size of the data structure representing a node of a red and black tree is of variable size.
• each node has a constant and predefined size. Consequently, the key CLE is replaced by a "reduced key" consisting of a predetermined number of bits.
• the replacement of a key of variable size by a key of fixed size can consequently result in the transition from a total order of the nodes to a partial order in which two nodes having different keys have the same reduced key. It is always possible to ensure that the passage of the key to the reduced key preserves the order of the nodes, at least in the sense of a partial order; thus if the key of the node n is greater than the key of the node m, then the reduced key of the node n is greater than or equal to that of the node m. In the case of equality, a software post-processing can be used to resolve the scheduling ambiguity by returning (outside the hardware accelerator) to a complete representation of the key.
• the color takes a binary value
• the 32-bit encoding of the conventional implementation is highly redundant; this is of no serious consequence in the case of purely software processing, but unnecessarily increases the cost and complexity of a hardware accelerator. Therefore, in a data structure optimized for the implementation of the invention the color is coded on a single bit.
• all the data fields representing a node have the same size, for example 32 bits.
• a CRCO field containing a reduced key subfield CR (hereinafter referred to simply as a "key"), at 31 bits, and a subfield of color CO, at only 1 bit;
• the representation of a red and black tree by the data structure of FIG. 1B is not essential, but is preferred.
• variable X of type "rb_tree_node_t * " (pointer to a node of red and black tree) contains the address of the first field of data of such a node (here, the field CRCO, but this is not essential ).
• a hardware accelerator according to the invention executes, on behalf of a processor, certain instructions necessary for handling red and black trees, and in particular:
• the parameter of the function (data supplied as input to the hardware accelerator) is the address of the node whose successor must be found; the output value of the function and the address of said successor node.
• the parameter of the function is the address of the node whose successor must be found; the output value of the function and the address of said predecessor node.
• the parameters of the function are the address of an access point to the tree and the address of the node to be deleted; the output value, optional, is the node address of the deleted tree, corresponding to the second parameter of the function.
• the access point to the tree is usually its head node.
• the accelerator may also perform other instructions as well. It is also possible to consider other games equivalent instructions, also allowing them to handle red and black trees.
• the accelerator must have access to a memory shared with the processor, storing the data structures to be manipulated.
• This memory must be the level 1 cache of the processor, or a memory maintained coherent with said cache by mechanisms known from the prior art.
• the accelerator receives the instructions and their parameters from the processor, and returns the output value to it.
• an accelerator comprises at least two (preferably three) registers capable of storing all of the data fields of a node, and logic circuits for executing operations more simple, in which the above instructions can be decomposed. These operations are as follows:
• the output value, supplied to the processor, is an address field.
• FIG. 2 schematically illustrates the architecture of such an accelerator, which comprises:
• a UC control unit modeled by a finite state machine
• a processing unit UT in turn comprising a SUB / SEL selection and subtraction unit, a RORG reorganization unit, multiplexers MUX1 and MUX2 situated at the inputs of these units, comparators at zero (or, in an equivalent manner, a) CMP1, CMP2, CMP3 and a RDD data distribution network comprising in turn a multiplexer MUX3 and demultiplexers DEMUX1, DEMUX2;
• nodes RN1, RN2, RN3 three registers of nodes RN1, RN2, RN3 (as mentioned above, two of these registers could be enough, three is the optimal number while a higher number does not bring any particular advantage), to 128 bits in the case of the representation of FIG. 1B, as well as two additional registers capable of storing a single data field (32 bits, in the case of the representation of FIG. 1B): a "temporary" register TEMP for storing a field of address and a REF reference register for storing a key / color field.
• the control unit can be modeled by a finite state machine. It performs the following operations:
• an instruction to execute for example one of the instructions A to F described functionally above - as well as its arguments - typically , one or two respective node addresses of a red and black tree stored in a memory MEM, and optionally a reference key value.
• the address type parameters are communicated to the IM memory interface which retrieves the corresponding data and writes them to one or more node registers via the data distribution network.
• a possible reference key type parameter is stored in the said register of reference REF.
• the instruction determines the control sequence executed by the control unit.
• an internal state and received condition signals send control signals to the various components of the processing unit (such as for the condition signals, the paths of these signals are not represented in full).
• the first multiplexer MUX1 selects, as a function of a control signal, either the contents A T EMP of the temporary register TEMP, or that (CREF) of the reference register REF.
• the selected data (32 bits) is transmitted to a first input of the SUB / SEL selection and subtraction unit.
• the second multiplexer MUX2 selects, according to a control signal, the contents of one of the node registers RN1, RN2, RN3.
• the different fields of the data (128) bits thus selected are treated differently:
• the CRCO field (reduced key and color) is supplied to a second input of the SUB / SEL selection and subtraction unit and also supplied as input to the reorganization unit;
• the SUB / SEL selection and subtraction unit can, depending on a control signal, compare its inputs (subtraction) or select one of them. Its output is input to the RORG reorganization unit.
• the RORG reorganization unit has three outputs (which are not necessarily active at the same time):
• a first 32-bit output on which is found one of the data fields present at its inputs; if this field is a key and color field, the indicative bit of the color can be changed; the selection of the input at the first output and the eventual change of the color bit depend on a control signal;
• a second 32-bit output on which is found one of the address fields present at its inputs and coming from a node register via the second multiplexer; the selection of the address field at the first output depends on a control signal;
• a third 128-bit output on which a reconstituted node structure is found by selecting and swapping four of the data fields present at the inputs of the unit; the selection and the permutation performed depends on a control signal.
• said third output comprises a key and color field from the first or second input, with possible modification of the color indicator bit, and three address fields from the third, fourth and fifth inputs (of which order can be changed).
• the first DEMUX1 demultiplexer makes it possible to supply the data at the first output of the reorganization unit to the input of the temporary register or of the reference register; the data at the second output of the reorganization unit (necessarily an address) is supplied to the memory interface IM;
• the data at the third output of the reorganization unit is also supplied to the memory interface IM to be stored in the memory MEM at the address specified by the data at the second output; it is also input to the third multiplexer MUX3.
• This third multiplexer MUX3 also receives, at another input, a node data structure (128 bits) coming from the memory MEM - the contents of the memory cell whose address has been provided either by the control unit or by the second aforementioned output of the reorganization unit.
• the multiplexer selects one of its inputs, and sends it to the second multiplexer DEMUX2, which transfers it to one of the registers of nodes RN1, RN2, RN3.
• the data at the first address of the reorganization unit (an address) can be supplied to the control unit, which in turn transmits it to the processor PROC as output data;
• a reference key received as an instruction parameter may be transmitted from the control unit to the reference register REF for recording there.
• the processing unit UT can therefore perform, under the control of the control unit UC, the following "elementary" operations:
• the first step includes the selection of the reorganization unit inputs and the selection and subtraction unit by the multiplexers MUX1 and MUX2, as well as the loading of new data into the registers, the second stage corresponds to the processing carried out by the reorganization unit and the unit of selection and subtraction.
• the architecture of Figure 2 is optimized to reduce the cost, complexity and consumption of the accelerator by reusing the same components to perform multiple operations where possible.
• One consequence of this optimization is that useless operations are possible in principle (for example: a comparison between a key / color data and an address in the SUB / SEL unit). This does not matter because control sequences of the control unit make the execution of these operations impossible.
• a hardware accelerator according to one embodiment can be integrated into the "pipeline" of a processor so as to constitute a functional unit of the latter.
• the hardware accelerator has direct access to the level 1 cache and its use involves processor-specific instructions.
• Figure 3 schematically illustrates the structure and operation of such a processor.
• the pipeline includes a "FETCH” unit responsible for loading an instruction from the memory, a "DECODE” unit for decoding the instruction and storing the decoded instruction in a queue Q, an ISSUE unit that selects an instruction ready (of which all the inputs are available) from the instructions of the queue Q and transmits this instruction to a functional unit chosen from: an INT unit (in charge of the so-called integer operations), a MULT unit (in charge of the multiplication operations) , an L / S unit ("Load / Store”: in charge of read / write from / to memory) and hardware accelerator RBT, the latter two units having direct access to the level 1 cache memory, MC. Each unit transmits the result of the processing it performs to the unit WB.
• a functional unit chosen from: an INT unit (in charge of the so-called integer operations), a MULT unit (in charge of the multiplication operations) , an L / S unit (“Load / Store”: in charge of read / write
• the WB (write-back) unit is then in charge of updating the registers of the processor.
• This embodiment is preferred because it allows to fully benefit from the acceleration of the handling of red and black trees.
• it is difficult to implement because it requires a modification of the processor and its instruction set.
• FIG. 4 very schematically illustrates another embodiment, in which the hardware accelerator is implemented in the form of a coprocessor CPR, communicating with a processor PROC and a memory MEM via a BUS system bus.
• the processor processes the accelerator as a device, and communicates with it by means of system functions. Since the accelerator does not have direct access to the level 1 cache of the processor, these system functions implement cache coherence protocols, known per se (alternatively, other cache coherence mechanisms known to those skilled in the art, other than coherence protocols, may be used).
• This embodiment is much simpler to implement, but the processor / accelerator communication is slower, which reduces the advantage of accelerating the handling functions of red and black trees.
• a user gains access to hardware accelerator functionality through convenient function libraries, replacing standard libraries.
• FIG. 5 illustrates, in the form of a histogram, the relationship between the time spent in the manipulation of associative arrays (implemented by red and black trees) with respect to the total compile time for a plurality of source codes indicated on the abscissa.
• the total compile time of source code compilation refers to the runtime of the LLC compiler, from the LLVM environment, passed to the compilation of a given source code.
• the various input source codes of the LLC compiler come from a well-known source code package called "MiBench”. For each compilation of source code by the LLC compiler, this report was measured for the software implementation of the standard C ++ library (bars in light gray), for an optimized software implementation (bars in intermediate gray) and for an implementation using the hardware accelerator according to the invention, in its implementation integrated with the processor (bars in dark gray).

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