EP2912646B1 - Versatile sil2 detector having two outputs and one test input - Google Patents

Versatile sil2 detector having two outputs and one test input Download PDF

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Publication number
EP2912646B1
EP2912646B1 EP13770668.5A EP13770668A EP2912646B1 EP 2912646 B1 EP2912646 B1 EP 2912646B1 EP 13770668 A EP13770668 A EP 13770668A EP 2912646 B1 EP2912646 B1 EP 2912646B1
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Prior art keywords
detector
output
test
power supply
logic unit
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German (de)
French (fr)
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EP2912646A1 (en
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Jacques Bernard
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Schneider Electric Industries SAS
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Schneider Electric Industries SAS
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/12—Checking intermittently signalling or alarm systems
    • G08B29/123—Checking intermittently signalling or alarm systems of line circuits

Definitions

  • the present invention relates to a security detector having two outputs and a test input.
  • This detector has a security level SIL at least equal to 2.
  • a detection system for securing the operation of an application. For example, to secure access to a machine located in a room, it is known to provide a secure detection system that allows not to allow the start of the machine when the means of access to the room is open.
  • a detection system comprises one or more detectors, a logic processing unit receiving the state of each detector and one or more actuators controlled by the logic processing unit taking into account the state of each detector.
  • SIL Safety Integrity Level
  • IEC 61508 or IEC 62061 for SIL2 level IEC 61508 or IEC 62061 for SIL2 level.
  • An SIL2 detection system is preferably carried out by employing an SIL2 detector or a plurality of detectors of level lower than SIL2.
  • a first solution is to provide a detector with two NO type outputs (for "Normally Opened", that is to say normally open) connected to the logic processing unit.
  • the detector integrates a diagnostic module allowing it to diagnose the failure of one of the two NO outputs and to open the other output in case of failure.
  • a break in the cable is detected by the logic processing unit and a short circuit on the cable is detected by the detector's diagnostic module.
  • a second solution is to provide a detector with a NO output and NC output (for "Normally Closed", that is to say normally closed).
  • the failure of one of the two outputs is detected by the logic processing unit, for example by checking the complementarity of the two output signals.
  • a cut of the cable and a short circuit on the cable are detected by the logical processing unit, immediately or during the change of state of the outputs.
  • a third solution is to provide a detector with an NO output and a cyclic test input allowing the logic processing unit to check the output of the detector.
  • faults on the detector output, on the cable, as well as on the input of the logic processing unit are detected by the logic processing unit during the test cycle.
  • US 2005/0112942 discloses a secure system for monitoring an industrial process in accordance with a desired SIL.
  • the object of the invention is to provide a versatile detector to overcome the disadvantages listed above while remaining compatible with a connection to four connection points imposed by the connector type M12.
  • the test module comprises a comparison module arranged to generate the output signal according to the state of the test input signal with respect to a determined threshold value.
  • the detector comprises a power supply module comprising a capacitor arranged to charge in normal operation and to discharge while maintaining a sufficient supply voltage for the proper functioning of the detector during the output test.
  • the detector comprises four connection terminals arranged to receive an M12 type connector.
  • the first output is of the "normally open” type.
  • the second output is normally "normally closed” type.
  • the detector of the invention is arranged to present a security level SIL at least equal to 2.
  • At least one detector D1 is connected by a connection cable to a logic processing unit 2 to form a secure detection system.
  • the logic processing unit 2 for example supplies the power supply to the detector via said cable which is connected to two supply terminals (A1 and A2) present on the detector D1.
  • the two power supply terminals are hereinafter referred to as the first power supply terminal A1 and the second power supply terminal A2.
  • the logic processing unit 2 is connected to one or more actuators 3 and makes it possible to control these actuators 3 as a function of the state of the output signal of the detector D1.
  • a safe detection state and an unsafe detection state are defined.
  • the detector D1 is arranged to generate at least a first output signal which is interpreted by the processing logic unit 2 as an operating authorization of the secure application.
  • the detector D1 is arranged to generate at least a second output signal which is interpreted by the processing logic unit 2 as a secure setting of the secure application.
  • the safe detection state may correspond to the detection of the target in front of the detector D1 or the non-detection of the target in front of the detector D1.
  • the unsafe detection state may correspond to the detection of the target in front of the detector D1 or the non-detection of the target in front of the detector D1.
  • the detector D1 of the invention may be of any known type, all or nothing output, such as for example inductive, capacitive, ultrasonic or photoelectric, or pressure switches or thermostats.
  • the detector therefore comprises a sensor member 10 adapted to perform its function.
  • the detector D1 comprises a detection stage 11 connected to the sensor member 10 and intended to generate a detection signal representative of the state of secure detection or of the unsafe detection state.
  • the detection signal is preferably binary.
  • the detector D1 comprises a processing stage 12 connected to the detection stage 11 and intended to generate one or more output signals.
  • the detector of the invention has the particularity of being versatile. It can adapt to the different processing and control configurations of the logic processing unit 2 connected to it.
  • the detector D1 of the invention can thus indifferently connect to a logic processing unit 2 which is able to manage a detector with two complementary outputs NO and NC complementary or able to manage a NO or NC output detector and a cyclic test input.
  • the detector D1 could also include two NO type outputs or two NC type outputs.
  • the detector D1 of the invention is arranged to have a simple and standard connection at four connection points, such as the M12 connector.
  • the detector D1 of the invention therefore comprises two output terminals O1, O2, that is to say a first output terminal O1 connected to the first output (NO type on the appended figures) and a second output terminal O2 connected to the second output (NC type in the appended figures).
  • Each output of the detector comprises a PNP or NPN type transistor controlled by a control device connected to the processing stage.
  • the detector D1 of the invention comprises a test module MT connected to the first supply terminal A1 or to the second supply terminal A2.
  • the test module is connected to the first power supply terminal.
  • the test module MT comprises a comparison module comprising a first input receiving a predetermined threshold value Vthreshold and a second input connected to the first supply terminal A1 and receiving an input signal. S_test test from the logic processing unit 2.
  • the comparison module comprises an output on which is applied an output signal Sig whose state depends on the comparison between the test input signal S_test applied on the second input of the comparison module and the threshold value Vthreshold applied to the first input.
  • the test module MT makes it possible to test that the first output (NO) and / or the second output (NC) of the detector D1 are in perfect working order when the detector is connected to a logic processing unit 2 having an output Out_test ( figure 3B for example).
  • the output signal Sig is sent to the processing stage 12 which then controls the simultaneous blocking of the two outputs.
  • the detector D1 also includes a power supply unit MA allowing it to remain powered when the output test is in progress.
  • This power supply module MA comprises a capacitor Cp periodically charged by the supply voltage applied by the logic processing unit 2 between the two supply terminals A1, A2 of the detector and a voltage regulator 13 intended to regulate the voltage supply to the terminals of the capacitor.
  • the power supply module MA is connected to the second supply terminal of the detector.
  • the detector D1 of the invention is thus able to adapt to the two conventional configurations of connection to a logic processing unit 2.
  • the figure 3A illustrates a first configuration in which the detector D1 of the invention is provided with two redundant outputs (identical or complementary) connected to two inputs in1, in2 of the logic processing unit 2.
  • the test module MT of detector is not used.
  • the two power supply terminals A1, A2 of the detector are connected to two power supply terminals +, - of the logic processing unit 2.
  • the figure 3B illustrates a second configuration in which the detector D1 of the invention is employed in an operating mode with an output (NO or NC) connected to an input in1 of the logic processing unit.
  • the detector D1 is powered by the test output of the logic processing unit 2 and its first power supply terminal A1 receives the test input signal S_test.
  • the Figure 4A represents the state of the test input signal S_test sent by the Out_test test output of the process logic unit 2 to the first power supply terminal A1 of the detector.
  • the test input signal S_test periodically alternates between two values (0 or 1 in binary).
  • the detector D1 operates normally and is powered by the logic processing unit 2.
  • the logic processing unit 2 tests each output of the detector and the detector D1 is no longer supplied by the logic processing unit 2.
  • the Figure 4B represents the state of charge and discharge of the capacitor Cp.
  • the capacitor Cp is charged when the test input signal applied to the first power supply terminal A1 is at 1, that is to say when the detector D1 is supplied by the logic processing unit.
  • the test input signal is at the value 0, the detector D1 is no longer supplied by the logic processing unit 2 and then feeds on the energy stored in the capacitor Cp, which discharges.
  • the figure 4C represents the state of the output signal Sig of the comparison module.
  • the value 1 of the output signal Sig corresponds to the inhibition command of each output of the detector D1.
  • the output signal Sig is at the value 1 when the test input signal S_test is at the value 0.
  • the figure 4D represents the state of the two outputs NO and NC of the detector D1 (even if only one output is connected to the processing logic unit 2, the two outputs switch simultaneously).
  • the two outputs NO, NC take alternately a complementary state (C) when the detector D1 operates normally and a blocking common state (B) when the logic processing unit 2 passes the test input signal S_test to the value 0 to test the two outputs NO and NC.
  • test module MT described above could have a different operation than that described above. Indeed, the main idea is to periodically inhibit the outputs so as to test them, on solicitation of the logical processing unit. The comparison made by the comparison module for the generation of the output signal Sig could therefore be different from that described above.

Description

Domaine technique de l'inventionTechnical field of the invention

La présente invention se rapporte à un détecteur de sécurité doté de deux sorties et d'une entrée de test. Ce détecteur présente un niveau de sécurité SIL au moins égal à 2.The present invention relates to a security detector having two outputs and a test input. This detector has a security level SIL at least equal to 2.

Etat de la techniqueState of the art

Il est connu de proposer des systèmes de détection sécurisée permettant de sécuriser le fonctionnement d'une application. Par exemple, pour sécuriser l'accès à une machine située dans un local, il est connu de prévoir un système de détection sécurisée qui permet de ne pas autoriser le démarrage de la machine lorsque le moyen d'accès au local est ouvert. Un tel système de détection comporte un ou plusieurs détecteurs, une unité logique de traitement recevant l'état de chaque détecteur et un ou plusieurs actionneurs commandés par l'unité logique de traitement en tenant compte de l'état de chaque détecteur.It is known to provide secure detection systems for securing the operation of an application. For example, to secure access to a machine located in a room, it is known to provide a secure detection system that allows not to allow the start of the machine when the means of access to the room is open. Such a detection system comprises one or more detectors, a logic processing unit receiving the state of each detector and one or more actuators controlled by the logic processing unit taking into account the state of each detector.

Lorsque le système de détection est sécurisé, il présente un certain niveau de sécurité, appelé SIL (pour "Safety Integrity Level"). Ces niveaux de sécurité sont définis par différentes normes (par exemple IEC 61508 ou IEC 62061 pour le niveau SIL2). Dans un système de détection à niveau SIL2 ou supérieur, l'une des problématiques principales est de savoir diagnostiquer les pannes sur les sorties du détecteur ainsi que sur le câble qui permet de raccorder le détecteur à l'unité logique de traitement. Un système de détection SIL2 est préférentiellement réalisé en employant un détecteur SIL2 ou plusieurs détecteurs de niveau inférieur à SIL2.When the detection system is secure, it has a certain level of security, called SIL (for "Safety Integrity Level"). These safety levels are defined by different standards (eg IEC 61508 or IEC 62061 for SIL2 level). In a SIL2 level detection system or higher, one of the main problems is to know how to diagnose faults on the outputs of the detector as well as on the cable that connects the detector to the logic processing unit. An SIL2 detection system is preferably carried out by employing an SIL2 detector or a plurality of detectors of level lower than SIL2.

Dans l'état de la technique, il a été proposé différentes solutions pour attribuer un niveau SIL2 ou supérieur à un détecteur.In the state of the art, it has been proposed different solutions to assign a level SIL2 or higher than a detector.

Une première solution consiste à proposer un détecteur doté de deux sorties de type NO (pour "Normally Opened", c'est-à-dire normalement ouverte) connectées à l'unité logique de traitement. Dans cette solution, le détecteur intègre un module de diagnostic lui permettant de diagnostiquer la panne de l'une des deux sorties NO et d'ouvrir l'autre sortie en cas de panne. Dans cette solution, une coupure du câble est détectée par l'unité logique de traitement et un court-circuit sur le câble est détecté par le module de diagnostic du détecteur.A first solution is to provide a detector with two NO type outputs (for "Normally Opened", that is to say normally open) connected to the logic processing unit. In this solution, the detector integrates a diagnostic module allowing it to diagnose the failure of one of the two NO outputs and to open the other output in case of failure. In this solution, a break in the cable is detected by the logic processing unit and a short circuit on the cable is detected by the detector's diagnostic module.

Une deuxième solution consiste à proposer un détecteur doté d'une sortie NO et d'une sortie NC (pour "Normally Closed", c'est-à-dire normalement fermée). Dans cette solution, la panne de l'une des deux sorties est détectée par l'unité logique de traitement, par exemple en vérifiant la complémentarité des deux signaux de sortie. Une coupure du câble et un court-circuit sur le câble sont détectés par l'unité logique de traitement, immédiatement ou lors du changement d'état des sorties.A second solution is to provide a detector with a NO output and NC output (for "Normally Closed", that is to say normally closed). In this solution, the failure of one of the two outputs is detected by the logic processing unit, for example by checking the complementarity of the two output signals. A cut of the cable and a short circuit on the cable are detected by the logical processing unit, immediately or during the change of state of the outputs.

Une troisième solution consiste à proposer un détecteur doté d'une sortie NO et d'une entrée de test cyclique permettant à l'unité logique de traitement de vérifier la sortie du détecteur. Dans cette solution, les pannes sur la sortie du détecteur, sur le câble, ainsi que sur l'entrée de l'unité logique de traitement, sont détectées par l'unité logique de traitement lors du cycle de test.A third solution is to provide a detector with an NO output and a cyclic test input allowing the logic processing unit to check the output of the detector. In this solution, faults on the detector output, on the cable, as well as on the input of the logic processing unit, are detected by the logic processing unit during the test cycle.

Ces trois solutions permettent d'attribuer un niveau 2 de SIL au détecteur.These three solutions make it possible to assign a level 2 of SIL to the detector.

Cependant, elles présentent toutes certains inconvénients listés ci-dessous :

  • Nécessité d'un module de diagnostic intégré au détecteur dans la première solution.
  • Peu d'unité logique de traitement du commerce sont compatibles avec un détecteur du type de la deuxième solution, à deux sorties complémentaires.
  • Nécessité de proposer deux variantes de détecteur du type de la première ou de la troisième solution pour pouvoir surveiller l'absence ou la présence de la cible.
However, they all have some of the disadvantages listed below:
  • Need a diagnostic module built into the detector in the first solution.
  • Few commercial logic unit are compatible with a detector of the type of the second solution, with two complementary outputs.
  • Need to propose two variants of detector type of the first or the third solution to be able to monitor the absence or the presence of the target.

US 2005/0112942 divulgue un système sécurisé destiné à surveiller un processus industriel conformément à un SIL souhaité. US 2005/0112942 discloses a secure system for monitoring an industrial process in accordance with a desired SIL.

Le but de l'invention est de proposer un détecteur polyvalent permettant de pallier les inconvénients listés ci-dessus tout en restant compatible avec une connectique à quatre points de connexion imposée par le connecteur de type M12.The object of the invention is to provide a versatile detector to overcome the disadvantages listed above while remaining compatible with a connection to four connection points imposed by the connector type M12.

Exposé de l'inventionPresentation of the invention

Ce but est atteint par un détecteur conforme à la revendication 1.This object is achieved by a detector according to claim 1.

Selon une particularité, le module de test comporte un module de comparaison agencé pour générer le signal de sortie selon l'état du signal d'entrée de test par rapport à une valeur seuil déterminée.According to a particularity, the test module comprises a comparison module arranged to generate the output signal according to the state of the test input signal with respect to a determined threshold value.

Selon une autre particularité, le détecteur comporte un module d'alimentation comprenant un condensateur agencé pour se charger en fonctionnement normal et à se décharger en maintenant une tension d'alimentation suffisante pour le bon fonctionnement du détecteur lors du test des sorties.According to another feature, the detector comprises a power supply module comprising a capacitor arranged to charge in normal operation and to discharge while maintaining a sufficient supply voltage for the proper functioning of the detector during the output test.

Selon une autre particularité, le détecteur comporte quatre bornes de connexion agencées pour recevoir un connecteur de type M12.According to another particularity, the detector comprises four connection terminals arranged to receive an M12 type connector.

Selon une autre particularité, la première sortie est de type "normalement ouvert".According to another feature, the first output is of the "normally open" type.

Selon une autre particularité, la deuxième sortie est de type normalement "normalement fermé".According to another feature, the second output is normally "normally closed" type.

L'invention concerne également un système de détection qui comporte :

  • une unité logique de traitement comprenant au moins une entrée et une sortie de test,
  • un détecteur tel que défini ci-dessus, dont la première borne de sortie est connectée à ladite entrée de l'unité logique de traitement et une borne d'alimentation est connectée à la sortie de test de l'unité logique de traitement, l'unité logique de traitement étant agencée pour générer un signal d'entrée de test appliqué sur ladite borne d'alimentation du détecteur afin de tester chaque sortie du détecteur connectée à l'unité logique de traitement.
The invention also relates to a detection system which comprises:
  • a logic processing unit comprising at least one input and one test output,
  • a detector as defined above, whose first output terminal is connected to said input of the processing logic unit and a power supply terminal is connected to the test output of the logic unit of processing, the logic processing unit being arranged to generate a test input signal applied to said detector power terminal to test each output of the detector connected to the logic processing unit.

L'invention concerne enfin un système de détection comprenant :

  • une unité logique de traitement comprenant deux entrées et deux bornes d'alimentation,
  • un détecteur tel que défini ci-dessus, dont les deux bornes d'alimentation sont connectées aux deux bornes d'alimentation de l'unité logique de traitement et les deux bornes de sortie sont connectées aux deux entrées de l'unité logique de traitement de manière à proposer une redondance entre les deux sorties du détecteur.
The invention finally relates to a detection system comprising:
  • a logic processing unit comprising two inputs and two supply terminals,
  • a detector as defined above, the two power supply terminals are connected to the two power terminals of the logic processing unit and the two output terminals are connected to the two inputs of the logic processing unit of to provide redundancy between the two outputs of the detector.

Brève description des figuresBrief description of the figures

D'autres caractéristiques et avantages vont apparaître dans la description détaillée qui suit faite en regard des dessins annexés dans lesquels :

  • La figure 1 représente un système de détection comprenant notamment un détecteur et une unité logique de traitement,
  • la figure 2 représente de manière schématique un détecteur de l'invention,
  • la figure 3A représente un système de détection dans une première configuration de connexion du détecteur de l'invention à une unité logique de traitement, le détecteur étant dans un mode de fonctionnement à deux sorties redondantes,
  • la figure 3B représente un système de détection dans une deuxième configuration de connexion du détecteur de l'invention à une unité logique de traitement, le détecteur étant dans un mode de fonctionnement à au moins une sortie et une entrée de test.
  • les figures 4A à 4D illustrent le principe de fonctionnement du détecteur de l'invention dans la deuxième configuration de connexion.
Other features and advantages will appear in the following detailed description with reference to the accompanying drawings in which:
  • The figure 1 represents a detection system including in particular a detector and a logic processing unit,
  • the figure 2 schematically represents a detector of the invention,
  • the figure 3A represents a detection system in a first connection configuration of the detector of the invention to a logic processing unit, the detector being in an operating mode with two redundant outputs,
  • the figure 3B represents a detection system in a second connection configuration of the detector of the invention to a logic processing unit, the detector being in an operating mode to at least one output and a test input.
  • the Figures 4A to 4D illustrate the operating principle of the detector of the invention in the second connection configuration.

Description détaillée d'au moins un mode de réalisationDetailed description of at least one embodiment

Le détecteur de l'invention est agencé pour présenter un niveau de sécurité SIL au moins égal à 2.The detector of the invention is arranged to present a security level SIL at least equal to 2.

En référence à la figure 1, au moins un détecteur D1 est connecté par un câble de raccordement à une unité logique de traitement 2 afin de former un système de détection sécurisée. L'unité logique de traitement 2 fournit par exemple l'alimentation au détecteur via ledit câble qui est connecté à deux bornes d'alimentation (A1 et A2) présentes sur le détecteur D1. Les deux bornes d'alimentation sont désignées ci-après première borne d'alimentation A1 et deuxième borne d'alimentation A2. L'unité logique de traitement 2 est connectée à un ou plusieurs actionneurs 3 et permet de commander ces actionneurs 3 en fonction de l'état du signal de sortie du détecteur D1.With reference to the figure 1 at least one detector D1 is connected by a connection cable to a logic processing unit 2 to form a secure detection system. The logic processing unit 2 for example supplies the power supply to the detector via said cable which is connected to two supply terminals (A1 and A2) present on the detector D1. The two power supply terminals are hereinafter referred to as the first power supply terminal A1 and the second power supply terminal A2. The logic processing unit 2 is connected to one or more actuators 3 and makes it possible to control these actuators 3 as a function of the state of the output signal of the detector D1.

Pour la suite de la description, on définit un état de détection sûr et un état de détection non sûr. Dans l'état de détection sûr, le détecteur D1 est agencé pour générer au moins un premier signal de sortie qui est interprété par l'unité logique de traitement 2 comme une autorisation de fonctionnement de l'application sécurisée. Dans l'état de détection non sûr, le détecteur D1 est agencé pour générer au moins un deuxième signal de sortie qui est interprété par l'unité logique de traitement 2 comme une mise en sécurité de l'application sécurisée.For the rest of the description, a safe detection state and an unsafe detection state are defined. In the safe detection state, the detector D1 is arranged to generate at least a first output signal which is interpreted by the processing logic unit 2 as an operating authorization of the secure application. In the unsafe detection state, the detector D1 is arranged to generate at least a second output signal which is interpreted by the processing logic unit 2 as a secure setting of the secure application.

Selon la configuration de l'application à sécuriser, l'état de détection sûr peut correspondre à la détection de la cible devant le détecteur D1 ou à la non-détection de la cible devant le détecteur D1. De même, l'état de détection non sûr peut correspondre à la détection de la cible devant le détecteur D1 ou à la non-détection de la cible devant le détecteur D1.Depending on the configuration of the application to be secured, the safe detection state may correspond to the detection of the target in front of the detector D1 or the non-detection of the target in front of the detector D1. Similarly, the unsafe detection state may correspond to the detection of the target in front of the detector D1 or the non-detection of the target in front of the detector D1.

Le détecteur D1 de l'invention peut être de tous types connus, à sortie tout ou rien, tels que par exemple inductif, capacitif, à ultrasons ou photoélectrique, voire des pressostats ou thermostats. Le détecteur comporte donc un organe capteur 10 adapté pour remplir sa fonction.The detector D1 of the invention may be of any known type, all or nothing output, such as for example inductive, capacitive, ultrasonic or photoelectric, or pressure switches or thermostats. The detector therefore comprises a sensor member 10 adapted to perform its function.

Le détecteur D1 comporte un étage de détection 11 connecté à l'organe capteur 10 et destiné à générer un signal de détection représentatif de l'état de détection sûr ou de l'état de détection non sûr. En sortie de l'étage de détection 11, le signal de détection est préférentiellement binaire.The detector D1 comprises a detection stage 11 connected to the sensor member 10 and intended to generate a detection signal representative of the state of secure detection or of the unsafe detection state. At the output of the detection stage 11, the detection signal is preferably binary.

Le détecteur D1 comporte un étage de traitement 12 connecté à l'étage de détection 11 et destiné à générer un ou plusieurs signaux de sortie.The detector D1 comprises a processing stage 12 connected to the detection stage 11 and intended to generate one or more output signals.

Le détecteur de l'invention présente la particularité d'être polyvalent. Il peut s'adapter aux différentes configurations de traitement et de commande de l'unité logique de traitement 2 qui lui est connecté.The detector of the invention has the particularity of being versatile. It can adapt to the different processing and control configurations of the logic processing unit 2 connected to it.

Pour cela, en référence à la figure 2, le détecteur de l'invention comporte :

  • une première sortie, par exemple de type NO (pour "Normally Opened", c'est-à-dire normalement ouverte),
  • une deuxième sortie, par exemple de type NC (pour "Normally Closed", c'est-à-dire normalement fermée),
  • une entrée de test cyclique reliée à l'une de ses bornes d'alimentation.
For this, with reference to the figure 2 the detector of the invention comprises:
  • a first output, for example of type NO (for "Normally Opened", that is to say normally open),
  • a second output, for example NC type (for "Normally Closed", that is to say normally closed),
  • a cyclic test input connected to one of its supply terminals.

Dans cette configuration, le détecteur D1 de l'invention pourra ainsi indifféremment se connecter sur une unité logique de traitement 2 qui est apte à gérer un détecteur à deux sorties NO et NC complémentaires ou apte à gérer un détecteur à sortie NO ou NC et une entrée de test cyclique.In this configuration, the detector D1 of the invention can thus indifferently connect to a logic processing unit 2 which is able to manage a detector with two complementary outputs NO and NC complementary or able to manage a NO or NC output detector and a cyclic test input.

Bien entendu, le détecteur D1 pourrait également comporter deux sorties de type NO ou deux sorties de type NC.Of course, the detector D1 could also include two NO type outputs or two NC type outputs.

Par ailleurs, le détecteur D1 de l'invention est agencé pour disposer d'une connectique simple et standard à quatre points de connexion, telle que la connectique M12. En plus de ses deux bornes d'alimentation, le détecteur D1 de l'invention comporte donc deux bornes de sortie O1, O2, c'est-à-dire une première borne de sortie O1 connectée à la première sortie (de type NO sur les figures annexées) et une deuxième borne de sortie O2 connectée à la deuxième sortie (de type NC sur les figures annexées). Chaque sortie du détecteur comporte un transistor de type PNP ou NPN commandé par un dispositif de commande relié à l'étage de traitement.Moreover, the detector D1 of the invention is arranged to have a simple and standard connection at four connection points, such as the M12 connector. In addition to its two power supply terminals, the detector D1 of the invention therefore comprises two output terminals O1, O2, that is to say a first output terminal O1 connected to the first output (NO type on the appended figures) and a second output terminal O2 connected to the second output (NC type in the appended figures). Each output of the detector comprises a PNP or NPN type transistor controlled by a control device connected to the processing stage.

Par ailleurs, le détecteur D1 de l'invention comporte un module de test MT connecté à la première borne d'alimentation A1 ou à la deuxième borne d'alimentation A2. Sur la figure 2, le module de test est connecté à la première borne d'alimentation.Furthermore, the detector D1 of the invention comprises a test module MT connected to the first supply terminal A1 or to the second supply terminal A2. On the figure 2 , the test module is connected to the first power supply terminal.

Le module de test MT comporte un module de comparaison comprenant une première entrée recevant une valeur seuil Vseuil prédéterminée et une deuxième entrée connectée à la première borne d'alimentation A1 et recevant un signal d'entrée de test S_test en provenance de l'unité logique de traitement 2. Le module de comparaison comporte une sortie sur laquelle est appliqué un signal de sortie Sig dont l'état dépend de la comparaison entre le signal d'entrée de test S_test appliqué sur la deuxième entrée du module de comparaison et la valeur seuil Vseuil appliquée sur la première entrée. Le module de test MT permet de tester que la première sortie (NO) et/ou la deuxième sortie (NC) du détecteur D1 sont en parfait état de fonctionnement lorsque le détecteur est connecté à une unité logique de traitement 2 disposant d'une sortie de test Out_test (figure 3B par exemple). Lors du test des sorties, le signal de sortie Sig est envoyé à l'étage de traitement 12 qui commande alors le blocage simultané des 2 sorties.The test module MT comprises a comparison module comprising a first input receiving a predetermined threshold value Vthreshold and a second input connected to the first supply terminal A1 and receiving an input signal. S_test test from the logic processing unit 2. The comparison module comprises an output on which is applied an output signal Sig whose state depends on the comparison between the test input signal S_test applied on the second input of the comparison module and the threshold value Vthreshold applied to the first input. The test module MT makes it possible to test that the first output (NO) and / or the second output (NC) of the detector D1 are in perfect working order when the detector is connected to a logic processing unit 2 having an output Out_test ( figure 3B for example). When testing the outputs, the output signal Sig is sent to the processing stage 12 which then controls the simultaneous blocking of the two outputs.

Par ailleurs, le détecteur D1 comporte également un module d'alimentation MA lui permettant de rester alimenté lorsque le test des sorties est en cours. Ce module d'alimentation MA comporte un condensateur Cp chargé périodiquement par la tension d'alimentation appliquée par l'unité logique de traitement 2 entre les deux bornes d'alimentation A1, A2 du détecteur et un régulateur de tension 13 destiné à réguler la tension d'alimentation aux bornes du condensateur. Le module d'alimentation MA est connecté à la deuxième borne d'alimentation du détecteur.In addition, the detector D1 also includes a power supply unit MA allowing it to remain powered when the output test is in progress. This power supply module MA comprises a capacitor Cp periodically charged by the supply voltage applied by the logic processing unit 2 between the two supply terminals A1, A2 of the detector and a voltage regulator 13 intended to regulate the voltage supply to the terminals of the capacitor. The power supply module MA is connected to the second supply terminal of the detector.

En référence aux figures 3A et 3B, par sa polyvalence, le détecteur D1 de l'invention est ainsi capable de s'adapter aux deux configurations classiques de connexion à une unité logique de traitement 2.With reference to Figures 3A and 3B by its versatility, the detector D1 of the invention is thus able to adapt to the two conventional configurations of connection to a logic processing unit 2.

La figure 3A illustre une première configuration dans laquelle le détecteur D1 de l'invention est doté de deux sorties redondantes (identiques ou complémentaires) connectées à deux entrées in1, in2 de l'unité logique de traitement 2. Dans cette configuration, le module de test MT du détecteur n'est pas employé. Les deux bornes d'alimentation A1, A2 du détecteur sont connectées à deux bornes d'alimentation +, - de l'unité logique de traitement 2.The figure 3A illustrates a first configuration in which the detector D1 of the invention is provided with two redundant outputs (identical or complementary) connected to two inputs in1, in2 of the logic processing unit 2. In this configuration, the test module MT of detector is not used. The two power supply terminals A1, A2 of the detector are connected to two power supply terminals +, - of the logic processing unit 2.

La figure 3B illustre une deuxième configuration dans laquelle le détecteur D1 de l'invention est employé dans un mode de fonctionnement à une sortie (NO ou NC) connectée à une entrée in1 de l'unité logique de traitement. Le détecteur D1 est alimenté par la sortie de test de l'unité logique de traitement 2 et sa première borne d'alimentation A1 reçoit le signal d'entrée de test S_test.The figure 3B illustrates a second configuration in which the detector D1 of the invention is employed in an operating mode with an output (NO or NC) connected to an input in1 of the logic processing unit. The detector D1 is powered by the test output of the logic processing unit 2 and its first power supply terminal A1 receives the test input signal S_test.

Le principe de fonctionnement du détecteur D1 de l'invention dans cette deuxième configuration est illustré par les figures 4A à 4D.The operating principle of the detector D1 of the invention in this second configuration is illustrated by the Figures 4A to 4D .

La figure 4A représente l'état du signal d'entrée de test S_test envoyé par la sortie de test Out_test de l'unité logique de traitement 2 sur la première borne d'alimentation A1 du détecteur. Afin de tester la sortie du détecteur D1 de manière cyclique, le signal d'entrée de test S_test alterne périodiquement entre deux valeurs (0 ou 1 en binaire). Lorsque le signal d'entrée de test S_test est à 1, le détecteur D1 fonctionne normalement et est alimenté par l'unité logique de traitement 2. Lorsque le signal d'entrée de test S_test est à 0, l'unité logique de traitement 2 teste chaque sortie du détecteur et le détecteur D1 n'est donc plus alimenté par l'unité logique de traitement 2.The Figure 4A represents the state of the test input signal S_test sent by the Out_test test output of the process logic unit 2 to the first power supply terminal A1 of the detector. In order to test the output of the detector D1 cyclically, the test input signal S_test periodically alternates between two values (0 or 1 in binary). When the test input signal S_test is at 1, the detector D1 operates normally and is powered by the logic processing unit 2. When the test input signal S_test is at 0, the logic processing unit 2 tests each output of the detector and the detector D1 is no longer supplied by the logic processing unit 2.

La figure 4B représente l'état de charge et décharge du condensateur Cp. Le condensateur Cp se charge lorsque le signal d'entrée de test appliqué sur la première borne d'alimentation A1 est à 1, c'est-à-dire lorsque le détecteur D1 est alimenté par l'unité logique de traitement. Lorsque le signal d'entrée de test est à la valeur 0, le détecteur D1 n'est plus alimenté par l'unité logique de traitement 2 et s'alimente alors sur l'énergie emmagasinée dans le condensateur Cp, qui se décharge.The Figure 4B represents the state of charge and discharge of the capacitor Cp. The capacitor Cp is charged when the test input signal applied to the first power supply terminal A1 is at 1, that is to say when the detector D1 is supplied by the logic processing unit. When the test input signal is at the value 0, the detector D1 is no longer supplied by the logic processing unit 2 and then feeds on the energy stored in the capacitor Cp, which discharges.

La figure 4C représente l'état du signal de sortie Sig du module de comparaison. La valeur 1 du signal de sortie Sig correspond à la commande d'inhibition de chaque sortie du détecteur D1. Le signal de sortie Sig est à la valeur 1 lorsque le signal d'entrée de test S_test est à la valeur 0.The figure 4C represents the state of the output signal Sig of the comparison module. The value 1 of the output signal Sig corresponds to the inhibition command of each output of the detector D1. The output signal Sig is at the value 1 when the test input signal S_test is at the value 0.

La figure 4D représente l'état des deux sorties NO et NC du détecteur D1 (même si une seule sortie est connectée à l'unité logique de traitement 2, les deux sorties basculent simultanément). Par exemple, les deux sorties NO, NC prennent alternativement un état complémentaire (C) lorsque le détecteur D1 fonctionne normalement et un état commun de blocage (B) lorsque l'unité logique de traitement 2 passe le signal d'entrée de test S_test à la valeur 0 pour tester les deux sorties NO et NC.The figure 4D represents the state of the two outputs NO and NC of the detector D1 (even if only one output is connected to the processing logic unit 2, the two outputs switch simultaneously). For example, the two outputs NO, NC take alternately a complementary state (C) when the detector D1 operates normally and a blocking common state (B) when the logic processing unit 2 passes the test input signal S_test to the value 0 to test the two outputs NO and NC.

Le module de test MT décrit ci-dessus pourrait présenter un fonctionnement différent de celui décrit ci-dessus. En effet, l'idée principale consiste à inhiber périodiquement les sorties de manière à les tester, sur sollicitation de l'unité logique de traitement. La comparaison effectuée par le module de comparaison pour la génération du signal de sortie Sig pourrait donc être différente de celle décrite ci-dessus. The test module MT described above could have a different operation than that described above. Indeed, the main idea is to periodically inhibit the outputs so as to test them, on solicitation of the logical processing unit. The comparison made by the comparison module for the generation of the output signal Sig could therefore be different from that described above.

Claims (8)

  1. A detector (D1) comprising:
    - a sensor member (10),
    - a detection stage (11) connected to the sensor member (10) and intended to generate a detection signal representative, depending on the position of a target relative to the detector, of a safe detection state or of an unsafe detection state,
    - a first power supply terminal (A1) and a second power supply terminal (A2) between which can be applied a power supply voltage required to power the device,
    - a first output terminal (O1) connected to a first output,
    - a second output terminal (O2) connected to a second output,
    - a processing stage (12) intended to process the detection signal and to control the first output and the second output as a function of the detection signal received,
    - characterized in that it comprises a test module (MT) connected to the first power supply terminal (A1) or to the second power supply terminal and arranged to receive a cyclical test input signal (S_test) arriving from an external processing logic unit (2) on said first power supply terminal or second power supply terminal, said test module being arranged to generate an output signal (Sig) sent to the processing stage (12) in order to place each output in a determined state that can be interpreted by said external processing logic unit (2).
  2. The detector as claimed in claim 1, characterized in that the test module (MT) comprises a comparison module arranged to generate the output signal (Sig) according to the state of the test input signal (S_test) relative to a determined threshold value (Vseuil).
  3. The detector as claimed in claim 1 or 2, characterized in that it comprises a power supply module (MA) comprising a capacitor (Cp) arranged to charge in normal operation and to discharge while maintaining a sufficient power supply voltage for the correct operation of the detector when the outputs are being tested.
  4. The detector as claimed in one of claims 1 to 3, characterized in that it comprises four connection terminals arranged to receive a connector of M12 type.
  5. The detector as claimed in one of claims 1 to 4, characterized in that the first output is of "normally open" (NO) type.
  6. The detector as claimed in claim 5, characterized in that the second output is of "normally closed" (NC) type.
  7. A detection system, characterized in that it comprises:
    - a processing logic unit comprising at least one input (in1) and one test output (Out_test),
    - a detector (D1) as defined in one of the preceding claims, the first output terminal (01) of which is connected to said input (in1) of the processing logic unit (2) and a power supply terminal (A1, A2) of which is connected to the test output of the processing logic unit (2), the processing logic unit (2) being arranged to generate a test input signal (S_test) applied to said power supply terminal of the detector (D1) in order to test each output (NO, NC) of the detector (D1) connected to the processing logic unit (2).
  8. A detection system, characterized in that it comprises:
    - a processing logic unit comprising two inputs (in1, in2) and two power supply terminals (+, -),
    - a detector (D1) as defined in one of the preceding claims, the two power supply terminals (A1, A2) of which are connected to the two power supply terminals (+, -) of the processing logic unit (2) and the two output terminals (O1, O2) of which are connected to the two inputs (in1, in2) of the processing logic unit (2) so as to offer redundancy between the two outputs of the detector.
EP13770668.5A 2012-10-26 2013-09-24 Versatile sil2 detector having two outputs and one test input Active EP2912646B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1260248A FR2997537B1 (en) 2012-10-26 2012-10-26 SIL2 MULTIPURPOSE DETECTOR WITH TWO OUTPUTS AND TEST ENTRY
PCT/EP2013/069853 WO2014063889A1 (en) 2012-10-26 2013-09-24 Versatile sil2 detector having two outputs and one test input

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EP2912646A1 EP2912646A1 (en) 2015-09-02
EP2912646B1 true EP2912646B1 (en) 2016-10-05

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JP (1) JP6219398B2 (en)
CN (1) CN104620292B (en)
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CN107016839B (en) * 2016-01-28 2019-02-15 陕西飞机工业（集团）有限公司 A kind of aircraft fire alarm control box analyser

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DE4123828C2 (en) * 1991-07-18 1997-06-19 Balluff Gebhard Feinmech Non-contact proximity switch
DE4200207C1 (en) * 1992-01-07 1993-01-28 Ifm Electronic Gmbh, 4300 Essen, De Electronic switch, e.g. inductive, capacitive or opto-electronic proximity switch - has switching distance set through external terminals and voltage supplied from external source
US5986839A (en) * 1996-09-17 1999-11-16 International Business Machines Corporation Electronic magnetoresistive sensor biasing using a transducer equivalent circuit and current sources
JP3424489B2 (en) * 1997-03-24 2003-07-07 日産自動車株式会社 Semiconductor overcurrent detection circuit and its inspection method
MXPA05009713A (en) * 2003-03-12 2005-11-04 Joule Microsystems Canada Inc Signal processing system and method.
US7117119B2 (en) * 2003-08-01 2006-10-03 Invensys Systems, Inc System and method for continuous online safety and reliability monitoring
WO2005013098A2 (en) * 2003-08-01 2005-02-10 Invensys Systems, Inc. Continuous online safety and reliability monitoring
US8180466B2 (en) * 2003-11-21 2012-05-15 Rosemount Inc. Process device with supervisory overlayer
JP2010271659A (en) * 2009-05-25 2010-12-02 Funai Electric Co Ltd Liquid crystal module
JP5557577B2 (en) * 2010-03-31 2014-07-23 パナソニック デバイスＳｕｎｘ株式会社 Safety controller
FR2971841B1 (en) * 2011-02-22 2013-09-13 Schneider Electric Ind Sas DETECTOR AND DEVICE FOR CONFIGURING THE DETECTOR

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EP2912646A1 (en) 2015-09-02
JP6219398B2 (en) 2017-10-25
FR2997537B1 (en) 2014-11-21
FR2997537A1 (en) 2014-05-02
CN104620292B (en) 2016-08-24
JP2016502173A (en) 2016-01-21
CN104620292A (en) 2015-05-13
WO2014063889A1 (en) 2014-05-01

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