EP2883241A1

EP2883241A1 - Method of producing semiconductor substrate product and etching liquid

Info

Publication number: EP2883241A1
Application number: EP13827735.5A
Authority: EP
Inventors: Akiko Koyama; Atsushi Mizutani; Tetsuya Kamimura; Tetsuya Shimizu; Tadashi Inaba
Original assignee: Fujifilm Corp
Current assignee: Fujifilm Corp
Priority date: 2012-08-10
Filing date: 2013-07-24
Publication date: 2015-06-17
Also published as: EP2883241A4; WO2014024737A1; JP2014057039A; TW201412948A; TWI625382B

Abstract

A method of producing a semiconductor substrate product, having the steps of: providing a semiconductor substrate having two or more impurity-containing silicon layers and a silicon oxide layer, each of the impurity-containing silicon layers containing a different impurity from one another; applying an etching liquid onto the semiconductor substrate, the etching liquid comprising water, a hydrofluoric acid compound, and an anionic compound; and selectively etching the silicon oxide layer.

Description

DESCRIPTION

METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE PRODUCT AND

ETCHING LIQUID

TECHNICAL FIELD

{0001 }

The present invention relates to a method of producing a semiconductor substrate product and an etching liquid.

BACKGROUND ART

{0002}

An insulated gate field effect transistor has been developed, with installing a high-dielectric constant (high-k) film for a gate insulator film and a metal for a gate electrode. This type of transistor can reduce its gate-leak current and to keep the power consumption at a low level. The insulated gate field effect transistor can be prepared according to the following method. That is, a dummy non-dielectric film is formed from a silicon oxide film on a silicon substrate and a dummy gate is formed thereon, and thereafter n-type impurities (or p-type impurities) are introduced into silicon substrates on both sides of the dummy gate to form a source/a drain. Further, after forming a sidewall of a silicon nitride film at both sides of the dummy gate, and via the step of removing the dummy gate and the dummy film in this order, and then both a high-dielectric constant gate insulator film and a metal gate electrode are formed. {0003}

In the above production process, there is, as an example, a method of using a diluted hydrofluoric acid in order to selectively remove the dummy film of the silicon oxide film after removing the dummy gate. However, in the wet etching of the dummy film using a diluted hydrofluoric acid, although selective etching is possible for the sidewall, a selective etching capacity for the source/drain is poor. As a result, a part of the source/drain exposed on the tip of the dummy gate under the sidewall is etched whereby a void (depression) is generated (for reference, see Non-Patent Literature 1) (see void v, Fig. 2). It is thought that this void is caused by undergoing bimetallic corrosion (Galvanic Corrosion). To be specific, this is described below. In such category of transistor structure, impurity concentration of the source/drain is higher than that of the silicon substrate that becomes a channel-forming region between the source/drain. As a result, a difference occurs between electrode potentials that the materials have at the time of wet etching. Furthermore, in cooperation with impurity doped in the source/drain and impurity doped in the channel-forming region each of which has opposite conductivity type to one another, the above-described bimetallic corrosion is facilitated. It is understood that as a result, an end of the source/drain is dissolved with an etching liquid.

{0004}

Also in a case of forming extension layers at gate ends of the source and the drain, the phenomenon similarly arises that the gate end sides of the extension layers are etched. This is because although the impurity concentration of the extension layer is lower than that of the source or the drain, there is a difference in the impurity concentration between the extension layer and the channel-forming region, and the conductivity type of the impurity is opposite to one another. When a void generates at the gate end side of the extension layer, a gate insulator film to be formed at the end of the extension layer is formed in the void in the case of forming a transistor. As a result, electric field gets centered on the portion, which gets to insulation breakdown. Thus, sometimes the transistor does not run.

CITATION LIST

{Non-Patent Literature}

{0005}

{Non-Patent Literature 1 } Antoine Pacco et al.,ECS Trans., Vol.4 l,Issue5,p.37-43

DISCLOSURE OF INVENTION TECHNICAL PROBLEM

{0006}

The present invention addresses to the provision of a method of producing a semiconductor substrate product and an etching liquid, each of which enables selective etching of a silicon oxide layer by protecting a layer containing impurity, while keeping a sufficient etching rate. Further, the present invention addresses to the provision of a method of producing a semiconductor substrate product and an etching liquid, each of which enables, if needed, no variation in etching between substrates and exhibits good production suitability with suppression of foaming.

SOLUTION TO PROBLEM

{0007}

According to the present invention, there is provided the following means:

{ 1 } A method of producing a semiconductor substrate product, having the steps of: providing a semiconductor substrate having two or more impurity-containing silicon layers and a silicon oxide layer, each of the impurity-containing silicon layers containing a different impurity from one another;

applying an etching liquid onto the semiconductor substrate, the etching liquid having water, a hydrofluoric acid compound, and an anionic compound; and

selectively etching the silicon oxide layer.

{2} The method of producing a semiconductor substrate product as described in item { 1 } , wherein the hydrofluoric acid compound in the etching liquid has a concentration from 0.01 mass% to 10 mass%.

{3} The method of producing a semiconductor substrate product as described in item { 1 } or {2}, wherein the anionic compound in the etching liquid has a concentration from 0.00001 mass% to 85 mass%.

{4} The method of producing a semiconductor substrate product as described in any one of items { 1 } to {3 } , wherein the anionic compound is a compound represented by any one of formulae (1) to (3):

R¹ Ac_n (1) _R3_{h A|}. Q _Ar

R² _m Ar— Ac_n (2) ^Α¾ Ac_k (3)

wherein R¹ to R³ each independently represent an alkyl group or an alkenyl group; Ar represents an aromatic ring; Ac represents -SO3M or -COOM; M represents a hydrogen atom or a cation; n represents an integer of 1 to 3; m represents an integer of 0 to 3; h represents an integer of 1 to 3; j represents 0 or 1; k represents 0 or 1; and the total of j and k j+k) is 1 or 2.

{5} The method of producing a semiconductor substrate product as described in item {4}, wherein the anionic compound represented by formula (2) is a compound represented by formula (2-1) or (2-2):

(2-1 ) (2-2)

wherein R , Ac, m, and n have the same meanings as those of formula (2), respectively.

{6} The method of producing a semiconductor substrate product as described in item {4} or {5} ,

wherein the content of the anionic compound is adjusted to be within the following range:

from 40 mass% to 85 mass%, when R¹ has 1 to 2 carbon atom(s) in formula (1);

from 20 mass% to 85 mass%, when R¹ has 3 to 5 carbon atoms in formula (1); from 0.1 ppm (mass standard) to 1 mass%, when R¹ has 6 or more carbon atoms in formula (1);

from 5 mass% to 70 mass%, when R has 0 to 2 carbon atom(s) in total in formula (2-1);

from 1 mass% to 60 mass%, when R has 3 to 4 carbon atoms in total in formula (2-1);

from 0.1 ppm (mass standard) to 1 mass%, when R² has 5 or more carbon atoms in total in formula (2-1);

from 0.5 mass% to 20 mass%, when R² has 0 to 2 carbon atom(s) in total in formula (2-2); and

from 0.1 ppm (mass standard) to 1 mass %, when R² has 3 or more carbon atoms in total in formula (2-2). {7} The method of producing a semiconductor substrate product as described in any one of. items { 1 } to {6},

wherein the anionic compound is an alkylbenzene sulfonic acid, an

alkylnaphthalene sulfonic acid, an alkyldiphenylether disulfonic acid, or a salt thereof. {8} The method of producing a semiconductor substrate product as described in any one of items { 1 } to {7} ,

wherein the impurity-containing silicon layer constitutes a ground for the silicon oxide layer.

{9} The method of producing a semiconductor substrate product as described in any one of items { 1 } to {8},

wherein at least two of the impurity-containing silicon layers are an n-type semiconductor layer and a p-type semiconductor layer.

{ 10} The method of producing a semiconductor substrate product as described in any one of items { 1 } to {9} ,

wherein the impurity-containing silicon layer is disposed at the position such that the impurity-containing silicon layer comes into contact with the etching liquid at the time of etching processing.

{ 11 } The method of producing a semiconductor substrate product as described in any one of items {1 } to { 10},

the impurity-containing silicon layer has at least boron as an impurity.

{12} The method of producing a semiconductor substrate product as described in any one of items { 1 } to { 1 1 } ,

wherein the impurity-containing silicon layer has at least phosphorus or arsenic as an impurity.

{ 13} An etching liquid, having:

water,

a hydrofluoric acid compound, and

an anionic compound;

the etching liquid for being applied onto a substrate, the substrate having two or more impurity-containing silicon layers and a silicon oxide layer, each of the impurity-containing silicon layers containing a different impurity from one another, the etching liquid for selectively etching the silicon oxide layer.

{ 14} The etching liquid as described in item { 13},

wherein the hydrofluoric acid compound has a concentration from 0.01 mass% to 10 mass%.

{ 15} The etching liquid as described in item { 13} or { 14},

wherein the anionic compound has a concentration from 0.00001 mass% to 85 mass%.

{ 16} The etching liquid as described in any one of items {13} to {15}, wherein the anionic compound is a compound represented by any one of formulae (1) to (3):

R¹ Ac„ (1) _R3_{h Ar}__{0 Ar} R² _in Ar— Ac_n (2) A_Cj Ac_k (3)

wherein R¹ to R³ each independently represent an alkyl group or an alkenyl group; Ar represents an aromatic ring; Ac represents -S0₃M or -COOM; M represents a hydrogen atom or a cation; n represents an integer of 1 to 3; m represents an integer of 0 to 3; h represents an integer of 1 to 3; j represents 0 or 1; k represents 0 or 1; and the total of j and k (j+k) is 1 or 2.

{ 17} The etching liquid as described in item { 16}, wherein the anionic compound represented by formula (2 is a compound represented by formula (2-1) or (2-2):

(2-1 ) (2-2)

wherein R², Ac, m and n have the same meanings as those in formula (2), respectively.

{ 18} The etching liquid as described in item { 16} or { 17},

from 40 mass% to 85 mass%, when R¹ has 1 to 2 carbon atom(s) in formula (1);

from 5 mass% to 70 mass%, when R² has 0 to 2 carbon atom(s) in total in formula (2-1);

from 1 mass% to 60 mass%, when R² has 3 to 4 carbon atoms in total in formula (2-1);

from 0.1 ppm (mass standard) to 1 mass %, when R² has 5 or more carbon atoms in total in formula (2-1);

from 0.5 mass% to 20 mass%, when R has 0 to 2 carbon atom(s) in total in formula (2-2); and

from 0.1 ppm (mass standard) to 1 mass %, when R² has 3 or more carbon atoms in total in formula (2-2).

{ 19} A method of producing a semiconductor substrate product, having the steps of: preparing a silicon substrate having a p-type impurity layer, an n-type impurity layer, and a silicon oxide layer in the state of the layers each capable of being exposed on the surface of the silicon substrate, each of the p-type impurity layer and n-type impurity layer being an impurity-doped layer of silicon;

preparing an etching liquid comprising water, a hydrofluoric acid compound, and an anionic compound; and

applying the etching liquid onto the silicon substrate, thereby selectively etching the silicon oxide layer.

{20} A method of producing a semiconductor element, having the steps of:

producing a semiconductor substrate product through the processes recited in any one of items { 1 } to { 12} and {19}; and

producing the semiconductor element by using the same.

In the present specification, the term "having" is to be construed in the open- ended meaning as well as the term "comprising" or "containing." Further, the term "preparing" or "providing" is to be construed in the broadest manner as the meaning of making materials ready to be used, e.g., not only the meaning of producing or synthesizing the materials, but also purchasing them.

{0008} An anionic surfactant has a containment relationship with the anionic compound. Typically, among the anionic compounds, anionic compounds having 3 or more carbon atoms act as the anionic surfactant. ADVANTAGEOUS EFFECTS OF INVENTION

{0009}

According to the production method of the present invention, the silicon oxide layer can be subjected to selective etching with respect to the impurity-containing silicon layer with a sufficient etching rate. As a result, this method is able to produce a higher-quality semiconductor substrate product such as a High-K/Metal Gate transistor, of which miniaturization has been further advanced recently, and a higher-quality semiconductor device using the same. Further, the production method of the present invention realizes, if needed, a good etching with suppression of variation in etching between substrates (substrate dependency) and good production suitability with suppression of foaming.

Further, the etching liquid of the present invention is useful for application to production of the semiconductor substrate product and the semiconductor device each of which achieves high quality as described above.

{0010}

In the above-described chemical formulae, when a plurality of the substituent or substitution number is represented by the same symbol, it means that the substituent or substitution number may be different from one another. For example, in formula (2), when n is 2 or more, a plurality of Ac may be different from one another.

Other and further features and advantages of the invention will appear more fully from the following description, appropriately referring to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

{001 1 }

{Fig. 1 }

Fig.l is a main part-enlarged sectional view schematically showing one of preferable embodiments of the production method according to the present invention. {Fig- 2}

Fig.2 is a main part-enlarged sectional view schematically showing one of preferable embodiments (continued) of the production method according to the present invention (however, the enlarged portion inside of the circle shows the state of an example of the conventional art).

MODE FOR CARRYING OUT THE INVENTION

{0012}

Hereinafter, preferable embodiments of the production method and the etching liquid of the present invention are described in detail with reference to Fig. 1. In the following detailed descriptions, one step of the production process in accordance with a so-called "gate-last process" of an nMOS insulated gate field effect transistor is described as one example. However, the present invention should not be construed by limiting thereto.

{0013 }

(Embodiment)

As shown in Fig. 1 (process (a)), a single crystal silicon substrate is used as substrate 1 1. On the substrate 1 1 , well 12 is formed in the region where a transistor is formed, and further a channel dope layer 13 is formed. In a case of producing an nMOS transistor, the well 12 is prepared so as to get a p-type well. For example, in accordance with an ion implantation method, boron (B⁺) is used as an ion species, and an implant energy from lOOkeV to 2MeV and a dose amount of 1 χ 10^{1 1} atom/cm² to 1 χ 10¹² atom/cm are employed. In a case of producing a pMOS transistor, the well 12 is prepared so as to get an n-type well. The well 12 may not be produced depending on a conductivity type of the substrate 1 1.

Further, in a case of producing the nMOS transistor, the channel dope layer 13 is prepared so as to get a p-type. For example, in accordance with the ion implantation method, boron (B⁺) is used as an ion species, and an implant energy from lOkeV to 20KeV and a dose amount of 1 χ 10¹² atom/cm² to 2χ 10¹³ atom/cm² are employed. In a case of producing the pMOS transistor, the channel dope layer 13 is prepared so as to 0 get an n-type. Before or after forming the well 12, an element isolation (not shown in Fig. 1) that electrically sectionalizes a formation region of an element such as a transistor is usually formed by an insulating film element isolation (for example, STI; Shallow Trench Isolation), or a diffusion layer element isolation.

As the above-described substrate 11 , besides the above-described single crystal silicon substrate, various kinds of substrates having silicon layer, such as SOI (Silicon On Insulator) substrate, SOS (Silicon On Sapphire) substrate, a compound

semiconductor substrate having silicon layer may be used. A circuit, an element, and the like may be formed, in advance, on the substrate 1 1.

{0014}

Next, in the following order, a dummy film and a dummy gate film (not shown in Fig. 1) are formed on the substrate 1 1. A silicon oxide film is used as the dummy film 14. The silicon oxide film is formed, for example, in accordance with a CVD method, a thermal oxidation method, a rapid thermal oxidation method, a radical oxidation method, or the like, and impurities such as germanium, carbon, or the like may be incorporated in the film.

Next, the dummy gate film and the dummy film are processed using a lithographic technique to form a dummy gate (not shown in Fig. 1). At this time, the simultaneously processed dummy film 14 is left at the foot of the dummy gate.

{0015}

Hereinafter, an nMOS transistor is described. Next, using the dummy gate as a mask, extension layers 15 and 16 are formed above the substrate 1 1 at each side of the dummy gate so that these layers are incorporated under the end of gate electrode, in order to improve pressure resistance by reducing a hot carrier. In the extension layers 15 and 16, n-type impurities (for example, arsenic (As⁺)) are doped by using, for example, an ion implantation technique. As an example, implantation is performed under the conditions of implantation energy: from 0.1 KeV to 5KeV and dose amount from 5x l0¹³ atom/cm² to 2x l0¹⁶ atom/cm². In addition, in the extension layers 15 and 16, carbon may be doped at the formation region of the extension layers 15 and 16, in order to improve mobility of transistor. This is because tensile stress is generated by doping carbon into the extension layers 15 and 16, and the channel dope layer 13 receives the resultant tensile stress whereby mobility of an nMOS (nMIS) transistor is improved. In addition, in a case of a pMOS transistor, germanium that generates compressive stress is doped into the extension layers 15 and 16, in order to improve mobility of transistor.

Further, using the ion implantation technique, halo layers 19 and 20 are formed at the positions that becomes respectively the end of source 17 and the end of drain 18 under the extension layers 15 and 16. For example, the halo layers are formed by using BF₂ ⁺ as an ion species of a p-type impurity under the conditions of implantation energy: from lOKeV to 15KeV and dose amount from l x lO¹² atom/cm² to 1 >< 10¹⁵ atom/cm². The halo layers 19 and 20 are provided to reduce the impact of punch through generated in association with a short channel effect, and to adapt transistor characteristics to a desired value. Further, these layers are formed by ion implantation of impurities each having a conductivity type opposite to that of the source 17 and the drain 18, and are usually formed so that impurity concentration of the halo layers is higher than that of the channel dope layer 13. Fig. 1 (a) shows the state immediately after formation of the halo layers 19 and 20. Formation of the halo layers 19 and 20 prior to removal of the dummy film 14 has the advantage that the dummy film 14 acts as a buffer film whereby damage to the channel dope layer 13 due to ion implantation is suppressed.

{0016}

Next, after formation of a side wall-forming insulation film on the entire surface of the substrate 1 1 of the side where the dummy gate (not shown in Fig., but the dummy gate is presumed to be formed in region W) has been formed, the side wall- forming insulation film is etched using an etchback technique in a manner such that the side wall-forming insulation film is left at a sidewall of the dummy gate. Thus, sidewalls 21 are formed at the sidewalls of the dummy gate. The side wall-forming insulation film is formed of a silicon nitride film, favorably in accordance with a usual chemical vapor deposition.

{0017}

Next, using the dummy gate and the sidewalls 21 as a mask, the source 17 and the drain 18 are formed on the substrate 1 1. Ordinarily, the source 17 and the drain 18 are formed using, for example, an ion implantation technique in a manner such that n type impurities (for example, phosphorus (P⁺) or arsenic (As⁺)) are doped up to the position deeper than the extension layers 15 and 16. For example, the source 17 and the drain 18 are formed using arsenic (As⁺) as n-type impurities under the conditions of implantation energy: from lOKeV to 50KeV and dose amount from l x lO¹² atom/cm² to 5 l0¹⁶ atom/cm².

{0018}

Next, in accordance with a conventional film formation technique, an interlayer insulation layer 22 is formed on the entire surface of the substrate 11 of the side where a dummy gate has been formed. Further, the surface of the interlayer insulation layer 22 is subjected to a planarization step. The interlayer insulation layer 22 is formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. Thereafter, an upper portion of the dummy gate is exposed from the interlayer insulation layer 22 in accordance with a chemical mechanical polishing (CMP: Chemical Mechanical Polishing), or the etchback technique. Further, the dummy gate is selectively removed by etching using the interlayer insulation layer 22 as an etching mask. The etching of the dummy gate may be a wet etching or a dry etching.

{0019}

Next, the above-described dummy film 14 is selectively removed in accordance with the wet etching. In the wet etching, an etching liquid containing water, a hydrofluoric acid compound, and an anionic compound is used. The etching liquid is described below. The state immediately after removal of the dummy film 14 is shown in Fig. 2 (process (b)). As a result, the state in which the channel dope layer 13 is exposed between both sidewalls 21 is obtained. Using the etching liquid, only the dummy film 14 of silicon oxide is removed by etching without etching the extension layers 15 and 16 that are the underlying silicon layer. By this, generation of void is prevented in the extension layers 15 and 16 at the gate end. Accordingly, even though a gate insulator film is formed at this portion, electric field concentration is difficult to be caused whereby reliability of the transistor is improved. In Fig. 2, for the sake of convenience to understand, the tip of the extension layer 16 is shown by enlarging it in a circle. The state in which a void (depression) v generates there is illustrated. According to the present invention, the void v can be favorably suppressed or prevented. {0020}

Next, though not shown in Fig. 2, a gate insulator film is formed on a surface of the exposed channel dope layer 13 and on sidewalls of the sidewalls 21, and the gate electrode film is formed so as to implant it between both sidewalls 21. After that, redundant gate electrode film and gate insulator film on the interlayer insulation layer 22 are removed. For the removal, a CMP technique is ordinarily used. As a result, a gate electrode that is composed of a gate electrode film is formed on the channel dope layer 13 between both side walls 21 through the gate insulator film.

As the above gate film, High-k film can be used. Examples of High-k film include hafnium oxide (Hf0₂), hafnium aluminum oxide (HfA10₂), hafnium silicate

(HfSiO), tantalum oxide (Ta₂0₅), aluminum oxide (A1₂0₃), and zirconium oxide (Zr0₂). Usual methods such as ALD: Atomic Layer Deposition and CVD: Chemical Vapor Deposition are used for film formation of the film. The film thickness of the gate film is preferably 1 nm to 3 nm. Further, the gate insulator film may be a laminated film of a silicon oxide film and a silicon oxynitride film.

Examples of the above gate electrode include titanium nitride (TiN), titanium (Ti), titanium silicon (TiSi), nickel (Ni), nickel silicide (NiSi), hafnium (Hf), hafnium silicide (HfSi), tungsten (W), tantalum (Ta), tantalum silicide (TaSi), tantalum nitride silicide (TaSiN), cobalt (Co), cobalt silicide (CoSi), ruthenium (Ru), and indium (Ir). The film is usually formed by ALD method or PVD: Physical Vapor Deposition) method.

After that, an interlayer insulation film is formed, and then a wire formation step and other element formation steps are performed.

The dose amount and the implantation energy described in the above-described ion implantation steps, are examples, and these amount and energy are appropriately determined according to the required characteristics of a transistor.

{0021 }

In the present invention, as the impurity-containing silicon layer, at least two layers exist, and the impurities that has been introduced into the two layers are different from one another. The impurity-containing silicon layer is preferably disposed at the position such that the impurity-containing silicon layer comes into contact with the etching liquid at the time of etching processing. More specifically, an embodiment is exemplified in which the impurity-containing silicon layer constitutes a ground for the silicon oxide layer that is removed by etching. When the impurity is explained by the above-described example, by virtue of the fact that the conductivity type impurity (for example, p-type) of a channel dope layer and the conductivity type impurity (for example, n-type) of an extension layer are different from one another, the effects of the present invention are more favorably exhibited. In the case where different-type (n-type, p-type) semiconductor layers are exposed to environment in which these layers are etched, the above-described bimetallic corrosion becomes conspicuous. According to a preferable embodiment of the present invention that favorably conforms such conditions, a damage of the layer, that becomes base in particular under the conditions that an unevenness of noble /base in potential appears on the exposed area, can be suppressed or prevented.

{0022}

Examples of the impurity-containing semiconductor layer that is applied to the production method of the present invention are arranged in a table below. Among them, an nMOS form is preferred, and No. 1 is particularly preferred. In the present invention, each layer may contain impurities or accessory components, insofar as a desired effect is exhibited. For example, the silicon oxide layer may contain elements other than both silicon and oxygen (for example, carbon, nitrogen or the like).

{0023}

TableA

{0024}

(Etching liquid)

Next, a preferable embodiment of the etching liquid of the present invention is explained. The etching liquid of the present invention can be quite efficiently used for the wet etching that has been explained in the step of removing the above-described dummy film 14. The etching liquid of the present embodiment contains water, a hydrofluoric acid compound, and an anionic compound. This enables the above- described removal of a silicon oxide layer without excessively etching the impurity- doped silicon layer that is disposed as a ground of the silicon oxide layer. The reason why such special effect is exhibited is not clear. However, an explanation including some presumption is as follows.

Extension layers 15 and 16 are constituted of an impurity-containing silicon layer, and it is thought that a Si-H bond is exposed on the surface of this silicon layer. It is presumed that the anionic compound in the etching liquid adsorbs to the Si-H bond to form a protective layer, thereby inhibiting the silicon layer from being etched. On the other hand, it is thought that a hydrogen bond (Si-O-H) also exists on the surface of silicon oxide and the anionic compound adsorbs thereto. However, it is presumed that the anionic compound adsorbs selectively or predominantly to the Si-H, which results in achievement of a desirable selectivity while maintaining good etching rate.

{0025}

(Anionic compound)

The etching liquid of the present invention contains an anionic compound. In the present invention, the anionic compound, although it is not particularly limited, typically means a compound having a hydrophilic group and a lipophilic group in the molecule thereof, wherein a portion of the hydrophilic group dissociates in an aqueous solution to become an anion or to have an anionic property. Herein, the anionic compound may exist as an acid with a hydrogen atom, or may be an anion derived from dissociation of the acid, or may be a salt thereof. The anionic compound may be a non- dissociative compound, as long as it has an anionic property, and therefore an acid ester and the like are included therein.

{0026}

The anionic compound preferably has at least one carbon atom. When an anionic surfactant is used, the carbon number thereof is preferably at least 3, more preferably at least 5, and particularly preferably at least 10. The upper limit of the carbon number is not particularly limited. However, the carbon numbers of 40 or less are practical. By setting the carbon number to the lower limit or greater, effective etching selectivity is preferably achieved.

{0027}

Examples of the anionic compound having from 1 to 40 carbon atom(s) include a carboxylic acid compound having from 1 to 40 carbon atom(s), a phosphoric acid compound having from 1 to 40 carbon atom(s), and a sulfonic acid compound having from 1 to 40 carbon atom(s). An alkylsulfonic acid, an alkylbenzene sulfonic acid, an alkylnaphthalene sulfonic acid, an alkyldiphenylether sulfonic acid (preferably mono- sulfonic acid or disulfonic acid), an aliphatic acid amide sulfonic acid, a

polyoxyethylene alkylether carboxylic acid, a polyoxyethylene alkyl ether acetic acid, a polyoxyethylene alkylether propionic acid, an alkyl phosphoric acid, an aliphatic acid and salts of these acids are preferred. Among them, an alkylbenzene sulfonic acid, an alkylnaphthalene sulfonic acid, an alkyldiphenylether mono-sulfonic acid, an alkyldiphenylether disulfonic acid, or salts of these acids, or mixtures thereof are preferred. Examples of the above-described "salt" include an ammonium salt, a sodium salt, a potassium salt, and a tetramethyl ammonium.

{0028}

The above-described anionic compound is preferably constituted of the compound represented by any one of formulae (1) to (3) described below. An alkylbenzene sulfonic acid, an alkylnaphthalene sulfonic acid, an alkyldiphenylether mono-sulfonic acid, an alkyldiphenylether disulfonic acid, or salts of these acids, or mixtures thereof are more preferred. An alkyldiphenylether mono-sulfonic acid, an alkyldiphenylether disulfonic acid, or salts of these acids, or mixtures thereof are particularly preferred. Note that the compounds represented by the formulae (1) to (3) are typically known as a surfactant.

{0029}

R¹ Ac_n (1) _R3_{h Ar}__{0 Ar}

R² _m Ar— Ac_n (2) A_Cj Ac_k (3)

In formulas (1) to (3), R¹ to R³ each independently represent an alkyl group or an alkenyl group. Ar represents an aromatic ring. Ac represents -S0₃M or -COOM. M represents a hydrogen atom or a cation, n represents an integer of 1 to 3. m represents an integer of 0 to 3. h represents an integer of 1 to 3. j represents 0 or 1; k represents 0 or 1. The total of j and k (j+k) is 1 or 2.

{0030}

The compound represented by formula (2) is preferably a compound

represented by formula (2-1) or (2-2).

(2-1 ) (2-2)

In formulas (2-1) and (2-2), R², Ac, m and n have the same meanings as those in formula (2), respectively.

{0031 }

• R¹ to R³

R¹ to R³ each independently represent an alkyl group or an alkenyl group.

Each of R¹ and R³ is preferably an alkyl group having from 1 to 20 carbon atom(s), or an alkenyl group having from 2 to 22 carbon atoms. When suppression of foaming is emphasized, the carbon number is more preferably from 1 to 10 and particularly preferably from 1 to 6. Each R² is preferably an alkyl group having from 0 to 20 carbon atom(s), or an alkenyl group having from 0 to 22 carbon atom(s). When suppression of foaming is emphasized, the carbon number is more preferably from 0 to 10 and particularly preferably from 0 to 6. Note that the carbon number "0" described herein means that number of substituent for R is 0.

When viewpoints other than the foaming are emphasized, the carbon number for each of R¹ to R³ is preferably from 5 to 20 and more preferably from 8 to 20. Note that in the case where the foaming is emphasized (a second embodiment), a preferable range of a compounding amount with respect to each of the structure and the carbon number is described below.

1 3

Each of R to R may have a substituent and examples of the substituent include an alkyl group having from 1 to 3 carbon atom(s), a halogen atom (fluorine atom, chlorine atom and the like), a cyano group, an amino group, and a hydroxyl group. I o

{0032}

• Ar

Ar represents an aromatic ring. Especially, an aromatic ring having from 6 to 24 carbon atoms is preferred, and an aromatic ring having from 6 to 14 carbon atoms is more preferred. Examples thereof include a benzene ring, a naphthalene ring, an anthracene ring, and a phenanthrene ring. A benzene ring or a naphthalene ring is more preferred. The aromatic ring Ar may have a substituent. The substituent has the same definition as the substituent which the each of R¹ to R³ may have.

{0033}

- Ac

Ac represents -S0₃M or -COOM. M represents a hydrogen atom or a cation. Examples of M include an alkali metal, ammonium, tetramethyl ammonium, and triethanolamine. M is preferably a cation other than the alkali metal, and more preferably ammonium. Herein, when M is referred to as "a cation", it means that M provides a salt with a counter anion (SO ^", COO^"). However, the salt may dissociate in water to become a pair of ions.

{0034}

(First embodiment)

The content of the anionic compound is preferably 85% by mass or less, more preferably 75% by mass or less, and particularly preferably 65% by mass or less, with respect to the total amount of the etching liquid according to the present embodiment. In the case where it is added in small amounts, the content of 5% by mass or less is preferred, the content of 1% by mass or less is more preferred, and the content of 0.6% by mass or less is still more preferred. The lower limit thereof is preferably 0.00001% by mass or greater, more preferably 0.001% by mass or greater, still more preferably 0.01 ) by mass or greater, and still more preferably 0.1% by mass or greater. In the case other than the addition of small amount, the content of 1 % by mass or greater is particularly preferred. By setting the content to the upper limit or less, both etching rate and etching selectivity are more improved, and also suppression of foaming can be preferably achieved. Setting of the content to the lower limit or greater is preferable from the viewpoint of corrosion inhibition. {0035}

In the second embodiment relating to the content of the anionic compound, it is preferred that the content is set according to the structure and the carbon number of the anionic compound as described below. Note that each ppm is based on mass standard. {0036}

When R¹ has 1 to 2 carbon atom(s) in formula (1),

the content of the anionic compound is

preferably from 40 mass% to 85 mass%,

more preferably from 50 mass% to 85 mass%, and

particularly preferably from 60 mass% to 85 mass%.

When R¹ has 3 to 5 carbon atoms in formula (1),

the content of the anionic compound is

preferably from 20 mass% to 85 mass%,

more preferably from 30 mass% to 85 mass%, and

particularly preferably from 40 mass% to 85 mass%.

When R¹ has 6 or more carbon atoms in formula (1),

the content of the anionic compound is

preferably from 0.1 ppm to 1 mass%,

more preferably from 100 ppm to 1 mass%, and

particularly preferably from 1,000 ppm to 1 mass%.

When R² has 0 to 2 carbon atom(s) in total in formula (2-1),

the content of the anionic compound is

preferably from 5 mass% to 70 mass%,

more preferably from 10 mass% to 70 mass%, and

particularly preferably from 20 mass% to 70 mass%.

When R² has 3 to 4 carbon atoms in total in formula (2-1),

the content of the anionic compound is

preferably from 1 mass% to 60 mass%,

more preferably from 5 mass% to 60 mass%, and

particularly preferably from 10 mass% to 60 mass%.

When R^z has 5 or more carbon atoms in total in formula (2-1), the content of the anionic compound is

preferably from 0.1 ppm to 1 mass%,

more preferably from 100 ppm to 1 mass%, and

particularly preferably from 1,000 ppm to 1 mass%.

When R² has 0 to 2 carbon atom(s) in total in formula (2-2),

the content of the anionic compound is

preferably from 0.5 mass% to 20 mass%,

more preferably from 1 mass% to 20 mass%, and

particularly preferably from 3 mass% to 20 mass%.

When R² has 3 or more carbon atoms in total in formula (2-2),

the content of the anionic compound is

preferably from 0.1 ppm to 1 mass%,

more preferably from 100 ppm to 1 mass%, and

particularly preferably from 1,000 ppm to 1 mass%.

In formula (3), the content of 5% by mass or less is preferable, the content of

1% by mass or less is more preferable, and the content of 0.6% by mass or less is still more preferable. The lower limit thereof is preferably 0.00001% by mass or greater, more preferably 0.001% by mass or greater, still more preferably 0.01% by mass or greater, and particularly preferably 0.1% by mass or greater.

{0037}

Among the above, with respect to the embodiment of 1%» by mass or less, suppression of foaming is emphasized. In other embodiments, the content is preferably set as described above from the viewpoints of solubility or removability of silicon oxide in addition to the foaming.

{0038}

The total carbon number of R (the total carbon number of R¹, R² and R³ which are contained in the molecule thereof) is, in formula (1), preferably from 1 to 6, more preferably from 1 to 4, and particularly preferably 1 or 2, in terms of the carbon number for R¹, from the viewpoint that the anionic compound can be more highly concentrated. In formula (2) (including formula (2-1) and formula (2-2)), the total carbon number of R² is preferably from 0 to 5, more preferably from 0 to 4, and particularly preferably from 0 to 2. The total carbon number of R is preferably from 1 to 30, more preferably from 1 to 20, and particularly preferably from 5 to 20. Due to highly-concentrated components of the chemical liquid, preferably its activity is hard to be reduced even when it is continuously used.

{0039}

These anionic compounds may be used singly as one compound, or by mixing compounds of two or more kinds.

In the present invention, the reason why the anionic compound exhibits such effects is not clear. However, it is thought that due to interaction between its hydrophilicity and hydrophobicity, the anionic compound favorably adsorbs to the surface of the impurity-containing silicon layer, which results in prevention from contact with hydrofluoric acid, thereby enabling corrosion inhibition of the above- described silicon layer. At this moment, a possibility of forming a favorable adsorption state with a layer surface of more "basic" compound is suggested, and it is presumed that an excellent effect is exhibited by suppression and prevention of bimetallic corrosion.

{0040}

(Aqueous medium)

The etching liquid of the present invention is preferably an aqueous solution in which water is used as a medium and each of components contained therein is uniformly dissolved. The content of water (aqueous medium) is preferably from 10 to 99.5% by mass and more preferably from 15 to 99% by mass, with respect to the total mass of the etching liquid. Thus, in a case where a composition is composed primarily of water (50% by mass or more), the composition is preferable in terms of more inexpensive and more adaptable to the environment, compared to a composition with a high ratio of an organic solvent. The water (aqueous medium) may be an aqueous medium containing components dissolved therein in an amount by which the effects of the present invention are not deteriorated, or may contain inevitable microscopic amount of mixed components. Especially, distilled water or an exchanged water, or water which has been subjected to a purifying process, such as ultrapure water is preferable and the ultrapure water which is used for production of the semiconductor is particularly preferable.

{0041 }

(Hydrofluoric acid compound)

A hydrofluoric acid compound is defined as a compound which means a compound generating a fluorine ion (F-) in a system, examples of which include fluoric acid (hydrofluoric acid) and salts thereof. Specifically, examples of the fluoric acid compound include fluoric acid, alkali metal fluoride (NaF, KF, and the like), amine hydrofluoride (monoethylamine hydrofluoride, triethylamine trihydrofluoride, and the like), pyridine hydrofluoride, ammonium fluoride, quaternary alkyl ammonium fluoride (tetramethyl ammonium fluoride, tetra n-butyl ammonium fluoride, and the like), H₂SiF₆, HBF₄ and HPF₆. Among them, fluoric acid, amine hydrofluoride

(monoethylamine hydrofluoride, triethylamine trihydrofluoride, and the like), pyridine hydrofluoride, ammonium fluoride, quaternary alkyl ammonium fluoride (tetramethyl ammonium fluoride, tetra n-butyl ammonium fluoride, and the like), H₂SiF₆, HBF₄ and HPF₆ are preferably, fluoric acid, ammonium fluoride, quaternary alkyl ammonium fluoride (tetramethyl ammonium fluoride), H₂SiF₆, HBF₄ and HPF₆ are more preferably, fluoric acid is particularly preferred.

{0042}

The hydrofluoric acid compound is preferably incorporated within the amount of at least 0.01% by mass, more preferably incorporated in an amount of at least 0.05% by mass, and particularly preferably incorporated in an amount of at least 0.1% by mass, with respect to the total mass of the etching liquid according to the present embodiment. The upper limit thereof is preferably 20% by mass or less, more preferably 10% by mass or less, and particularly preferably 3% by mass or less. When the content is controlled to the above-described upper limit or less, etching of the silicon layer can be preferably suppressed. When the content is controlled to the above-described lower limit or more, a silicon oxide layer can be preferably etched at a velocity sufficient to do it.

In the present specification, when the name of a chemical is called by putting the term "compound" at the foot of the chemical name, or when the chemical is shown by a specific name or a chemical formula, a showing of the compound is used to mean 3 not only the compound itself, but also a salt or ion thereof and the like. Further, the showing of the compound is also used to mean incorporation of derivatives modified by a predefined configuration to an extent necessary to obtain a desired effect. Further, in the present specification, a substituent (including a linking group) in which substitution or non-substitution is not explicitly stated means that the substituent may have any substituent.

{0043}

• Water-soluble organic solvent

In the etching liquid used of the present invention, further a water-soluble organic solvent may be added thereto. The term "water-soluble organic solvent" means an organic solvent that can be mixed with water in an arbitrary proportion. This is effective at capability of improving in-plane uniform etching property of the wafer.

Examples of the water-soluble organic solvent include: alcohol compound solvents, such as methyl alcohol, ethyl alcohol, 1 -propyl alcohol, 2-propyl alcohol, 2- butanol, ethylene glycol, propylene glycol, glycerol, 1,6-hexanediol, cyclohexanediol, sorbitol, xylitol, 2-methyl-2,4-pentanediol, 1 ,3-butanediol, and 1,4-butanediol; ether compound solvents, such as an alkylene glycol alkyl ether including ethylene glycol monomethyl ether, ethylene glycol monobuthyl ether, diethylene glycol, dipropylene glycol, propylene glycol monomethyl ether, diethylene glycol monomethyl ether, triethylene glycol, poly(ethylene glycol), dipropylene glycol monomethyl ether, tripropylene glycol monomethyl ether, and diethylene glycol monobutyl ether.

Among these solvents, preferred are alcohol compound solvents having 2 to 15 carbon atoms and ether compound solvents having 2 to 15 carbon atoms (preferably ether compound solvents containing a hydroxyl group). More preferred are alcohol compound solvents having 2 to 10 carbon atoms and at least 2 hydroxyl groups and ether compound solvents having 2 to 10 carbon atoms and at least 2 hydroxyl groups (preferably ether compound solvents containing a hydroxyl group). Especially preferred are alkyleneglycol alkylethers having 3 to 8 carbon atoms. The water-soluble organic solvent may be used singly or appropriately in combination of two or more kinds. In the present specification, a compound having a hydroxyl group (-OH) and an ether group (-0-) in the molecule thereof shall be included in the category of the ether compound in principle (not called as the alcohol compound). When a compound having both a hydroxyl group and an ether group is mentioned in particular, the compound may be preferably called as "hydroxyl group-containing ether compound".

The water-soluble organic solvent can preferably be the compounds represented in following formula (O- 1 ).

Rⁿ-(-0-R¹³-)n-0-R¹² - - - (O-l)

1 1 12

R and R" are, respectively and dependently, a hydrogen atom or an alkyl group having carbon number of 1 to 5. R is liner or branched alkyl ene group having

13

carbon number of 1 to 4. A plurality of R can be respectively differed, n is integer of 1 to 6.

Especially among these compounds, propyleneglycol and dipropyleneglycol are preferable, more preferably dipropyleneglycol. The addition amount thereof is preferably from 0.1 to 70% by mass and more preferably from 10 to 50% by mass, with respect to the total mass of the etching liquid. By setting the addition amount to the above-described lower limit or greater, improvement in uniformity of the above- described etching can be effectively realized.

{0044}

(Antifoamer)

Examples of the antifoamer (antifoaming agent) which is applicable to the etching liquid include the above-described water-soluble organic solvent and a silicone compound. As for the content of the antifoamer, when the antifoamer is a water-soluble organic solvent (for example, alkyleneglycol ether) or a silicone compound, it is preferably incorporated in a range of from 0.00001 to 3% by mass, more preferably from 0.0001 to 1% by mass, and still more preferably from 0.001 to 0.1% by mass, with respect to the total mass of the etching liquid of the present embodiment. When the antifoamer is a water-soluble organic solvent, the antifoamer is preferably incorporated in a range of from 10 to 90% by mass, more preferably from 20 to 85% by mass, and still more preferably from 30 to 80% by mass, with respect to the total mass of the etching liquid of the present embodiment. By incorporation of the antifoamer in this amount, inhibition of etching due to bubbles which generate at the time of etching is prevented and, as a result, etching resistance properties of the conductivity type impurity-containing silicon layer are preferably enhanced.

{0045}

{pH}

The pH of the etching liquid according to the present invention, although it is not particularly limited, is preferably 5 or less, more preferably 4.5 or less, and particularly preferably 4 or less. The lower limit thereof is not particularly limited, but the pH of 1 or greater is practical. By setting the pH of the etching liquid to this range, a good balance between a good etching rate of the silicon oxide layer and a protective effect of the impurity-containing layer can be preferably achieved.

{0046}

The concentration of each component in the above-described etching liquid is suitable for use at the time of etching processing, but in preservation, distribution and the like, the etching liquid may be kept as a stock solution which is a concentrate of the etching liquid. The concentration rate, although it may be determined as appropriate, is preferably from 2 to 20 times. As for the concentration of the concentrated stock solution, a hydrofluoric acid compound is preferably from 0.1 to 50% by mass, and more preferably from 1 to 30% by mass. The anionic compound is preferably from 0.001 to 95% by mass, and more preferably of from 0.01 to 85% by mass.

{0047}

{Kit}

The etching liquid of the present invention may be constituted as a kit in which the raw materials thereof are divided into multiple parts. Examples of the kit include an embodiment in which, as a first liquid, a liquid composition in which the above- described anionic compound is contained in a water medium is prepared, and, as a second liquid, a liquid composition in which the above-described hydrofluoric acid compound is contained in a water medium is prepared. As an example of the use thereof, preferred is an embodiment in which both liquids are mixed to prepare an etching liquid, and after that, the etching liquid is applied to the above-described etching process on a timely basis. This avoids it from raising deterioration of the liquid properties due to decomposition of each components whereby a desired etching function can be effectively exhibited. The composition and the like of the first liquid and the second liquid in the kit are the same as those described above.

{0048}

(Container)

The etching liquid of the present invention (whether it is a kit or not) can be stored, transported and used by filling it into an arbitrary container, as far as corrosion resistance properties and the like are not concerned. Further, it is preferred for semiconductor application that the container has high cleanness and less elution properties of impurities from the container. Examples of usable containers include "Clean Bottle" series, manufactured by AICELLO CHEMICAL CO., LTD., and "Pure Bottle", manufactured by KODAMA PLASTICS Co., Ltd. The present invention is not limited to these.

{0049}

(Workpiece material)

Any of a structure, a shape, a size and the like of a semiconductor substrate product to be processed is not particularly limited. However, in the production process of insulated gate field effect transistor which forms an extension layer and source/drain using a dummy gate, a dummy film and a sidewall, as described above, it is preferable to determine the structure, the shape, the size and the like so that high effect is obtained in etching of the dummy film after removal of the dummy gate in particular.

The production method and the etching liquid of the present invention is not only applied to the above-described production process, but also can be used for various kinds of etching without any particular limitation.

{0050}

(Etching method)

The etching equipment used in the present invention is not particularly limited, but single wafer type etching equipment or batch type etching equipment can be used. Single wafer type etching is a method of etching the wafers one by one. One embodiment of the single wafer etching is a method of causing the etching liquid spread to the whole surface of the wafer by a spin coater.

Liquid temperature of the etching liquid, discharge rate of the etching liquid and rotation speed of the wafer of the spin coater are used to select the appropriate value by the choice of substrate to be etched.

{0051 }

In the present embodiment, although the etching condition is not particularly limited, the single wafer type etching is preferred. In the single wafer type etching, semiconductor substrates are transported or rotated in the predetermined direction, and an etching liquid is discharged (spray, falling, drop) in a space among them to put the etching liquid on the semiconductor substrate. According to the necessity, etching liquid may be sprayed while rotating the semiconductor substrate using a spin coater. On the other hand, in the batch-type etching, a semiconductor substrate is immersed in a liquid bath composed of an etching liquid, thereby bringing the semiconductor substrate into contact with the etching liquid in the liquid bath. It is preferred that these etching types be appropriately used depending on structures, materials and the like of the element.

{0052}

An environmental temperature of etching is described below. In the case of the single wafer type, the temperature of the spraying interspace for etching is set to a range of preferably from 15 to 40°C, and more preferably from 20 to 30°C. On the other hand, the temperature of the etching liquid is preferably set from 15 to 40°C, and more preferably from 20 to 30°C. It is preferable to set the temperature to the above- described lower limit or more because an adequate etching rate with respect to a silicon oxide layer can be ensured by the temperature. It is preferable to set the temperature to the above-described upper limit or less because selectivity of etching can be ensured by the temperature. The supply rate of the etching liquid is not particularly limited, but is set to a range of preferably from 0.3 to 3 L/min, and more preferably from 0.5 to 2 L/min. It is preferable to set the supply rate to the above-described lower limit or more because uniformity of etching in a plane can be ensured by the supply rate. It is preferable to set the supply rate to the above-described upper limit or less because stable selectivity at the time of continuous processing can be ensured by the supply rate.

When the semiconductor substrate is rotated, it is preferable from the same view point as the above to rotate the semiconductor substrate at a rate from 100 to 1,000 rpm, even though the rate may depend on the size or the like of the semiconductor substrate. {0053}

(Chemical liquid supply system and temperature regulation)

In the present invention, although the temperature-regulated chemical liquid supply line system is not particularly limited, preferable examples thereof are described below. The term "temperature regulation" herein used refers to maintaining the chemical liquid at a predetermined temperature. Ordinarily, the chemical liquid is maintained by heating at a predetermined temperature.

Examples of chemical supply line

(1) (a) Chemical storage tank→ (b) Temperature-regulating tank→ (c) Inline temperature regulation→ (d) Ejection to wafer→ Return to (a) or (b).

(2) (a) Chemical liquid tank→ (b) Temperature-regulating tank→ (d) Ejection to wafer → Return to (a) or (b).

(3) (a) Chemical liquid tank→ (c) Inline temperature regulation→ (d) Ejection to wafer→ Return to (a)

(4) (a) Chemical liquid tank→ (b) Temperature-regulating tank→ (e) Etching bath (Circulation temperature regulation).

(5) (a) Chemical liquid tank— > (e) Etching bath (Circulation temperature regulation).

(6) (b) Temperature- regulating tank→ (d) Ejection to wafer→ Return to (b).

(7) (b) Temperature-regulating tank→ (c) Inline temperature regulation→ (d) Ejection to wafer→ Return to (b).

(8) (b) Temperature-regulating tank→ (e) Etching bath (Circulation temperature regulation). The above methods are used.

{0054}

The chemical liquid already used in the method of the present invention can be re-used by circulation. Preferable method is not "free-flowing" (without re-use), but reuse by circulation. It is possible to continue circulation for 1 hour or longer after heating, which makes it possible to perform a repetitive etching. Although there is no particular upper time limit of the circulating-reheating, exchange within a week is preferable because etching rate deteriorates with age. The exchange within 3 days is more preferable. An exchange to a flesh liquid once a day is particularly preferable. In the etching of the above-described line system, the measurement position of the temperature-regulated temperature may be determined appropriately by the relation to a line configuration or a wafer. Typically, the measurement position is regulated by adjusting the tank temperature. In the case where relatively more strict conditions in terms of performance are required, wherever the measurement and the regulation are feasible, the temperature-regulated temperature may be defined by a wafer surface temperature. In this case, temperature measurement is conducted using a radiation thermometer.

{0055}

The underlayer in the preferable embodiment of the present invention is a silicon layer having a p-type impurity layer and an n-type impurity layer, or a silicon layer having a p-type impurity layer and an n-type impurity layer and further incorporating therein germanium or carbon. The silicon layer herein used typically refers to one single crystal grain of a single crystal silicon layer or a polycrystal silicon layer. The single crystal silicon layer refers to a silicon crystal in which orientation of the atomic arrangement is aligned throughout the crystal. In fact, however, when observed at the atomic level, the presence of various defects is found. Further, the p- type impurity layer refers to a layer in which p-type impurities (for example, B⁺, BF²⁺ and the like) are doped in the above-described silicon layer. On the other hand, the n- type impurity layer refers to a layer in which n-type impurities (for example, P⁺, As⁺, Sb⁺ and the like) are doped in the above-described silicon layer.

A layer to be etched in the present embodiment refers to a layer containing silicon and oxygen as constituent elements. Specifically, the layer to be etched is composed of silicon dioxide (Si0₂), a silicon dioxide derivative of which Si has a dangling bond, a silicon dioxide derivative in which a dangling bond of Si combines with hydrogen, or the like. Further, the other elements may be incorporated therein, for example, germanium or carbon may be incorporated therein.

On the other hand, the etching liquid for silicon oxide according to a preferable embodiment of the present invention makes it possible to remove a layer to be etched of a silicon oxide or a germanium or carbon-containing silicon oxide, by etching it without causing galvanic corrosion, even in the case where a silicon layer having different conductive type impurity layers is disposed as a ground. {0056}

In the present specification, the term "semiconductor substrate" is not only used to mean a silicon substrate (wafer), but also used in a broader meaning that includes a whole substrate structure on which a circuit structure is provided. The semiconductor substrate member refers to a member that constitutes the above-defined semiconductor substrate, and may be composed of a single material or a plurality of materials. The processed semiconductor substrate may be called a semiconductor substrate product in order to distinguish it from a pre-processed semiconductor substrate. For further discrimination, if needed, a chip picked up by singulation after a processing of the semiconductor substrate product, and a chip processed product are called a semiconductor element or semiconductor device. That is, in a broad sense, the semiconductor element (semiconductor device) belongs to the semiconductor substrate product. The direction of the semiconductor substrate is not particularly limited.

However, for convenience of description, in the present specification, the side of sidewall 21 is specified as upside (upper side), while the side of substrate 1 1 is specified as lower side (bottom side). The structure of the semiconductor substrate or its members is illustrated in the attached figures by simplifying them. Accordingly, they should be interpreted as an appropriate form, as needed. EXAMPLES

{0057}

The present invention will be described in more detail based on examples given below, but the invention is not meant to be limited by these.

(Example 1 and Comparative example 1)

Etching liquids having the components and the composition (% by mass) of each of the test Nos. shown in Table 1 below were prepared.

{0058}

First substrate: Boron doping was conducted to a bare wafer composed of a single crystal <100> silicon substrate by ion implantation under the conditions of the dose amount of 3>< 10¹⁴ atom/cm² and the implantation energy of 210 keV. 1

Second substrate: Boron doping was conducted to a bare wafer composed of a single crystal <100> silicon substrate by ion implantation under the conditions of the dose amount of 3 χ 10¹⁴ atom/cm² and the implantation energy of 210 keV. Then, arsenic doping was also conducted thereto by ion implantation under the conditions of the dose amount of 5 χ 10¹⁵ atom/cm² and the implantation energy of 210 keV.

As for the evaluation test, potential measurement of each substrate was conducted using a potentiostat (VersaSTAT 3 (trade name), manufactured by Princeton Applied Research) to obtain a potential difference between the first substrate and the second substrate. The measuring temperature was set to 25°C. As for the electrolyte used for measurement, etching liquids shown in Table lwere used. The counter electrode of the potentiostat is platinum, and the standard electrode is silver/silver chloride electrode.

{0059}

The pattern shown in the above-mentioned Fig. 1 (process a) and produced by the production method described in the above embodiment was prepared

Using a single crystal <100> silicon substrate as a substrate, ion implantation of boron into the substrate under the conditions of dose amount of 3* 10¹⁴ atom/cm² and implant energy of 210KeV was conducted to form a channel dope layer. Further, in order to form extension layers, ion implantation of arsenic was conducted under the conditions of dose amount of 1.0x 10¹⁵ atom/cm² and implant energy of 3KeV.

A silicon nitride film was used for a sidewall, and a Si0₂ film was used for a dummy film.

The substrate having the above-described dummy film and sidewall formed thereon was etched under the following conditions using single wafer equipment (POLOS (trade name), manufactured by SPS-Europe B.V.).

(Etching condition)

• Temperature of chemical liquid: 25°C

• Discharge rate: 2 L/min.

· Wafer rotation number: 500 rpm

After etching, rinse with water and then drying was conducted. {0060}

(Temperature T (wafer) measuring method)

The above-described chemical liquid temperature was measured as follows. A radiation thermometer IT-550F manufactured by HORIBA Ltd. was fixed at the height of 30cm from a wafer in the single wafer equipment. Temperature was measured while flowing the chemical liquid in a manner such that the thermometer was pointed to a wafer surface at the distance of 2cm outside from the center of the wafer. The temperature was output digitally from the radiation thermometer and recorded using a personal computer. With respect to the timing of measurement, because an initial temperature of the etching treatment is heading for an upturn, and thereafter the temperature becomes lower, an average value of the temperature for the last- 10 seconds of the treatment time as a sufficiently stable timing was defined as a temperature on the wafer.

{0061 }

Evaluation was conducted in terms of removal property of a Si0₂ film on the channel dope layer and existence or non-existence of the void of the extension layer. In either evaluation, cross-section observation of the extension layer was visually performed using TEM. The removal rate was evaluated using a ratio of areas of the extension layer before and after the treatment.

(Removal property of Si0₂ film)

Evaluation of the removal property of the Si0₂ film was conducted by way categorizing the removal rate as follows.

A: Removal rate was 100%.

B: Removal rate was from 80% to less than 100%

C: Removal rate was from 50% to less than 80%

D: Removal rate was less than 50%

(Existence or non-existence of void)

Evaluation of void was performed by determining if a void generated in the extension layer, and the case where the void generated was expressed by "existence", while the case where no void generated was expressed by "None-existence". {0062}

(Measurement of pH)

The pH shown in the table is a value that was obtained by measuring the etching liquid at room temperature (25°C) using F-51 (trade name), manufactured by HORIBA, Ltd.

{0063} Table 1

Table 1 -continued

{0064}

As seen from the above-described results, according to the production method and the etching liquid each of which is the present invention, selective etching of the layer to be etched that is composed of a Si0₂ layer was achieved with respect to the underlayer composed of the silicon layers having the p-type impurity layer (boron) and the n-type impurity layer (arsenic) without excessive etching against the underlayer. In view of this, it is seen that in the production process of MIS transistors having a step of forming a gate insulator film and a gate electrode by removing a dummy gate and a dummy film, application of the method of the present invention especially to the step of removing the dummy film is extremely effective and exhibits excellent effects.

{0065}

Further, despite differences in conditions of the substrate, good performances have been achieved. In view of this, it is seen that the present invention enables efficient and generic process with a less dependency on substrates.

{0066}

(Example 2 and Comparative example 2)

Evaluation of each item was conducted in the same manner as Example 1, except that a semiconductor substrate incorporating carbon or germanium in a silicon layer as an underlayer thereof was prepared. As a result, it was confirmed that the production method and the etching liquid each of which is the present invention exhibit equally excellent effects as Example 1.

{0067}

(Example 3 and Comparative example 3)

Antifoamers having components and compositions (mass%) described below were added to the above-described etching liquids containing water, the hydrofluoric acid compound and the anionic compound to prepare etching liquids (test liquids). As for the following addition amounts, concentrations of the components incorporated in final chemical liquids were indicated.

Dl : Surfynol 440; addition amount: 0.01 mass% (manufactured by Air Products, acetylene alcohol)

D2: Surfynol DF1 10D; addition amount: 0.01 mass% (manufactured by Air Products, acetylene alcohol)

D3: Ethylene glycol; addition amount: 50 mass%

D4: Ethylene glycol monomethyl ether; addition amount: 50 mass%

D5: Ethylene glycol monobutyl ether; addition amount: 50 mass%

D6: Propylene glycol monomethyl ether; addition amount: 50 mass%

{0068}

The test of antifoaming property was conducted by placing 5 mL of a test liquid in a stoppered test tube having approximately 15 mm of inner diameter and approximately 200mm of length, and then mixing it by shaking vigorously for 3 minutes, and then an elapsed time until the generated bubbles almost had disappeared was measured. A stopwatch was used for time measurement.

{0069}

In the result of the test of antifoaming property, with respect to all the embodiments where any one of the antifoamers Dl to D6 was used in the 101 to 104 chemical liquids shown in Table 1, bubbles disappeared within 5 seconds. On the other hand, foaming which continues for 5 seconds or more was confirmed in etching liquids containing water, the hydrofluoric acid compound and the anionic compound, but not containing the antifoamer. With respect to any of the 101 to 104 chemical liquids, the same results were obtained.

{0070}

Further, in the chemical liquid containing a solvent, suppression of the corrosion current of each film was already achieved. Measurement conditions were the same as those of the above-described electrochemical measurement. With respect to any of the 101 to 104 chemical liquids, the same results were obtained.

{0071 }

(Example 4)

Etching tests were conducted in the same manner as Example 1, except that the chemical liquids were changed as shown in the following Table 2. Each of the Test Nos. 101 A to 104A and 108 A means that the chemical liquid having the same formulation as each of 101 to 104 and 108 shown in Table 1 was used respectively.

{0072}

To the present Example 4, the following test of antifoaming property was added. The other tests are the same as Example 1.

A: less than 30 seconds

B: from 30 seconds to less than 2 minutes

C: 2 minutes or more {0073}

Table 2

*: Total number of carbon atoms of R to R in formulae (1) to (3)

„_Λ

Table 2-continued

{0074}

From the above results, it is seen that by suitably adjusting both the structure and the content of the anionic compound, high antifoaming effect is achieved while maintaining a good etching property. Further, by suppressing the foaming of the chemical liquid, an operational glitch of the equipment can be prevented.

{0075}

In the case where 40 L of the chemical liquid was used in cycle, the

performance of the No. 406 chemical liquid (anionic compound concentration: 22% by mass) after processing of 1,000 sheets of 12 inch wafers was same as before. In contrast, with respect to the No.108 chemical liquid (anionic compound concentration: 0.3% by mass), a slight increase in the potential difference was observed (0.05V→ 0.10V).

From this result, it is seen that the No.406 chemical liquid has a long life as compared with the No.108 chemical liquid.

{0076}

Having described our invention as related to the present embodiments, it is our 4 intention that the invention not be limited by any of the details of the description, unless otherwise specified, but rather be construed broadly within its spirit and scope as set out in the accompanying claims.

{0077}

This application claims priorities on Patent Applications No. 2012-283429 filed in Japan on December 26, 2012 and No. 2012-179042 filed in Japan on August 10, 2012 which are entirely herein incorporated by reference.

REFERENCE SIGNS LIST

{0078}

1 1 Silicon substrate

12 Well

13 Channel dope layer

14 Dummy film

15 and 16 Extension layers

17 and 18 Halo layers

19 Source

20 Drain

21 Sidewall

22 Interlayer insulation layer

v Void (depression)

Claims

1. A method of producing a semiconductor substrate product, comprising the steps of:

providing a semiconductor substrate having two or more impurity-containing silicon layers and a silicon oxide layer, each of the impurity-containing silicon layers containing a different impurity from one another;

applying an etching liquid onto the semiconductor substrate, the etching liquid comprising water, a hydrofluoric acid compound, and an anionic compound; and

selectively etching the silicon oxide layer.

2. The method of producing a semiconductor substrate product as according to Claim 1 , wherein the hydrofluoric acid compound in the etching liquid has a concentration from 0.01 mass% to 10 mass%.

3. The method of producing a semiconductor substrate product according to Claim 1 or 2, wherein the anionic compound in the etching liquid has a concentration from 0.00001 mass% to 85 mass%.

4. The method of producing a semiconductor substrate product according to any one of Claims 1 to 3, wherein the anionic compound is a compound represented by any one of formulae (1) to (3):

R> Ac_n (1) _R3_{h Ar}__{0 Ar}

R² _m— Ar— Ac_n (2) ACj Ac_k (3)

1 3

wherein R to R each independently represent an alkyl group or an alkenyl group; Ar represents an aromatic ring; Ac represents -S0₃M or -COOM; M represents a hydrogen atom or a cation; n represents an integer of 1 to 3; m represents an integer of 0 to 3; h represents an integer of 1 to 3; j represents 0 or 1; k represents 0 or 1; and the total of j and k is 1 or 2.

5. The method of producing a semiconductor substrate product according to Claim 4, wherein the anionic compound represented by formula (2) is a compound represented by formula (2-1) or (2-2):

(2-1 ) (2-2)

6. The method of producing a semiconductor substrate product according to Claim 4 or 5,

from 40 mass% to 85 mass%, when R¹ has 1 to 2 carbon atom(s) in formula

(i);

from 20 mass% to 85 mass%, when R¹ has 3 to 5 carbon atoms in formula (1); from 0.1 ppm in terms of mass standard to 1 mass%, when R¹ has 6 or more carbon atoms in formula (1);

from 0.1 ppm in terms of mass standard to 1 mass%, when R² has 5 or more carbon atoms in total in formula (2-1);

from 0.1 ppm in terms of mass standard to 1 mass %, when R² has 3 or more carbon atoms in total in formula (2-2).

7. The method of producing a semiconductor substrate product according to any one of Claims 1 to 6,

wherein the anionic compound is an alkylbenzene sulfonic acid, an alkylnaphthalene sulfonic acid, an alkyldiphenylether disulfonic acid, or a salt thereof.

8. The method of producing a semiconductor substrate product according to any one of Claims 1 to 7,

9. The method of producing a semiconductor substrate product according to any one of Claims 1 to 8,

10. The method of producing a semiconductor substrate product according to any one of Claims 1 to 9,

1 1. The method of producing a semiconductor substrate product according to any one of Claims 1 to 10,

the impurity-containing silicon layer comprises at least boron as an impurity.

12. The method of producing a semiconductor substrate product according to any one of Claims 1 to 11,

wherein the impurity-containing silicon layer comprises at least phosphorus or arsenic as an impurity.

13. An etching liquid, comprising:

water; a hydrofluoric acid compound; and

an anionic compound,

14. The etching liquid according to Claim 13,

wherein the hydrofluoric acid compound has a concentration from 0.01 mass% to l0 mass%.

15. The etching liquid according to Claim 13 or 14,

16. The etching liquid according to any one of Claims 13 to 15, wherein the anionic compound is a compound represented by any one of formulae (1) to (3) :

R¹ Ac_n (1) _R3_{h Ar}__{0 Ar}

R² _m Ar— Ac_n (2) ^Α¾ Ac_k (3)

wherein R¹ to R³ each independently represent an alkyl group or an alkenyl group; Ar represents an aromatic ring; Ac represents -S0₃M or -COOM; M represents a hydrogen atom or a cation; n represents an integer of 1 to 3; m represents an integer of 0 to 3; h represents an integer of 1 to 3; j represents 0 or 1 ; k represents 0 or 1; and the total of j and k is 1 or 2.

17. The etching liquid according to Claim 16, wherein the anionic compound represented by formula (2) is a compound represented by formula (2-1) or (2-2):

(2-1 ) (2-2)

18. The etching liquid according to Claim 16 or 17,

from 40 mass% to 85 mass%, when R¹ has 1 to 2 carbon atom(s) in formula

(i);

from 0.1 ppm in terms of mass standard to 1 mass %, when R² has 5 or more carbon atoms in total in formula (2-1);

19. A method of producing a semiconductor substrate product, comprising the steps of:

preparing a silicon substrate having a p-type impurity layer, an n-type impurity layer, and a silicon oxide layer in the state of the layers each capable of being exposed on the surface of the silicon substrate, each of the p-type impurity layer and n-type impurity layer being an impurity-doped layer of silicon;

20. A method of producing a semiconductor element, comprising the steps of: producing a semiconductor substrate product through the processes recited in any one of Claims 1 to 12 and 19; and

producing the semiconductor element by using the same.