EP2870278A1 - Substrate comprising a layer of silicon and/or germanium and one or a plurality of nanowires oriented perpendicular to the surface of the substrate - Google Patents
Substrate comprising a layer of silicon and/or germanium and one or a plurality of nanowires oriented perpendicular to the surface of the substrateInfo
- Publication number
- EP2870278A1 EP2870278A1 EP13744670.4A EP13744670A EP2870278A1 EP 2870278 A1 EP2870278 A1 EP 2870278A1 EP 13744670 A EP13744670 A EP 13744670A EP 2870278 A1 EP2870278 A1 EP 2870278A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- layer
- silicon
- germanium
- monocrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 189
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 115
- 239000010703 silicon Substances 0.000 title claims abstract description 115
- 239000002070 nanowire Substances 0.000 title claims abstract description 106
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 102
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 102
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 113
- 229910052751 metal Inorganic materials 0.000 claims description 76
- 239000002184 metal Substances 0.000 claims description 76
- 238000002425 crystallisation Methods 0.000 claims description 35
- 230000008025 crystallization Effects 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 26
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000007787 solid Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000004630 atomic force microscopy Methods 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- 229910005540 GaP Inorganic materials 0.000 claims description 2
- 229910005542 GaSb Inorganic materials 0.000 claims description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 2
- 229910002059 quaternary alloy Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910002058 ternary alloy Inorganic materials 0.000 claims description 2
- 230000012010 growth Effects 0.000 description 62
- 239000000463 material Substances 0.000 description 15
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 229910052787 antimony Inorganic materials 0.000 description 6
- 238000004581 coalescence Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000001341 grazing-angle X-ray diffraction Methods 0.000 description 4
- 239000011133 lead Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000004627 transmission electron microscopy Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910017817 a-Ge Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229920001940 conductive polymer Polymers 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000005350 fused silica glass Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000399 optical microscopy Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000004626 scanning electron microscopy Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910002796 Si–Al Inorganic materials 0.000 description 1
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 230000003698 anagen phase Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000001887 electron backscatter diffraction Methods 0.000 description 1
- 238000002003 electron diffraction Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000009304 pastoral farming Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001350 scanning transmission electron microscopy Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B1/00—Single-crystal growth directly from the solid state
- C30B1/02—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
- C30B1/023—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing from solids with amorphous structure
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
- C30B23/025—Epitaxial-layer growth characterised by the substrate
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/08—Germanium
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- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
- C30B29/605—Products containing multiple oriented crystallites, e.g. columnar crystallites
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/068—Nanowires or nanotubes comprising a junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
Definitions
- the present invention relates to a substrate comprising a continuous or discontinuous layer of silicon and / or germanium consisting of one or more monocrystalline grains, and on this layer, one or more nanowires whose longitudinal axis is oriented perpendicularly to the surface. of the substrate.
- the invention also relates to a method of manufacturing such a substrate.
- Nanowires oriented perpendicular to the surface of a substrate have remarkable properties vis-à-vis the phenomena of transport and electronic or optical confinement.
- the orthogonality of the growth of nanowires with respect to the surface of a substrate is of great interest because this feature facilitates not only their insertion in electronic devices, but also optical or optoelectronic.
- a glass substrate comprising a crystallized silicon layer on which is deposited an insulating layer having openings serving as growth zones of the nanowires.
- the crystallized silicon layer comprises monocrystalline grains defined by grain boundaries.
- the vertical growth of the nanowires is made possible by the choice of a surface size to delimit the areas of growth below the surface of each monocrystalline silicon grain.
- This document discloses that out of 28 openings, 10 are facing a grain edge. Through these 10 apertures, 8 nanowires grow vertically but with a smaller diameter than the nanowires growing in apertures not including a grain edge and 2 openings do not lead to nanowire growth.
- the crystallized silicon layer has a thickness of between 10 and 100 nm, preferably 50 nm.
- the monocrystalline grains have an average lateral dimension of 200 nm to about 1 ⁇ .
- the only crystallization process of the silicon layer described in this document is laser annealing. No indication is given on the surface roughness of such a crystallized silicon layer.
- a deviation from normal to the substrate (or surface) more or less important can be observed and attributed to various causes such as the intrinsic roughness of the substrate or an inclination of monocrystalline grains on the substrate reverberating on the growth of nanowires.
- the present invention relates to the manufacture of vertical nanowires on various substrates which may be amorphous or have a crystalline orientation other than the orientation suitable for vertical growth, or even on substrates incompatible with the growth of nanowires, obtained by a method which is simple to use. enforce.
- substrates which may be amorphous or have a crystalline orientation other than the orientation suitable for vertical growth, or even on substrates incompatible with the growth of nanowires, obtained by a method which is simple to use. enforce.
- the applicants have developed a substrate:
- the invention therefore relates to a substrate comprising on at least a portion of one of its surfaces a layer of silicon and / or germanium of thickness E consisting of one or more monocrystalline grains, all oriented so that they have planes (111) parallel to the surface of the substrate, and on this layer, one or more nanowires whose longitudinal axis is oriented perpendicular to the surface of the substrate characterized in that: the one or more monocrystalline grains of the silicon and / or germanium layer have a lateral dimension D, defined as a chord of the grain edge, on all grains strictly greater than 1 ⁇ , preferably greater than 2 ⁇ and at best greater than 5 ⁇ ,
- the ratio D / E between the lateral dimension D and the thickness of the layer of silicon and / or germanium is greater than 25, preferably 100.
- chord D a line segment joining two points of the outline of a grain.
- the lateral dimension of the grains can be measured by image processing obtained by any microscopic observation mode, direct or indirect, such as scanning electron microscopy, transmission electron microscopy, backscatter electron diffraction (Electron backscatter diffraction "), Atomic force microscopy and optical microscopy.
- this characteristic is considered to be satisfied when at least 80%, preferably at least 90%, better still at least 95% and even better 100% of the grains have at least one lateral dimension D greater than 1 ⁇ .
- the invention relates to a substrate comprising, on at least a part of one of its surfaces, one or more monocrystalline grains of non-joined silicon and / or germanium and all oriented so that they present planes (111) parallel to the surface of the substrate, and on each grain one or more nanowires whose longitudinal axis is oriented perpendicular to the surface of the substrate.
- non-contiguous monocrystalline grains are grains isolated from each other by a distance, preferably of at least 10 nm, the assembly thus forming a discontinuous layer.
- the invention also relates to a method of manufacturing a substrate comprising the following steps:
- the invention also relates to any device based on such a substrate and capable of in particular be chosen from light receiving or emitting elements such as photovoltaic solar cells, laser diodes, light emitting diodes, photocathodes or from electronic components such as bipolar transistors and metal-insulator-semiconductor (MIS) transistors. ).
- light receiving or emitting elements such as photovoltaic solar cells, laser diodes, light emitting diodes, photocathodes or from electronic components such as bipolar transistors and metal-insulator-semiconductor (MIS) transistors.
- a nanowire whose longitudinal axis is oriented perpendicular to the surface of the substrate corresponds to a nanowire pushing from the silicon and / or germanium layer in a direction perpendicular to the substrate.
- the nanowires of perpendicular orientation according to the invention form an angle at very close to 90 ° with respect to the surface of the substrate.
- the angle ⁇ may deviate from the value of 90 ° for example because of disorder, defects or stress during the growth of nanowires and monocrystalline grains.
- At least 90%, preferably at least 95%, better 100% of perpendicular orientation nanowires have an angle ⁇ with respect to the surface of the substrate of 90 ° ⁇ 10 °, preferably 90 ° ⁇ 5 ° or better 90 ° ⁇ 2.5 °.
- the epitaxy of the nanowires on the thin layer of silicon and / or intermediate germanium allows vertical growth of the nanowires, without contact or coalescence between them.
- the silicon and / or germanium layer consists of one or more monocrystalline grains with high lateral extension and low roughness.
- the monocrystalline grains are all oriented so that they have planes (111) parallel to the surface of the substrate although having extremely low thicknesses (of the order of ten nanometers). All of these characteristics contribute to obtaining excellent vertical growth of nanowires.
- the substrate of the invention does not require an insulating layer comprising openings serving as a growth zone to obtain the vertical growth of the nanowires.
- Another beneficial aspect of the invention lies in the fact that the advantageous properties of the silicon and / or germanium layer are obtained for thin layers.
- nanowires to be integrated in complex devices, must be connected to a conductive electrode.
- This electrode may therefore for example be a conductive layer deposited between the substrate and the silicon and / or germanium layer. The lower the thickness of the silicon and / or germanium layer, the less the conductivity through this layer will be obstructed and the easier it will be to connect the nanowires to the electrode.
- the manufacturing process which comprises the formation induced by a metal-induced crystallization ("Metal Induced Lateral Crystallization") of the layer of silicon and / or germanium consisting of one or more monocrystalline grains.
- the crystallization induced by a metal is obtained by depositing a metal layer above or below a layer of the material that it is desired to crystallize, that is to say a layer of silicon and / or or amorphous germanium.
- the metal layer may be a layer of a metal selected from aluminum (Al), silver (Ag), gold (Au), antimony (Sb), copper (Cu), nickel ( Ni) or lead (Pb).
- the layer of amorphous material (a-Si or a-Ge) crystallizes at a chosen temperature, sufficient and less than the temperature of the eutectic between the metal and the material to be crystallized.
- a-Si or a-Ge amorphous material
- Crystalline growth is achieved at the interface between the metal layer and the amorphous layer.
- the crystals formed fit and then grow in the metal layer.
- different stacks are obtained at the end of crystallization.
- the metal layer When one deposits successively on the substrate, the metal layer then the amorphous layer, one obtains, after crystallization, a substrate comprising a crystalline layer covered with a metal layer. To allow the growth of the nanowires, it is necessary to eliminate this metal layer.
- the layer of silicon and / or germanium consisting of one or more monocrystalline grains is formed below the metal layer, the latter is removed by selective etching.
- the aluminum layer can be etched completely and selectively by using a mixture of concentrated hydrochloric acid and nitric acid.
- the surface oxides of aluminum and / or silicon can also be etched for example with fluoridic acid (5%).
- the amorphous layer then the metal layer When one deposits successively on the substrate, the amorphous layer then the metal layer, one obtains, after crystallization, a layer of silicon and / or germanium consisting of one or more monocrystalline grains formed above the metal layer.
- the presence of this metal layer interposed between the substrate and the layer of silicon and / or germanium consisting of one or more monocrystalline grains is interesting because it can partially or completely provide an electrode function.
- the substrate may therefore comprise a metal layer, preferably aluminum, interposed between said substrate and the layer of silicon and / or germanium consisting of one or more monocrystalline grains.
- the choice of the metal used to catalyze the crystallization may give the silicon and / or germanium layer particular properties.
- the metal layer and the layer of silicon and / or amorphous germanium can be deposited by any conventional deposition methods such as chemical and physical vapor deposition.
- these layers are deposited by magnetic field assisted sputtering ("magnetron deposition").
- the grains can grow until they coalesce.
- the relative thickness of the deposited layers is a key parameter allowing or not the coalescence of the grains:
- the layer of crystallized materials forms a discontinuous layer
- the layer of crystallized materials forms a continuous layer
- the layer of crystallized material forms a continuous layer further comprising prominent islands.
- the silicon and / or germanium layer consisting of one or more monocrystalline grains may be continuous or discontinuous.
- thickness E is understood to mean the average thickness of the monocrystalline grains constituting it.
- the thickness of the silicon and / or germanium layer E is, in order of increasing preference, less than 50 nm, less than 40 nm, less than 30 nm, less than 20 nm, of between 5 and 15 nm.
- the roughness of the surface of the grain (s) constituting the silicon and / or germanium layer measured by the atomic force microscopy technique is less than 5 nm, preferably less than 2 nm, and better than 1 nm. According to the invention is called "roughness", the standard deviation of the relief of the upper surface of a monocrystalline grain, taken at the scale of the grain surface.
- the monocrystalline grains have a wafer shape whose edges are irregular.
- the monocrystalline grains may have various forms more or less elongated.
- the monocrystalline grain or grains of the continuous or discontinuous layer of silicon and / or germanium may have a lateral dimension D strictly greater than 1 ⁇ , preferably greater than 2 ⁇ .
- the silicon and / or germanium layer may be n or p doped.
- the layer of silicon and / or germanium consisting of one or more monocrystalline grains can be obtained by crystallization induced by antimony.
- the silicon and / or germanium layer further comprises antimony atoms and can be doped with antimony.
- an antimony layer may also be interposed between the substrate and the silicon and / or germanium layer.
- the silicon and / or germanium layer may be p-doped.
- the layer of silicon and / or germanium consisting of one or more monocrystalline grains is preferably obtained by crystallization induced by aluminum.
- the silicon and / or germanium layer furthermore comprises aluminum atoms and can therefore be doped with aluminum.
- an aluminum layer may also be interposed between the substrate and the silicon and / or germanium layer. According to the first embodiment, a continuous layer can be obtained when the grains grow until they coalesce. A discontinuous layer can also be obtained.
- a masking step consisting in depositing a layer above the substrate and for structuring openings in this layer before the step of depositing a metal layer above above or below a layer of silicon and / or amorphous germanium. This step makes it possible to selectively deposit the metal layer and the amorphous silicon and / or germanium layer in an ordered pattern on the substrate.
- the monocrystalline grain or grains advantageously have at least one of the following characteristics:
- the monocrystalline grains have a lateral dimension D greater than 2 ⁇ , preferably greater than 4 ⁇ and better still greater than 5 ⁇ ,
- the ratio D / E between the lateral dimension D and the thickness of the layer of silicon and / or germanium is in order of increasing preference greater than 50, greater than 100, greater than 200, greater than 400, greater than 500 ,
- the monocrystalline grain or grains have at least two lateral dimensions D1 and D2 perpendicular strictly greater than 1 ⁇ , preferably greater than 2 ⁇ , and better still greater than 5 ⁇ ,
- the ratio between the lateral dimensions D, D1 and / or D2 and the height H of the nanowires is greater than 1, preferably 2.
- the non-contiguous monocrystalline grains may also satisfy the characteristics defined above.
- the substrate comprises one or more monocrystalline grains of non-joined silicon and / or germanium, the assembly thus forming a discontinuous layer.
- This discontinuous layer consisting of non-contiguous monocrystalline grains can be obtained by adjusting the deposition parameters such as the thickness ratio between the metal layer and the layer of amorphous material or by decreasing the duration of the growth phase in order to prevent the coalescence of monocrystalline grains.
- the discontinuous layer consisting of non-contiguous monocrystalline grains can be obtained by adding, during the manufacturing process, a step of depositing a layer above the substrate and of a step of structuring apertures of controlled size in this layer before the deposition step, in the desired order, of a metal layer and a layer of silicon and / or amorphous germanium.
- This additional step makes it possible not only to selectively deposit the metal layer and the layer of amorphous silicon and / or germanium in a predetermined pattern on the substrate, but above all, by choosing nanometric openings, it is possible to obtain in each opening the growth of one and only one monocrystalline grain.
- the monocrystalline grains preferably have a predetermined pattern having a maximum lateral dimension of 100 nm.
- the monocrystalline grains may have larger lateral dimensions. This advantageous variant therefore makes it possible to obtain a substrate comprising one or more monocrystalline grains in a predetermined pattern.
- the grains preferably have a maximum lateral dimension of less than 5 ⁇ , preferably less than 2 ⁇ .
- the silicon and / or germanium layer may further comprise metal atoms selected from aluminum, silver, gold, antimony, copper, nickel, and lead. These atoms can come from the process for preparing the silicon and / or germanium layer comprising monocrystalline grains.
- the invention advantageously makes it possible to grow nanowires on any type of substrate.
- These substrates have at least a part of their flat surface, a sufficiently low surface roughness and a thermal compatibility with the conditions of the manufacturing process including melting points or sufficiently high glass transition temperatures.
- the substrates used according to the invention may be flat over the entire surface of the surface or locally on sections of the surface.
- a substrate comprising a texturing may be used according to the invention insofar as at least a portion of one of its surfaces corresponding to the area where it is desired to grow the nanowires is plane.
- the substrate may therefore be chosen from amorphous, inorganic or organic substrates, the solid crystalline substrates comprising an orientation incompatible with vertical growth of nanowires, in particular an orientation other than (111), or simply incompatible with the growth of the nanowires.
- amorphous substrate that is particularly suitable according to the invention, mention may be made of glass substrates.
- a solid crystalline substrate that is particularly suitable according to the invention, mention may be made of solid silicon substrates having in particular a crystalline orientation other than that (111), such that (001).
- a solid crystalline substrate having an orientation other than that allowing the vertical growth of nanowires is also interesting.
- silicon substrates having a (001) orientation are used in microelectronics for reasons of manufacturing processes.
- this orientation does not allow vertical growth of nanowires.
- the method of the invention therefore makes it possible to convert a surface that is not adapted to the vertical growth of the nanowires into a suitable surface, allowing the integration of vertical nanowires into microelectronics.
- the substrate is a solid silicon substrate not comprising its planes (111) parallel to the surface of the substrate, that is to say comprising an orientation other than (111), optionally covered by a silicon oxide layer, or any other layer compatible with the crystallization process, such as a zinc oxide (ZnO) layer.
- ZnO zinc oxide
- fused silica and borosilicates which have a glass transition temperature higher than the necessary temperatures of the manufacturing process.
- the substrate may further comprise one or more layers located between the substrate and the layer of silicon and / or germanium consisting of one or more monocrystalline grains. This or these layer (s) can confer multiple properties on the substrate.
- the substrate comprises at least one conductive layer providing the function of an electrode.
- the substrate comprises the following stack defined starting from the substrate:
- nanowires an upper electrode.
- the lower and upper electrodes each comprise at least one electrically conductive layer.
- the conductive layer may comprise transparent conductive oxides (TCO), that is, materials that are both good conductors and transparent in the visible, such as tin oxide and indium (ITO) , In203, Sn02 doped with antimony or fluorine (SnO2: F) or ZnO doped with aluminum (ZnO: Al).
- TCO transparent conductive oxides
- ITO tin oxide and indium
- ITO indium
- the conductive layer may also comprise transparent conductive polymers which are organic compounds with conjugated double bonds whose conductivity can be enhanced by chemical or electrochemical doping. These conductive layers based on conductive oxides or conductive polymers are preferably deposited on thicknesses of the order of 50 to 100 nm.
- the conductive layer may also be a metal layer, for example Ag, Al, Pd, Cu, Pd, Pt, In, Mo, Au.
- the electroconductive metal layer may be a thin layer, called TCC ("transparent conductive coating") having, preferably, a thickness between 2 and 50 nm.
- Nanowires are objects of high crystalline quality. Their small lateral dimension makes it possible to elastically relax the stresses and to effectively trap potential defects extended to their free surface. Nanowires typically have diameters of the order of 10 to 200 nm and heights (or lengths) ranging from a few hundred nanometers to a few microns. The composition of the nanowire can be modulated at will along and perpendicular to its axis of growth. The nanowires can therefore comprise different substructures such as radial or axial heterostructures, or else different doping.
- a height H preferably of at least 100 nm or at least 1 ⁇
- the nanowires are chosen from metal oxides, silicon, germanium and the semiconductors III-V and II-VI,
- III-V semiconductors may be chosen from GaAs, GaN, GaP, GaSb, InAs, InP, InSb, InN, and from among all the ternary or quaternary alloys intermediate between these binary compounds.
- the stage of development or growth of the nanowires can be carried out by any which crystal growth technique and in particular by chemical vapor deposition (CVD), by laser ablation, by molecular beam epitaxy, by plasma assisted deposition, by chemical means in the liquid phase.
- CVD chemical vapor deposition
- laser ablation by laser ablation
- molecular beam epitaxy by plasma assisted deposition
- plasma assisted deposition by chemical means in the liquid phase.
- WO 2009/054804 describes for example the conditions for the growth of semiconductor nanowires III-V by a chemical vapor deposition process that can be applied according to the present invention. However, it is preferred to carry out the growth step by molecular beam epitaxy.
- the parameters of the growth step of the nanowires are chosen to selectively grow the nanowires only on the monocrystalline grains. These parameters are in particular the flows of injected starting materials and the temperature of the substrate.
- the nanowires can be placed on the substrate randomly or in an ordered pattern.
- ordered patterns can be obtained by assigning a predetermined location to each nanowire.
- the ordered patterns can also be achieved by assigning a predetermined location to multiple nanowires defining a set of nanowires. In this case, the ordered pattern is not obtained by the pattern resulting from the location of each nanowire but by the pattern resulting from the location of the different sets of nanowires.
- the method further comprises a step of depositing a layer above the silicon and / or germanium layer and a step of structuring openings, in this layer making it possible to grow nanowires according to ordered patterns.
- the method of manufacturing the substrate further comprises a step of depositing a layer above the substrate and a step of structuring openings, in this layer for selectively depositing the metal layer and the amorphous silicon and / or germanium layer in an ordered pattern.
- This method also comprises a nanowire growth step on the ordered patterns of monocrystalline grains of silicon and / or germanium.
- the pattern will be defined by the location of each nanowire or each set of nanowires.
- the size of the openings is preferably nanometric.
- FIGS. 1 to 5 illustrate various diagrams representing the method of manufacturing a substrate according to the invention with perspective views and sectional views:
- FIG. 1 represents a method of manufacturing a substrate according to the first embodiment of the invention with a crystallization induced by a so-called "direct” metal
- FIG. 2 represents a method of manufacturing a substrate according to FIG. first embodiment of the invention with crystallization induced by a so-called "inverse" metal
- FIG. 3 represents a method of manufacturing a substrate according to the first embodiment of the invention in which a layer of silicon and / or germanium is obtained placed on the substrate in a defined pattern
- FIG. 4 represents a method for manufacturing a substrate according to the second embodiment of the invention in which controlled growth is achieved in order to obtain non-contiguous monocrystalline grains
- FIG. 5 represents a method of manufacturing a substrate according to the second embodiment of the invention according to which a masking step is used to obtain non-contiguous monocrystalline grains in a predetermined pattern which will allow the nanowires to grow in accordance with a ordered pattern.
- FIG. 6 is a scanning electron microscope image and a schematic representation of said image
- FIG. 7 represents the profile of the contrast in the light field, taken perpendicular to the plane of the substrate as a function of the depth in nanometer, of an image obtained by transmission electron microscopy on a thinned slice sample after crystallization and etching,
- FIG. 8 corresponds to an X-ray diffraction spectrum at grazing incidence of the silicon layer after crystallization and etching
- FIG. 9 represents an image taken under a scanning electron microscope of a nanowire.
- the diagram of FIG. 1 represents the main steps of the method of manufacturing a substrate according to the first embodiment of the invention with a crystallization induced by a so-called "direct" metal, that is to say by a layer of silicon and / or amorphous germanium above a metal layer.
- the process of Figure 1 comprises the following four steps.
- the first step consists of depositing successively and in this order on a substrate 1, a metal layer 3 and a layer of silicon and / or amorphous germanium 2a.
- the second step corresponds to the actual crystallization of the layer of silicon and / or amorphous germanium 2a. Crystallization occurs at the interface between the metal layer 3 and the amorphous layer 2a (a-Si and / or a-Ge). The formed crystals then grow in the metal layer, rejecting the metal above, which leads to the end of the crystallization step at a reverse of the stack.
- a substrate is obtained comprising a layer of silicon and / or germanium 2c consisting of one or more monocrystalline grains formed below the metal layer 3.
- the third step is to eliminate by selective etching the metal layer 3 to allow the growth of the nanowires.
- the fourth step corresponds to the actual growth of the nanowires on the monocrystalline grains constituting the crystallized layer of silicon and / or germanium 2c.
- the process described by the scheme of Figure 2 differs essentially from that of Figure 1 in that the crystallization induced by a metal is called "inverse".
- the process of Figure 2 comprises the following three steps.
- the first step consists in depositing successively and in this order on a substrate 1, a layer of silicon and / or amorphous germanium 2a and a metal layer 3.
- the second step corresponding to the crystallization leads to obtaining a substrate comprising a layer of silicon and / or germanium 2c consisting of one or more monocrystalline grains formed above the metal layer 3. it is not necessary to carry out an etching step contrary to the method illustrated in FIG.
- the third step corresponds to the proper growth of the nanowires on the monocrystalline grains constituting the crystallized layer of silicon and / or germanium 2c.
- the diagram of FIG. 3 represents the main steps of the method of manufacturing a substrate according to the first embodiment of the invention with crystallization induced by a so-called "direct" metal in which a layer of silicon and / or of germanium according to a defined pattern.
- This method includes the use of a mask to mask the part of the surface of the substrate on which it is not desired grow nanowire.
- the first step consists in depositing on the substrate a layer of the masking material 5.
- the second step is to structure openings in this layer 5.
- these first two steps can be replaced by the use of a mask or stencil simply applied to the substrate.
- the third step consists in depositing successively on the substrate 1 comprising the structured layer 5, a metal layer 3 and a layer of silicon and / or amorphous germanium 2a.
- the structured layer 5 can be removed before or after the crystallization of silicon.
- the fourth step consists of the removal of the layer 5 used for the structuring.
- a substrate 1 is thus obtained, successively comprising a metal layer 3 and a layer of silicon and / or amorphous germanium 2a.
- the fifth step leads to obtaining a substrate comprising a layer of silicon and / or germanium 2c consisting of one or more monocrystalline grains formed above the metal layer 3 deposited in the pattern corresponding to the opening of the structured layer.
- the sixth step is to eliminate by selective etching the metal layer 3 to allow the growth of the nanowires.
- the seventh step corresponds to the actual growth of the nanowires on the monocrystalline grains constituting the crystallized layer of silicon and / or germanium 2c.
- the fourth step corresponds to the crystallization and leads to obtaining a substrate comprising a layer of silicon and / or germanium 2c consisting of one or more monocrystalline grains formed below the metal layer 3
- the fifth step consists in eliminating the metal layer 3 by selective etching.
- the sixth step consists of the removal of the layer used for structuring 5. This gives a substrate 1 comprising a layer of silicon and / or germanium 2c consisting of one or more monocrystalline grains deposited in the pattern corresponding to the opening of the structured layer 5.
- the seventh step corresponds to the actual growth of the nanowires on the monocrystalline grains constituting the crystallized layer of silicon and / or germanium 2c.
- the process illustrated in FIG. 3 makes it possible to grow the nanowires in ordered patterns.
- the diagram of FIG. 4 represents the main steps of the process for manufacturing a substrate according to the second embodiment of the invention with a crystallization induced by a so-called "direct" metal in which controlled growth is achieved in order to obtain unconjugated monocrystalline grains.
- the process of Figure 4 comprises the following four steps.
- the first step consists in successively depositing on a substrate 1, a metal layer 3 and a layer of silicon and / or amorphous germanium 2a.
- the second step corresponds to the crystallization of the layer of silicon and / or amorphous germanium 2a.
- the crystalline growth is controlled to prevent coalescence of the grains for example by choosing to deposit a metal layer 3 thicker than the layer of silicon and / or amorphous germanium 2a.
- a substrate is obtained comprising a layer of silicon and / or germanium 2c consisting of one or more non-contiguous monocrystalline grains formed below the metal layer 3.
- the third step is to eliminate by selective etching the metal layer 3 to allow the growth of the nanowires.
- the fourth step corresponds to the actual growth of the nanowires on the monocrystalline grains constituting the layer of silicon and / or germanium 2c. Thanks to adequate experimental conditions, the nanowires do not grow on the surface of the substrate which does not comprise a monocrystalline grain.
- FIG. 5 represents the fabrication of a substrate according to the second embodiment of the invention according to which a masking step is used to obtain non-contiguous monocrystalline grains in a pattern and one or more predetermined shapes. This method differs from that of FIG. 3 in that to obtain non-contiguous monocrystalline grains, the patterns of the mask used must have sufficiently small lateral dimensions.
- the first step consists in depositing a layer 5 on the substrate 1.
- the second step consists in structuring openings of controlled size in this layer 5.
- the maximum lateral dimension of the openings D 0 must preferably be less than 5 ⁇ .
- the choice of the nature of the layer used to achieve this structuring will be depending on the conditions of the process.
- the resins conventionally used in lithography can be mentioned as a layer. It is also possible to envisage oxide layers that could be structured by selective etching.
- the third step consists in depositing successively on a substrate 1, a metal layer 3 and a layer of silicon and / or amorphous germanium 2a.
- the fourth step consists in removing the layer used for structuring 5. This gives a substrate 1 successively comprising a metal layer 3 and a layer of silicon and / or amorphous germanium 2a.
- the fifth step leads to obtaining a substrate comprising a layer of silicon and / or germanium 2c consisting of monocrystalline grains of silicon and / or non-joined germanium formed below the metal layer 3 and deposited according to the pattern corresponding to the opening of the structured layer 5.
- the sixth step is to eliminate by selective etching the metal layer 3 to allow the growth of the nanowires.
- the seventh step corresponds to the actual growth of the nanowires on the non-joined monocrystalline grains constituting the layer of silicon and / or germanium 2c. It is then possible to grow one or more nanowires according to the characteristics of the growth, and / or the size of the monocrystalline grains.
- the substrate comprising on at least a portion of one of its surfaces a continuous or discontinuous layer of silicon and / or germanium consisting of one or more monocrystalline grains, all oriented so that they have plans (111). ) parallel to the surface of the substrate can allow the growth of any other object of varied shape such as layers and pads, consisting of materials that require substrates having an adequate crystalline orientation (111) for their growth by epitaxy.
- These objects are of the same nature as the nanowires and preferably are semiconductors III-V or II-VII.
- the invention may also relate to a substrate comprising on at least a portion of one of its surfaces a layer of silicon and / or germanium consisting of one or more monocrystalline grains, all oriented so that they have plans ( 111) parallel to the surface of the substrate, and on this layer, one or more objects of varied shape.
- a substrate finds application in various fields such as electronics, optics or optoelectronics. Examples
- the amorphous aluminum-silicon stack is deposited by DC magnetron sputtering onto fused silica, glass, and oxidized Si (100) substrates (250 nm surface-amorphous SiO 2 obtained by wet oxidation of Si (100) at 950 ° C). All types of substrates were previously rinsed with acetone, ethanol and deionized water.
- a layer of 10 nm of aluminum is deposited at a power of 50 W, under an argon pressure of 1.5 ⁇ bar, at room temperature, and placed at a floating electric potential (deposition rate of 2.24 ⁇ "1). the 10 nm of amorphous silicon are deposited consecutively to aluminum, without breaking the vacuum, and a power of 20 W (all other identical operating conditions) (deposition rate of 0.46 s" 1).
- the stacks are annealed at 400 ° C. for 15 h under a nitrogen atmosphere (2 L min -1 ).
- the surface aluminum layer is etched wet: the substrate is immersed in a concentrated hydrochloric acid solution (37% by weight) for 15 minutes at room temperature; where appropriate, the amorphous oxide layer Al-Si-O (present at the p-Si-Al interface) may be etched with a dilute aqueous solution of hydrofluoric acid (5% by weight).
- the morphology of the layers is analyzed by optical microscopy, scanning electron microscopy and transmission electron microscopy.
- FIG. 6 is a scanning electron microscope image, as well as a schematic representation of said image, of an oxidized silicon substrate (001) on which a silicon layer has crystallized.
- the thickness of the layer comprising monocrystalline grains of silicon is 10 nm.
- the hatched parts delimit the grains and the white parts the Si0 2 .
- Roughness at the grain surface level was measured using an atomic force microscope (AFM). By measuring this roughness on several grains, the most unfavorable roughness measured on a grain is 1, 2 nm.
- FIG. 7 represents the profile of the contrast in a light field, taken perpendicular to the plane of the substrate as a function of the depth in nanometer, of an image obtained by transmission electron microscopy on a thinned slice sample after crystallization and etching.
- the resulting profile is characteristic of grain crystallization with (111) planes parallel to the surface of the substrate.
- the crystalline properties of the p-Si layer were also analyzed by grazing incidence X-ray diffraction (GIXRD: Grazing Incidence X-Ray Diffraction), due to the fineness of the layer.
- GIXRD grazing incidence X-ray diffraction
- the layers of p-Si have a perfect texture (111) as shown by the spectrum of figure 8. Only the families of plane ⁇ 220 ⁇ and ⁇ 422 ⁇ are observed by GIXRD: it is the signature of the texture (111 ) complete movie.
- the nanowires are obtained by evacuating and degassing the substrate comprising the thin layer followed by a conventional nanowire growth procedure (any catalyst and any III-V material).
- GaAs nanowires autocatalysts The growth of GaAs nanowires autocatalysts is carried out by molecular beam epitaxy (MBE) MBE in a frame 32 of Riber, under a rotation of 7 rounds min "1 and a flow equivalent to a planar Gallium growth of 2.0 ⁇ s "1 (pressure of 3.0-10 7 Torr).
- MBE molecular beam epitaxy
- the thin film substrates are degassed under vacuum at 450 ° C. for 1 hour.
- the substrate is transferred to the growth chamber and is heated to 450 ° C.
- Gallium is deposited for 60 s (amount equivalent to 19 monolayers of Ga).
- the temperature is raised from 450 ° C to 580 ° C (growth temperature) in 10 minutes using a ramp.
- the shutter As (in the form of As 4) and Ga are opened simultaneously, respectively providing flow 4,2- 10 "6 torr and 10 3,0- “7 Torr.
- Arsenic pressure is linearly increased to 5,2- 10 "6 torr, 300 s. Growth is maintained under these conditions for an additional 300 s.
- the sources of As 4 and Ga are simultaneously closed, and the sample is transferred out of the growth chamber.
- FIG. 9 represents an image taken under a scanning electron microscope of a nanowire obtained according to the method of the invention.
- the nanowire is vertical on the surface of a monocrystalline grain of silicon.
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Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1256374A FR2992980B1 (en) | 2012-07-03 | 2012-07-03 | SUBSTRATE COMPRISING A SILICON AND / OR GERMANIUM LAYER AND ONE OR MORE PERPENDICULAR ORIENTATION NANOWILS ON THE SURFACE OF THE SUBSTRATE |
PCT/FR2013/051552 WO2014006319A1 (en) | 2012-07-03 | 2013-07-02 | Substrate comprising a layer of silicon and/or germanium and one or a plurality of nanowires oriented perpendicular to the surface of the substrate |
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EP2870278A1 true EP2870278A1 (en) | 2015-05-13 |
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EP13744671.2A Withdrawn EP2870279A2 (en) | 2012-07-03 | 2013-07-02 | Substrate comprising a layer of silicon and/or germanium and one or a plurality of objects of varying shapes |
EP13744670.4A Withdrawn EP2870278A1 (en) | 2012-07-03 | 2013-07-02 | Substrate comprising a layer of silicon and/or germanium and one or a plurality of nanowires oriented perpendicular to the surface of the substrate |
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EP13744671.2A Withdrawn EP2870279A2 (en) | 2012-07-03 | 2013-07-02 | Substrate comprising a layer of silicon and/or germanium and one or a plurality of objects of varying shapes |
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FR (1) | FR2992980B1 (en) |
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US20070224788A1 (en) * | 2006-03-23 | 2007-09-27 | Board Of Trustees Of The University Of Arkansas | Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon |
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EP2541625A1 (en) * | 2010-02-25 | 2013-01-02 | National University Corporation Hokkaido University | Semiconductor device and method for manufacturing semiconductor device |
KR101050467B1 (en) * | 2010-04-14 | 2011-07-20 | 삼성모바일디스플레이주식회사 | Polysilicon film, the method for fabrication thereof, thin film transistor with the polysilicon film and organic light emitting display device with the thin film transistor |
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- 2013-07-02 WO PCT/FR2013/051553 patent/WO2014006320A2/en active Application Filing
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US20070224788A1 (en) * | 2006-03-23 | 2007-09-27 | Board Of Trustees Of The University Of Arkansas | Fabrication of large grain polycrystalline silicon film by nano aluminum-induced crystallization of amorphous silicon |
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FR2992980B1 (en) | 2018-04-13 |
WO2014006319A1 (en) | 2014-01-09 |
EP2870279A2 (en) | 2015-05-13 |
WO2014006320A3 (en) | 2014-04-03 |
WO2014006320A2 (en) | 2014-01-09 |
FR2992980A1 (en) | 2014-01-10 |
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