EP2862266A2

EP2862266A2 - Reversible matrix converter circuit

Info

Publication number: EP2862266A2
Application number: EP13737162.1A
Authority: EP
Inventors: Ignace Rasoanarivo
Original assignee: Universite de Lorraine
Current assignee: Universite de Lorraine
Priority date: 2012-06-18
Filing date: 2013-06-18
Publication date: 2015-04-22
Also published as: WO2013189952A2; FR2992116B1; WO2013189952A3; FR2992116A1; US20150131348A1; US9577549B2

Abstract

The invention relates to a reversible matrix converter circuit with n levels per phase comprising n conversion arms exhibiting on one side n ends for generating or receiving respectively n intermediate DC voltage levels, and exhibiting on another side n ends linked at a common point of AC signal input or output. This circuit comprises:- two external arms linked respectively to the highest level of positive voltage and to the lowest level of negative voltage, these two external arms each comprising a single IGBT transistor or two power transistors, linked by their emitter, - two IGBT power transistors, linked in series by their emitter on each of the n-1 internal arms, - filtering capacitors disposed respectively between the n intermediate voltage levels.

Description

"Reversible matrix converter circuit."

The present invention relates to a n-phase reversible rectifier-inverter matrix converter circuit.

Multilevel rectifier circuits are known on the one hand. Such circuits can be controlled or not and can rectify a three-phase AC signal. WO 01/47094 A2, "Method and Control Circuitry for a Three-Phase ThreeLevel Boost Rectifier", describes a 3-phase three-phase rectifier in which a diode bridge is used which makes the assembly non-reversible. Document FR2881294 describes a reversible rectifier based on IGBT transistors but in a non-multi-level structure. US6005787 which discloses a multi-level matrix converter circuit comprising a plurality of conversion arms powered by different intermediate positive voltages and connected in output to a common point generating an output current. The switches are embodied by MOS transistors and not IGBTs. In addition, the voltages are only positive.

Also known are n-phase matrix inverter circuits comprising n conversion arms fed respectively by n intermediate voltage levels and connected in output to a common point generating an output current. Such a circuit is described in particular in document WO 2011/058273 A2, Multi-level multi-level matrix converter circuit, and method for implementing such a circuit.

It is an object of the present invention to provide a n-phase reversible rectifier-inverter matrix converter circuit in which the quality of the rectified AC side currents can be further improved over prior art systems. In particular, it is desired to obtain the most sinusoidal input and / or output currents possible. Another object of the invention is to achieve a high recovery gain for the rectifier operation.

At least one of the above-mentioned objectives is reached with a reversible matrix converter circuit with n levels per phase, n being mainly an odd number. This converter circuit comprises n conversion arms presenting on one side n ends for generating or receiving respectively n intermediate DC voltage levels, and having on the other side n connected ends at a common input or output AC signal, characterized in that the n conversion arms are distributed as follows:

two dedicated external arms on the side of the intermediate DC voltages at the two highest positive and negative voltage levels in absolute value + V _N _ ₁ , -V _N _ ₁ ; these two external arms including

2 2

each at least one IGBT transistor provided with an internal antiparallel diode, the current in these arms being controlled in one direction and natural in the other,

n-2 internal arms dedicated to the other n-2 intermediate DC voltage levels, these n-2 internal arms each comprising two IGBT transistors provided with an internal anti-parallel diode and connected in series by their emitter,

n-1 filter capacitors arranged respectively between the n intermediate DC voltage levels, and

a management circuit for controlling the IGBT transistors in rectifier or inverter mode. The present invention proposes a new reversible rectifier structure with n levels dedicated in particular to the low voltage. By way of non-limiting example, this rectifier will preferably be used for n less than or equal to seven.

The use of IGBT transistors, combining the advantages of bipolar and MOS technologies, associated in particular with a relatively low switching frequency, of the order of a few kHz, allows a reduction of commutation and conduction losses and the implementation of 'a simplified order and little dissipative. We can also consider applications in medium and high power: in this case, we can replace the single transistor IGBT of the outer arm by two transistors in series connected by their emitter, so the same topology as the transistors of the internal arms.

With the converter circuit according to the invention, the reversible "inverter-rectifier" operation can open wide possibilities as to the management of electrical energy in both directions of energy conversion: upstream-downstream and downstream-upstream.

With this reversible converter circuit according to the invention, it leads to an efficient topology where the current conduction is provided by a single transistor with two quadrants (with its internal diode), on the outer arms and a transistor four quadrants on the arms internal. The conduction and switching losses of the switches, especially at low switching frequency, can be comparable, if not lower than those of conventional multilevel converters.

With the use of the IGBT transistors, the reversible converter circuit according to the invention can operate in hard commutation with, however, increased strength and viability: by the combined choice of a relatively low switching frequency, the gate resistance R _G0 N smaller than the grid resistance R ₉ OFF, and the connection of the power switches by the principle of bus-bars with the outermost plates connected to the ground. This type of wiring is widely recognized for effective protection against electromagnetic interference. According to the invention, in rectifier mode, in said n-2 internal arms:

for arms dedicated to positive intermediate DC voltage levels, the IGBT transistors arranged on the DC intermediate voltage side have their emitter connected to their gate; the positive current flowing in the IGBT transistor connected to the AC common point and in the internal diode of the other transistor of the same arm, and

for arms dedicated to negative intermediate DC voltage levels, the IGBT transistors arranged on the common point side have their emitter connected to their gate; the negative current flowing in the IGBT transistor connected on the DC intermediate voltage side and in the internal diode of the other IGBT transistor of the same arm connected to the AC common point.

According to an advantageous characteristic of the invention, the management circuit comprises: a modulated hysteresis control circuit for ensuring the sinusoidal currents of the currents in the alternating parts of the converter circuit,

a stage switching circuit defining a stage switching level parameter v * _st used for controlling the transistors

IGBT, and

a distribution circuit, such as a programmable circuit, for distributing control signals to the IGBT transistors from pulse width modulation signals from the modulated hysteresis control circuit and from the switching level parameter of 'floor.

By distribution circuit, is meant for example a programmable circuit parameterized to distribute control signals to different transistors.

With such a modulated hysteresis control, the current harmonic distortion ratio (TDHi) can tend to zero and the power factor is greatly improved. This quality is particularly interesting for all-electric on-board systems whose source has a limited energy in time: the efficiency of the converter is greatly improved mainly due to the low value of the switching frequency and a perfectly flat voltage on the side. continuous and free of high frequency harmonic components.

Control and control by modulated hysteresis current can be either of completely analog embodiment, or of completely digital realization, so simple and robust. The management circuit may comprise at least one DSP ("Digital Signal Processor") circuit for digital management.

Preferably, the modulated hysteresis control circuit comprises a modulated current hysteresis control module having as input:

- a positive reference current I _ref + for positive half-waves of the rectifier input signal,

- a negative reference current I _re f. for negative alternations of the input signal of the rectifier,

a triangular signal to be superimposed on the positive or negative reference current, and - a line current per phase to be compared to the positive or negative reference current thus superimposed with the triangular signal.

In particular, the positive reference current I _ref + can be obtained by adding a current reference I _re fo with a positive variation AI + _ref of the reference current. In the same way, the negative reference current Iref- can be obtained by adding a reference current I _re fo with a negative variation AI _re f- of the reference current.

This reference current I _re fo may for example be obtained from a reference current of a load of the rectifier: according to fixed values of active power and reactive power of the load.

Preferably, the positive variation AI _re f + of the reference current is a signal coming from a corrector having as input:

an upper reference voltage V _re f_ _sup , and

one of the positive intermediate DC voltages.

One of the positive intermediate DC voltages may be the highest intermediate DC voltage.

In addition, the negative variation AI _re f- of the reference current is advantageously a signal coming from a corrector having as input:

an upper reference voltage V _re f_ _sup , and

one of the negative intermediate DC voltages.

In the same way, one of the negative intermediate DC voltages may be the most negative intermediate DC voltage.

In addition to the above, the floor switching circuit is powered by:

a positive stage switching parameter V * _{st +} coming from a corrector having as input a lower reference voltage V _re fjnf and one of the positive intermediate DC voltages, and

- A negative stage switching parameter V * _st- from a corrector having as input the lower reference voltage V _re fjnf and one of the negative intermediate DC voltages.

On the other hand, one of the positive or negative intermediate DC voltages is the highest or the lowest positive DC voltage respectively. According to an advantageous characteristic of the invention, the correctors are of proportional integral type derived by fractional order.

With the converter circuit according to the invention, the input and output currents are perfectly sinusoidal and are totally controlled. The voltages of the capacitors are perfectly flat and symmetrical, and can be continuously regulated. In this case, for example with a rectifier provided for 5 levels, one can then have either 5 levels or 3 levels in output voltage. With efficient signal management, the voltage and current edges that are the source of electromagnetic disturbances on the environment more or less close to the circuit are limited.

In addition, the recovery gain is higher than that of a conventional rectification in three-phase mode. The operation of the converter is decomposable into two main sequences:

- When one of the switches of the central arm is controlled and all the other OFF, the additional inductance λ of the network stores magnetic energy,

When these switches are OFF and at least one of the switches of the arms is ON, this magnetic energy is transferred into the output capacitors and into the load. This is the characteristic operating principle of a BOOST converter. This will be explained later.

By way of non-limiting example, the external arms may each comprise two IGBT transistors provided with an internal anti-parallel diode, these two IGBT transistors being connected in series by their emitter.

According to the invention, there is provided a system comprising two converter circuits as described above, one of the two converter circuits being configured as a rectifier, the other as an inverter; the two converter circuits being arranged back-to-back. Other advantages and characteristics of the invention will appear on examining the detailed description of a non-limiting mode of implementation, essentially in rectifier mode of operation, and the appended drawings, in which:

FIG. 1 is a simplified schematic view illustrating an N (uneven) level rectifier arm according to the invention; - Figures 2 to 4 are schematic views illustrating the topology of an arm for a rectifier respectively 3 levels, 5 levels, 7 levels;

FIG. 5 is a schematic view illustrating a configuration for the positive alternation of the supply voltage e;

FIGS. 6a and 6b are schematic views illustrating configurations for two main sequences of 'Boost' operating modes;

FIG. 7 is a schematic view illustrating two possibilities of close control;

FIG. 8 is a schematic view illustrating a control of currents;

FIG. 9 is a simplified schematic view illustrating an overall control of the multi-level three-phase rectifier according to the invention;

FIG. 10 is a simplified schematic view illustrating two back-to-back converters for five-level converters.

FIGS. 11a, 11b and 11c are simplified schematic views illustrating curves obtained by simulation emphasizing the role of the parameter K _{V rmsl} ;

FIG. 12 is a simplified schematic view illustrating curves obtained by simulation underlining the influence of the reference v _{ref inf} with

V _{ref sup} = 400V)

FIG. 13 is a simplified schematic view illustrating relative variation curves of the four voltages + v ₂ , -v ₂ , + v ₁ and -v, as a function of the load of the inverter;

FIG. 14 is a simplified schematic view illustrating waveforms and performance during abrupt changes in the load of the inverter.

FIG. 15 is a simplified schematic view illustrating waveforms and performance during abrupt variations in the operating frequency of the inverter.

FIG. 16 is a simplified schematic view illustrating waveforms during abrupt variations of references v _{ref sup} and v _{ref inf} . ;

FIGS. 17a and 17b are schematic views of the arms of an N (odd) -converter in fully reversible mode; FIG. 18 is a simplified schematic view illustrating an electrical network with unbalanced operating compensation;

FIGS. 19 and 20 are simplified schematic views illustrating a compensation circuit for an imbalance on the negative and then positive alternation of the voltage;

FIGS. 21a, 21b and 21c are simplified schematic views illustrating examples of topology of an arm for a 3 level (left), 5 level (center), 7 level (right) rectifier;

FIG. 22 is a simplified schematic view illustrating a configuration for the positive alternation of the supply voltage e;

FIGS. 23a, 23b and 23c are simplified schematic views illustrating configurations during the positive half-cycle of the supply voltage e for the control of the voltage V ₂ . ;

FIGS. 24a, 24b and 24c are simplified schematic views illustrating configurations during the positive half-cycle of the supply voltage e for the control of the voltage V _l ;

- Figures 25a and 25b are simplified schematic views illustrating two possibilities of close control;

FIG. 26 is a simplified schematic view illustrating two back-to-back converters based on five-level converters for a completely reversible conversion; and

FIG. 27 is a simplified schematic view illustrating the management of currents based on a PIDOF corrector for the rectifier. FIG. 1 shows a reversible single-phase topology according to the invention for N (odd) levels, with

• T _t . : the numbering of the IGBT switches,

• the potential of an exit point;

• y ₀ = ov, the potential of the midpoint.

In a rectifying operation, the input signal e (t) is applied, via an inductive circuit having a resistance p and an inductance λ, to a common point connecting N conversion arm. The two external conversion arms comprise a single IGBT transistor Tl and T _2N-2 . The emitter of transistor T1 receives the input signal e (t). The issuer of transistor T _2N -2 is connected to the most negative DC output voltage point: -V _(N- i _{) / 2} .

There are n-2 other internal conversion arms each having two IGBT transistors connected in series by their emitter. Filtering capacitors C are arranged respectively between the n intermediate voltage levels.

To ensure the rectifier operation, the transistors numbered between τ _ι and τ _Ν _ _{ , as well as those also numbered between τ _3Ν _ ₁ and

2 2 T _2N _ ₂ must be blocked. Examples of topology at 3, 5 and 7 levels are shown in Figures 2, 3 and 4, with resistive loads at the output.

For example, the operating analysis can be done on the single-phase converter at five levels: the neutral of the network and the 0V are connected. Assuming a symmetrical operation of the rectifier, a qualitative analysis of operation is performed during the positive half-cycle of the supply voltage e, according to the diagram of FIG. 5. In this case, the transistors τ ₅ and τ ₆ (resp. r, and τ ₄ ) are controlled during the positive (or negative) alternation of the supply voltage e, see Figure 5. The transistors T ₂ and T ₇ are off.

Thus, the operating analysis is based on the two main sequences shown in Figures 6a and 6b:

In FIG. 6-a, the voltage v ₂ is controlled by the transistor τ ₆ and the diode D _j : the sequence change is natural as of the blocking command of τ ₆ ;

In FIG. 6-b, the voltage v is controlled by the transistors τ ₆ and τ ₅ : to ensure the continuity of the current in the inductance λ, the transistor τ ₅ must be switched on before blocking the transistor τ ₆ . Concerning the control of the IGBT transistors, two types of close control can be provided. The "Boosf" effect is conventionally obtained by a simple PWM command with a variable duty cycle for the transistor τ _6. As seen previously, for the sequence of the

Fig.6-b, the transistor τ ₅ must be switched on before blocking the transistor τ ₆ . Thus, one can consider as illustrated in Fig.7 two ways to generate triggers ("triggers" in English) command on τ ₅ (Typel and Type2 strategies). These two strategies are based on a simple comparison of a DC voltage level v _st with respect to the supply voltage e, thus defining a stage switching level parameter v * according to: v * E being the value of peak voltage of the input voltage e.

So :

when T ₅ = OFF and T ₆ commanded, then the voltage + v ₂ is controlled and the voltage + v _l is deduced by a voltage division rule. In this case, the five voltage levels are well output: + v ₂ , + v _l , 0V, - Vj, and - v ₂ ;

when T ₅ = ON and T ₆ controlled, then the voltage + v _l is controlled and for the voltage + v _{2 /} the capacitor is discharged in its resistance. If during all the positive alternation of the source voltage e, T ₅ remains on, the voltage + v ₂ becomes zero. In this case, only three levels of voltages are available at output: + v _lf W, and -v _x ; The general strategy of controlling the transistors can be developed in the case of back-to-back operation of two converters according to the invention: a rectifier circuit head to tail with an inverter circuit according to the invention. The behavior of the current / supplied by the supply network depends on the control strategy of the transistor τ ₆ . One can opt for a modulated current hysteresis control (Modulated Hysteresis Control Current MHCC) for the control of the currents discharged by the network and also the load currents of the inverter. Preferably, a PIDOF corrector is used, as will be seen in particular in FIG. 27. FIG. 8 shows a back-to-back rectifier with an inverter, with: i _ref , the reference current of the network, and i _{ref Jnv} the reference current of the inverter. FIG. 8 presents the control block diagram for the line currents II, I2 and I3 of the rectifier, and iA, iB and iC of the inverter. Similarly, Figure 27 below incorporates a PIDOF corrector instead of the MHCC of the rectifier to manage line currents. The PIDOF can also be used to manage the currents of the inverter.

Thus, for active powers P and reactive Q provided by the inverter, we put:

To solve this equation, we know either the value of the fundamental v _{A msl} of the simple voltage of the inverter, or the reference current i _{ref inv} . In general, fast Fourier transform analysis

(FFT for "Fast Fourier Transform" in English) of the simple voltage of the inverter v _AN highlights a very strong correlation of the fundamental of this voltage v _{A msl} rather with the voltages + v ₂ and -v ₂ that with the voltages + v _l and -v _; . Thus, in symmetrical regime, one poses;

^V 2 * ^ A (2)

The coefficient κ _{ν msl} can be defined by simulation: it depends very strongly on the operating mode of the multi-level inverter. The operating mode of the multi-level inverter is as described in WO 2011/058273 A2. Assuming the perfect switches, the conservation of the active powers between the network and the load of the inverter gives approximately:

^ ref O ^ A rmsl

* COI (>

In the uncontrolled operating mode, the four DC voltages at the output of the rectifier can be quite arbitrary. Controlling these tensions requires individualized monitoring of their instantaneous evolution. The general block diagram of the control according to the invention can be described in FIG. The control is applied around a point of operation defined by the reference current i _ref0 of the rectifier (according to equation 3).

In FIG. 8, it can be seen that each converter circuit is associated with a management circuit CG I or CG2 based on DSP. On the left, the rectifier is for example connected to an alternative source such as a power supply network. On the right, the inverter is in particular connected to an alternative autonomous source having the dual function of turbine or generator. Back-to-back converters according to the invention constitute a reversible assembly. The CG I and CG2 management circuits are used to adjust the signals passing through the converters according to whether the pump is operating in a turbine or a generator. Conversion is one way or the other.

In FIG. 9, it can be seen that the reference current I _ref0 is obtained from a current i _{ref Jnv} , P, Q and v _{A msl} . In the general case, for a load of the inverter, given by a simple value of effective value v _{A msl} , an active power P and reactive Q, this current is defined by: In general, the calculations are performed numerically by means of a DSP circuit.

The comparison of the reference voltage v _{ref sup} with the most positive output voltage + v ₂ (respectively v _{ref sup} and with the most negative voltage -v ₂ ) produced by means of another corrector named correcteurl a variation M _{ref +} (resp 4 / _{re /} _) of the reference current. The reference currents i _{ref +} and i _ref _ resulting from the addition between I _ref0 and respectively M _{ref +} and M _ref _ serve as new references in the control M HCC or preferably PIDOF, and will be associated respectively with the positive half cycle ( or negative) of the three line currents i ₁ , i _{2 3} .

The comparison by means of another corrector named corrector2, v _{ref inf} with + v, (resp -v _; ), generates the level parameter of positive stage switching v _{st +} and negative v _st _: the level v _{st +} (respectively v _st _) is associated with the positive (or negative) alternations of the three three-phase voltages of sources e _I , e ₂ , e ₃ .

The four correctors used in this diagram are of type 'Proportional Integral Derived with Fractional Order'. The main interests of this corrector are: fast dynamics, low overshoot and almost zero phase shift of the response signal. The answer is almost instantaneous, no discharge. The PIDOF correction is optimized by a DSP-managed algorithm.

In fact, by the individualized action of the four correctors:

• the reference v _{ref sup} acts on the reference current of the three input currents to impose by the control PIDOF or MHCC sinusoidal paces and also control the flatness and the symmetry of the voltages + v ₂ and - v ₂ ;

• the reference V _{ref inf} directly controls the flatness and the symmetry of the voltages + v _l and - v _x ;

An example of simulated operation of the converter circuit according to the invention will now be described below. The following data is used:

• Three-phase power source: E = i30Vrms; f = 50Hz,

• Inductance coil in series on the network side: p = 0.1Ω, λ = 1.25mH)

· Capacitor batteries: C = 3000IF.

r

• Fundamental of the simple voltage of the inverter: v _ANI = 230Vrms.

In FIG. 9, the various correctors, the PIDOF controller (or MHCC) and the switching stage are advantageously implemented within the management circuit based on one or more DSP circuits. The signal distributor Ti may be hardwired logic.

Simulation analysis can be carried out directly on the simplified installation of two back-to-back three-phase inverters in Figure 10: the left converter is a rectifier and the right converter is an inverter. 1- steady state analysis

The steady-state analysis makes it possible to determine the K _{Y MSL} coefficient indicated in equation (3). To do this, we assume that we are in controlled mode, so the voltages + v ₂ and -v ₂ , as well as + v _l and -v, are perfectly symmetrical. Thus, we put: v _{ref SUP} = K _{V rnsl} * v _{Arnsl l} and

Figures 11a, 11b and 11c show the simulation results as a function of the parameter κ _{ν msl} . In FIG. 1a, the voltages + v ₂ , -v ₂ , + v ₁ and -v; have a perfectly linear _shape , and in the variation range of the parameter κ _{ν msl} , the fundamental of the single voltage v _{A msl} of the inverter does not vary greatly around 230V. In addition, it can be seen that the DC output voltages of the rectifier are symmetrical. In Figure 11b, the currents evolve linearly, with harmonic distortion rates (THD) around 5%, validating perfectly their sinusoidal pace. On Figure 11c, the p input powers and output _in p _out with a load of the inverter having a 10 ° pitch, are adjustable substantially linearly with the parameter _κ ν _msl, with a yield around 90%. For the rest of the work, in order to be able to fix around 5%, the harmonic distortion rate current THD _I rectifier and \ emDi _A inverter, and for a value of 230V for the fundamental of the simple voltage of the inverter, one then choose v _{ref sup} = 400v.

Firstly, the Boost effect of the converter is effective because with an input voltage of 130V rms, a maximum DC voltage of 800V is obtained.

We can then show the influence of the parameter v _s * _t . Figures 12a,

12b and 12c show the simulation results as a function of the reference v _{ref inf} , for a load of the inverter around 10kW and an angle of 10 ° for the argument of the load. In Figure 12a, the voltages ^{+ V} 2 and ^{V ~} 2 t _its well flat and opposite, while the voltages ^{+ V /} ^V and ^/ are linearly opposite. In Figure 12b, the current THDs remain below 8%, thus underlining their almost sinusoidal appearance. The reference V_ also makes it possible to adjust the input and output currents. In Figure 12c, the simple voltage of the inverter can change depending on V_ _f but with a THD around

30%.

Finally, we present the results underlining the rigidity of the four DC voltages at the output of the rectifier, with powers provided by the inverter of P = 5, 7.5, w, 12.5, 15 kw and load angles φ = ιο, 20, 30 °, and for the reference values: v _{ref sup} = 400v and v _{ref inf} = 200v. Figure 13 shows the relative variations of the four voltages + v ₂ , -v ₂ , + v _l and -v; depending on the load of the inverter: it is found that the greatest relative variation does not exceed ± 2% and these variations depend only very slightly on the load angle φ.

2- Dynamic analysis

The following results describe a dynamic behavior of the montage, highlighting the validity of the strategy developed. These results are of three kinds, following abrupt variations:

• the load of the inverter;

• the working frequency of the inverter;

• references v ^r _f u and v ref ref ^r _f i n _f ■. a-Influence of the load of the inverter

In Figure 14, the waveforms and performance of the two back-to-back converters are shown in four sudden changes in inverter load, represented by the power supplied p _out . It can be seen that the responses of the two converters are almost instantaneous. In addition, the voltages + v _{2 l} + v ₁ , -v ₁ , and -v ₂ are perfectly flat and symmetrical with a ratio ± Σ2_ ₌ Î2H and remain insensitive to abrupt

+ Vj 150

imposed variations. AC input and output currents are perfectly sinusoidal with low values of harmonic distortion THD D. The fundamental value of the simple voltage of the inverter as well as the associated TH D are practically invariant. The adjustment ratio is _{= 2,631}

b-Influence of the working frequency of the inverter

In this part, we abruptly change the working frequency of the inverter from 30Hz to 50Hz, with a report. On the face

15, one verifies the perfect flatness and symmetry of the DC output voltages of the rectifier. The input and output AC currents are sinusoidal with small THD values. These values are optimal when the PIDOF control is used for both converters. When using an M HCC command, they can be improved by further refining the M HCC command of both converters. The fundamental of the simple voltage of the inverter v _AN does not vary enormously, with a quasi-constant TH D. These results underline the perfect frequency decoupling of the two converters.

V rej _t sup 400F

For this section, we operate in three parts: during

V rej _f m ■ _r i 300F e _sup _ 400F V rej, sup 300F

during t _rl + t ₂ , and finally and during

V rej _f m-, i 200F

t _r2 + t ₃ . The load of the inverter remained the same during these operations. In Figure 16, the impacts of the variations of the references v _{ref sup} and v _{ref inf} are minimal on the operation of the inverter: invariant pace of the simple voltage v _AN and three-phase sinusoidal currents. This also highlights the decoupling of operation of the two converters. In addition, during the time interval t _rl where a variation of v _{ref inf} is imposed, the two voltages + v ₂ and -v ₂ are practically invariant, while the two voltages + v ₁ and -v vary symmetrically. During the second time interval t _r2 , the four voltages vary at the same time, and it is observed during the first moments t ₀ that the currents of the input network are zero, validating the configuration where the rectifier is fully open. Note also that during these disturbances, the reaction of the system vis-à-vis the AC magnitudes of the two converters is almost instantaneous, and that the input currents remain substantially sinusoidal.

In general, the topology described in WO2001 / 058273 is partially reversible: the current flowing in the diodes of the outermost arms can not be regulated. On the other hand, it is totally reversible for the internal arms with a control of the exchanges of energy.

In addition to the above description, the present invention also relates to a completely reversible operation in rectifier and inverter multilevel converters. Like so-called matrix converters, the fundamental principle is to use for all arms a switch equivalent to 4 quadrants, called in English 'Four Quadrants Switch' (FQS). This equivalent switch is composed of two power transistors provided with their internal diode and put in series by their collector. The direction of the current in the arm is then imposed and controlled by the controlled switch. The notable difference with the previous structure of the patent WO 2011/058273 A2 is the addition of the transistors on the most positive bus-bar and on the most negative arm as can be seen in Figures 17a and 17b. Figures 17a and 17b show the fully reversible single-phase topology for N (odd) levels. Figure 17a relates to operation in multilevel rectifier. Figure 17b relates to multi-level recovery operation. The quantities ρ, λ can be provided by a coupling transformer. We note in Figures 17a and 17b: • 7: the numbering of the IGBT switches,

• V _i the potential assigned to a busbar output;

• V ₀ = 0V, the potential of the midpoint.

In particular, two modes of operation are provided:

• Inverter;

• In rectifier.

The operation in inverter is similar to that of document WO 2011/058273 A2, while integrating the specific commands of transistors 7 ^ and T ' _2N _ ₂ . However, two modes of operation can be apprehended:

• Balanced balanced mode;

• Unbalanced and / or asymmetrical mode.

In the case of a symmetrical balanced mode, if the reversibility with a total control is not required, the transistors 7 ^ and T ' _2N _ ₂ can be removed and the topology of the document WO 2011/058273 A2 is found.

The unbalanced and (or asymmetrical) mode can for example be the case in an unbalanced electrical network, see Figure 18. If the voltages at the terminals of the use are in imbalance, the present converter compensates for these imbalances. This type of operation is commonly encountered in isolated, isolated networks (for example, a shipboard network, etc.).

In the case of an unbalanced mode and (or) asymmetrical, the two transistors 7 and T ^ _N _ ₂ o an important role to play. Two examples of voltage unbalance compensation are shown in FIGS. 4 and 5, using a five-level converter. The close controls of the power switches are those already described in patent WO 2011/058273 A2, while integrating the specific commands of transistors T and T ' _2N _ ₂ . In Figure 19, we see on the left a structure for the compensation of an imbalance on the negative half of the voltage. The wave of the output voltage is shown on the right.

In Figure 20, we see on the left a structure for the compensation of an imbalance on the positive half of the voltage. The wave of the output voltage is shown on the right.

In a negative alternation of the voltage, the transistor T'1 is blocked while the transistors T8 and T'8 are active. The operation is reversed alternately positive, T'8 blocked while Tl and T'is active.

If the imbalance disappears, the converter operates as a rectifier to maintain the capacitor loads

Rectifier mode operation can be described from the 3, 5 and 7 level topology examples according to Figs. 21a, 21b and 21c for resistive output loads.

The expected objectives are of three kinds:

- AC input currents are perfectly sinusoidal and are fully controlled: the harmonic content of these currents must comply with the current standards of Electromagnetic Compatibility.

- The voltages of the capacitors are perfectly flat (so do not contain pulsating components). They can be continuously and individually regulated. And thanks to the command, one can also have indifferently, for example for a rectifier with 5 levels, either 5 levels, or 4 levels, three levels, or two levels for the output voltage. The possibility of operation with symmetrical two-to-two or asymmetrical output voltages can be considered.

- The recovery gain is higher than that of a conventional rectification in three-phase mode.

1- Function analysis in rectifier mode The operation analysis can be performed on the five-level single-phase converter of Figure 21b: the neutral of the network and the 0V are connected. The symmetrical operation analysis of the rectifier can be as follows. The qualitative analysis during the positive half-cycle of the supply voltage e is based on the diagram in FIG. 22. The transistors T,

T ₅ and T ₆ are controlled during the positive alternation (respectively r ₃ , T ₄ and T during the negative half cycle) of the supply voltage e.

Thus, the operating analysis is based on the main sequences shown in Figures 23 and 24:

Fig.23a shows the sequence for the control of voltage V ₂ . Fig. 23b, by the ignition of T ₆ magnetizes the inductance! ; in this case the control of the transistor T can be indifferently equal to 0 or 1 because the diode D _l remains locked (voltage at its terminals equal to - V ₂ ). The Fig.23c is valid as soon as the transistor T ₆ is controlled blocking but however having previously switched on the transistor T. The two sequences of Fig.23b and 23c are the two main sequences describing a mode of operation chopper or BOOST.

Fig.24a shows the sequence for the control of the voltage V _x . Fig. 24b, by the ignition of T ₆ magnetizes the inductance λ; in this case the commands of the transistors T and T ₅ may be indifferently equal to 0 or 1 because the diodes D ₁ and D ₂ remain blocked (voltage across D ₁ equal to V ₁ - V ₂ , voltage across D ₂ equal to - V _x ). FIG. 24c is valid as soon as the transistor T ₆ is controlled at the blocking stage, but however having previously switched on the transistor T ₅ . The two sequences of Fig.24b and 24c are the two main sequences describing a mode of operation chopper or BOOST.

2- Close order

The 'Boost' effect is conventionally obtained by a simple PWM command with a variable duty cycle for the transistor T ₆ . The control of the voltage V _{2 is} performed with the controls of the transistors T and T ₆ , while that of the voltage control V _l with the controls of the transistors r ₅ and T ₆ . Thus, Figs. 25a and 25b present two ways of generating the control triggers on T, T ₅ and T ₆ according to the strategies of Typel and

Type2. These two strategies rely on a simple comparison of a DC voltage level v _st relative to a unit wave in phase with the supply voltage E, thus defining the floor ^fifth switching level parameter by:

So :

• When T ₅ = OFF, T = ON, and T ₆ commanded, then the voltage + v ₂ is controlled and the voltage + v _l is deduced by a simple voltage division rule. In this case, the five voltage levels are well output: + v ₂ , + v _l , 0V, - v _l , and - v ₂ ;

• when T ₅ = ON, T = OFF, and T ₆ commanded, then the voltage + v _l is controlled and for the voltage + v ₂ , the capacitor is discharged in its resistance.

· If during all the positive alternation of the source voltage e, T ₅ always remains on and T remains always blocked, the voltage + v ₂ may become zero. In this case, only three voltage levels are available at output: + v _l , 0V, and - v _l ;

It can be seen that the output voltage can have either 5 levels or 3 levels.

By stage switching circuit is meant a circuit for changing steps in the voltage pattern of a multi-level inverter. This bearing change can be fine (it goes from the stage i, so the voltage level i at i + 1 stage, the voltage level i + 1), or coarse (we go from the stage i to the stage k).

The stage switching level can be defined as follows. If N is the number of levels of the DC voltage, the levels of stage switching are DC voltages between + 1 and -1 and compared to sinusoidal waves of unit amplitude A _t (t), e in phase with the simple voltages of the alternating side e. (t), with z ^' e [1,2,3] for a

N - l three - phase system. If N is odd the number of these levels is. If N

N - 2

is the number of these levels is - -. These quantities are only defined for N greater than or equal to 3. And for N = 3, the value of this level is OV, thus a symmetrical operation.

In the general case, for symmetrical operation, these voltage levels are two to two opposite. For any operation, the

N - l

number of voltage levels is positive sign, while the

N - l

number of voltage levels is negative sign.

In our case, for a 5-level inverter and symmetrical operation, we have two opposite sign voltage levels, with + v _st e - v _st .

For the transistors of the positive arm (respectively negative arm), therefore connected to the bus-bars of positive (respectively negative) voltages:

• When A _i (t) ≤v _st (resp. A _i (t) ≥ _v-st) are the transistors connected to the first voltage of the next higher bus-bar (resp. Lower) than the potential 0 that are set implemented (ignition and blocking). · When A _i (t)> v _st (resp. ( ^<_ O _') ^{these are the} transistors connected to the second positive (or negative) voltage of the bus-bar after the previous one which are implemented (ignition and blocking) .

Therefore, according to the value of the reference unit voltage A _t (t) in front of the stage switching voltage levels, arbitrarily controlling (switching on and blocking) the transistors of the arm connected to a voltage of the bus-bar well defined and thus generating a plateau of the DC voltage.

The reference unit voltage (and the stage switching voltage levels are part of the overall control strategy of the set.) These quantities are fundamentally useful in ensuring the existence of different voltage levels for multi-level inverters. This is where the term floor switching circuit comes into play.

3- General order strategy

The general control strategy is to make closed loops on the operation of the converter. We can take the example of a particular mode of use: the case of back-to-back operation of the two converters, whose schematic diagram is given in FIG. 26. The main interest is mainly focused on the rectifier operation, so the converter on the left of figure 26.

The expected objectives consist in feeding the multilevel converter (right converter of FIG. 26), with perfectly flat busbar voltages (not loaded with oscillating components), and symmetrical two by two, input currents _{15 2} , ₃ sinusoidal in full compliance with EMC standards, a virtually unitary power factor, and minimal converter losses. The behavior of line currents ₂ , ₃ provided by the power supply network depends on the control strategy. Thus, currently, several high-performance correctors can be used:

• Modulated current hysteresis control Modulated Hysteresis Control Current MHCC);

· A new type of control: Proportional Integral Diverter to

Fractional Order '(PIDOF).

In this case, it is preferable to use a PIDOF for the rectifier and / or for the inverter. Figure 27 describes a mode where a PIDOF is used for the rectifier and an MHCC for the inverter.

FIG. 26 shows the same structural base as FIG. 10, completing it so as to be completely reversible with a command based on PIDOF.

The description for FIGS. 8, 9 and 10 can be repeated for FIGS. 26 and 27 in that they have in common. The reversible inverter-rectifier operation of a converter can open wide possibilities especially on aspects of optimum management of electrical energy in both directions of energy conversion: upstream-downstream and downstream-upstream. This approach is not yet widespread for multilevel converters. It must be implemented in full compliance with the very stringent standards of Electromagnetic Compatibility and high performance operation of the energies involved: very good efficiency (low switching losses and conduction of power switches), high reliability and very wide viability, highly secure integrity of the power switches, very interesting dynamic behavior and very stable steady state,

Of course, the invention is not limited to the examples which have just been described and many adjustments can be made to these examples without departing from the scope of the invention.

Claims

A n-phase reversible matrix converter circuit comprising n conversion arms having on one side n ends for generating or receiving respectively n intermediate DC voltage levels, and having on the other side n connected ends at a common point d alternating signal input or output, characterized in that the n conversion arms are distributed as follows:

two dedicated external arms on the side of the intermediate DC voltages at the two highest positive and negative voltage levels, respectively, in absolute value (+ V _N- ₁ , -V _N- ₁ ); these two external arms comprising

2 2

each at least one IGBT transistor provided with an internal antiparallel diode,

characterized in that it further comprises a management circuit for controlling the IGBT transistors in rectifier or inverter mode, this management circuit comprising at least one fractional order derivative integral proportional corrector said corrector PIDOF.

2. Converter circuit according to claim 1, characterized in that in rectifier mode, in said n-2 internal arms:

3. Converter circuit according to claim 1 or 2, characterized in that the management circuit comprises at least one DSP ("Digital Signal Processor") circuit for digital management.

4. Converter circuit according to any one of claims 1 to 3, characterized in that the management circuit comprises:

a PIDOF corrector to ensure the sinusoidal currents of currents in the alternating parts of the converter circuit,

a stage switching circuit defining a stage switching level parameter (v * _st ) used for controlling the IGBT transistors, and a distributing circuit for distributing control signals to the IGBT transistors from pulse width modulation signals from the PIDOF corrector and from the floor switching level parameter.

Converter circuit according to Claim 4, characterized in that the corrector PIDOF has as input:

- a positive reference current (I _ref +) for the positive alternations of the rectifier input signal,

- a negative reference current (I _re f) for the negative alternations of the rectifier input signal,

a triangular signal to be superimposed on the positive or negative reference current, and

- a line current per phase to be compared to the positive or negative reference current thus superimposed with the triangular signal.

6. Converter circuit according to claim 5, characterized in that the positive reference current (I _re f +) is obtained by adding a reference current (I _re fo) with a positive variation (AI _re f ++) of the current of reference.

7. Converter circuit according to claim 5 or 6, characterized in that the negative reference current (I _ref -) is obtained by adding a reference current (I _ref o) with a negative variation (AI _ref .) Of reference current.

8. Converter circuit according to claim 6 or 7, characterized in that the reference current (I _ref o) is obtained from a reference current of a load of the rectifier.

9. Converter circuit according to claim 6, characterized in that the positive variation (AI _{ref +} ) of the reference current is a signal from a corrector having as input:

an upper reference voltage (V _ref _ _sup ), and

one of the positive intermediate DC voltages.

Converter circuit according to Claim 9, characterized in that one of the positive intermediate DC voltages is the highest intermediate DC voltage.

11. Converter circuit according to claim 7, characterized in that the negative variation (AI _ref -) of the reference current is a signal from a corrector having as input:

an upper reference voltage (V _ref _ _sup ), and

one of the negative intermediate DC voltages.

Converter circuit according to Claim 11, characterized in that one of the negative intermediate DC voltages is the most negative DC DC voltage.

Converter circuit according to one of Claims 4 to 12, characterized in that the stage switching circuit is powered by:

a positive stage switching parameter (V * _{st +} ) coming from a corrector having as input a lower reference voltage (V _ref jn _f ) and one of the positive intermediate DC voltages, and

a negative stage switching parameter (V * _st- ) coming from a corrector having as input the lower reference voltage (V _ref jn _f ) and one of the negative intermediate DC voltages.

14. The converter circuit as claimed in claim 13, characterized in that one of the positive or negative intermediate DC voltages is the highest or the lowest positive DC voltage, respectively.

15. Converter circuit according to any one of claims 9 to 14, characterized in that the very high performance correctors are proportional integral type derivative fractional order.

16. Converter circuit according to any one of the preceding claims, characterized in that the outer arms each comprise two IGBT transistors provided with an internal diode anti-parallel, these two IGBT transistors being connected in series by their emitter.

17. System comprising two converter circuits according to any one of the preceding claims, one of the two converter circuits being configured as a rectifier, the other inverter; the two converter circuits being arranged back-to-back.