EP2798415A2 - Étalonnage d'un compteur de temps charge-numérique - Google Patents

Étalonnage d'un compteur de temps charge-numérique

Info

Publication number
EP2798415A2
EP2798415A2 EP12813377.4A EP12813377A EP2798415A2 EP 2798415 A2 EP2798415 A2 EP 2798415A2 EP 12813377 A EP12813377 A EP 12813377A EP 2798415 A2 EP2798415 A2 EP 2798415A2
Authority
EP
European Patent Office
Prior art keywords
calibration
charge
phase
phases
digital timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12813377.4A
Other languages
German (de)
English (en)
Inventor
Petri Heliö
Petri Korpi
Paavo Väänänen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OCT Circuit Technologies International Ltd
Original Assignee
ST Ericsson SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/338,390 external-priority patent/US8659360B2/en
Priority claimed from US13/338,550 external-priority patent/US8618965B2/en
Application filed by ST Ericsson SA filed Critical ST Ericsson SA
Publication of EP2798415A2 publication Critical patent/EP2798415A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

Definitions

  • the invention described herein generally relates to time-to-digital converters that measure a time difference separating two signals, and more particularly relates to calibrating a charge-to-digital timer.
  • TDCs Time-to-Digital Converters
  • RF Radio Frequency
  • PLL Phase-Locked Loop
  • TDCs may also be used to detect light/photons in nuclear medical imaging, e.g., Positron Emission Tomography (PET), for Time- Of-Flight (TOF) measurements, e.g., in radiation detection and in laser radars, and in a variety of other space, nuclear, and measurement science applications.
  • nuclear medical imaging e.g., Positron Emission Tomography (PET)
  • TOF Time- Of-Flight
  • TDC Charge-to-Digital Timer
  • the basic architecture for a conventional CDT comprises a current source, an integrator, and a flash analog-to-digital converter, such as disclosed in "Fast TDC for On-Line TOF Using Monolithic Flash AID
  • Another exemplary TDC comprises a Vernier Delay Line (VDL), which uses a Complementary Metal-Oxide Semiconductor (CMOS) buffer/inverter delay to measure the time difference between the start and stop signals.
  • VDL Vernier Delay Line
  • CMOS Complementary Metal-Oxide Semiconductor
  • the TDC may achieve resolutions smaller than those achievable with a single inverter delay. For example, a VDL may achieve -20 ps resolution with a 65 nm CMOS process.
  • TDCs used for PLLs rely on delay line based phase quantization.
  • the calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to- digital timer to address at least some of the above-described problems associated with conventional calibration techniques.
  • the calibration method disclosed herein measures multiple calibration phases based on multiple start and stop signals separated by known time differences, and therefore having known phases, and adjusts at least one of the capacitive load and the charging current of the charge-to-digital timer based on the measured calibration phases. In so doing, the disclosed calibration method optimizes the quantization step to minimize the quantization noise over a large frequency range.
  • One exemplary method initializes a capacitive load and a charging current of a charge-to-digital timer.
  • first start and stop signals separated in time by a first number of oscillator cycles are applied to the charge-to-digital timer to measure a first calibration phase during a first calibration time period
  • second start and stop signals separated in time by a second number of oscillator cycles are applied to the charge-to-digital timer to measure a second calibration phase during a second calibration time period.
  • the second number of oscillator cycles has a known relationship to the first number of oscillator cycles.
  • the calibration method further includes adjusting at least one of the capacitive load and the charging current based on the first and second calibration phases.
  • the calibration method is implemented responsive to a calibration instruction during an open-loop process independent from closed-loop operations of the charge-to-digital timer, where the closed-loop operations are used to measure unknown time differences between start and stop signals.
  • the calibration method is continuously implemented in parallel with the closed-loop operations of the charge-to-digital timer.
  • Figure 1 depicts a block diagram of a digital phase-locked loop (DPLL) according to one exemplary embodiment.
  • DPLL digital phase-locked loop
  • Figure 2 depicts a block diagram of one exemplary charge-to-digital timer for the DPLL of Figure 1.
  • Figure 3 depicts an exemplary calibration process for the charge-to-digital timer of Figure 2.
  • Figure 4 depicts a block diagram of one exemplary calibration system for a charge- to-digital timer associated with a phase-locked loop.
  • Figure 5 depicts a block diagram of one exemplary phase detector for the calibration system of Figure 4.
  • Figure 6 depicts a block diagram of another exemplary phase detector for the calibration system of Figure 4.
  • Figure 7 depicts a circuit diagram for an exemplary charge-to-digital timer.
  • Figure 8 depicts an exemplary adjustment process for the calibration process of Figure 3.
  • Figure 9 depicts a circuit diagram for another exemplary charge-to-digital timer.
  • Figure 10 depicts another exemplary adjustment process for the calibration process of Figure 3.
  • Figures 11 A-11 C depict simulated calibration results using the calibration process disclosed herein.
  • Figures 12A-12C depict measurement values for the exemplary adjustment process of Figure 10.
  • Figures 13A-13E depict additional simulated calibration results using the calibration process disclosed herein.
  • the calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer based on calibration phases measured by the charge-to-digital timer for known time differences having corresponding known phases. While the calibration method disclosed herein generally applies to charge-to-digital timers, it will be appreciated that the disclosed calibration method may apply to other time-to- digital converters.
  • FIG. 1 shows a block diagram of one exemplary DPLL 10 comprising a digital phase detector/filter 20, a digitally controlled oscillator (DCO) 30, and phase quantizer 40 comprising a counter 50 and the CDT 100 disclosed herein.
  • Phase quantizer 40 quantizes the phase of the signal output by the DCO 30.
  • counter 50 counts the integer number of DCO cycles to determine PhaseN , which represents an integer measurement of the instantaneous DCO phase
  • CDT 100 determines PhaseF , which represents a fractional measurement of the instantaneous DCO phase, based on the elapsed time between start and stop signals applied to the CDT 100 ( Figure 2).
  • Digital phase detector/filter 20 determines a phase error between the input frequency control word (FCW) and the quantized phase provided by the CDT 100, where the output phase error controls the DCO 320 to generate an output signal at a desired frequency. As disclosed further herein, calibrating the CDT 100 improves the performance of the DPLL 10 by improving the accuracy of the quantized phase output by the CDT 100.
  • FCW input frequency control word
  • Measurement unit 120 measures the time between the start and stop signals during a measurement phase that begins after the stop signal is applied to the measurement unit 120 by first determining the fractional phase associated with the time difference between the start and stop signals and converting the determined phase to an estimated time difference. During closed-loop non-calibration operations, measurement unit 120 outputs the estimated time T esl .
  • measurement unit 120 outputs the fractional phase, PhaseF .
  • measurement unit 120 comprises a voltage stepping unit 122, including a known capacitive load 123, a comparator 124, and an estimation unit 125 comprising a control unit 126 and a converter 128.
  • Voltage stepping unit 122 outputs a ramping voltage V x and a fixed voltage V 2 , where one of V y and V 2 is derived from a load voltage generated by the capacitive load 123 responsive to the charging current I ch , and where the voltage stepping unit 122 ramps V in a plurality of discrete voltage steps. Each discrete voltage step used to ramp V x is also output to the control unit 126.
  • Comparator 124 outputs a trigger to the estimation unit 125 when a comparison between V x and V 2 satisfies a
  • estimation unit 125 estimates the load voltage V load est based on V 2 and a combination of the discrete voltage steps associated with the voltage stepping unit 122, and then outputs the fractional phase PhaseF , which is also denoted herein as PF , which represents a numerical estimate of the DCO clock phase. More particularly, control unit 126 samples the state of the buffer line associated with the voltage steps (see Figures 7 and 9), and outputs an index (BN) to the converter 128 representative of the combination of the discrete voltage steps. During calibration operations, converter 128 converts the format of the load voltage V loaJ est to generate PhaseF .
  • converter 128 may determine an estimate of the elapsed time T esl based on the capacitance of the capacitive load 123, the known current, and an estimated load voltage V load est determined based on BN.
  • V load est directly depends on the phase because the sum of the discrete voltage steps should correspond to one oscillator cycle.
  • the calibration operations disclosed herein adjust the capacitive load 123 and/or I chg so that the sum of the discrete voltage steps presents one oscillator cycle.
  • FIG. 3 depicts one exemplary calibration method 200 for charge-to-digital timer 100.
  • first start and stop signals are applied during a first calibration period to the measurement unit 120, which outputs a first calibration phase PF ⁇ n based on the first start and stop signals as described above (block 220), where the first start and stop signals are separated in time by a first number of oscillator cycles.
  • the charge-to-digital timer 100 outputs a second calibration phase PF cal2 based on second start and stop signals applied during a second calibration period to the measurement unit 120 as described above (block 230), where the second start and stop signals are separated in time by a second number of oscillator cycles having a known relationship to the first number of oscillator cycles.
  • the capacitive load 123 and/or I ch are subsequently adjusted based on the first and second calibration phases (block 240).
  • the calibration process (blocks 220-240) repeats as necessary.
  • the calibration process 200 occurs during open-loop operations of the charge-to-digital timer 100 independent of any closed-loop operations, e.g., responsive to a calibration command.
  • calibration process 200 may continuously occur in parallel with the closed-loop operations.
  • FIG 4 depicts a block diagram of a calibration system 300 that may be used to calibrate the charge-to-digital timer 100 according to the process 200 of Figure 3.
  • Calibration system 300 includes the charging unit 110 and measurement unit 120 of the charge-to-digital timer 100, a calibration controller 310, and a sync unit 60.
  • the calibration system 300 also includes the counter 50 and phase detector 22 (which is included in the digital phase detector/filter 20 of Figure 1).
  • Sync unit 60 generates and synchronizes the start and stop signals with an oscillator clock (DCO clock) and a reference clock (REF clock) according to a sync control signal received from the calibration controller 310, where the number N CYC of oscillator cycles per REF clock may be determined based on the oscillator frequency f DCO and the REF clock frequency f REF , e.g., according to:
  • a first number of oscillator cycles after the sync unit 60 applies a first start signal to the measurement unit 120 the sync unit 60 applies a first stop signal to the measurement unit 120.
  • the sync unit 60 applies a second stop signal to the measurement unit.
  • the time difference separating the first start and stop signals generally corresponds to a first number of whole oscillator cycles known to the calibration controller 310.
  • the time difference separating the second start and stop signals also generally corresponds to a second number of whole oscillator cycles known to the calibration controller 310.
  • the second number of whole oscillator cycles have a know relationship to the first number of whole oscillator cycles.
  • the first number of whole oscillator cycles may comprise m oscillator cycles
  • the second number of whole oscillator cycles may comprise m + n oscillator cycles.
  • the calibration controller 310 calibrates the charge-to-digital timer 100 based on the non-zero differences, e.g., by adjusting the load capacitance and/or the charging current of the charge-to-digital timer 100. For example, the calibration controller 310 may subtract PhaseF l and PhaseF 2 to determine an instantaneous fractional frequency, and subtract PhaseN ⁇ and PhaseN 2 to determine an instantaneous integer frequency, and subsequently adjust the capacitive load 123 and/or the charging current based on the integer and fractional frequencies.
  • the calibration operations may further include optimizing the performance of the DPLL.
  • calibration controller 310 may also output a digital gain control signal to a phase detector 22 of the DPLL to control the quantization gain of the phase, as depicted in Figure 4.
  • the digital gain control signal may be used to generate a scaling factor applied to fractional phases determined during the closed-loop charge-to-digital timer operations (e.g., non-calibration operations used to measure unknown time differences).
  • phase detector 22 may be presented according to the following z-domain transfer function: ⁇ (z) (2) where FCW represents a frequency control word for a digital reference frequency and F scak represents a scaling factor.
  • the scaling factor which may e.g., be retrieved from a look-up table responsive to the digital gain control signal scales one or more of the phases determined during closed-loop charge-to-digital timer operations, as depicted in Figure 5.
  • the z "1 blocks represent a unit delay of one REF clock cycle
  • the LUT block represents the look-up table of scaling factors
  • FreqN represents an integer frequency derived from
  • FreqF represents an instantaneous fractional frequency derived from consecutive PhaseF
  • ACC represents an accumulator for converting a measured frequency to a PLL phase.
  • Figure 6 shows an alternative structure for determining F scale responsive to the digital gain control signal, where F scale is calculated based on FreqN , FreqF , the gain control signal, the sync control signal, and various mathematical operations.
  • the z "1 blocks represent a unit delay of one REF clock cycle
  • FreqN represents an integer frequency derived from consecutive PhaseN values
  • FreqF represents an instantaneous fractional frequency derived from consecutive PhaseF
  • ACC represents an accumulator for converting a measured frequency to a PLL phase.
  • Figures 7 and 9 depict exemplary charge-to-digital timers 100, while Figures 8 and 10 respectively depict the corresponding adjustment process 240.
  • the timers 100 in Figures 7 and 9 both comprise a charging unit 1 10 with a current source to generate the charge current I chg , and a voltage stepping unit 122 that receives I chg during a charge phase and outputs V and V 2 to the comparator 124 during a measurement phase.
  • the differences between the timers 100 of Figures 7 and 9 lie in the configuration of the voltage stepping unit 122.
  • the following focuses on the specific implementations of the voltage stepping units 122, followed by details of the corresponding adjustment process 240.
  • the voltage stepping unit 122 of Figure 7 sets V x equal to V load and step-wise ramps V load for comparison relative to a fixed reference voltage
  • V 2 V ref .
  • a first input of comparator 124 receives V 2 from an external source, e.g., an external controller, and a second input of the comparator 124 receives V x from the voltage stepping unit 122.
  • the voltage stepping unit 122 comprises a plurality of serially connected buffers 130, a first switch S ⁇ 140, a second switch S 2 142, a third switch S 3 144, a variable scale capacitor C s 134, a variable gain capacitor C 136, a parasitic capacitance C p 138, and a plurality of ramp capacitors C r 132, where the charging unit 1 10 charges C p , C s , C , and the ramp capacitors during the charge phase to generate the charged capacitive load 123.
  • Scale capacitor C s 134 operatively connects at a first node to the output of the charging unit 1 10 and the second input of the comparator 124, and at a second node to a common node of the ramp capacitors 132.
  • Gain capacitor C g 136 connects between the second node of C s 134 and ground, while the parasitic capacitance 138 is modeled as being connected between the second input of the comparator 124 and ground.
  • each buffer 130 comprises a digital buffer that functionally implements a switching function to switch the buffer output from a first fixed voltage, e.g., 0 V, to second fixed voltage, e.g., V dd , during the ramping of the measurement phase when the reference clock passes through the buffer chain.
  • a charge is injected into the capacitive network formed by the N ramp capacitors C r
  • the total capacitance C tot in this case is formed by C g in parallel with the series connection of C s and C p and in parallel with C rl , C r2 , and C r3 .
  • the voltage step depends on V dd and C rJ I C tot .
  • the first switch 5, 140 connects between the output of the charging unit 1 10 and the first node of C s 134.
  • the second switch S 2 142 connects in parallel with C g 136, and the third switch 5*3 144 connects in parallel with C p 138.
  • S l 140 is actuated to a closed position while S 2 and S 3 142, 144 are maintained in an open position to enable the capacitive load 123 to charge responsive to I chg , where the charged capacitive load 123 may be defined by:.
  • S x 140 is actuated to the open position to disconnect the charge unit 110 from the voltage stepping unit 122, while S 2 and S 3 142, 144 remain in the open position.
  • S 2 and S 3 142, 144 are actuated to the closed position to enable the capacitive load 123 to discharge to ground.
  • Capacitive load 123 comprises a variable scale capacitor C s 134, a variable gain capacitor C g 136, a parasitic capacitance C p 138, and a plurality of ramp capacitors C r 132.
  • the initial value of V load ramps e.g., increases, by a first voltage step stored in the first ramp capacitor C rX 132a, and the voltage stepping unit 122 outputs the first voltage step to the controller 126.
  • Figure 8 depicts an adjustment process 240 for the exemplary calibration process 200 of Figure 3 for the charge-to-digital timer 100 of Figure 7, where in this example, the calibration process 200 and adjustment process 240 occurs during open-loop operations of the charge-to-digital timer 100 independent of the normal closed-loop timer operations.
  • the calibration controller 310 subtracts the first and second calibration phases to determine a phase difference PF diff (block 241 ). Further, calibration controller 310 either compares PF ⁇ to a first threshold TH l , or compares PF 2 to a second threshold TH 2 (block 242), and compares PF diff to a difference threshold TH diff (block
  • calibration controller 310 adjusts at least one of the capacitive load and I chg (block 244).
  • the calibration controller 310 may adjust C s based on the comparison between PF and ⁇ ⁇ , or between PF cal2 and TH 2 , and may adjust
  • FIG. 9 depicts an alternative charge-to-digital timer 100
  • V ref V ref
  • the voltage stepping unit 122 provides both V x and V 2 to respective first and second inputs of the comparator 124.
  • the voltage stepping unit 122 comprises a plurality of serially connected buffers 130, a first switch S, 140, a second switch S 2 142, a third switch S 4 146, a fourth switch S 5 148, a variable gain capacitor C 136, a charge capacitor C chg 152, a plurality of ramp capacitors C r
  • the charging unit 1 10 charges only C chg , which represents the capacitive load 123 in this embodiment, during the charge phase.
  • the voltage over the capacitive load 123 still changes during the charge phase responsive to I ch , where the charge time changes between consecutive reference cycles, e.g., by one DCO cycle.
  • the changing charge times gives a difference in charged voltage, which equals to one DCO cycle in time.
  • Scale capacitors C sl 150a and C s2 150b operatively connect between a common node of the N ramp capacitors C r 132 and an input to the buffers 130, where the fourth switch S 5 148 selectively connects the second scale capacitor
  • the first and second scale capacitors C sl 150a and C s2 150b are sized to match the amount of charge difference applied to the charge capacitor C chg 152 during the charge phase between consecutive reference clock cycles.
  • Gain capacitor C g 136 connects between the second input of the comparator 124 and ground, while , 152 connects between the first input of the comparator 124 and a power supply. While not explicitly shown, it will be appreciated that C chg may be tunable.
  • a charge is injected into the capacitive network formed by the ramp capacitors C r 132, the gain capacitor C g 136, and the first scale capacitor C sl 150a as the reference clock passes through the buffer chain.
  • the fourth switch closes causing the capacitive network to further include the second scale capacitor C s2 150b.
  • the step height of each voltage step during the measurement phase depends on V dd and the capacitance ratio C rj /C tot , where C m represents the total capacitance seen from the comparator input to ground, represents the buffer stage, and C ri represents the unit capacitance for the z ' th buffer stage.
  • C rl may alternatingly be determined according to:
  • the total capacitance C tot may thus be determined for all reference clock cycles according to:
  • First switch S l 140 connects between the output of the charging unit 1 10 and the first input of the comparator 124, while second switch S 2 142 connects in parallel with C g 136 and third switch S 4 146 connects in parallel with C ch 152.
  • 140 is actuated to the closed position while S 2 and S 4 142, 146 are maintained in the open position to enable the capacitive load 123 to charge responsive to I chg .
  • S l 140 is opened to disconnect the charge unit 1 10 from the voltage stepping unit 122, while S 2 and S 4 142, 146 remain in the open position.
  • S 5 may start the measurement phase in either the position connecting C s2 to ground or C s2 to a first buffer 130a output, and thereafter alternatingly changing the position responsive to alternating reference clock cycles.
  • S l 140 is opened, while S 2 and S 4 142, 146 are actuated to the closed position to enable the capacitive load 123, e.g., C chg , and the remaining capacitors in the voltage stepping unit 122 to discharge to ground.
  • the initial value of V ref ramps, e.g., increases, by a first voltage step stored in the first ramp capacitor C rX 132a, and the voltage stepping unit 122 outputs the first voltage step to the controller 126.
  • the adjustment process 240 of Figure 8 may be applied to the charge-to-digital timer 100 of Figure 9.
  • the calibration controller 310 may adjust C g based on the comparison between PF X and TH X or the comparison between PF 2 and TH 2 , and may adjust C chg or I ch based on the comparison between PF diff and TH diff .
  • the adjustment process 240 of Figure 10 may be used with the charge- to-digital timer 100 of Figure 9, where in this case, the calibration operations continuously occur in parallel with the normal closed-loop charge-to-digital timer operations.
  • the adjustment process 240 comprises counting the integer number of oscillator cycles DCO l between the first start and stop signals to determine a first integer phase PN X (block 245), and counting the integer number of oscillator cycles DC0 2 between the second start and stop signals to determine a second integer phase PN 2 (block 246).
  • a first instantaneous frequency f x is determined based on a difference between the first and second integer phases
  • a second instantaneous frequency f 2 is determined based on a difference between the first and second fractional phases (block 247).
  • the calibration controller 310 adjusts at least one of the capacitive load 123 and the charging current based on f x and f 2 (block 248).
  • the calibration controller 310 may adjust at least one of C g and I ch based on f x and f 2 .
  • the adjustment process/step 240 of Figure 10 may also be applied to the charge-to-digital 100 of Figure 7. In this case, the calibration controller 310 may adjust at least one of C , C s , and I ch based on f x and f 2 .
  • an exemplary phase detector 22 of DPLL may scale PF and/or PN during closed-loop operations based on a scaling factor Fscale .
  • the calibration controller 310 may also estimate Fscale during the calibration process based on f 2 , where the calibration controller 310 applies the estimated scaling factor to the fractional phases determined during the closed-loop operations (independently from the calibration operations). It will be appreciated that when the calibration process associated with Figure 8 is used, the scaling factor is determined during the open-loop calibration operations, and is applied during the closed-loop non-calibration operations. When the calibration process associated with Figure 10 is used, the scaling factor is determined during the closed-loop calibration operations, and is applied during the closed-loop non-calibration operations.
  • the first and second calibration periods comprise consecutive calibration periods, such that the second start and stop signals of the second calibration period are applied to the charge-to-digital timer after the first start and stop signals of the first calibration period are applied to the charge-to-digital timer.
  • the first and second calibration phases are determined during the first and second calibration periods and are stored, e.g., in memory, and the calibration controller 310 implements the calibration process based on the stored first and second calibration phases.
  • the adjustment process 240 of Figures 8 and 10 may be more directly applied to the charge-to-digital timer 100 of Figure 7 according to the following detailed steps:
  • the calibration time may be predefined as a fixed number of reference
  • the calibration time may comprise a variable time defined as the time required to stabilize C s and/or C g , e.g., 5 ⁇ for C s and 8 ⁇ for C g , as depicted in Figures 11A-11 C.
  • the calibration controller 310 may use the difference value determined in step 8 to estimate a scaling factor Fscale for scaling the PhaseF measurement obtained during closed-loop operations.
  • Fscale is inversely proportional to the difference value determined in step 8.
  • one open-loop embodiment closes S 5 148 at all times to keep C s2 connected to ground at all times, while another open-loop embodiment implements open-loop calibration operations for both positions of S 5 148, which is more complex and time consuming.
  • a measurement control loop runs in parallel with a calculation loop to determine the first and second calibration phases to implement a calibration process based on multiple first and second calibration phases. For example, the first start and stop signals of the first calibration period followed by the second start and stop signals of the second calibration period are repeatedly applied during the measurement control loop, which comprises a plurality of consecutive first and second calibration periods. One or more first and second calibration phases are determined for one or more of the corresponding first and second calibration periods during the calculation loop, which runs in parallel with the measurement control loop. In this case, the calibration controller 310 tracks the first calibration phases determined during the calculation loop to determine a minimum calibration phase, and tracks the second calibration phases during the calculation loop to determine a maximum calibration phase.
  • the calibration controller 310 then compares the minimum calibration phase to a minimum threshold, e.g., TH l , or compares the maximum calibration phase to a maximum threshold, e.g., TH 2 , and determines the calibration difference PF dlff by subtracting the minimum and maximum calibration phases.
  • a minimum threshold e.g., TH l
  • a maximum threshold e.g., TH 2
  • the adjustment process 240 of Figures 8 and 10 may be more directly applied to the charge-to-digital timer 100 of Figure 7 according to the following detailed steps:
  • the calibration controller 310 may use the difference value to estimate a scaling factor Fscale for scaling the PhaseF measurement during closed-loop operations.
  • Fscale is inversely proportional to the difference value determined.
  • Figures 12A-12C depict exemplary signals for the maximum and minimum calibration phases, and the corresponding difference between the maximum and minimum calibration phases.
  • the measurement control loop may run for some predetermined time before the calculation loop begins running in parallel with the measurement control loop. For example, the measurement control loop may start running at t « 0.1 ⁇ , and the calculation loop may start running at t « 1 ⁇ , as depicted in Figure 12A.
  • Lines 500 and 510 in Figures 12A and 12B show the target value/value ranges where the difference between the minimum PhaseF and maximum PhaseF and the actual minimum PhaseF values, respectively, should converge.
  • Figures 13A-13E show an exemplary simulation of the calibration process associated with Figure 10.
  • the cycling of the calibration can be seen with the envelope of the charge voltage in Figure 13C.
  • Figure 13A shows the ripple ( ⁇ 8) generated by the gain error where the gain error measurement and the calibration begins. The gain error is monitored digitally in phase detector 22.
  • the charge current is tuned (Figure 13B) so as to minimize the ripple in PhaseF (Figure 13D), which causes the converter to be optimized for certain frequencies, as shown by the frequency error data of Figure 13E. It will be appreciated that the gain error measurement result can also be used to tune the digital gain scaling factor.
  • FIGS 2, 4, 7, and 9 show the start and stop signals as being applied to the measurement unit 120
  • the start and stop signals may alternatively be applied to the charging unit 110 when the corresponding switches are also included in the charging unit 110.
  • the start signal is generally applied to switch S 3 (and optionally switch S 2 ) and the stop signal is generally applied to switch S l .
  • the switches controlled by the start and stop signals will also be part of the charging unit 110 in such a way as to make the same type of connections shown in Figures 7 and/or 9.

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  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
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Abstract

Procédé d'étalonnage qui permet l'étalonnage d'une charge capacitive et/ou d'un courant de charge commandant un compteur de temps charge-numérique (CDT). En général, selon ledit procédé d'étalonnage, des phases d'étalonnage multiples sont mesurées sur la base de signaux de démarrage et d'arrêt séparés par une différence de temps connue, et ayant par conséquent une phase connue, et la charge capacitive et/ou le courant de charge du CDT sont ajustés sur la base des phases d'étalonnage mesurées. Ainsi, le procédé d'étalonnage décrit permet de réduire la dissipation de puissance et les courants de crête sur la plage de fréquences du CDT.
EP12813377.4A 2011-12-28 2012-12-27 Étalonnage d'un compteur de temps charge-numérique Withdrawn EP2798415A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/338,390 US8659360B2 (en) 2011-12-28 2011-12-28 Charge-to-digital timer
US13/338,550 US8618965B2 (en) 2011-12-28 2011-12-28 Calibration of a charge-to-digital timer
PCT/EP2012/076994 WO2013098357A2 (fr) 2011-12-28 2012-12-27 Étalonnage d'un compteur de temps charge-numérique

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EP2798415A2 true EP2798415A2 (fr) 2014-11-05

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107884780B (zh) * 2016-09-30 2021-03-26 比亚迪股份有限公司 测距方法、激光雷达及车辆

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2224759A1 (en) * 1973-04-05 1974-10-31 Onera (Off Nat Aerospatiale) Period to voltage convertor for testing FM units - displays dots rising or falling with period
DE3834938C1 (fr) * 1988-10-13 1989-12-07 Horst Prof. Dipl.-Phys. Dr. 4790 Paderborn De Ziegler
US8098085B2 (en) * 2009-03-30 2012-01-17 Qualcomm Incorporated Time-to-digital converter (TDC) with improved resolution
EP2388923B1 (fr) * 2010-05-21 2013-12-04 Stichting IMEC Nederland Convertisseur analogique/numérique de pente numérique asynchrone et procédé associé

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2013098357A2 *

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