EP2779761B1 - Méthode et appareil d'acquisition de synchronisation dans un système d'accès multiple à répartition de code. - Google Patents

Méthode et appareil d'acquisition de synchronisation dans un système d'accès multiple à répartition de code. Download PDF

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Publication number
EP2779761B1
EP2779761B1 EP13179496.8A EP13179496A EP2779761B1 EP 2779761 B1 EP2779761 B1 EP 2779761B1 EP 13179496 A EP13179496 A EP 13179496A EP 2779761 B1 EP2779761 B1 EP 2779761B1
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Prior art keywords
frame
sub
hypothesis
values
downlink synchronization
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German (de)
English (en)
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EP2779761A3 (fr
EP2779761A2 (fr
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Myung-Joon Shim
Seung-Hwan Won
Sang-Won Choi
Jong-Gun Moon
Jong-Yoon Hwang
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects

Definitions

  • the present invention relates to a Code Division Multiple Access (CDMA) system. More particularly, the present invention relates to a method and an apparatus for acquiring frame synchronization in a CDMA system.
  • CDMA Code Division Multiple Access
  • Time Division Duplex (TDD) scheme is applied to a CDMA system, and the CDMA system based on the TDD scheme can use the same frequency band shared by both a downlink and an uplink and freely control and operate data capacities thereof by changing allocation of Time Slots (TSs) depending on the situation.
  • TSs Time Slots
  • TD-SCDMA Time Division Synchronous Code Division Multiple Access
  • FIG. 1 illustrates a structure of a sub-frame used in TD-SCDMA according to the related art.
  • one sub-frame includes seven TSs having the same length for data transmission and a Special Time Slot (STS).
  • STS is used to distinguish between the downlink and the uplink, and includes a Downlink Pilot Time Slot (DwPTS), a Guard Period (GP), and an Uplink Pilot Time Slot (UpPTS).
  • DwPTS and the UpPTS include information for physical transmission synchronization. For example, a sequence for synchronization of forward link transmission is transmitted in a DwPTS field and a sequence for synchronization of reverse link transmission is transmitted in an UpPTS field.
  • the TS in which data transmission is performed includes a data symbol interval and a mid-amble, wherein user data is included in the data symbol interval and pilot signal information for a channel estimation is included in the mid-amble.
  • TS0 is mainly used for data transmission for a broadcasting channel within a cell
  • TS1 to TS6 are used for forward or reverse data transmission.
  • D and U within each TS block refer to the downlink and the uplink, respectively.
  • FIG. 2 illustrates a structure of a DwPTS used for initial synchronization acquisition in a downlink according to the related art.
  • the DwPTS includes GP and SYNC-DL codes.
  • the SYNC-DL code is transmitted with constant power and is not spread. Power of a SYNC-DL sequence is determined by higher layer signaling.
  • the initial synchronization acquisition generally includes three operations described below and may be embodied in various types according to the implementation.
  • Operation 1 Search of the DwPTS and identification of the SYND-DL sequence.
  • a SYNC-DL sequence index is determined by performing slot synchronization by using the SYNC-DL sequence in the DwPTS in a Second TS (STS) of one sub-frame. This is determined through a comparison between a threshold and a maximum value among 32x6400 hypotheses acquired by performing a correlation through a matched filter. At this time, it may be required to acquire a plurality of hypotheses in consideration of several cells and the number of effective multi-path for each cell.
  • STS Second TS
  • Operation 2 Identification of Scrambling and basic mid-amble codes.
  • a corresponding mid-amble code group can be known from the SYNC-DL sequence acquired in the first operation, and a corresponding mid-amble code is identified among four basic mid-amble codes included in the group. The identified mid-amble code is equally used during one sub-frame. Further, since a relation between the mid-amble code and the scrambling code corresponds to a one-to-one correspondence mapping relation, when the mid-amble code is determined, the scrambling code is automatically determined. A correlation between the mid-amble code and the scrambling code is shown in Table 1 below.
  • Operation 3 Control multi-frame synchronization.
  • a phase of a channel value through a mid-amble of a Primary-Common Control Physical CHannel (P-CCPCH) is reflected to the SYNC-DL, and a position of a control multi-frame is determined by using information on a phase of the DwPTS.
  • P-CCPCH Primary-Common Control Physical CHannel
  • Operation 4 Broadcasting Channel (BCH) decoding.
  • BCH Broadcasting Channel
  • channels related to initial synchronization having the structure shown in FIG. 1 are periodically received. More particularly, since the SYNC-DL including 64 chips is received every 5 ms interval in TD-SCDMA, the TD-SCDMA system has relatively low detection capabilities in comparison with Wide-band Code Division Multiple Access (W-CDMA)/Frequency Division Duplex (FDD) systems in which initial synchronization is acquired using successively received pilot channels.
  • W-CDMA Wide-band Code Division Multiple Access
  • FDD Frequency Division Duplex
  • phase modulation based on the phase of the mid-amble of the first time slot (i.e., a time-slot 0) when modulating the DwPCH and a phase modulation value equally remains during one sub-frame.
  • phase quadruple Four phase modulation values acquired during four successive sub-frames are referred to as "phase quadruple", and there are two types of phase quadruple, such as S1 and S2.
  • Table 2 below shows meanings of S1 and S2.
  • the P-CCPCH is a physical channel into which the BCH corresponding to a transport channel is mapped.
  • Table 2 Case Phase quadruple Meaning S1 135, 45, 225, 135 The P-CCPCH is in next four sub-frames.
  • S2 315, 225, 315, 45 The P-CCPCH is not in next four sub-frames.
  • a frame synchronization acquisition searcher performing the third operation of the initial synchronization acquisition estimates the "phase quadruple" during four sub-frames and determines whether the estimated "phase quadruple” corresponds to S1 or S2.
  • the frame synchronization acquisition searcher determines that there is the P-CCPCH in a next sub-frame and starts receiving the BCH transmitted through the P-CCPCH.
  • the process of estimating the "phase quadruple” includes a process of estimating a phase modulation value of a downlink SYNC-DL for each sub-frame.
  • a method of the related art for performing the process is largely classified into the following two methods.
  • the method of (1) first estimates the phase value through a complex multiplication of the received downlink synchronization code and the synchronization code already known to the terminal. Thereafter, a modulated phase of the downlink synchronization code is calculated by applying arctangent and hard decision is performed. Thereafter, "phase quadruple" corresponding to the modulated phase value during four sub-frames is compared with S1 and S2. As a result of the comparison, when “phase quadruple” corresponds to S1, the BCH is received in four following sub-frames. When “phase quadruple” does not correspond to S1, it is determined that there is no BCH in the four following sub-frames, so that the process of estimating "phase quadruple” is continuously repeated.
  • the method of estimating the modulated phase value of the downlink synchronization code by using arctangent generally replaces the operation of arctangent with table mapping by a look up table. Accordingly, since a lot of table values should be stored in a memory for the accurate operation, the memory is excessively increased. Further, the modulated phase value of the downlink synchronization code may be distorted by a frequency offset and channel, and significantly degrades accuracy of a result estimated through the method particularly in an environment where a level of the received signal is low. Accordingly, in the method using the phase of the downlink synchronization code by the hard decision, calculation of the accurate phase modulation value is difficult.
  • the method of (2) uses a correlation value between the received signal and the reference vector by using the reference vector for the phase in order to address the issues of method of (1). Further, the method of (2) performs a frame synchronization estimation in consideration of all available phase modulation possibilities and the frequency offset. Specifically, with respect to M successive sub-frames transmitted from the base station, a phase difference between the downlink synchronization code and the mid-amble code included in each sub-frame is acquired. Thereafter, a complex inner product of the reference vector corresponding to a vector expression of M reference phase values and the phase vector corresponding to a vector expression of phase differences acquired for the M successive sub-frames, and the frame synchronization is estimated using the calculated inner value. When the frame synchronization is estimated by the calculated inner value, a threshold may vary depending on existence or non-existence of the frequency offset or size of the frequency offset.
  • the method of (2) has a condition based on a frequency offset value generated in a multi-path fading channel, and the frequency offset should be estimated in advance to determine the condition. Further, a frequency offset estimation value should be compared with a reference value. When the estimation value and the reference value are similar to each other, thresholds used herein may be relatively inaccurate values.
  • the frequency offset is estimated through a general method in the TDD system, it takes a lot of time corresponding to a minimum of dozens to over one hundred sub-frames according to accuracy of the frequency offset. In analyzing a convergence degree of the frequency offset under various multi-path environments, the frequency offsets converge on significantly different values behind a specific observation section, and one reference value has a difficulty in satisfying the various multi-path environments. Accordingly, "phase quadruple" estimated in an actual environment through the method degrades the accuracy.
  • the two methods degrade detection capabilities in an area, such as a cell boundary, and have a high probability of generating a false alarm according to the channel and residual frequency offset values. Accordingly, the time corresponding to a minimum of 50 sub-frames should be additionally used for residual frequency offset compensation to successfully decode the BCH.
  • an aspect of the present invention is to provide a method and an apparatus for acquiring efficient initial frame synchronization and for estimating a residual frequency offset in a Code Division Multiple Access (CDMA) downlink system based on a Time Division Duplex (TDD) scheme.
  • CDMA Code Division Multiple Access
  • TDD Time Division Duplex
  • a method of acquiring downlink frame synchronization in a code division multiple access mobile communication system includes phase-rotating a mid-amble of a first Time Slot (TS) of a received sub-frame within an area and estimating a Channel Impulse Response (CIR), calculating a Maximum Likelihood (ML) between a downlink synchronization code of the received sub-frame and a downlink synchronization code generated in a terminal by using the estimated CIR, correlating downlink synchronization codes of a plurality of sub-frames and the downlink synchronization code generated in the terminal and calculating ML values of the plurality of sub-frames with respect to the plurality of sub-frames corresponding to M Transmission Time Intervals (TTIs), calculating hypothesis values of hypotheses according to a frequency interval and a phase offset of the generated downlink synchronization code based on the calculated ML values of the plurality of sub-frames and drawing a frequency offset and a hypothesis
  • TTIs Transmission Time Intervals
  • an apparatus for acquiring downlink frame synchronization in a code division multiple access mobile communication system includes a CIR estimator configured to phase-rotate a mid-amble of a first TS of a received sub-frame within an area and estimates a CIR, an ML value calculator configured to calculate an ML between a downlink synchronization code of the received sub-frame and a downlink synchronization code generated in a terminal by using the estimated CIR, and configured to correlate downlink synchronization codes of a plurality of sub-frames and the downlink synchronization code generated in the terminal and calculate ML values of the plurality of sub-frames with respect to the plurality of sub-frames corresponding to M TTIs, a frequency offset and hypothesis estimator configured to calculate hypothesis values of hypotheses according to a frequency interval and a phase offset of the generated downlink synchronization code based on the calculated ML values of the plurality of sub-frames and configured to draw a frequency offset corresponding
  • a Code Division Multiple Access (CDMA) based system In a Code Division Multiple Access (CDMA) based system, all channels are distinguished by a channelization code, and information on the cell can be acquired through reception of control related information transmitted from the base station. Accordingly, the terminal requires acquisition of information on initial synchronization of the desired cell to acquire the control related information. Further, since there is a channel including information for initial synchronization acquisition in a specific Time Slot (TS), the Time Division Duplex (TDD) system should perform an initial synchronization acquisition process by acquiring timing of a pilot sequence, such as the SYNC-DL code of Time Division Synchronous Code Division Multiple Access (TD-SCDMA) periodically transmitted and a code IDentification (ID).
  • a pilot sequence such as the SYNC-DL code of Time Division Synchronous Code Division Multiple Access (TD-SCDMA) periodically transmitted and a code IDentification (ID).
  • FIG. 3 illustrates a Primary-Common Control Physical CHannel (P-CCPCH) transmission type according to an embodiment of the present invention.
  • P-CCPCH Primary-Common Control Physical CHannel
  • a frame synchronization acquisition searcher acquires frame synchronization based on phase information carried on a SYNC-DL signal transmitted for each sub-frame and determines whether there is the P-CCPCH in four following sub-frames.
  • a multi-path searcher estimates a position of a Channel Impulse Response (CIR) through a basic mid-amble index of time slot 0 detected in the second operation and estimates a channel phase in the position.
  • a reference SYNC-DL signal is made through convolution with the local SYNC-DL signal estimated in the first operation. By taking Maximum Likelihood (ML) between the made reference SYNC-DL signal and the received SYNC-DL signal, phase information of the received SYNC-DL signal can be acquired.
  • CIR Channel Impulse Response
  • ML Maximum Likelihood
  • the phase information of the SYNC-DL signal transmitted in every sub-frame is compared with S1 and S2 of Table 2.
  • TTI Transmission Time Interval
  • P-CCPCH transmission is periodically generated. Further, in principle, the P-CCPCH is repeatedly transmitted by the number of times in each cycle, and matters, such as a repeated interval and a repeated length, are determined by higher layer signaling.
  • Table 3 shows common TS information, and FIG. 3 illustrates a transmission form of the P-CCPCH using the common TS information.
  • Table 3 Information Element/Group name Type and reference Semantics description Repeated interval Integer(1, 2,4,8,16,32,64) Default is continuous allocation. Value 1 indicate continuous Repeated length Integer (1... Repetition period -1) NOTE: This is empty if repetition period is set to 1.
  • the frame synchronization acquisition searcher uses a phase of the SYNC-DL code included in every sub-frame to determine whether there is the P-CCPCH coded over one TTI. As described above, it can be determined whether the P-CCPCH exists according to a phase pattern of the SYNC-DL code, and the phase pattern is made over a total of four sub-frames, so that it takes a minimum of one TTI time for frame synchronization acquisition. In order to improve the detection capability, the frame synchronization can be detected using a time corresponding to a multiple of the TTI. However, when the observation section increases, the number of hypotheses according to the phase pattern increases in proportion to the increase of the observation section.
  • the number of hypotheses is "N" in one TTI
  • the number of hypotheses increases two times, that is, "2N" in two TTIs. Accordingly, it is possible to control the capability of the frame synchronization acquisition searcher by using various TTI sections.
  • FIG. 4 illustrates a configuration of a frame synchronization acquisition searcher according to an embodiment of the present invention.
  • the frame synchronization acquisition searcher includes a CIR estimator 410, an ML value calculator 420, a frequency offset and hypothesis estimator 430, and a post processor 440.
  • the CIR estimator 410 phase-rotates the received mid-amble of time slot 0 within -/+ X [Hz] area at regular frequency intervals and estimates the CIR.
  • the MR value calculator 420 calculates an ML value between the received SYNC-DL code of the sub-frame and the SYNC-DL code according to four phases generated in a local generator (not shown) by using the estimated CIR, correlates the generated SYNC-DL and the received SYNC-DL, and calculates the ML value of the corresponding sub-frame. Accordingly, ML values are calculated by performing such a process over a total of M TTIs.
  • the frequency offset and hypothesis estimator 430 operates a total of (2*X/Y+1)*M*N hypothesis values according to hypotheses by a frequency interval Y and a phase offset value of the SYNC-DL code determined based on the calculated ML values and draws a frequency and a hypothesis corresponding to a maximum value among the hypothesis values. Further, the frequency offset and hypothesis estimator 430 generates reference phase offset sets within a +/- X[Hz] range by using the CIR and estimates a residual frequency offset by using the generated reference phase offset sets. The post processor 440 compares an estimation result of the frequency offset and hypothesis estimator 430 with a preset hypothesis to determine whether to end the frame synchronization acquiring process.
  • a controller for controlling re-performance of some or all of the synchronization acquiring processes may be further included.
  • the controller corrects the residual frequency offset by an Auto Frequency Control (AFC), and controls calculation of the ML values through the ML value calculator 420.
  • AFC Auto Frequency Control
  • the controller identifies whether the drawn hypothesis is included in the hypothesis indicating successful synchronization acquisition.
  • the controller determines that the synchronization acquisition is successful.
  • the controller identifies whether the number of times that the synchronization is attempted exceeds the number of times. When the number of times that the synchronization is attempted does not exceed the number of times, the controller controls the residual frequency offset by the AFC and controls the ML value calculator 420 to re-calculate the ML values.
  • FIG. 5 is a flowchart illustrating a frame synchronization acquiring process according to an embodiment of the present invention.
  • initial input parameters M, N, X, Y, and L are initialized at operation 501.
  • M refers to the number of sub-frames calculating ML values for frame synchronization acquisition
  • N refers to the number of hypotheses corresponding to one TTI
  • X refers to a range within which a phase rotation is performed
  • Y refers to a frequency interval
  • L refers to the maximum number of times that frame synchronization acquisition is performed.
  • the received mid-amble of time slot 0 is phase-rotated within a -/+ X [Hz] area at regular frequency intervals and the CIR is estimated.
  • an ML value of a corresponding sub-frame is calculated by correlating the received SYNC-DL and the SYNC-DL code according to four phases generated in a local generator by using the estimated CIR.
  • FIGS. 6A to 6C illustrate a method of calculating a Maximum Likelihood (ML) value for frame synchronization acquisition according to an embodiment of the present invention.
  • ML Maximum Likelihood
  • the ML value of the sub-frame can be calculated through one of the following three methods.
  • a total of (2*X/Y+1)*M*N hypotheses are operated according to hypotheses by the frequency interval Y and the phase offset of the SYNC-DL code based on the ML value calculated at operation 504, and a frequency and a hypothesis corresponding to a maximum ML value are drawn at operation 506.
  • the maximum ML value is compared with a threshold at operation 507. When the maximum ML value exceeds the threshold, the process proceeds to operation 509 in which hypothesis post processing is performed. When the maximum ML value does not exceed the threshold, it is determined that the residual frequency offset is still large, so that the process proceeds to operation 508 in which the residual frequency offset is corrected by the AFC, and returns to operation 504.
  • the hypothesis post processing is performed at operation 509, it is identified whether the estimated hypothesis is included in the hypothesis indicating successful synchronization acquisition at operation 510.
  • the hypothesis is included in the hypothesis indicating the successful synchronization acquisition, it is determined that the frame synchronization acquisition is successful and thus, the frame synchronization acquisition process ends.
  • a position of a frame boundary varies according to the phase offset of the SYNC-DL code, and the frame synchronization acquisition is completed after a corresponding offset of a sub-frame length according to each combination.
  • the hypothesis is not included in the hypothesis indicating the successful synchronization acquisition, it is identified whether the total number of times that the synchronization acquisition is attempted exceeds L times at operation 511.

Claims (16)

  1. Un procédé d'acquisition d'une synchronisation de trame en liaison descendante dans un système de communication mobile à accès multiples par répartition de code, le procédé comprenant :
    la rotation de phase d'un milieu d'amble d'un premier intervalle de temps (TS) d'une sous-trame reçue à l'intérieur d'une zone et l'estimation d'une réponse impulsionnelle de canal (CIR),
    le calcul d'une probabilité maximale (ML) entre un code de synchronisation en liaison descendante de la sous-trame reçue et un code de synchronisation en liaison descendante généré dans un terminal au moyen de la CIR estimée,
    la corrélation de codes de synchronisation en liaison descendante d'une pluralité de sous-trames correspondant à M intervalles temporels de transmission (TTI) et du code de synchronisation en liaison descendante généré dans le terminal et le calcul de valeurs de ML de la pluralité de sous-trames,
    le calcul de valeurs d'hypothèse d'hypothèses en fonction d'un intervalle de fréquence et d'un décalage de phase du code de synchronisation en liaison descendante généré dans le terminal en fonction des valeurs de ML calculées de la pluralité de sous-trames et la déduction d'un décalage de fréquence et d'une hypothèse correspondant à une valeur maximale parmi les valeurs d'hypothèse calculées, et
    la comparaison d'une valeur maximale des valeurs de ML à un seuil et la détermination qu'une acquisition de synchronisation de trame a réussi lorsque la valeur maximale des valeurs de ML est supérieure au seuil et l'hypothèse déduite est incluse dans une hypothèse indiquant une acquisition de synchronisation réussie.
  2. Le procédé selon la Revendication 1, où le calcul de la ML entre le code de synchronisation en liaison descendante de la sous-trame reçue et le code de synchronisation en liaison descendante généré dans le terminal comprend au moins une opération parmi :
    le calcul de la ML par la corrélation du code de synchronisation en liaison descendante de la sous-trame reçue et du code de synchronisation en liaison descendante généré dans le terminal, qui reflète un décalage de phase de référence généré à l'intérieur de la zone,
    le calcul de la ML par le reflet d'un décalage de phase de référence généré à l'intérieur de la zone vers le code de synchronisation en liaison descendante de la sous-trame reçue et la corrélation du code de synchronisation en liaison descendante de la sous-trame reçue et du code de synchronisation en liaison descendante généré dans le terminal, et
    le calcul de la ML par le reflet d'un décalage de phase de référence généré à l'intérieur de la zone vers le code de synchronisation en liaison descendante généré dans le terminal et la corrélation du code de synchronisation en liaison descendante généré dans le terminal et du code de synchronisation en liaison descendante de la sous-trame reçue.
  3. Le procédé selon la Revendication 1, comprenant en outre :
    la commande d'un décalage de fréquence résiduel par le reflet du décalage de fréquence déduit.
  4. Le procédé selon la Revendication 1, où, lorsque la valeur maximale des valeurs de ML est égale ou inférieure au seuil, un décalage de fréquence résiduel est commandé et le procédé revient à l'estimation de la CIR.
  5. Le procédé selon la Revendication 1, où, une fois qu'il est déterminé que l'acquisition de synchronisation de trame a réussi, l'acquisition de synchronisation de trame est achevée après une durée correspondant au décalage de fréquence dans une sous-trame correspondante.
  6. Le procédé selon la Revendication 1, où, lorsque l'hypothèse déduite n'est pas incluse dans l'hypothèse indiquant l'acquisition de synchronisation réussie, il est déterminé que l'acquisition de synchronisation de trame a échoué et le procédé revient au calcul des valeurs de ML de la pluralité de sous-trames après une durée correspondant au décalage de fréquence dans une sous-trame correspondante.
  7. Le procédé selon la Revendication 6, où, lorsque l'hypothèse déduite n'est pas incluse dans l'hypothèse indiquant l'acquisition de synchronisation réussie, il est identifié si un nombre de fois où l'acquisition de synchronisation est tentée dépasse un nombre de fois, et il est déterminé que l'acquisition de synchronisation de trame a échoué lorsque le nombre de fois où l'acquisition de synchronisation est tentée dépasse le nombre de fois et, lorsque le nombre de fois où l'acquisition de synchronisation est tentée ne dépasse pas le nombre de fois, le procédé revient au calcul des valeurs de ML de la pluralité de sous-trames.
  8. Un appareil d'acquisition d'une synchronisation de trame en liaison descendante dans un système de communication mobile à accès multiples par répartition de code, l'appareil comprenant :
    un estimateur de réponse impulsionnelle de canal (CIR) configuré de façon à mettre en rotation de phase un milieu d'amble d'un premier intervalle de temps (TS) d'une sous-trame reçue à l'intérieur d'une zone et à estimer une CIR,
    un calculateur de valeurs de probabilité maximale (ML) configuré de façon à calculer une ML entre un code de synchronisation en liaison descendante de la sous-trame reçue et un code de synchronisation en liaison descendante généré dans un terminal au moyen de la CIR estimée, et configuré de façon à corréler des codes de synchronisation en liaison descendante d'une pluralité de sous-trames correspondant à M intervalles temporels de transmission (TTI) et le code de synchronisation en liaison descendante généré dans le terminal et à calculer des valeurs de ML de la pluralité de sous-trames,
    un estimateur de décalage de fréquence et d'hypothèse configuré de façon à calculer des valeurs d'hypothèse d'hypothèses en fonction d'un intervalle de fréquence et d'un décalage de phase du code de synchronisation en liaison descendante généré dans le terminal en fonction des valeurs de ML calculées de la pluralité de sous-trames et configuré de façon à déduire un décalage de fréquence correspondant à une valeur maximale parmi les valeurs d'hypothèse calculées et une hypothèse, et
    un post-processeur configuré de façon à comparer une valeur maximale des valeurs de ML à un seuil et à déterminer qu'une acquisition de synchronisation de trame a réussi lorsque la valeur maximale des valeurs de ML est supérieure au seuil et que l'hypothèse déduite est incluse dans une hypothèse indiquant une acquisition de synchronisation réussie.
  9. L'appareil selon la Revendication 8, où le calculateur de valeurs de ML calcule la ML entre le code de synchronisation en liaison descendante de la sous-trame reçue et le code de synchronisation en liaison descendante généré dans le terminal par la corrélation du code de synchronisation en liaison descendante de la sous-trame reçue et du code de synchronisation en liaison descendante généré dans le terminal, qui reflète un décalage de phase de référence généré avec la zone, ou par le reflet d'un décalage de phase de référence généré à l'intérieur de la zone vers le code de synchronisation en liaison descendante de la sous-trame reçue et la corrélation du code de synchronisation en liaison descendante de la sous-trame reçue et du code de synchronisation en liaison descendante généré dans le terminal, ou par le reflet d'un décalage de phase de référence généré à l'intérieur de la zone vers le code de synchronisation en liaison descendante généré dans le terminal et la corrélation du code de synchronisation en liaison descendante généré dans le terminal et du code de synchronisation en liaison descendante de la sous-trame reçue.
  10. Le procédé selon la Revendication 1 ou l'appareil selon la Revendication 8, où les valeurs d'hypothèse sont calculées par l'équation suivante (2*X/Y+1)*M*N, dans laquelle X désigne une zone où une rotation de phase est exécutée, Y désigne un intervalle de fréquence et N désigne un nombre d'hypothèses correspondant à un TTI.
  11. L'appareil selon la Revendication 8, où l'estimateur de décalage de fréquence et d'hypothèse commande un décalage de fréquence résiduel par le reflet du décalage de fréquence déduit.
  12. L'appareil selon la Revendication 8, comprenant en outre :
    un dispositif de commande configuré de façon à commander un décalage de fréquence résiduel par une commande de fréquence automatique (AFC) et à commander un calcul des valeurs de ML de la pluralité de sous-trames par l'intermédiaire du calculateur de valeurs de ML lorsque la valeur maximale des valeurs de ML est égale ou inférieure au seuil.
  13. L'appareil selon la Revendication 8, où, après la détermination que l'acquisition de synchronisation de trame a réussi, le post-processeur achève l'acquisition de synchronisation de trame après une durée correspondant au décalage de fréquence dans une sous-trame correspondante.
  14. L'appareil selon la Revendication 12, où, lorsque l'hypothèse déduite n'est pas incluse dans l'hypothèse indiquant l'acquisition de synchronisation réussie, le dispositif de commande détermine que l'acquisition de synchronisation de trame a échoué et commande le calcul des valeurs de ML de la pluralité de sous-trames par l'intermédiaire du calculateur de valeurs de ML après une durée correspondant au décalage de fréquence dans une sous-trame correspondante.
  15. L'appareil selon la Revendication 14, où, lorsque l'hypothèse déduite n'est pas incluse dans l'hypothèse indiquant l'acquisition de synchronisation réussie, le post-processeur identifie si un nombre de fois où l'acquisition de synchronisation est tentée dépasse un nombre de fois et détermine que l'acquisition de synchronisation de trame a échoué lorsque le nombre de fois où l'acquisition de synchronisation est tentée dépasse le nombre de fois.
  16. L'appareil selon la Revendication 15, où, lorsque le nombre de fois où l'acquisition de synchronisation est tentée ne dépasse pas le nombre de fois, le dispositif de commande commande le calcul des valeurs de ML de la pluralité de sous-trames par l'intermédiaire du calculateur de valeurs de ML.
EP13179496.8A 2013-03-11 2013-08-06 Méthode et appareil d'acquisition de synchronisation dans un système d'accès multiple à répartition de code. Not-in-force EP2779761B1 (fr)

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CN104053225B (zh) 2018-10-12
CN104053225A (zh) 2014-09-17
EP2779761A3 (fr) 2016-10-19
US20140254562A1 (en) 2014-09-11
US9025569B2 (en) 2015-05-05
KR20140111464A (ko) 2014-09-19
EP2779761A2 (fr) 2014-09-17
KR102023373B1 (ko) 2019-09-23

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