EP2647157A1

EP2647157A1 - Method and apparatus for performing symmetrical stream encryption of data

Info

Publication number: EP2647157A1
Application number: EP11796910.5A
Authority: EP
Inventors: René-Michael Cordes; Ernst Schobesberger
Original assignee: Individual
Current assignee: Individual
Priority date: 2010-12-02
Filing date: 2011-12-01
Publication date: 2013-10-09
Also published as: WO2012071597A1; AT510730B1; US20170264598A1; AT510730A1

Abstract

In a method for performing symmetrical stream encryption of data using a key stream and for transmitting the encrypted data, wherein the key stream is generated using at least one feedback shift register which is filled with a defined bit sequence in order to initialize it, the data to be encrypted are split into data packets, with each data packet being encrypted separately. The feedback shift register(s) is/are reinitialised for the encryption of each data packet, with the feedback shift register(s) being initialized by using at least a first bit sequence and a second bit sequence in each case, wherein the first bit sequence is added to the respectively encrypted data packet in plain text or in encoded form and the second bit sequence represents a secret key, which is not added to the encrypted data packets. The encrypted data packets are transmitted in packet-switched fashion together with the respective added bit sequence and possibly header data.

Description

Method and apparatus for performing symmetric stream encryption of data

The invention relates to a method for performing a symmetric stream encryption of data using a keystream and for transmitting the encrypted data, wherein the generation of the keystream is performed using at least one feedback shift register, which is filled to its initialization with a defined bit sequence.

The invention further relates to a corresponding method for decrypting encrypted data by means of a symmetric stream encryption.

The invention further relates to a device for encrypting data by means of a symmetric stream encryption using a keystream, wherein for generating the keystream at least one fed-back shift register is provided, which is filled to its initialization each with a defined bit sequence. The invention further relates to a device for decrypting encrypted data by means of a symmetric stream encryption.

Current encryption is a cryptographic algorithm in which characters of the plain text are linked individually with the characters of a key stream. In the case of power encryption of digital data - only the characters 0 and 1 are used - the clear text stream is linked to the keystream using the XOR function. The keystream is a pseudo-random string. Most stream ciphers use a symmetric key. The key determines the initial state of the system.

At least one feedback shift register is used to generate the keystream. Linear feedback shift registers can be efficiently implemented both directly in hardware such as FPGAs and in software. Feedback shift registers are fast and produce pseudo-random sequences with good statistical properties. A feedback shift register is implemented in digital technology as a shift register with n memory elements. The individual memory elements are typically D flip-flops, which can each store one bit. In contrast to a conventional shift register, there are branches between certain D flip-flops, which represent the feedback. For feedback, an XOR function is usually used in each case. Instead of the XOR link, however, an XNOR link can also be used.

For initialization, the shift register can be filled with XOR feedback with arbitrary values which determine the key stream generated by the shift register in the sequence. Like any other shift register, the feedback shift register also has a clock input: at each clock pulse, the sequence state is changed, ie when a bit is to be output, all bits in the shift register are shifted by one memory location; the new bit at the end of the shift register is calculated depending on the other bits. This process counts as one bar. For a complete run of all combinations 2 ^n_1 clock pulses are necessary. Such a code sequence thus has a length of 2 ^n_1 bits (n = number of code-generating units). W

- 3 - connected in series memory elements of the shift register). As a key-current generator, a plurality of linear feedback shift registers are generally used, which are usually of different lengths and have different feedback polynomials. This combines linear feedback shift registers to non-linear generators.

The greater the length of the code sequence of the key stream or the code, the harder it is to decrypt. For example, an infinite code did not need to be hidden because it is never known. Functionally, any code that is not repeated before the end of the information to be encrypted is considered to be infinite. A functionally infinite code has the disadvantage that it can not be transmitted; it has to be generated.

A disadvantage of code generators in the form of conventional feedback shift registers is the fact that the structure of the generator can easily be deduced from the code sequence, so that it can be regenerated with an identically constructed generator. A significant improvement is achieved in this regard by the known from WO 03/075507 AI code generator.

Another disadvantage of conventional data stream encryption is the fact that it can only be used for packet-switched data transmission (eg, via the Internet via the IP protocol) while reducing encryption security. In the case of packet-switched data transmission, each data packet must be encrypted separately and used for the encryption of each data packet. W

The key used must be known to the recipient for the purpose of decryption in order to enable decryption even if individual data packets are lost, packets arrive twice at the receiver, packets take different paths or packets arrive fragmented at the receiver. The simplest way to guarantee a clear assignment of data with the key or keystream even under the conditions of these malfunctions is to use the same key stream for each data packet. This makes it easier to break the encryption.

The present invention therefore aims to provide a method and an apparatus for encrypting and / or decrypting data using a power encryption and decryption, wherein the encrypted data should be in packets of any size, so that they are simultaneous Transmission of high frequency binary data streams over long periods in packet-organized data networks are suitable. The encryption should be as secure as possible, with a break in the encryption should be virtually impossible.

In order to achieve this object, according to a first aspect of the invention, the encryption method of the type mentioned at the outset is developed in such a way that the data to be encrypted are divided into data packets, that each data packet is encrypted separately, wherein the feedback shift register (s) for the Ver - Initialization of each data packet is reinitialized or, wherein for initialization of the or the feedback shift register respectively at least a first bit sequence and a second bit sequence is used, wherein the first bit sequence is added to the respective encrypted data packet in plain text or in coded form and the second bit sequence represents a secret key which is not added to the encrypted data packets, and in that the encrypted data packets together with the respective added bit sequence and possibly header data are transmitted packet-switched.

In order to decrypt the data packets, it is provided according to a second aspect of the invention that the data to be decrypted are received as data packets, that each received data packet is decrypted separately, wherein the feedback shift register (s) for the decryption of each data packet is re-initialized or de-initialized In each case, at least one first bit sequence and one second bit sequence are used to initialize the feedback shift register, the first bit sequence being read out of the respective data packet to be decrypted in plaintext or in coded form and the second bit sequence representing a secret key that can not be read from the data packets to be decrypted.

Thus, according to the invention, all the information required for the decryption of each individual data packet except the secret key is carried in the respective packet, so that the communication partners only have to exchange the secret key or the information required for the generation of the secret key before the data transmission. Since, according to the invention, each data packet contains the first bit sequence in plain text or in coded form which was used to encrypt the respective data packet, this first bit sequence can be read from the recipient of the respective data package and used for decrypting. This makes it possible to encrypt each data packet with a different key, thus making it difficult to break the encryption. If, as is the case with a preferred procedure, the first bit sequence selected is a bit sequence which is unique to the data packet to be encrypted and which is added to the respective encrypted data packet as a packet identifier in plain text or in coded form, it is ensured that two data packets with the same clear text content are not are also encrypted identically, so the encrypted data packets differ from each other. Conclusions on the transmitted characters by a statistical evaluation of the data packets are made more difficult.

The second bit sequence, ie the secret key, is preferably generated from a unique identifier of the sender and a unique identifier of the recipient. As a unique identifier here, for example, a hardware identifier of the transmitter or the receiver can be used, in particular a stamped chip number or the like. The generation of the second bit sequence is preferably done by linking the unique identifier of the transmitter and the unique identifier of the receiver using a XOR function. For this it is necessary that the transmitters and receivers exchange their identifiers before the data transmission. As mentioned, the first and second bit sequences are used in the context of encryption and decryption to initialize the feedback shift register (s). This is done especially when generating the key stream only a single feedback shift register is used, such that the first and the second bit sequence are linked by means of an XOR function and the result of the combination bit sequence for initialization is supplied to the feedback shift register. Alternatively, and in particular for the case where at least two feedback shift registers interconnected with one another are used for generating the key stream, the procedure is such that at least a first feedback shift register is filled with the first bit sequence for its initialization and at least one second feedback loop is filled Shift register is filled to its initialization with the second bit sequence. This procedure makes it difficult to determine the structure of the key-current generator and / or the secret key on the basis of the first bit sequence transmitted in plain text.

An even higher level of security results if, as is the case with another preferred procedure, a third bit sequence is used for initializing the feedback shift register (s). The third bit sequence is generated with advantage from a current date and / or time. The third bit sequence is preferably fed for initialization to a third feedback shift register.

A further advantage of the method according to the invention is that the generation of the keystream can already begin as soon as at least one of the feedback shift registers is filled with the first bit from the respective bit sequence. In particular, the feedback shift registers become simultaneously with the respective bit sequence filled.

As is known per se, the structure of the key-current generator is preferably such that at least one XOR gate is used for the feedback of the shift register or registers. The complexity of the generator can be increased in a simple manner in that the feedback shift registers are interconnected in such a way that, depending on the state of a shift register, the at least one XOR gate of the other shift register is switched on or off.

A highly preferred development results when a code generator is used, as described in WO 03/075507 AI, reference being made to claims 15 and 16 and 31 to 36 of the present application. With such a code generator, the encryption can not even be broken if both the structure of the code generator and the algorithm running in it are known. Namely, the structure of the generator is such that it is capable of generating such a large number of different codes in such a large length that the discovery of the code just used as well as the currently produced position in the code sequence is extremely small Probability is possible. The code can not be regenerated if the generator can create so many different codes that one section of the single code can not conclude its continuation.

According to another aspect of the present invention, an encryption and a decryption direction.

The device according to the invention for encrypting data by means of a symmetric stream encryption using a key stream, wherein at least one feedback shift register is provided for generating the key stream, which is filled in each case with a defined bit sequence for its initialization, characterized in that the data in that there are provided means for generating and / or storing at least one first bit sequence and a second bit sequence which interact with the shift register (s) such that at least the first bit sequence and the second bit sequence are used for initialization the feedback shift register (s) are re-initialized for the encryption of each data packet, and data packet processing means are provided with which the means for generating or storing are provided n of the first and the second bit sequence cooperate in such a way that the first bit sequence is added to the respective encrypted data packet in plain text or in coded form and the second bit sequence represents a secret key which is not added to the encrypted data packets and in that data transmission means are packet-switched Sending the encrypted data packets together with the respective added bit sequence and possibly header data are provided. The device according to the invention for decrypting data encrypted by means of a symmetric stream encryption using a keystream, at least one being used for generating the keystream. peltes shift register is provided, which is filled in each case with a defined bit sequence for its initialization, is characterized in that the encrypted data is divided into data packets that means for reading a first bit sequence in plain text or in coded form from the data packets and means for generating and / or storing at least one second bit sequence which cooperate with the shift register (s) such that at least the first bit sequence and the second bit sequence are used to initialize the feedback shift register (s), the feedback one or more (n) shift register is re-initialized for the decryption of each data packet, the second bit sequence representing a secret key which can not be read from the encrypted data packets.

Preferred developments emerge from the subclaims.

The invention will be explained in more detail below with reference to embodiments shown schematically in the drawing. 2 shows a decoding device according to the invention, FIGS. 3, 4, 5 and 6 show various configurations of a key-current generator used in the device.

In Fig. 1, a data packet to be encrypted is designated by 1, wherein the data packet 1 comprises a plurality of bits in plain text. The encryption is carried out in principle such that the bits of the bit stream 2 of the plaintext with the bits of a keystream 3 individually by means of a XOR gates 4 are linked. The generation of the key flow 3 is a code generator 5, which will be described in more detail with reference to FIGS. 3 to 6. The code generator 5 generates the key stream 3 on the basis of a plurality of bit strings 6, 7 and 8, which are supplied to the code generator 5 as a key. A first bit sequence 6 is stored in a memory 9 and represents a unique identifier of the data packet 1 to be encrypted. The uniqueness here must be given at least within the total number of data packets to be transmitted coherently. The length of the first bit sequence is thus at least log (N; 2) bits (N = total number of transmitted packets). The second bit sequence 7 is stored in a memory 10 and is generated from a unique identifier 11 of the sender and a unique identifier 12 of the receiver. The generation of the second bit sequence 7 takes place in that the bits of the unique identifier 11 and the bits of the unique identifier 12 are linked together by means of an XOR gate 13. Due to the use of the second bit sequence 7 as the key for the generation of the key stream 3, it is ensured that only the recipient, who must also be aware of the unique identifiers 11 and 12, can decrypt the encrypted data packets. The third bit sequence 8 is stored in a memory 14 or is generated there, based on a current date or time. For example, the bit sequence 8 corresponds to the current date. As a result, key stream 3 has a completely different structure every day, making it difficult to break encryption.

The encrypted data of the data packet are now supplied to data packet processing means 15, with which the memory 9 cooperates for the first bit sequence 6 such that the first bit sequence 6 is added to the encrypted data packet in plain text. By contrast, the second bit sequence 7 and the third bit sequence 8 are not added to the encrypted data packet, but are known anyway at the receiver. The data packet processing means 15 further ensure that the encrypted data packet is provided with the usual header data required for the packet-switched transmission in a computer network. The data packet prepared for the transmission thus consists of header data 16, the first bit sequence as packet identifier 17 and the encrypted user data 18. The data transmission means for packet-switched transmission of the data packet are designated by 19.

The device shown in Fig. 2 for decrypting the encrypted data packets is constructed essentially analog. The packet containing the header data 16, the first bit sequence as packet identifier 17 and the encrypted user data 18 is supplied on arrival to read means 20, in which the second bit sequence 17 is read out and fed to a memory 21. The encrypted user data 18 are subsequently fed to an XOR gate 22, in which the bits of the encrypted bit stream 23 and the bits of the keystream 3 are linked to one another in order to obtain the decrypted data packet 1 in this way.

The keystream 3 used to decrypt a particular data packet must be the same as the keystream used to encrypt that data packet. For this purpose, the same bit strings 6, 7 and 8 are supplied to the generator 5 as a key and used for decryption Generator 5 is identical to the generator 5 used for the encryption. The memory for the second bit sequence 7 is denoted by 24. The memory 24, the coupled via the XOR gate 25 transmitter and receiver identifiers 11 and 12 are supplied. The third bit sequence 8 is stored in the memory 26 or is generated there.

3 shows a basic circuit of a key-current generator 5 with a shift register 27, which consists of a plurality of memory elements which are combined to form a code-producing row, namely flip-flops FF1, FF2,... FF9. An XOR gate XORpl is connected so that one input of the XOR gate XORpl is connected to the output of the memory element FF2 located in the code-producing line, and the other input of the XOR gate XORpl is connected to the output of the memory element located in the code-producing line FF5 and the output of the XOR gates XORP1 is connected to the input of the memory element FF3 in the series downstream of the memory element FF3 connected in series with the one input of the XOR gate XORpl, in other words recursively. Furthermore, it can be seen that the last memory element FF9 is connected to the first memory element FF1 via an inverter INV. As soon as the shift register 27 is filled with a bit sequence, a code sequence is obtained with this circuit. If, as is the case with the embodiment according to FIG. 3, only a single shift register is used, the bit sequences 6, 7 and 8 are supplied to the shift register 27 in such a way that first the bit sequences 6 and 7 are reset by means of an XOR Gate 28 are linked together and then the linked bit sequence with the bit string 8 using the XOR gate 29 is linked. It is preferred that the generated from the bit sequences 6, 7 and 8, the Shift register 27 is not longer than this corresponds to the number of memory elements in the shift register 27, since the bit sequence would otherwise be superimposed ge of the next via the inverter INV from the memory elements FF9 Bitfol- ge.

In the modified embodiment according to FIG. 4, a total of three shift registers 30, 31 and 32 are used. The memory elements of the individual shift registers are interconnected recursively in this example in the same way as in FIG. 3. The shift registers are further interconnected such that the function of the XOR gate XORpl of the recursive interconnection depends on the state of the second shift register 31 of the first shift register 30 is switched on and off. The function of the XOR gate XORppl of the recursive connection of the second shift register 31 is in turn switched on and off in dependence on the state of the third shift register 32. For this purpose, the output of the flip-flop FFp2 or FFpp2 of the one shift register 31 and 32, respectively, is connected to the input of an AND gate ANDpl or UNDppl, which is connected to the respective recursive function XORpl or XORppl of the shift registers 30 and 31, respectively is inserted. The result is a code generator 5 with three levels, wherein the code generation is influenced on each level by initializing the respective shift register 30, 31 and 32 with the bit sequence 6, 7 and 8. In this case, the initialization can preferably take place such that the first bit sequence 6 is supplied to the shift register 30 of the first level, the second bit sequence 7 to the shift register 31 of the second level, and the third bit sequence 8 to the shift register 32 of the third level, the bit sequences 6, 7 and 8 is preferred are defined as in FIGS. 1 and 2 described.

In the embodiment according to FIG. 5, the structure shown in FIG. 4 is made even more complex and, in particular, longer code-producing series and a plurality of recursive interconnections are provided. In this case, a number of continuously connected in series memory elements in the form of shift registers SRG1, SRG2, ... realized that functionally together form a shift register 33 in the context of the invention. It doubles the length of the code per added memory element, so the length of the code is calculated as follows

Lc = 2 ⁿ -l

(Lc = length of the code sequence, n = number of code-generating memory elements connected in series)

If this unit is operated with a specific clock, the duration of the code is as follows:

2 ⁿ - 1

Tc =

fc

(Tc = duration until code repeats; fc = code generation rate frequency)

With less than 50 memory elements at a code generation clock rate of 384,000 bps, the code runs for more than a year without repeating the sequence so that a signal to be encrypted can be sent and decrypted encrypted over a long period of time over a dedicated line so that transfers Live over an equally long period are possible.

If, with a corresponding length of the shift register 33, an XOR gate XORpl, p2, p3, is connected to a plurality of locations of this shift register 33 between a memory element FF1, 2, 3, 4 and the next in-line memory element FF2, 3, 4, 5 Inserting p4 and then feeding it with the signal from a third memory element FF8,15,20,23, so you changed each of the code generated thereby (Figure 5).

With a plurality of code-changing XOR gates XORpl, p2, p3, p4, see FIG. 5, it should be ensured that the various code-changing XOR gates XORpl, p2, p3, p, have their first input from an output of a memory element FF1, 2, 3, 4, each having its second input fed from the output of a memory element FF8, 15, 20, 23, which is a number of memory elements in the flow direction away from the first-mentioned memory element FF1, 2, 3, 4, respectively corresponds to a different prime number that is greater than 1 but not a fractional amount of the total number of memory elements connected in series R, so that no code sequence shortening resonance effects occur in influencing the code sequence. Between the corresponding memory element pairs FF1,8; FF2,15; FF3,20; Thus, FF4, 23 each has a number of 7, 13, 17 and 19 (prime numbers) memory elements.

If one of the two inputs of the respective XOR gate XORpl or XORpl, p2, p3, p4, the output of an AND gate UNDpl or ANDP1, p2, p3, p4 whose one input at the output of the memory element FF3 or FF8, 15,20,23 hangs, connects, then you can XORP this XOR gate or XORpl, p2, p3, p4 in its code-changing effect via the second input of the AND gate ANDP1 and ANDP1, p2, p3, p4 on and off and if you have a further memory element FFpl or FFpl, p2, p3, p4, the activation and deactivation of the code-influencing effect of the XOR gate XORpl or XORpl, 2, p3, p4 make programmable. The code-programming memory elements FFpl, p2, p3, p4 can be interconnected to form a shift register 34. As a further consequence, the code-programming memory elements FFpl, p2, p3, p4 shift register 34 can in turn be recursively interconnected with the aid of an XOR gate XORppl.

The number of programmable differences is calculated as follows:

Nc = 2 ^pn - 1

(Nc = number of possible different codes, pn = number of programmable XOR gates

XORpl, p2, ... pn)

Now, if you are in possession of an identical code generator, and want to deduce the further course of the code sequence on the basis of a certain number of bits, then the probability of recognizing the correct continuation of the code sequence depends both on the number of memory elements used in the code generation FFl, 2, ... n as well as those of the programmable, code-changing XOR gates XORpl, p2 pn. This results in a probability to discover the programming underlying the code and thus to predict the further course of the code from: Nb

W =

(2 ⁿ - 1) * (2 ^pn - 1)

(Nb = number of bits observed in the code sequence; n = number of code-generating series-connected memory elements FFl, 2, ... n; pn = number of programmable code-changing XOR gates XORpl, p2, ... pn)

Example:

233 is the 52nd prime. If one does not use 1 and 233 expresses the total number of memory elements connected in series, then there are 50 different memory elements on this path, which are each at a distance from an output memory element which corresponds to a prime number (np = 50). Since each recursive XOR gate 1-50 is turned on between a next memory element 1-50 starting from the first one in series, the total length of the memory elements is extended to (n = 233 + 50 = 283). It follows:

(2 ⁿ - 1) * (2 ^pn - 1) (2 ²⁸³ - 1) * (2 ⁵⁰ - 1)

Nb

(1, 5541351138 * 10 ⁸⁵ - 1) * (1, 1258999068 * 10 ¹⁵ - 1) Nb

1, 7498005798 * 10 ¹⁰⁰ In other words, you have to observe the code sequence 1.7498005798 * 10 ¹⁰⁰ clock steps long, so that with the probability 1 discovered a particular sequence. If the clock frequency is 384,000 Hz, this gives a necessary observation time of 1, 4449430312 * 10 ⁸⁷ years.

By recursively interconnecting the code-programmed memory elements (FFpl, p2, p3, p4, 5, p6) of the shift register 34 so that they are within the time interval

2 ^pn - 1

T pn =

fp

(T pn = flow time of all possible programming states; pn = number of program-storage elements; fp = Programming clock frequency) run through all possible state combinations, results in the programming of a certain time span ^¬ in which the code-programming storage elements are supplied with a program clock.

In order to ensure that the programming time can not be approximated, the programming can be carried out in two stages. For this purpose, another programming level can be added by connecting the code-repeating XOR gate XORppl itself, with the interposition of an AND gate UNDppl, to a memory element row RRR and thus making it programmable, again using an XOR gate XORpppl for the recursive Circuit of the shift register 37 is used (Figure 6). Based on the above calculation example, this ensures that the (2 ²⁸³ -l) * (2 ⁵⁰ -l) different states are decomposed into 2 ⁵⁰ -l different sections, one of which is selected in the first programming phase. This selection process is carried out in a maximum of 2 ^ppn - 1 steps (ppn = number of primes contained in the number of primes used in programming (50), ie 16). This means that a maximum of 2 ¹⁶ steps must be taken before all sections are visited. At a programming clock frequency of 1 MHz, this process is completed in 0.065 seconds. A period of time that is likely to be measured with each programming because it is below the reaction time of humans, which is why it is ensured that no conclusions about the programming of the keys can be drawn from the actually elapsed programming time.

Claims

Claims:

Method for performing a symmetric stream encryption of data using a key stream and for transmitting the encrypted data, wherein the generation of the key stream is performed using at least one feedback shift register which is filled with a defined bit sequence for its initialization, characterized in that the data to be encrypted are divided into data packets, that each data packet is encrypted separately, wherein the feedback shift register (s) for the encryption of each data packet are reinitialized, whereby the initialization of the data is back-triggered. At least one first bit sequence and a second bit sequence are used, wherein the first bit sequence is added to the respective encrypted data packet in plain text or in coded form and the second bit sequence represents a secret key which contains the versc keyed data packets is not added, and that the encrypted data packets are transmitted together with the respective added bit sequence and possibly header data packet-switched.

2. A method for decrypting encrypted by means of a symmetric stream encryption data using a keystream, wherein the generation of the keystream is carried out using at least one feedback shift register, which is filled to its initialization in each case with a defined bit sequence, characterized in that the decrypting data are received as data packets that each received data packet is decrypted separately, the or the feedback shift register (s) for the decryption of each data packet is reinitialized, wherein at least one first bit sequence and one second bit sequence are used to initialize the feedback shift register (s), the first bit sequence being from the respective one to be decrypted data packet in plain text or in coded form is read out and the second bit sequence represents a secret key that can not be read from the data packets to be decrypted.

3. The method according to claim 1 or 2, characterized in that the first and the second bit sequence are linked by means of an XOR function and the bit sequence resulting from the combination is fed to the feedback shift register for initialization.

4. The method of claim 1 or 2, characterized in that at least a first feedback shift register is filled to its initialization with the first bit sequence and at least a second feedback shift register is filled to its initialization with the second bit sequence.

5. The method according to any one of claims 1 to 4, characterized in that as the first bit sequence for the data packet to be encrypted unique bit sequence is selected, which is added to the respective encrypted data packet as a packet identifier in plain text or in coded form.

6. The method according to any one of claims 1 to 5, characterized in that the second bit sequence from a clear tigen identifier of the sender and a unique identifier of the recipient is generated.

7. The method according to claim 6, characterized in that the generation of the second bit sequence by linking the unique identifier of the transmitter and the unique identifier of the receiver by means of an XOR function.

8. The method according to any one of claims 1 to 7, characterized in that for initialization of the or the feedback shift register further a third bit sequence is used.

9. The method according to claim 8, characterized in that the third bit sequence is generated from a respective current date and / or time.

10. The method according to claim 8 or 9, characterized marked, that the third bit sequence for initialization is supplied to a third feedback shift register.

11. The method according to any one of claims 1 to 10, characterized in that the generation of the key stream begins as soon as at least one of the feedback shift registers is filled with the first bit from the respective bit sequence.

12. The method according to any one of claims 1 to 11, characterized in that the feedback shift registers are filled simultaneously with the respective bit sequence.

13. The method according to any one of claims 1 to 12, characterized in that at least one XOR gate is used to feed back the shift register or registers.

14. The method according to any one of claims 1 to 13, characterized in that the feedback shift registers are interconnected in such a way that depending on the state of a shift register, the at least one XOR gate of the other shift register is turned on or off.

15. The method according to any one of claims 1 to 14, characterized in that the at least one feedback shift register has a plurality of memory elements connected to a codeproduzierenden row, wherein the output of the last row in the memory element to the input of the first memory element in the row is connected together with the aid of the at least one XOR gate in such a way that the first input of the XOR gate with the output of a memory element located in the codeproducing row, the second input with the output of another in the code-producing row memory element and the output is connected to the input of the code-producing row in the memory element connected to the first input of the XOR gate subsequent memory element.

16. The method according to claim 15, characterized in that in the second input of the at least one XOR gate and the output of the other in the codeproducing row located memory element line connecting an AND gate is connected such that the output of the AND gate with the second input of the XOR gate, the first input of the AND gate is connected to the output of the further memory element located in the code-producing row, and the second input of the AND gate is connected to the output of a code-coding memory element, a memory element of a further feedback shift register being used as code-coding memory element, and in that preferably the output of a memory element located in the code-producing row is connected to the input of an inverter and the output of the inverter is connected to the input of another memory element arranged in the code-producing row.

17. An apparatus for encrypting data by means of a symmetric stream encryption using a keystream (3), in particular for carrying out the method according to one of claims 1 and 3 to 16, wherein at least one feedback shift register (11) is used to generate the keystream (3). 27, 30, 31, 32, 33, 34, 35, 36, 37), which is filled with a defined bit sequence for its initialization, characterized in that the data are divided into data packets (1) such that means ( 9, 10) are provided for generating and / or storing at least one first bit sequence (6) and a second bit sequence (7) which are connected to the shift register (s) (27; 30, 31, 32; 33, 34; 35, 36, 37) cooperate in such a way that at least the first bit sequence (6) and the second bit sequence (7) are used to initialize the feedback shift register (s) (27, 30, 31, 32; 33, 34; ), the feedback being) eregister (27; 30,31,32; 33.34; 35, 36, 37) for the encryption of each data packet (1) is reinitialized or that data packet processing is initiated. are provided, with which the means (9,10) for generating or storing the first (6) and the second (7) bit sequence cooperate in such a way that the first bit sequence (6) is transmitted to the respective encrypted data packet in plaintext ( 17) or in coded form and the second bit string (7) represents a secret key which is not added to the encrypted data packets, and that data transmission means (19) for packet-switching the encrypted data packets together with the respective added bit sequence (17) and if necessary . Header data (16) are provided.

18. An apparatus for decrypting data encrypted by means of a symmetrical stream encryption using a keystream (3), in particular for carrying out the method according to one of claims 2 to 16, wherein at least one feedback shift register (27; 31,32; 33,34; 35,36,37), which is filled in each case with a defined bit sequence for its initialization, characterized in that the encrypted data is divided into data packets (1) such that means (20 ) are provided for reading out a first bit sequence (6) in plain text or in coded form from the data packets and means (24) for generating and / or storing at least one second bit sequence (7) which is connected to the shift register or registers (6). 27, 30, 31, 32, 33, 34, 35, 36, 37) cooperate in such a way that at least the first bit sequence (6) and the second bit sequence (7) are used to initialize the feedback Sc bat register (27; 30,31,32; 33.34; 35, 36, 37), wherein the feedback shift register (s) (27; 30, 31, 32; 33, 34; 35, 36, 37) is re-initialized for the decryption of each data packet, wherein the second bit string (7) represents a secret key that can not be read from the encrypted data packets.

19. The apparatus of claim 17 or 18, characterized in that the means (9,10; 20,21,24) for generating, storing or reading the first (6) and the second (7) bit sequence with an XOR gate (28) cooperate in such a way that the first bit sequence (6) and the second bit sequence (7) are linked by means of an XOR function, the bit sequence resulting from the combination being fed to the feedback shift register (27) for initialization.

20. Device according to claim 17 or 18, characterized in that the first bit sequence (6) is fed to at least one first feedback shift register (30; 33; 35) for its initialization and the second bit sequence (7) to at least one second feedback shift register (31; 34; 36) is fed to its initialization.

21. Device according to one of claims 17 to 20, characterized in that the first bit sequence (6) is a for the data packet to be encrypted (1) unique bit sequence, the respective encrypted data packet as a packet identifier (17) in plain text or in coded form is added.

22. Device according to one of claims 17 to 21, characterized in that means (13; 25) are provided for generating the second bit sequence (7) from a unique identifier (11) of the transmitter and a unique identifier (12) of the receiver.

23. The device according to claim 22, characterized in that the means (13; 25) for generating the second bit sequence (7) comprises an XOR gate whose one input the unique identifier (11) of the transmitter and the other input the unique identifier (12) of the receiver is supplied.

24. Device according to one of claims 17 to 23, characterized in that means (14; 26) for generating and / or storing at least one third bit sequence (8) are provided, which with the or the shift register (s) (27; 32, 37) cooperate in such a way that also the third bit sequence (8) is used to initialize the feedback shift register (s) (27; 32; 37).

25. The apparatus of claim 24, characterized in that the third bit sequence (8) is generated from a respective current date and / or time.

26. Device according to claim 24 or 25, characterized in that the third bit sequence (8) is fed to a third feedback shift register (32, 37) for initialization.

27. The device according to one of claims 17 to 26, characterized in that the generation of the key stream (3) begins as soon as at least one of the feedback shift registers (27; 30,31,32; 33,34; 35,36,37) with the first bit from the respective bit sequence is filled.

28. Device according to one of claims 17 to 27, characterized in that the feedback shift registers (30,31,32; 33,34; 35,36,37) are filled simultaneously with the respective bit sequence.

29. Device according to one of claims 17 to 28, characterized in that for the feedback of the or the shift register (27; 30,31,32; 33,34; 35,36,37) at least one XOR gate (XORpl, XORp2 , XORp3, XORp4, XORppl, XORpppl).

30. Device according to one of claims 17 to 29, characterized in that the feedback shift registers (30, 31, 32; 33, 34; 35, 36, 37) are interconnected in such a way that, depending on the state of the one shift register the at least one XOR gate (XORpl, XORp2, XORp3, XORp4, XORppl) of the other shift register is turned on or off.

31. Device according to one of claims 17 to 30, characterized in that the at least one feedback shift register (30,31,32; 33,34; 35,36,37) has a plurality of memory elements (FF1, FF2.) Connected to a code-producing row , ...; FFpl, FFp2, ...; FFppl, FFpp2, ...), the output of the last memory element in the row being connected to the input of the first memory element in the series to form a circuit, wherein the feedback with the aid of the at least one XOR gate (XORpl, XORp2, XORp3, XORp4, XORppl, XORpppl) such that the first input of the XOR gate is connected to the output of a memory element (FF2) located in the code-producing row, the second input to the output of another memory element (FF5) located in the code-producing row, and the output having the input of the code in the code-producing row following the memory element connected to the first input of the XOR gate eicherelements (FF3) is connected.

32. Device according to claim 31, characterized in that the line connecting the second input of the at least one XOR gate (XORpl) and the output of the further memory element (FF5) located in the code-producing row (30; 33; 35) an AND gate (ANDpl) is connected such that the output of the AND gate (ANDpl) to the second input of the XOR gate (XORpl), the first input of the AND gate (ANDpl) to the output of the other in the and the second input of the AND gate is connected to the output of a code-pro- gramming memory element (FFp2) and that preferably the output of one of the code-producing series (30; 33 35), is connected to the input of an inverter (INV) and the output of the inverter (INV) is connected to the input of another memory element (FF1) arranged in the code producing line (30; 33; 35) a memory element of a further feedback shift register (31; 34; 36) is used.

33. Apparatus according to claim 31 or 32, characterized in that a plurality of XOR gates (XORpl, p2, p3, p4) is provided, whose first input is in each case from an output of one in the codeproduzierenden series (30; 33; 35) and the second input of which is fed in each case by the output of a further memory element (FF8, 15, 20, 23) located in the code-producing row (30; 33; 35) which has a number of stored memory elements (FF1, 2, 3, 4) of storage elements in the flow direction of the row (30; 33; 35) is removed from the respective storage element (FF1,2,3,3) connected to the first input. each corresponds to a different prime number which is greater than 1 and is not a partial amount of the total number of memory elements (FF1, 2, ..., n) connected in series (30; 33; 35).

34. Device according to one of claims 31 to 33, characterized in that a plurality of code-programming, in each case an AND gate (ANDP1, p2, p3, p) and an XOR gate (XORP1, p2, p3, p) associated Speicherele - Menten (FFpl, p2, p3, p4, ... pn) is provided and connected in a closed loop in a row (31; 34; 36) and at least one XOR gate (XORppl) is arranged, the first input with the output of a memory element (FFp6) located in the code-programming series (31; 34; 36), whose second input is connected to the output of another memory element (FFp5) located in the code-programming series (31; 34; 36) and whose output is connected to the input of the code-programmable row (31; 34; 36) to the memory element (FFp6) connected to the first input of the XOR gate (XORppl), which is connected to the first input of the XOR gate (XORppl).

35. Device according to one of claims 31 to 34, characterized in that in the second input of the at least one XOR gate (XORppl) and the output of the further in the code-programming row (31; 34; 36) located memory element (FFp3) connecting line is an AND gate (ANDppl) connected such that the output of the AND gate (ANDppl) to the second input of the XOR gate (XORppl), the first input of the AND gate (ANDppl) to the output of the other in the code-programming series (31; 34; 36) located memory element (FFp3) and the second input of the AND gate (UNDppl) with connected to the output of a memory element (FFpp5) serving to program the code-programming series (31; 34; 36).

36. Device according to one of claims 31 to 35, characterized in that a plurality of the programming of the code-programming series (31; 34; 36) serving, in each case an AND gate (ANDppl) and an XOR gate (XORppl) associated memory elements (FFppl, pp2, pp3, pp4, ... ppn) and is connected in a closed series (32, 37) and at least one XOR gate (XORpppl) is arranged, the first input of which is connected to the output of an in the second input is connected to the output of another memory element (FFpp3) in the row (32, 37) and whose output is connected to the input of the in-line (32, 37) memory element (FFppl) ) connected to the first input of the XOR gate (XORpppl) connected storage element (FFppl) subsequent storage element (FFpp2) is connected.